72 files changed, 9740 insertions, 0 deletions

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 486a0d6301e7..d552c65fa1b0 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -7,11 +7,240 @@
 config PLAT_SAMSUNG
         bool
         depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX
+        select NO_IOPORT
         default y
         help
           Base platform code for all Samsung SoC based systems
 
 if PLAT_SAMSUNG
 
+# boot configurations
+
+comment "Boot options"
+
+config S3C_BOOT_WATCHDOG
+        bool "S3C Initialisation watchdog"
+        depends on S3C2410_WATCHDOG
+        help
+          Say y to enable the watchdog during the kernel decompression
+          stage. If the kernel fails to uncompress, then the watchdog
+          will trigger a reset and the system should restart.
+
+config S3C_BOOT_ERROR_RESET
+        bool "S3C Reboot on decompression error"
+        help
+          Say y here to use the watchdog to reset the system if the
+          kernel decompressor detects an error during decompression.
+
+config S3C_BOOT_UART_FORCE_FIFO
+       bool "Force UART FIFO on during boot process"
+       default y
+       help
+         Say Y here to force the UART FIFOs on during the kernel
+         uncompressor
+
+
+config S3C_LOWLEVEL_UART_PORT
+        int "S3C UART to use for low-level messages"
+        default 0
+        help
+          Choice of which UART port to use for the low-level messages,
+          such as the `Uncompressing...` at start time. The value of
+          this configuration should be between zero and two. The port
+          must have been initialised by the boot-loader before use.
+
+# clock options
+
+config SAMSUNG_CLKSRC
+        bool
+        help
+          Select the clock code for the clksrc implementation
+          used by newer systems such as the S3C64XX.
+
+# options for IRQ support
+
+config SAMSUNG_IRQ_VIC_TIMER
+       bool
+       help
+         Internal configuration to build the VIC timer interrupt code.
+
+config SAMSUNG_IRQ_UART
+       bool
+       help
+         Internal configuration to build the IRQ UART demux code.
+
+# options for gpio configuration support
+
+config SAMSUNG_GPIOLIB_4BIT
+        bool
+        help
+          GPIOlib file contains the 4 bit modification functions for gpio
+          configuration. GPIOlib shall be compiled only for S3C64XX and S5P
+          series of processors.
+
+config S3C_GPIO_CFG_S3C24XX
+        bool
+        help
+          Internal configuration to enable S3C24XX style GPIO configuration
+          functions.
+
+config S3C_GPIO_CFG_S3C64XX
+        bool
+        help
+          Internal configuration to enable S3C64XX style GPIO configuration
+          functions.
+
+config S5P_GPIO_CFG_S5PC1XX
+        bool
+        help
+          Internal configuration to enable S5PC1XX style GPIO configuration
+          functions.
+
+config S3C_GPIO_PULL_UPDOWN
+        bool
+        help
+          Internal configuration to enable the correct GPIO pull helper
+
+config S3C_GPIO_PULL_DOWN
+        bool
+        help
+          Internal configuration to enable the correct GPIO pull helper
+
+config S3C_GPIO_PULL_UP
+        bool
+        help
+          Internal configuration to enable the correct GPIO pull helper
+
+config SAMSUNG_GPIO_EXTRA
+        int "Number of additional GPIO pins"
+        default 0
+        help
+          Use additional GPIO space in addition to the GPIO's the SOC
+          provides. This allows expanding the GPIO space for use with
+          GPIO expanders.
+
+config S3C_GPIO_SPACE
+        int "Space between gpio banks"
+        default 0
+        help
+          Add a number of spare GPIO entries between each bank for debugging
+          purposes. This allows any problems where an counter overflows from
+          one bank to another to be caught, at the expense of using a little
+          more memory.
+
+config S3C_GPIO_TRACK
+        bool
+        help
+          Internal configuration option to enable the s3c specific gpio
+          chip tracking if the platform requires it.
+
+# ADC driver
+
+config S3C_ADC
+        bool "ADC common driver support"
+        help
+          Core support for the ADC block found in the Samsung SoC systems
+          for drivers such as the touchscreen and hwmon to use to share
+          this resource.
+
+# device definitions to compile in
+
+config S3C_DEV_HSMMC
+        bool
+        help
+          Compile in platform device definitions for HSMMC code
+
+config S3C_DEV_HSMMC1
+        bool
+        help
+          Compile in platform device definitions for HSMMC channel 1
+
+config S3C_DEV_HSMMC2
+        bool
+        help
+          Compile in platform device definitions for HSMMC channel 2
+
+config S3C_DEV_I2C1
+        bool
+        help
+          Compile in platform device definitions for I2C channel 1
+
+config S3C_DEV_FB
+        bool
+        help
+          Compile in platform device definition for framebuffer
+
+config S3C_DEV_USB_HOST
+        bool
+        help
+          Compile in platform device definition for USB host.
+
+config S3C_DEV_USB_HSOTG
+        bool
+        help
+          Compile in platform device definition for USB high-speed OtG
+
+config S3C_DEV_NAND
+        bool
+        help
+          Compile in platform device definition for NAND controller
+
+config S3C64XX_DEV_SPI
+        bool
+        help
+          Compile in platform device definitions for S3C64XX's type
+          SPI controllers.
+
+# DMA
+
+config S3C_DMA
+        bool
+        help
+          Internal configuration for S3C DMA core
+
+comment "Power management"
+
+config SAMSUNG_PM_DEBUG
+        bool "S3C2410 PM Suspend debug"
+        depends on PM
+        help
+          Say Y here if you want verbose debugging from the PM Suspend and
+          Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
+          for more information.
+
+config S3C_PM_DEBUG_LED_SMDK
+       bool "SMDK LED suspend/resume debugging"
+       depends on PM && (MACH_SMDK6410)
+       help
+         Say Y here to enable the use of the SMDK LEDs on the baseboard
+         for debugging of the state of the suspend and resume process.
+
+         Note, this currently only works for S3C64XX based SMDK boards.
+
+config SAMSUNG_PM_CHECK
+        bool "S3C2410 PM Suspend Memory CRC"
+        depends on PM && CRC32
+        help
+          Enable the PM code's memory area checksum over sleep. This option
+          will generate CRCs of all blocks of memory, and store them before
+          going to sleep. The blocks are then checked on resume for any
+          errors.
+
+          Note, this can take several seconds depending on memory size
+          and CPU speed.
+
+          See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
+
+config SAMSUNG_PM_CHECK_CHUNKSIZE
+        int "S3C2410 PM Suspend CRC Chunksize (KiB)"
+        depends on PM && SAMSUNG_PM_CHECK
+        default 64
+        help
+          Set the chunksize in Kilobytes of the CRC for checking memory
+          corruption over suspend and resume. A smaller value will mean that
+          the CRC data block will take more memory, but wil identify any
+          faults with better precision.
+
+          See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
 
 endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 4478b9f7dc34..22c89d08f6e5 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -9,3 +9,48 @@ obj-m				:=
 obj-n                           := dummy.o
 obj-                            :=
 
+# Objects we always build independent of SoC choice
+
+obj-y                           += init.o
+obj-y                           += time.o
+obj-y                           += clock.o
+obj-y                           += pwm-clock.o
+obj-y                           += gpio.o
+obj-y                           += gpio-config.o
+
+obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT)      += gpiolib.o
+obj-$(CONFIG_SAMSUNG_CLKSRC)    += clock-clksrc.o
+
+obj-$(CONFIG_SAMSUNG_IRQ_UART)  += irq-uart.o
+obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o
+
+# ADC
+
+obj-$(CONFIG_S3C_ADC)   += adc.o
+
+# devices
+
+obj-$(CONFIG_S3C_DEV_HSMMC)     += dev-hsmmc.o
+obj-$(CONFIG_S3C_DEV_HSMMC1)    += dev-hsmmc1.o
+obj-$(CONFIG_S3C_DEV_HSMMC2)    += dev-hsmmc2.o
+obj-y                           += dev-i2c0.o
+obj-$(CONFIG_S3C_DEV_I2C1)      += dev-i2c1.o
+obj-$(CONFIG_S3C_DEV_FB)        += dev-fb.o
+obj-y                           += dev-uart.o
+obj-$(CONFIG_S3C_DEV_USB_HOST)  += dev-usb.o
+obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
+obj-$(CONFIG_S3C_DEV_NAND)      += dev-nand.o
+
+# DMA support
+
+obj-$(CONFIG_S3C_DMA)           += dma.o
+
+# PM support
+
+obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_PM)                += pm-gpio.o
+obj-$(CONFIG_SAMSUNG_PM_CHECK)  += pm-check.o
+
+# PWM support
+
+obj-$(CONFIG_HAVE_PWM)          += pwm.o
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
new file mode 100644
index 000000000000..0b5833b9ac5b
--- /dev/null
+++ b/arch/arm/plat-samsung/adc.c
@@ -0,0 +1,474 @@
+/* arch/arm/plat-samsung/adc.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
+ *
+ * Samsung ADC device core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+
+#include <plat/regs-adc.h>
+#include <plat/adc.h>
+
+/* This driver is designed to control the usage of the ADC block between
+ * the touchscreen and any other drivers that may need to use it, such as
+ * the hwmon driver.
+ *
+ * Priority will be given to the touchscreen driver, but as this itself is
+ * rate limited it should not starve other requests which are processed in
+ * order that they are received.
+ *
+ * Each user registers to get a client block which uniquely identifies it
+ * and stores information such as the necessary functions to callback when
+ * action is required.
+ */
+
+enum s3c_cpu_type {
+        TYPE_S3C24XX,
+        TYPE_S3C64XX
+};
+
+struct s3c_adc_client {
+        struct platform_device  *pdev;
+        struct list_head         pend;
+        wait_queue_head_t       *wait;
+
+        unsigned int             nr_samples;
+        int                      result;
+        unsigned char            is_ts;
+        unsigned char            channel;
+
+        void    (*select_cb)(struct s3c_adc_client *c, unsigned selected);
+        void    (*convert_cb)(struct s3c_adc_client *c,
+                              unsigned val1, unsigned val2,
+                              unsigned *samples_left);
+};
+
+struct adc_device {
+        struct platform_device  *pdev;
+        struct platform_device  *owner;
+        struct clk              *clk;
+        struct s3c_adc_client   *cur;
+        struct s3c_adc_client   *ts_pend;
+        void __iomem            *regs;
+
+        unsigned int             prescale;
+
+        int                      irq;
+};
+
+static struct adc_device *adc_dev;
+
+static LIST_HEAD(adc_pending);
+
+#define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
+
+static inline void s3c_adc_convert(struct adc_device *adc)
+{
+        unsigned con = readl(adc->regs + S3C2410_ADCCON);
+
+        con |= S3C2410_ADCCON_ENABLE_START;
+        writel(con, adc->regs + S3C2410_ADCCON);
+}
+
+static inline void s3c_adc_select(struct adc_device *adc,
+                                  struct s3c_adc_client *client)
+{
+        unsigned con = readl(adc->regs + S3C2410_ADCCON);
+
+        client->select_cb(client, 1);
+
+        con &= ~S3C2410_ADCCON_MUXMASK;
+        con &= ~S3C2410_ADCCON_STDBM;
+        con &= ~S3C2410_ADCCON_STARTMASK;
+
+        if (!client->is_ts)
+                con |= S3C2410_ADCCON_SELMUX(client->channel);
+
+        writel(con, adc->regs + S3C2410_ADCCON);
+}
+
+static void s3c_adc_dbgshow(struct adc_device *adc)
+{
+        adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n",
+                readl(adc->regs + S3C2410_ADCCON),
+                readl(adc->regs + S3C2410_ADCTSC),
+                readl(adc->regs + S3C2410_ADCDLY));
+}
+
+static void s3c_adc_try(struct adc_device *adc)
+{
+        struct s3c_adc_client *next = adc->ts_pend;
+
+        if (!next && !list_empty(&adc_pending)) {
+                next = list_first_entry(&adc_pending,
+                                        struct s3c_adc_client, pend);
+                list_del(&next->pend);
+        } else
+                adc->ts_pend = NULL;
+
+        if (next) {
+                adc_dbg(adc, "new client is %p\n", next);
+                adc->cur = next;
+                s3c_adc_select(adc, next);
+                s3c_adc_convert(adc);
+                s3c_adc_dbgshow(adc);
+        }
+}
+
+int s3c_adc_start(struct s3c_adc_client *client,
+                  unsigned int channel, unsigned int nr_samples)
+{
+        struct adc_device *adc = adc_dev;
+        unsigned long flags;
+
+        if (!adc) {
+                printk(KERN_ERR "%s: failed to find adc\n", __func__);
+                return -EINVAL;
+        }
+
+        if (client->is_ts && adc->ts_pend)
+                return -EAGAIN;
+
+        local_irq_save(flags);
+
+        client->channel = channel;
+        client->nr_samples = nr_samples;
+
+        if (client->is_ts)
+                adc->ts_pend = client;
+        else
+                list_add_tail(&client->pend, &adc_pending);
+
+        if (!adc->cur)
+                s3c_adc_try(adc);
+        local_irq_restore(flags);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(s3c_adc_start);
+
+static void s3c_convert_done(struct s3c_adc_client *client,
+                             unsigned v, unsigned u, unsigned *left)
+{
+        client->result = v;
+        wake_up(client->wait);
+}
+
+int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
+{
+        DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
+        int ret;
+
+        client->convert_cb = s3c_convert_done;
+        client->wait = &wake;
+        client->result = -1;
+
+        ret = s3c_adc_start(client, ch, 1);
+        if (ret < 0)
+                goto err;
+
+        ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
+        if (client->result < 0) {
+                ret = -ETIMEDOUT;
+                goto err;
+        }
+
+        client->convert_cb = NULL;
+        return client->result;
+
+err:
+        return ret;
+}
+EXPORT_SYMBOL_GPL(s3c_adc_read);
+
+static void s3c_adc_default_select(struct s3c_adc_client *client,
+                                   unsigned select)
+{
+}
+
+struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
+                                        void (*select)(struct s3c_adc_client *client,
+                                                       unsigned int selected),
+                                        void (*conv)(struct s3c_adc_client *client,
+                                                     unsigned d0, unsigned d1,
+                                                     unsigned *samples_left),
+                                        unsigned int is_ts)
+{
+        struct s3c_adc_client *client;
+
+        WARN_ON(!pdev);
+
+        if (!select)
+                select = s3c_adc_default_select;
+
+        if (!pdev)
+                return ERR_PTR(-EINVAL);
+
+        client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
+        if (!client) {
+                dev_err(&pdev->dev, "no memory for adc client\n");
+                return ERR_PTR(-ENOMEM);
+        }
+
+        client->pdev = pdev;
+        client->is_ts = is_ts;
+        client->select_cb = select;
+        client->convert_cb = conv;
+
+        return client;
+}
+EXPORT_SYMBOL_GPL(s3c_adc_register);
+
+void s3c_adc_release(struct s3c_adc_client *client)
+{
+        /* We should really check that nothing is in progress. */
+        if (adc_dev->cur == client)
+                adc_dev->cur = NULL;
+        if (adc_dev->ts_pend == client)
+                adc_dev->ts_pend = NULL;
+        else {
+                struct list_head *p, *n;
+                struct s3c_adc_client *tmp;
+
+                list_for_each_safe(p, n, &adc_pending) {
+                        tmp = list_entry(p, struct s3c_adc_client, pend);
+                        if (tmp == client)
+                                list_del(&tmp->pend);
+                }
+        }
+
+        if (adc_dev->cur == NULL)
+                s3c_adc_try(adc_dev);
+        kfree(client);
+}
+EXPORT_SYMBOL_GPL(s3c_adc_release);
+
+static irqreturn_t s3c_adc_irq(int irq, void *pw)
+{
+        struct adc_device *adc = pw;
+        struct s3c_adc_client *client = adc->cur;
+        enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
+        unsigned long flags;
+        unsigned data0, data1;
+
+        if (!client) {
+                dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__);
+                goto exit;
+        }
+
+        data0 = readl(adc->regs + S3C2410_ADCDAT0);
+        data1 = readl(adc->regs + S3C2410_ADCDAT1);
+        adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
+
+        client->nr_samples--;
+
+        if (cpu == TYPE_S3C64XX) {
+                /* S3C64XX ADC resolution is 12-bit */
+                data0 &= 0xfff;
+                data1 &= 0xfff;
+        } else {
+                data0 &= 0x3ff;
+                data1 &= 0x3ff;
+        }
+
+        if (client->convert_cb)
+                (client->convert_cb)(client, data0, data1, &client->nr_samples);
+
+        if (client->nr_samples > 0) {
+                /* fire another conversion for this */
+
+                client->select_cb(client, 1);
+                s3c_adc_convert(adc);
+        } else {
+                local_irq_save(flags);
+                (client->select_cb)(client, 0);
+                adc->cur = NULL;
+
+                s3c_adc_try(adc);
+                local_irq_restore(flags);
+        }
+
+exit:
+        if (cpu == TYPE_S3C64XX) {
+                /* Clear ADC interrupt */
+                writel(0, adc->regs + S3C64XX_ADCCLRINT);
+        }
+        return IRQ_HANDLED;
+}
+
+static int s3c_adc_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct adc_device *adc;
+        struct resource *regs;
+        int ret;
+        unsigned tmp;
+
+        adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL);
+        if (adc == NULL) {
+                dev_err(dev, "failed to allocate adc_device\n");
+                return -ENOMEM;
+        }
+
+        adc->pdev = pdev;
+        adc->prescale = S3C2410_ADCCON_PRSCVL(49);
+
+        adc->irq = platform_get_irq(pdev, 1);
+        if (adc->irq <= 0) {
+                dev_err(dev, "failed to get adc irq\n");
+                ret = -ENOENT;
+                goto err_alloc;
+        }
+
+        ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
+        if (ret < 0) {
+                dev_err(dev, "failed to attach adc irq\n");
+                goto err_alloc;
+        }
+
+        adc->clk = clk_get(dev, "adc");
+        if (IS_ERR(adc->clk)) {
+                dev_err(dev, "failed to get adc clock\n");
+                ret = PTR_ERR(adc->clk);
+                goto err_irq;
+        }
+
+        regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!regs) {
+                dev_err(dev, "failed to find registers\n");
+                ret = -ENXIO;
+                goto err_clk;
+        }
+
+        adc->regs = ioremap(regs->start, resource_size(regs));
+        if (!adc->regs) {
+                dev_err(dev, "failed to map registers\n");
+                ret = -ENXIO;
+                goto err_clk;
+        }
+
+        clk_enable(adc->clk);
+
+        tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
+        if (platform_get_device_id(pdev)->driver_data == TYPE_S3C64XX) {
+                /* Enable 12-bit ADC resolution */
+                tmp |= S3C64XX_ADCCON_RESSEL;
+        }
+        writel(tmp, adc->regs + S3C2410_ADCCON);
+
+        dev_info(dev, "attached adc driver\n");
+
+        platform_set_drvdata(pdev, adc);
+        adc_dev = adc;
+
+        return 0;
+
+ err_clk:
+        clk_put(adc->clk);
+
+ err_irq:
+        free_irq(adc->irq, adc);
+
+ err_alloc:
+        kfree(adc);
+        return ret;
+}
+
+static int __devexit s3c_adc_remove(struct platform_device *pdev)
+{
+        struct adc_device *adc = platform_get_drvdata(pdev);
+
+        iounmap(adc->regs);
+        free_irq(adc->irq, adc);
+        clk_disable(adc->clk);
+        clk_put(adc->clk);
+        kfree(adc);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        struct adc_device *adc = platform_get_drvdata(pdev);
+        u32 con;
+
+        con = readl(adc->regs + S3C2410_ADCCON);
+        con |= S3C2410_ADCCON_STDBM;
+        writel(con, adc->regs + S3C2410_ADCCON);
+
+        disable_irq(adc->irq);
+        clk_disable(adc->clk);
+
+        return 0;
+}
+
+static int s3c_adc_resume(struct platform_device *pdev)
+{
+        struct adc_device *adc = platform_get_drvdata(pdev);
+
+        clk_enable(adc->clk);
+        enable_irq(adc->irq);
+
+        writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
+               adc->regs + S3C2410_ADCCON);
+
+        return 0;
+}
+
+#else
+#define s3c_adc_suspend NULL
+#define s3c_adc_resume NULL
+#endif
+
+static struct platform_device_id s3c_adc_driver_ids[] = {
+        {
+                .name           = "s3c24xx-adc",
+                .driver_data    = TYPE_S3C24XX,
+        }, {
+                .name           = "s3c64xx-adc",
+                .driver_data    = TYPE_S3C64XX,
+        },
+        { }
+};
+MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
+
+static struct platform_driver s3c_adc_driver = {
+        .id_table       = s3c_adc_driver_ids,
+        .driver         = {
+                .name   = "s3c-adc",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = s3c_adc_probe,
+        .remove         = __devexit_p(s3c_adc_remove),
+        .suspend        = s3c_adc_suspend,
+        .resume         = s3c_adc_resume,
+};
+
+static int __init adc_init(void)
+{
+        int ret;
+
+        ret = platform_driver_register(&s3c_adc_driver);
+        if (ret)
+                printk(KERN_ERR "%s: failed to add adc driver\n", __func__);
+
+        return ret;
+}
+
+arch_initcall(adc_init);
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
new file mode 100644
index 000000000000..ae8b8507663f
--- /dev/null
+++ b/arch/arm/plat-samsung/clock-clksrc.c
@@ -0,0 +1,212 @@
+/* linux/arch/arm/plat-samsung/clock-clksrc.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/cpu-freq.h>
+
+static inline struct clksrc_clk *to_clksrc(struct clk *clk)
+{
+        return container_of(clk, struct clksrc_clk, clk);
+}
+
+static inline u32 bit_mask(u32 shift, u32 nr_bits)
+{
+        u32 mask = 0xffffffff >> (32 - nr_bits);
+
+        return mask << shift;
+}
+
+static unsigned long s3c_getrate_clksrc(struct clk *clk)
+{
+        struct clksrc_clk *sclk = to_clksrc(clk);
+        unsigned long rate = clk_get_rate(clk->parent);
+        u32 clkdiv = __raw_readl(sclk->reg_div.reg);
+        u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
+
+        clkdiv &= mask;
+        clkdiv >>= sclk->reg_div.shift;
+        clkdiv++;
+
+        rate /= clkdiv;
+        return rate;
+}
+
+static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate)
+{
+        struct clksrc_clk *sclk = to_clksrc(clk);
+        void __iomem *reg = sclk->reg_div.reg;
+        unsigned int div;
+        u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
+        u32 val;
+
+        rate = clk_round_rate(clk, rate);
+        div = clk_get_rate(clk->parent) / rate;
+        if (div > (1 << sclk->reg_div.size))
+                return -EINVAL;
+
+        val = __raw_readl(reg);
+        val &= ~mask;
+        val |= (div - 1) << sclk->reg_div.shift;
+        __raw_writel(val, reg);
+
+        return 0;
+}
+
+static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
+{
+        struct clksrc_clk *sclk = to_clksrc(clk);
+        struct clksrc_sources *srcs = sclk->sources;
+        u32 clksrc = __raw_readl(sclk->reg_src.reg);
+        u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size);
+        int src_nr = -1;
+        int ptr;
+
+        for (ptr = 0; ptr < srcs->nr_sources; ptr++)
+                if (srcs->sources[ptr] == parent) {
+                        src_nr = ptr;
+                        break;
+                }
+
+        if (src_nr >= 0) {
+                clk->parent = parent;
+
+                clksrc &= ~mask;
+                clksrc |= src_nr << sclk->reg_src.shift;
+
+                __raw_writel(clksrc, sclk->reg_src.reg);
+                return 0;
+        }
+
+        return -EINVAL;
+}
+
+static unsigned long s3c_roundrate_clksrc(struct clk *clk,
+                                              unsigned long rate)
+{
+        struct clksrc_clk *sclk = to_clksrc(clk);
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        int max_div = 1 << sclk->reg_div.size;
+        int div;
+
+        if (rate >= parent_rate)
+                rate = parent_rate;
+        else {
+                div = parent_rate / rate;
+                if (parent_rate % rate)
+                        div++;
+
+                if (div == 0)
+                        div = 1;
+                if (div > max_div)
+                        div = max_div;
+
+                rate = parent_rate / div;
+        }
+
+        return rate;
+}
+
+/* Clock initialisation code */
+
+void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce)
+{
+        struct clksrc_sources *srcs = clk->sources;
+        u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
+        u32 clksrc;
+
+        if (!clk->reg_src.reg) {
+                if (!clk->clk.parent)
+                        printk(KERN_ERR "%s: no parent clock specified\n",
+                                clk->clk.name);
+                return;
+        }
+
+        clksrc = __raw_readl(clk->reg_src.reg);
+        clksrc &= mask;
+        clksrc >>= clk->reg_src.shift;
+
+        if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
+                printk(KERN_ERR "%s: bad source %d\n",
+                       clk->clk.name, clksrc);
+                return;
+        }
+
+        clk->clk.parent = srcs->sources[clksrc];
+
+        if (announce)
+                printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
+                       clk->clk.name, clk->clk.parent->name, clksrc,
+                       clk_get_rate(&clk->clk));
+}
+
+static struct clk_ops clksrc_ops = {
+        .set_parent     = s3c_setparent_clksrc,
+        .get_rate       = s3c_getrate_clksrc,
+        .set_rate       = s3c_setrate_clksrc,
+        .round_rate     = s3c_roundrate_clksrc,
+};
+
+static struct clk_ops clksrc_ops_nodiv = {
+        .set_parent     = s3c_setparent_clksrc,
+};
+
+static struct clk_ops clksrc_ops_nosrc = {
+        .get_rate       = s3c_getrate_clksrc,
+        .set_rate       = s3c_setrate_clksrc,
+        .round_rate     = s3c_roundrate_clksrc,
+};
+
+void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
+{
+        int ret;
+
+        for (; size > 0; size--, clksrc++) {
+                if (!clksrc->reg_div.reg && !clksrc->reg_src.reg)
+                        printk(KERN_ERR "%s: clock %s has no registers set\n",
+                               __func__, clksrc->clk.name);
+
+                /* fill in the default functions */
+
+                if (!clksrc->clk.ops) {
+                        if (!clksrc->reg_div.reg)
+                                clksrc->clk.ops = &clksrc_ops_nodiv;
+                        else if (!clksrc->reg_src.reg)
+                                clksrc->clk.ops = &clksrc_ops_nosrc;
+                        else
+                                clksrc->clk.ops = &clksrc_ops;
+                }
+
+                /* setup the clocksource, but do not announce it
+                 * as it may be re-set by the setup routines
+                 * called after the rest of the clocks have been
+                 * registered
+                 */
+                s3c_set_clksrc(clksrc, false);
+
+                ret = s3c24xx_register_clock(&clksrc->clk);
+
+                if (ret < 0) {
+                        printk(KERN_ERR "%s: failed to register %s (%d)\n",
+                               __func__, clksrc->clk.name, ret);
+                }
+        }
+}
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
new file mode 100644
index 000000000000..1b25c9d8c403
--- /dev/null
+++ b/arch/arm/plat-samsung/clock.c
@@ -0,0 +1,409 @@
+/* linux/arch/arm/plat-s3c24xx/clock.c
+ *
+ * Copyright 2004-2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX Core clock control support
+ *
+ * Based on, and code from linux/arch/arm/mach-versatile/clock.c
+ **
+ **  Copyright (C) 2004 ARM Limited.
+ **  Written by Deep Blue Solutions Limited.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <plat/cpu-freq.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+/* clock information */
+
+static LIST_HEAD(clocks);
+
+/* We originally used an mutex here, but some contexts (see resume)
+ * are calling functions such as clk_set_parent() with IRQs disabled
+ * causing an BUG to be triggered.
+ */
+DEFINE_SPINLOCK(clocks_lock);
+
+/* enable and disable calls for use with the clk struct */
+
+static int clk_null_enable(struct clk *clk, int enable)
+{
+        return 0;
+}
+
+/* Clock API calls */
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        struct clk *p;
+        struct clk *clk = ERR_PTR(-ENOENT);
+        int idno;
+
+        if (dev == NULL || dev->bus != &platform_bus_type)
+                idno = -1;
+        else
+                idno = to_platform_device(dev)->id;
+
+        spin_lock(&clocks_lock);
+
+        list_for_each_entry(p, &clocks, list) {
+                if (p->id == idno &&
+                    strcmp(id, p->name) == 0 &&
+                    try_module_get(p->owner)) {
+                        clk = p;
+                        break;
+                }
+        }
+
+        /* check for the case where a device was supplied, but the
+         * clock that was being searched for is not device specific */
+
+        if (IS_ERR(clk)) {
+                list_for_each_entry(p, &clocks, list) {
+                        if (p->id == -1 && strcmp(id, p->name) == 0 &&
+                            try_module_get(p->owner)) {
+                                clk = p;
+                                break;
+                        }
+                }
+        }
+
+        spin_unlock(&clocks_lock);
+        return clk;
+}
+
+void clk_put(struct clk *clk)
+{
+        module_put(clk->owner);
+}
+
+int clk_enable(struct clk *clk)
+{
+        if (IS_ERR(clk) || clk == NULL)
+                return -EINVAL;
+
+        clk_enable(clk->parent);
+
+        spin_lock(&clocks_lock);
+
+        if ((clk->usage++) == 0)
+                (clk->enable)(clk, 1);
+
+        spin_unlock(&clocks_lock);
+        return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+        if (IS_ERR(clk) || clk == NULL)
+                return;
+
+        spin_lock(&clocks_lock);
+
+        if ((--clk->usage) == 0)
+                (clk->enable)(clk, 0);
+
+        spin_unlock(&clocks_lock);
+        clk_disable(clk->parent);
+}
+
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (IS_ERR(clk))
+                return 0;
+
+        if (clk->rate != 0)
+                return clk->rate;
+
+        if (clk->ops != NULL && clk->ops->get_rate != NULL)
+                return (clk->ops->get_rate)(clk);
+
+        if (clk->parent != NULL)
+                return clk_get_rate(clk->parent);
+
+        return clk->rate;
+}
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
+                return (clk->ops->round_rate)(clk, rate);
+
+        return rate;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret;
+
+        if (IS_ERR(clk))
+                return -EINVAL;
+
+        /* We do not default just do a clk->rate = rate as
+         * the clock may have been made this way by choice.
+         */
+
+        WARN_ON(clk->ops == NULL);
+        WARN_ON(clk->ops && clk->ops->set_rate == NULL);
+
+        if (clk->ops == NULL || clk->ops->set_rate == NULL)
+                return -EINVAL;
+
+        spin_lock(&clocks_lock);
+        ret = (clk->ops->set_rate)(clk, rate);
+        spin_unlock(&clocks_lock);
+
+        return ret;
+}
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+        return clk->parent;
+}
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int ret = 0;
+
+        if (IS_ERR(clk))
+                return -EINVAL;
+
+        spin_lock(&clocks_lock);
+
+        if (clk->ops && clk->ops->set_parent)
+                ret = (clk->ops->set_parent)(clk, parent);
+
+        spin_unlock(&clocks_lock);
+
+        return ret;
+}
+
+EXPORT_SYMBOL(clk_get);
+EXPORT_SYMBOL(clk_put);
+EXPORT_SYMBOL(clk_enable);
+EXPORT_SYMBOL(clk_disable);
+EXPORT_SYMBOL(clk_get_rate);
+EXPORT_SYMBOL(clk_round_rate);
+EXPORT_SYMBOL(clk_set_rate);
+EXPORT_SYMBOL(clk_get_parent);
+EXPORT_SYMBOL(clk_set_parent);
+
+/* base clocks */
+
+int clk_default_setrate(struct clk *clk, unsigned long rate)
+{
+        clk->rate = rate;
+        return 0;
+}
+
+struct clk_ops clk_ops_def_setrate = {
+        .set_rate       = clk_default_setrate,
+};
+
+struct clk clk_xtal = {
+        .name           = "xtal",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+};
+
+struct clk clk_ext = {
+        .name           = "ext",
+        .id             = -1,
+};
+
+struct clk clk_epll = {
+        .name           = "epll",
+        .id             = -1,
+};
+
+struct clk clk_mpll = {
+        .name           = "mpll",
+        .id             = -1,
+        .ops            = &clk_ops_def_setrate,
+};
+
+struct clk clk_upll = {
+        .name           = "upll",
+        .id             = -1,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+};
+
+struct clk clk_f = {
+        .name           = "fclk",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = &clk_mpll,
+        .ctrlbit        = 0,
+};
+
+struct clk clk_h = {
+        .name           = "hclk",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+        .ops            = &clk_ops_def_setrate,
+};
+
+struct clk clk_p = {
+        .name           = "pclk",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+        .ops            = &clk_ops_def_setrate,
+};
+
+struct clk clk_usb_bus = {
+        .name           = "usb-bus",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = &clk_upll,
+};
+
+
+struct clk s3c24xx_uclk = {
+        .name           = "uclk",
+        .id             = -1,
+};
+
+/* initialise the clock system */
+
+/**
+ * s3c24xx_register_clock() - register a clock
+ * @clk: The clock to register
+ *
+ * Add the specified clock to the list of clocks known by the system.
+ */
+int s3c24xx_register_clock(struct clk *clk)
+{
+        if (clk->enable == NULL)
+                clk->enable = clk_null_enable;
+
+        /* add to the list of available clocks */
+
+        /* Quick check to see if this clock has already been registered. */
+        BUG_ON(clk->list.prev != clk->list.next);
+
+        spin_lock(&clocks_lock);
+        list_add(&clk->list, &clocks);
+        spin_unlock(&clocks_lock);
+
+        return 0;
+}
+
+/**
+ * s3c24xx_register_clocks() - register an array of clock pointers
+ * @clks: Pointer to an array of struct clk pointers
+ * @nr_clks: The number of clocks in the @clks array.
+ *
+ * Call s3c24xx_register_clock() for all the clock pointers contained
+ * in the @clks list. Returns the number of failures.
+ */
+int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
+{
+        int fails = 0;
+
+        for (; nr_clks > 0; nr_clks--, clks++) {
+                if (s3c24xx_register_clock(*clks) < 0) {
+                        struct clk *clk = *clks;
+                        printk(KERN_ERR "%s: failed to register %p: %s\n",
+                               __func__, clk, clk->name);
+                        fails++;
+                }
+        }
+
+        return fails;
+}
+
+/**
+ * s3c_register_clocks() - register an array of clocks
+ * @clkp: Pointer to the first clock in the array.
+ * @nr_clks: Number of clocks to register.
+ *
+ * Call s3c24xx_register_clock() on the @clkp array given, printing an
+ * error if it fails to register the clock (unlikely).
+ */
+void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
+{
+        int ret;
+
+        for (; nr_clks > 0; nr_clks--, clkp++) {
+                ret = s3c24xx_register_clock(clkp);
+
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+}
+
+/* initalise all the clocks */
+
+int __init s3c24xx_register_baseclocks(unsigned long xtal)
+{
+        printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
+
+        clk_xtal.rate = xtal;
+
+        /* register our clocks */
+
+        if (s3c24xx_register_clock(&clk_xtal) < 0)
+                printk(KERN_ERR "failed to register master xtal\n");
+
+        if (s3c24xx_register_clock(&clk_mpll) < 0)
+                printk(KERN_ERR "failed to register mpll clock\n");
+
+        if (s3c24xx_register_clock(&clk_upll) < 0)
+                printk(KERN_ERR "failed to register upll clock\n");
+
+        if (s3c24xx_register_clock(&clk_f) < 0)
+                printk(KERN_ERR "failed to register cpu fclk\n");
+
+        if (s3c24xx_register_clock(&clk_h) < 0)
+                printk(KERN_ERR "failed to register cpu hclk\n");
+
+        if (s3c24xx_register_clock(&clk_p) < 0)
+                printk(KERN_ERR "failed to register cpu pclk\n");
+
+        return 0;
+}
+
diff --git a/arch/arm/plat-samsung/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c
new file mode 100644
index 000000000000..a90198fc4b0f
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-fb.c
@@ -0,0 +1,73 @@
+/* linux/arch/arm/plat-s3c/dev-fb.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for framebuffer device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <mach/regs-fb.h>
+
+#include <plat/fb.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_fb_resource[] = {
+        [0] = {
+                .start = S3C_PA_FB,
+                .end   = S3C_PA_FB + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_LCD_VSYNC,
+                .end   = IRQ_LCD_VSYNC,
+                .flags = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start = IRQ_LCD_FIFO,
+                .end   = IRQ_LCD_FIFO,
+                .flags = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start = IRQ_LCD_SYSTEM,
+                .end   = IRQ_LCD_SYSTEM,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_fb = {
+        .name             = "s3c-fb",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s3c_fb_resource),
+        .resource         = s3c_fb_resource,
+        .dev.dma_mask     = &s3c_device_fb.dev.coherent_dma_mask,
+        .dev.coherent_dma_mask = 0xffffffffUL,
+};
+
+void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
+{
+        struct s3c_fb_platdata *npd;
+
+        if (!pd) {
+                printk(KERN_ERR "%s: no platform data\n", __func__);
+                return;
+        }
+
+        npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+
+        s3c_device_fb.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
new file mode 100644
index 000000000000..4c05b39810e2
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-s3c/dev-hsmmc.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for hsmmc devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+
+#include <mach/map.h>
+#include <plat/sdhci.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#define S3C_SZ_HSMMC    (0x1000)
+
+static struct resource s3c_hsmmc_resource[] = {
+        [0] = {
+                .start = S3C_PA_HSMMC0,
+                .end   = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_HSMMC0,
+                .end   = IRQ_HSMMC0,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
+
+struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
+        .max_width      = 4,
+        .host_caps      = (MMC_CAP_4_BIT_DATA |
+                           MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+};
+
+struct platform_device s3c_device_hsmmc0 = {
+        .name           = "s3c-sdhci",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s3c_hsmmc_resource),
+        .resource       = s3c_hsmmc_resource,
+        .dev            = {
+                .dma_mask               = &s3c_device_hsmmc_dmamask,
+                .coherent_dma_mask      = 0xffffffffUL,
+                .platform_data          = &s3c_hsmmc0_def_platdata,
+        },
+};
+
+void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
+{
+        struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
+
+        set->max_width = pd->max_width;
+
+        if (pd->cfg_gpio)
+                set->cfg_gpio = pd->cfg_gpio;
+        if (pd->cfg_card)
+                set->cfg_card = pd->cfg_card;
+}
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
new file mode 100644
index 000000000000..e49bc4cd0ee6
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for hsmmc device 1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+
+#include <mach/map.h>
+#include <plat/sdhci.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#define S3C_SZ_HSMMC    (0x1000)
+
+static struct resource s3c_hsmmc1_resource[] = {
+        [0] = {
+                .start = S3C_PA_HSMMC1,
+                .end   = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_HSMMC1,
+                .end   = IRQ_HSMMC1,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
+
+struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
+        .max_width      = 4,
+        .host_caps      = (MMC_CAP_4_BIT_DATA |
+                           MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+};
+
+struct platform_device s3c_device_hsmmc1 = {
+        .name           = "s3c-sdhci",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s3c_hsmmc1_resource),
+        .resource       = s3c_hsmmc1_resource,
+        .dev            = {
+                .dma_mask               = &s3c_device_hsmmc1_dmamask,
+                .coherent_dma_mask      = 0xffffffffUL,
+                .platform_data          = &s3c_hsmmc1_def_platdata,
+        },
+};
+
+void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
+{
+        struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
+
+        set->max_width = pd->max_width;
+
+        if (pd->cfg_gpio)
+                set->cfg_gpio = pd->cfg_gpio;
+        if (pd->cfg_card)
+                set->cfg_card = pd->cfg_card;
+}
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
new file mode 100644
index 000000000000..824580bc0e06
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -0,0 +1,69 @@
+/* linux/arch/arm/plat-s3c/dev-hsmmc2.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ * Copyright (c) 2009 Maurus Cuelenaere
+ *
+ * Based on arch/arm/plat-s3c/dev-hsmmc1.c
+ * original file Copyright (c) 2008 Simtec Electronics
+ *
+ * S3C series device definition for hsmmc device 2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+
+#include <mach/map.h>
+#include <plat/sdhci.h>
+#include <plat/devs.h>
+
+#define S3C_SZ_HSMMC    (0x1000)
+
+static struct resource s3c_hsmmc2_resource[] = {
+        [0] = {
+                .start = S3C_PA_HSMMC2,
+                .end   = S3C_PA_HSMMC2 + S3C_SZ_HSMMC - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_HSMMC2,
+                .end   = IRQ_HSMMC2,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static u64 s3c_device_hsmmc2_dmamask = 0xffffffffUL;
+
+struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
+        .max_width      = 4,
+        .host_caps      = (MMC_CAP_4_BIT_DATA |
+                           MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+};
+
+struct platform_device s3c_device_hsmmc2 = {
+        .name           = "s3c-sdhci",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(s3c_hsmmc2_resource),
+        .resource       = s3c_hsmmc2_resource,
+        .dev            = {
+                .dma_mask               = &s3c_device_hsmmc2_dmamask,
+                .coherent_dma_mask      = 0xffffffffUL,
+                .platform_data          = &s3c_hsmmc2_def_platdata,
+        },
+};
+
+void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
+{
+        struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
+
+        set->max_width = pd->max_width;
+
+        if (pd->cfg_gpio)
+                set->cfg_gpio = pd->cfg_gpio;
+        if (pd->cfg_card)
+                set->cfg_card = pd->cfg_card;
+}
diff --git a/arch/arm/plat-samsung/dev-i2c0.c b/arch/arm/plat-samsung/dev-i2c0.c
new file mode 100644
index 000000000000..4c761529b949
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-i2c0.c
@@ -0,0 +1,71 @@
+/* linux/arch/arm/plat-s3c/dev-i2c0.c
+ *
+ * Copyright 2008-2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for i2c device 0
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+        [0] = {
+                .start = S3C_PA_IIC,
+                .end   = S3C_PA_IIC + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IIC,
+                .end   = IRQ_IIC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_i2c0 = {
+        .name             = "s3c2410-i2c",
+#ifdef CONFIG_S3C_DEV_I2C1
+        .id               = 0,
+#else
+        .id               = -1,
+#endif
+        .num_resources    = ARRAY_SIZE(s3c_i2c_resource),
+        .resource         = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
+        .flags          = 0,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+};
+
+void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+        struct s3c2410_platform_i2c *npd;
+
+        if (!pd)
+                pd = &default_i2c_data0;
+
+        npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        else if (!npd->cfg_gpio)
+                npd->cfg_gpio = s3c_i2c0_cfg_gpio;
+
+        s3c_device_i2c0.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/dev-i2c1.c b/arch/arm/plat-samsung/dev-i2c1.c
new file mode 100644
index 000000000000..d44f79110506
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-i2c1.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-s3c/dev-i2c1.c
+ *
+ * Copyright 2008-2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for i2c device 1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+        [0] = {
+                .start = S3C_PA_IIC1,
+                .end   = S3C_PA_IIC1 + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IIC1,
+                .end   = IRQ_IIC1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_i2c1 = {
+        .name             = "s3c2410-i2c",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s3c_i2c_resource),
+        .resource         = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
+        .flags          = 0,
+        .bus_num        = 1,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+};
+
+void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+        struct s3c2410_platform_i2c *npd;
+
+        if (!pd)
+                pd = &default_i2c_data1;
+
+        npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        else if (!npd->cfg_gpio)
+                npd->cfg_gpio = s3c_i2c1_cfg_gpio;
+
+        s3c_device_i2c1.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c
new file mode 100644
index 000000000000..a52fb6cf618f
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-nand.c
@@ -0,0 +1,129 @@
+/*
+ * S3C series device definition for nand device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/nand.h>
+
+static struct resource s3c_nand_resource[] = {
+        [0] = {
+                .start = S3C_PA_NAND,
+                .end   = S3C_PA_NAND + SZ_1M,
+                .flags = IORESOURCE_MEM,
+        }
+};
+
+struct platform_device s3c_device_nand = {
+        .name             = "s3c2410-nand",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s3c_nand_resource),
+        .resource         = s3c_nand_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_nand);
+
+/**
+ * s3c_nand_copy_set() - copy nand set data
+ * @set: The new structure, directly copied from the old.
+ *
+ * Copy all the fields from the NAND set field from what is probably __initdata
+ * to new kernel memory. The code returns 0 if the copy happened correctly or
+ * an error code for the calling function to display.
+ *
+ * Note, we currently do not try and look to see if we've already copied the
+ * data in a previous set.
+ */
+static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
+{
+        void *ptr;
+        int size;
+
+        size = sizeof(struct mtd_partition) * set->nr_partitions;
+        if (size) {
+                ptr = kmemdup(set->partitions, size, GFP_KERNEL);
+                set->partitions = ptr;
+
+                if (!ptr)
+                        return -ENOMEM;
+        }
+        
+        if (set->nr_map && set->nr_chips) {
+                size = sizeof(int) * set->nr_chips;
+                ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
+                set->nr_map = ptr;
+
+                if (!ptr)
+                        return -ENOMEM;
+        }
+
+        if (set->ecc_layout) {
+                ptr = kmemdup(set->ecc_layout,
+                              sizeof(struct nand_ecclayout), GFP_KERNEL);
+                set->ecc_layout = ptr;
+
+                if (!ptr)
+                        return -ENOMEM;
+        }
+        
+        return 0;
+}
+
+void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
+{
+        struct s3c2410_platform_nand *npd;
+        int size;
+        int ret;
+
+        /* note, if we get a failure in allocation, we simply drop out of the
+         * function. If there is so little memory available at initialisation
+         * time then there is little chance the system is going to run.
+         */ 
+
+        npd = kmemdup(nand, sizeof(struct s3c2410_platform_nand), GFP_KERNEL);
+        if (!npd) {
+                printk(KERN_ERR "%s: failed copying platform data\n", __func__);
+                return;
+        }
+
+        /* now see if we need to copy any of the nand set data */
+
+        size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
+        if (size) {
+                struct s3c2410_nand_set *from = npd->sets;
+                struct s3c2410_nand_set *to;
+                int i;
+
+                to = kmemdup(from, size, GFP_KERNEL);
+                npd->sets = to; /* set, even if we failed */
+
+                if (!to) {
+                        printk(KERN_ERR "%s: no memory for sets\n", __func__);
+                        return;
+                }
+                
+                for (i = 0; i < npd->nr_sets; i++) {
+                        ret = s3c_nand_copy_set(to);
+                        if (ret) {
+                                printk(KERN_ERR "%s: failed to copy set %d\n",
+                                __func__, i);
+                                return;
+                        }
+                        to++;
+                }
+        }
+
+        s3c_device_nand.dev.platform_data = npd;
+}
+
+EXPORT_SYMBOL_GPL(s3c_nand_set_platdata);
diff --git a/arch/arm/plat-samsung/dev-uart.c b/arch/arm/plat-samsung/dev-uart.c
new file mode 100644
index 000000000000..3776cd952450
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-uart.c
@@ -0,0 +1,44 @@
+/* linux/arch/arm/plat-samsung/dev-uart.c
+ *      originally from arch/arm/plat-s3c24xx/devs.c
+ *x
+ * Copyright (c) 2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Base S3C24XX platform device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+/* uart devices */
+
+static struct platform_device s3c24xx_uart_device0 = {
+        .id             = 0,
+};
+
+static struct platform_device s3c24xx_uart_device1 = {
+        .id             = 1,
+};
+
+static struct platform_device s3c24xx_uart_device2 = {
+        .id             = 2,
+};
+
+static struct platform_device s3c24xx_uart_device3 = {
+        .id             = 3,
+};
+
+struct platform_device *s3c24xx_uart_src[4] = {
+        &s3c24xx_uart_device0,
+        &s3c24xx_uart_device1,
+        &s3c24xx_uart_device2,
+        &s3c24xx_uart_device3,
+};
+
+struct platform_device *s3c24xx_uart_devs[4] = {
+};
diff --git a/arch/arm/plat-samsung/dev-usb-hsotg.c b/arch/arm/plat-samsung/dev-usb-hsotg.c
new file mode 100644
index 000000000000..33a844ab6917
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-usb-hsotg.c
@@ -0,0 +1,48 @@
+/* linux/arch/arm/plat-s3c/dev-usb-hsotg.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for USB high-speed UDC/OtG block
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+static struct resource s3c_usb_hsotg_resources[] = {
+        [0] = {
+                .start  = S3C_PA_USB_HSOTG,
+                .end    = S3C_PA_USB_HSOTG + 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_OTG,
+                .end    = IRQ_OTG,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 s3c_hsotg_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s3c_device_usb_hsotg = {
+        .name           = "s3c-hsotg",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s3c_usb_hsotg_resources),
+        .resource       = s3c_usb_hsotg_resources,
+        .dev            = {
+                .dma_mask               = &s3c_hsotg_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
diff --git a/arch/arm/plat-samsung/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c
new file mode 100644
index 000000000000..88165657fa53
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-usb.c
@@ -0,0 +1,69 @@
+/* linux/arch/arm/plat-s3c/dev-usb.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for USB host
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+#include <plat/usb-control.h>
+
+static struct resource s3c_usb_resource[] = {
+        [0] = {
+                .start = S3C_PA_USBHOST,
+                .end   = S3C_PA_USBHOST + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBH,
+                .end   = IRQ_USBH,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static u64 s3c_device_usb_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_ohci = {
+        .name             = "s3c2410-ohci",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s3c_usb_resource),
+        .resource         = s3c_usb_resource,
+        .dev              = {
+                .dma_mask = &s3c_device_usb_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+
+EXPORT_SYMBOL(s3c_device_ohci);
+
+/**
+ * s3c_ohci_set_platdata - initialise OHCI device platform data
+ * @info: The platform data.
+ *
+ * This call copies the @info passed in and sets the device .platform_data
+ * field to that copy. The @info is copied so that the original can be marked
+ * __initdata.
+ */
+void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
+{
+        struct s3c2410_hcd_info *npd;
+
+        npd = kmemdup(info, sizeof(struct s3c2410_hcd_info), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+
+        s3c_device_ohci.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/dma.c b/arch/arm/plat-samsung/dma.c
new file mode 100644
index 000000000000..cb459dd95459
--- /dev/null
+++ b/arch/arm/plat-samsung/dma.c
@@ -0,0 +1,84 @@
+/* linux/arch/arm/plat-samsung/dma.c
+ *
+ * Copyright (c) 2003-2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C DMA core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct s3c2410_dma_buf;
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+/* dma channel state information */
+struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
+struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
+
+/* s3c_dma_lookup_channel
+ *
+ * change the dma channel number given into a real dma channel id
+*/
+
+struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
+{
+        if (channel & DMACH_LOW_LEVEL)
+                return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
+        else
+                return s3c_dma_chan_map[channel];
+}
+
+/* do we need to protect the settings of the fields from
+ * irq?
+*/
+
+int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+        if (chan == NULL)
+                return -EINVAL;
+
+        pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
+
+        chan->op_fn = rtn;
+
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_set_opfn);
+
+int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+        if (chan == NULL)
+                return -EINVAL;
+
+        pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
+
+        chan->callback_fn = rtn;
+
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
+
+int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+        if (chan == NULL)
+                return -EINVAL;
+
+        chan->flags = flags;
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_setflags);
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
new file mode 100644
index 000000000000..44a84e896546
--- /dev/null
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -0,0 +1,166 @@
+/* linux/arch/arm/plat-s3c/gpio-config.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series GPIO configuration core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned long flags;
+        int offset;
+        int ret;
+
+        if (!chip)
+                return -EINVAL;
+
+        offset = pin - chip->chip.base;
+
+        local_irq_save(flags);
+        ret = s3c_gpio_do_setcfg(chip, offset, config);
+        local_irq_restore(flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c_gpio_cfgpin);
+
+int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned long flags;
+        int offset, ret;
+
+        if (!chip)
+                return -EINVAL;
+
+        offset = pin - chip->chip.base;
+
+        local_irq_save(flags);
+        ret = s3c_gpio_do_setpull(chip, offset, pull);
+        local_irq_restore(flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c_gpio_setpull);
+
+#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
+int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
+                                  unsigned int off, unsigned int cfg)
+{
+        void __iomem *reg = chip->base;
+        unsigned int shift = off;
+        u32 con;
+
+        if (s3c_gpio_is_cfg_special(cfg)) {
+                cfg &= 0xf;
+
+                /* Map output to 0, and SFN2 to 1 */
+                cfg -= 1;
+                if (cfg > 1)
+                        return -EINVAL;
+
+                cfg <<= shift;
+        }
+
+        con = __raw_readl(reg);
+        con &= ~(0x1 << shift);
+        con |= cfg;
+        __raw_writel(con, reg);
+
+        return 0;
+}
+
+int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
+                            unsigned int off, unsigned int cfg)
+{
+        void __iomem *reg = chip->base;
+        unsigned int shift = off * 2;
+        u32 con;
+
+        if (s3c_gpio_is_cfg_special(cfg)) {
+                cfg &= 0xf;
+                if (cfg > 3)
+                        return -EINVAL;
+
+                cfg <<= shift;
+        }
+
+        con = __raw_readl(reg);
+        con &= ~(0x3 << shift);
+        con |= cfg;
+        __raw_writel(con, reg);
+
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
+int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
+                                 unsigned int off, unsigned int cfg)
+{
+        void __iomem *reg = chip->base;
+        unsigned int shift = (off & 7) * 4;
+        u32 con;
+
+        if (off < 8 && chip->chip.ngpio > 8)
+                reg -= 4;
+
+        if (s3c_gpio_is_cfg_special(cfg)) {
+                cfg &= 0xf;
+                cfg <<= shift;
+        }
+
+        con = __raw_readl(reg);
+        con &= ~(0xf << shift);
+        con |= cfg;
+        __raw_writel(con, reg);
+
+        return 0;
+}
+#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
+
+#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
+int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
+                            unsigned int off, s3c_gpio_pull_t pull)
+{
+        void __iomem *reg = chip->base + 0x08;
+        int shift = off * 2;
+        u32 pup;
+
+        pup = __raw_readl(reg);
+        pup &= ~(3 << shift);
+        pup |= pull << shift;
+        __raw_writel(pup, reg);
+
+        return 0;
+}
+
+s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
+                                        unsigned int off)
+{
+        void __iomem *reg = chip->base + 0x08;
+        int shift = off * 2;
+        u32 pup = __raw_readl(reg);
+
+        pup >>= shift;
+        pup &= 0x3;
+        return (__force s3c_gpio_pull_t)pup;
+}
+#endif
diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c
new file mode 100644
index 000000000000..28d2ab8a08db
--- /dev/null
+++ b/arch/arm/plat-samsung/gpio.c
@@ -0,0 +1,156 @@
+/* linux/arch/arm/plat-s3c/gpio.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series GPIO core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-core.h>
+
+#ifdef CONFIG_S3C_GPIO_TRACK
+struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
+
+static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
+{
+        unsigned int gpn;
+        int i;
+
+        gpn = chip->chip.base;
+        for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
+                BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
+                s3c_gpios[gpn] = chip;
+        }
+}
+#endif /* CONFIG_S3C_GPIO_TRACK */
+
+/* Default routines for controlling GPIO, based on the original S3C24XX
+ * GPIO functions which deal with the case where each gpio bank of the
+ * chip is as following:
+ *
+ * base + 0x00: Control register, 2 bits per gpio
+ *              gpio n: 2 bits starting at (2*n)
+ *              00 = input, 01 = output, others mean special-function
+ * base + 0x04: Data register, 1 bit per gpio
+ *              bit n: data bit n
+*/
+
+static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long con;
+
+        local_irq_save(flags);
+
+        con = __raw_readl(base + 0x00);
+        con &= ~(3 << (offset * 2));
+
+        __raw_writel(con, base + 0x00);
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+static int s3c_gpiolib_output(struct gpio_chip *chip,
+                              unsigned offset, int value)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long dat;
+        unsigned long con;
+
+        local_irq_save(flags);
+
+        dat = __raw_readl(base + 0x04);
+        dat &= ~(1 << offset);
+        if (value)
+                dat |= 1 << offset;
+        __raw_writel(dat, base + 0x04);
+
+        con = __raw_readl(base + 0x00);
+        con &= ~(3 << (offset * 2));
+        con |= 1 << (offset * 2);
+
+        __raw_writel(con, base + 0x00);
+        __raw_writel(dat, base + 0x04);
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+static void s3c_gpiolib_set(struct gpio_chip *chip,
+                            unsigned offset, int value)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long dat;
+
+        local_irq_save(flags);
+
+        dat = __raw_readl(base + 0x04);
+        dat &= ~(1 << offset);
+        if (value)
+                dat |= 1 << offset;
+        __raw_writel(dat, base + 0x04);
+
+        local_irq_restore(flags);
+}
+
+static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        unsigned long val;
+
+        val = __raw_readl(ourchip->base + 0x04);
+        val >>= offset;
+        val &= 1;
+
+        return val;
+}
+
+__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
+{
+        struct gpio_chip *gc = &chip->chip;
+        int ret;
+
+        BUG_ON(!chip->base);
+        BUG_ON(!gc->label);
+        BUG_ON(!gc->ngpio);
+
+        if (!gc->direction_input)
+                gc->direction_input = s3c_gpiolib_input;
+        if (!gc->direction_output)
+                gc->direction_output = s3c_gpiolib_output;
+        if (!gc->set)
+                gc->set = s3c_gpiolib_set;
+        if (!gc->get)
+                gc->get = s3c_gpiolib_get;
+
+#ifdef CONFIG_PM
+        if (chip->pm != NULL) {
+                if (!chip->pm->save || !chip->pm->resume)
+                        printk(KERN_ERR "gpio: %s has missing PM functions\n",
+                               gc->label);
+        } else
+                printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
+#endif
+
+        /* gpiochip_add() prints own failure message on error. */
+        ret = gpiochip_add(gc);
+        if (ret >= 0)
+                s3c_gpiolib_track(chip);
+}
diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c
new file mode 100644
index 000000000000..8a8ba8bc1d96
--- /dev/null
+++ b/arch/arm/plat-samsung/gpiolib.c
@@ -0,0 +1,199 @@
+/* arch/arm/plat-samsung/gpiolib.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * SAMSUNG - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <mach/gpio.h>
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+#ifndef DEBUG_GPIO
+#define gpio_dbg(x...) do { } while (0)
+#else
+#define gpio_dbg(x...) printk(KERN_DEBUG x)
+#endif
+
+/* The samsung_gpiolib_4bit routines are to control the gpio banks where
+ * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
+ * following example:
+ *
+ * base + 0x00: Control register, 4 bits per gpio
+ *              gpio n: 4 bits starting at (4*n)
+ *              0000 = input, 0001 = output, others mean special-function
+ * base + 0x04: Data register, 1 bit per gpio
+ *              bit n: data bit n
+ *
+ * Note, since the data register is one bit per gpio and is at base + 0x4
+ * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
+ * the output.
+*/
+
+static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
+                                      unsigned int offset)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long con;
+
+        con = __raw_readl(base + GPIOCON_OFF);
+        con &= ~(0xf << con_4bit_shift(offset));
+        __raw_writel(con, base + GPIOCON_OFF);
+
+        gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
+
+        return 0;
+}
+
+static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
+                                       unsigned int offset, int value)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long con;
+        unsigned long dat;
+
+        con = __raw_readl(base + GPIOCON_OFF);
+        con &= ~(0xf << con_4bit_shift(offset));
+        con |= 0x1 << con_4bit_shift(offset);
+
+        dat = __raw_readl(base + GPIODAT_OFF);
+
+        if (value)
+                dat |= 1 << offset;
+        else
+                dat &= ~(1 << offset);
+
+        __raw_writel(dat, base + GPIODAT_OFF);
+        __raw_writel(con, base + GPIOCON_OFF);
+        __raw_writel(dat, base + GPIODAT_OFF);
+
+        gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
+
+        return 0;
+}
+
+/* The next set of routines are for the case where the GPIO configuration
+ * registers are 4 bits per GPIO but there is more than one register (the
+ * bank has more than 8 GPIOs.
+ *
+ * This case is the similar to the 4 bit case, but the registers are as
+ * follows:
+ *
+ * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
+ *              gpio n: 4 bits starting at (4*n)
+ *              0000 = input, 0001 = output, others mean special-function
+ * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
+ *              gpio n: 4 bits starting at (4*n)
+ *              0000 = input, 0001 = output, others mean special-function
+ * base + 0x08: Data register, 1 bit per gpio
+ *              bit n: data bit n
+ *
+ * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
+ * store the 'base + 0x4' address so that these routines see the data
+ * register at ourchip->base + 0x04.
+ */
+
+static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
+                                       unsigned int offset)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        void __iomem *regcon = base;
+        unsigned long con;
+
+        if (offset > 7)
+                offset -= 8;
+        else
+                regcon -= 4;
+
+        con = __raw_readl(regcon);
+        con &= ~(0xf << con_4bit_shift(offset));
+        __raw_writel(con, regcon);
+
+        gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
+
+        return 0;
+}
+
+static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
+                                        unsigned int offset, int value)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        void __iomem *regcon = base;
+        unsigned long con;
+        unsigned long dat;
+        unsigned con_offset = offset;
+
+        if (con_offset > 7)
+                con_offset -= 8;
+        else
+                regcon -= 4;
+
+        con = __raw_readl(regcon);
+        con &= ~(0xf << con_4bit_shift(con_offset));
+        con |= 0x1 << con_4bit_shift(con_offset);
+
+        dat = __raw_readl(base + GPIODAT_OFF);
+
+        if (value)
+                dat |= 1 << offset;
+        else
+                dat &= ~(1 << offset);
+
+        __raw_writel(dat, base + GPIODAT_OFF);
+        __raw_writel(con, regcon);
+        __raw_writel(dat, base + GPIODAT_OFF);
+
+        gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
+
+        return 0;
+}
+
+void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
+{
+        chip->chip.direction_input = samsung_gpiolib_4bit_input;
+        chip->chip.direction_output = samsung_gpiolib_4bit_output;
+        chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+}
+
+void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
+{
+        chip->chip.direction_input = samsung_gpiolib_4bit2_input;
+        chip->chip.direction_output = samsung_gpiolib_4bit2_output;
+        chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+}
+
+void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
+                                           int nr_chips)
+{
+        for (; nr_chips > 0; nr_chips--, chip++) {
+                samsung_gpiolib_add_4bit(chip);
+                s3c_gpiolib_add(chip);
+        }
+}
+
+void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
+                                            int nr_chips)
+{
+        for (; nr_chips > 0; nr_chips--, chip++) {
+                samsung_gpiolib_add_4bit2(chip);
+                s3c_gpiolib_add(chip);
+        }
+}
diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h
new file mode 100644
index 000000000000..e8382c7be10b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/adc.h
@@ -0,0 +1,35 @@
+/* arch/arm/plat-samsung/include/plat/adc.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simnte.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C ADC driver information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_ADC_H
+#define __ASM_PLAT_ADC_H __FILE__
+
+struct s3c_adc_client;
+
+extern int s3c_adc_start(struct s3c_adc_client *client,
+                         unsigned int channel, unsigned int nr_samples);
+
+extern int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch);
+
+extern struct s3c_adc_client *
+        s3c_adc_register(struct platform_device *pdev,
+                         void (*select)(struct s3c_adc_client *client,
+                                        unsigned selected),
+                         void (*conv)(struct s3c_adc_client *client,
+                                      unsigned d0, unsigned d1,
+                                      unsigned *samples_left),
+                         unsigned int is_ts);
+
+extern void s3c_adc_release(struct s3c_adc_client *client);
+
+#endif /* __ASM_PLAT_ADC_H */
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h
new file mode 100644
index 000000000000..e32f9edfd4b7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/audio.h
@@ -0,0 +1,25 @@
+/* arch/arm/plat-samsung/include/plat/audio.h
+ *
+ * Copyright (c) 2009 Samsung Electronics Co. Ltd
+ * Author: Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* The machine init code calls s3c*_ac97_setup_gpio with
+ * one of these defines in order to select appropriate bank
+ * of GPIO for AC97 pins
+ */
+#define S3C64XX_AC97_GPD  0
+#define S3C64XX_AC97_GPE  1
+extern void s3c64xx_ac97_setup_gpio(int);
+
+/**
+ * struct s3c_audio_pdata - common platform data for audio device drivers
+ * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
+ */
+struct s3c_audio_pdata {
+        int (*cfg_gpio)(struct platform_device *);
+};
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
new file mode 100644
index 000000000000..50a8ca7c3760
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
@@ -0,0 +1,83 @@
+/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h
+ *
+ * Parts taken from arch/arm/plat-s3c64xx/clock.c
+ *      Copyright 2008 Openmoko, Inc.
+ *      Copyright 2008 Simtec Electronics
+ *              Ben Dooks <ben@simtec.co.uk>
+ *              http://armlinux.simtec.co.uk/
+ *
+ * Copyright 2009 Ben Dooks <ben-linux@fluff.org>
+ * Copyright 2009 Harald Welte
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/**
+ * struct clksrc_sources - list of sources for a given clock
+ * @sources: array of pointers to clocks
+ * @nr_sources: The size of @sources
+ */
+struct clksrc_sources {
+        unsigned int    nr_sources;
+        struct clk      **sources;
+};
+
+/**
+ * struct clksrc_reg - register definition for clock control bits
+ * @reg: pointer to the register in virtual memory.
+ * @shift: the shift in bits to where the bitfield is.
+ * @size: the size in bits of the bitfield.
+ *
+ * This specifies the size and position of the bits we are interested
+ * in within the register specified by @reg.
+ */
+struct clksrc_reg {
+        void __iomem            *reg;
+        unsigned short          shift;
+        unsigned short          size;
+};
+
+/**
+ * struct clksrc_clk - class of clock for newer style samsung devices.
+ * @clk: the standard clock representation
+ * @sources: the sources for this clock
+ * @reg_src: the register definition for selecting the clock's source
+ * @reg_div: the register definition for the clock's output divisor
+ *
+ * This clock implements the features required by the newer SoCs where
+ * the standard clock block provides an input mux and a post-mux divisor
+ * to provide the periperhal's clock.
+ *
+ * The array of @sources provides the mapping of mux position to the
+ * clock, and @reg_src shows the code where to modify to change the mux
+ * position. The @reg_div defines how to change the divider settings on
+ * the output.
+ */
+struct clksrc_clk {
+        struct clk              clk;
+        struct clksrc_sources   *sources;
+
+        struct clksrc_reg       reg_src;
+        struct clksrc_reg       reg_div;
+};
+
+/**
+ * s3c_set_clksrc() - setup the clock from the register settings
+ * @clk: The clock to setup.
+ * @announce: true to announce the setting to printk().
+ *
+ * Setup the clock from the current register settings, for when the
+ * kernel boots or if it is resuming from a possibly unknown state.
+ */
+extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce);
+
+/**
+ * s3c_register_clksrc() register clocks from an array of clksrc clocks
+ * @srcs: The array of clocks to register
+ * @size: The size of the @srcs array.
+ *
+ * Initialise and register the array of clocks described by @srcs.
+ */
+extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size);
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
new file mode 100644
index 000000000000..60b62692ac7a
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -0,0 +1,115 @@
+/* linux/arch/arm/plat-s3c/include/plat/clock.h
+ *
+ * Copyright (c) 2004-2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/SWLINUX/
+ *      Written by Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/spinlock.h>
+
+struct clk;
+
+/**
+ * struct clk_ops - standard clock operations
+ * @set_rate: set the clock rate, see clk_set_rate().
+ * @get_rate: get the clock rate, see clk_get_rate().
+ * @round_rate: round a given clock rate, see clk_round_rate().
+ * @set_parent: set the clock's parent, see clk_set_parent().
+ *
+ * Group the common clock implementations together so that we
+ * don't have to keep setting the same fiels again. We leave
+ * enable in struct clk.
+ *
+ * Adding an extra layer of indirection into the process should
+ * not be a problem as it is unlikely these operations are going
+ * to need to be called quickly.
+ */
+struct clk_ops {
+        int                 (*set_rate)(struct clk *c, unsigned long rate);
+        unsigned long       (*get_rate)(struct clk *c);
+        unsigned long       (*round_rate)(struct clk *c, unsigned long rate);
+        int                 (*set_parent)(struct clk *c, struct clk *parent);
+};
+
+struct clk {
+        struct list_head      list;
+        struct module        *owner;
+        struct clk           *parent;
+        const char           *name;
+        int                   id;
+        int                   usage;
+        unsigned long         rate;
+        unsigned long         ctrlbit;
+
+        struct clk_ops          *ops;
+        int                 (*enable)(struct clk *, int enable);
+};
+
+/* other clocks which may be registered by board support */
+
+extern struct clk s3c24xx_dclk0;
+extern struct clk s3c24xx_dclk1;
+extern struct clk s3c24xx_clkout0;
+extern struct clk s3c24xx_clkout1;
+extern struct clk s3c24xx_uclk;
+
+extern struct clk clk_usb_bus;
+
+/* core clock support */
+
+extern struct clk clk_f;
+extern struct clk clk_h;
+extern struct clk clk_p;
+extern struct clk clk_mpll;
+extern struct clk clk_upll;
+extern struct clk clk_epll;
+extern struct clk clk_xtal;
+extern struct clk clk_ext;
+
+/* S3C64XX specific clocks */
+extern struct clk clk_h2;
+extern struct clk clk_27m;
+extern struct clk clk_48m;
+
+extern int clk_default_setrate(struct clk *clk, unsigned long rate);
+extern struct clk_ops clk_ops_def_setrate;
+
+/* exports for arch/arm/mach-s3c2410
+ *
+ * Please DO NOT use these outside of arch/arm/mach-s3c2410
+*/
+
+extern spinlock_t clocks_lock;
+
+extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
+
+extern int s3c24xx_register_clock(struct clk *clk);
+extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
+
+extern void s3c_register_clocks(struct clk *clk, int nr_clks);
+
+extern int s3c24xx_register_baseclocks(unsigned long xtal);
+
+extern void s5p_register_clocks(unsigned long xtal_freq);
+
+extern void s3c24xx_setup_clocks(unsigned long fclk,
+                                 unsigned long hclk,
+                                 unsigned long pclk);
+
+extern void s3c2410_setup_clocks(void);
+extern void s3c2412_setup_clocks(void);
+extern void s3c244x_setup_clocks(void);
+extern void s3c2443_setup_clocks(void);
+
+/* S3C64XX specific functions and clocks */
+
+extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
+
+/* Init for pwm clock code */
+
+extern void s3c_pwmclk_init(void);
+
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h
new file mode 100644
index 000000000000..80c4a809c721
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq.h
@@ -0,0 +1,145 @@
+/* arch/arm/plat-samsung/include/plat/cpu-freq.h
+ *
+ * Copyright (c) 2006-2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C CPU frequency scaling support - driver and board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/cpufreq.h>
+
+struct s3c_cpufreq_info;
+struct s3c_cpufreq_board;
+struct s3c_iotimings;
+
+/**
+ * struct s3c_freq - frequency information (mainly for core drivers)
+ * @fclk: The FCLK frequency in Hz.
+ * @armclk: The ARMCLK frequency in Hz.
+ * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
+ * @hclk: The HCLK frequency in Hz.
+ * @pclk: The PCLK frequency in Hz.
+ *
+ * This contains the frequency information about the current configuration
+ * mainly for the core drivers to ensure we do not end up passing about
+ * a large number of parameters.
+ *
+ * The @hclk_tns field is a useful cache for the parts of the drivers that
+ * need to calculate IO timings and suchlike.
+ */
+struct s3c_freq {
+        unsigned long   fclk;
+        unsigned long   armclk;
+        unsigned long   hclk_tns;       /* in 10ths of ns */
+        unsigned long   hclk;
+        unsigned long   pclk;
+};
+
+/**
+ * struct s3c_cpufreq_freqs - s3c cpufreq notification information.
+ * @freqs: The cpufreq setting information.
+ * @old: The old clock settings.
+ * @new: The new clock settings.
+ * @pll_changing: Set if the PLL is changing.
+ *
+ * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the
+ * notification can use this information that is not provided by just
+ * having the core frequency alone.
+ *
+ * The pll_changing flag is used to indicate if the PLL itself is
+ * being set during this change. This is important as the clocks
+ * will temporarily be set to the XTAL clock during this time, so
+ * drivers may want to close down their output during this time.
+ *
+ * Note, this is not being used by any current drivers and therefore
+ * may be removed in the future.
+ */
+struct s3c_cpufreq_freqs {
+        struct cpufreq_freqs    freqs;
+        struct s3c_freq         old;
+        struct s3c_freq         new;
+
+        unsigned int            pll_changing:1;
+};
+
+#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
+
+/**
+ * struct s3c_clkdivs - clock divisor information
+ * @p_divisor: Divisor from FCLK to PCLK.
+ * @h_divisor: Divisor from FCLK to HCLK.
+ * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
+ * @dvs: Non-zero if using DVS mode for ARMCLK.
+ *
+ * Divisor settings for the core clocks.
+ */
+struct s3c_clkdivs {
+        int             p_divisor;
+        int             h_divisor;
+        int             arm_divisor;
+        unsigned char   dvs;
+};
+
+#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
+
+/**
+ * struct s3c_pllval - PLL value entry.
+ * @freq: The frequency for this entry in Hz.
+ * @pll_reg: The PLL register setting for this PLL value.
+ */
+struct s3c_pllval {
+        unsigned long           freq;
+        unsigned long           pll_reg;
+};
+
+/**
+ * struct s3c_cpufreq_board - per-board cpu frequency informatin
+ * @refresh: The SDRAM refresh period in nanoseconds.
+ * @auto_io: Set if the IO timing settings should be generated from the
+ *      initialisation time hardware registers.
+ * @need_io: Set if the board has external IO on any of the chipselect
+ *      lines that will require the hardware timing registers to be
+ *      updated on a clock change.
+ * @max: The maxium frequency limits for the system. Any field that
+ *      is left at zero will use the CPU's settings.
+ *
+ * This contains the board specific settings that affect how the CPU
+ * drivers chose settings. These include the memory refresh and IO
+ * timing information.
+ *
+ * Registration depends on the driver being used, the ARMCLK only
+ * implementation does not currently need this but the older style
+ * driver requires this to be available.
+ */
+struct s3c_cpufreq_board {
+        unsigned int    refresh;
+        unsigned int    auto_io:1;      /* automatically init io timings. */
+        unsigned int    need_io:1;      /* set if needs io timing support. */
+
+        /* any non-zero field in here is taken as an upper limit. */
+        struct s3c_freq max;    /* frequency limits */
+};
+
+/* Things depending on frequency scaling. */
+#ifdef CONFIG_CPU_FREQ_S3C
+#define __init_or_cpufreq
+#else
+#define __init_or_cpufreq __init
+#endif
+
+/* Board functions */
+
+#ifdef CONFIG_CPU_FREQ_S3C
+extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
+#else
+
+static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
+{
+        return 0;
+}
+#endif  /* CONFIG_CPU_FREQ_S3C */
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
new file mode 100644
index 000000000000..d316b4a579f4
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -0,0 +1,84 @@
+/* linux/arch/arm/plat-samsung/include/plat/cpu.h
+ *
+ * Copyright (c) 2004-2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for S3C24XX CPU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* todo - fix when rmk changes iodescs to use `void __iomem *` */
+
+#ifndef __SAMSUNG_PLAT_CPU_H
+#define __SAMSUNG_PLAT_CPU_H
+
+#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
+
+/* forward declaration */
+struct s3c24xx_uart_resources;
+struct platform_device;
+struct s3c2410_uartcfg;
+struct map_desc;
+
+/* per-cpu initialisation function table. */
+
+struct cpu_table {
+        unsigned long   idcode;
+        unsigned long   idmask;
+        void            (*map_io)(void);
+        void            (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
+        void            (*init_clocks)(int xtal);
+        int             (*init)(void);
+        const char      *name;
+};
+
+extern void s3c_init_cpu(unsigned long idcode,
+                         struct cpu_table *cpus, unsigned int cputab_size);
+
+/* core initialisation functions */
+
+extern void s3c24xx_init_irq(void);
+extern void s3c64xx_init_irq(u32 vic0, u32 vic1);
+extern void s5p_init_irq(u32 *vic, u32 num_vic);
+
+extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
+extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
+extern void s5p_init_io(struct map_desc *mach_desc,
+                        int size, void __iomem *cpuid_addr);
+
+extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+extern void s3c24xx_init_clocks(int xtal);
+
+extern void s3c24xx_init_uartdevs(char *name,
+                                  struct s3c24xx_uart_resources *res,
+                                  struct s3c2410_uartcfg *cfg, int no);
+
+/* timer for 2410/2440 */
+
+struct sys_timer;
+extern struct sys_timer s3c24xx_timer;
+
+/* system device classes */
+
+extern struct sysdev_class s3c2410_sysclass;
+extern struct sysdev_class s3c2410a_sysclass;
+extern struct sysdev_class s3c2412_sysclass;
+extern struct sysdev_class s3c2440_sysclass;
+extern struct sysdev_class s3c2442_sysclass;
+extern struct sysdev_class s3c2443_sysclass;
+extern struct sysdev_class s3c6410_sysclass;
+extern struct sysdev_class s3c64xx_sysclass;
+
+extern void (*s5pc1xx_idle)(void);
+
+#endif
diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S
new file mode 100644
index 000000000000..dc6efd90e8ff
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/debug-macro.S
@@ -0,0 +1,87 @@
+/* arch/arm/plat-samsung/include/plat/debug-macro.S
+ *
+ * Copyright 2005, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <plat/regs-serial.h>
+
+/* The S5PV210/S5PC110 and S5P6442 implementations are as belows. */
+
+        .macro fifo_level_s5pv210 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                and     \rd, \rd, #S5PV210_UFSTAT_TXMASK
+        .endm
+
+        .macro  fifo_full_s5pv210 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                tst     \rd, #S5PV210_UFSTAT_TXFULL
+        .endm
+
+/* The S3C2440 implementations are used by default as they are the
+ * most widely re-used */
+
+        .macro fifo_level_s3c2440 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                and     \rd, \rd, #S3C2440_UFSTAT_TXMASK
+        .endm
+
+#ifndef fifo_level
+#define fifo_level fifo_level_s3c2440
+#endif
+
+        .macro  fifo_full_s3c2440 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                tst     \rd, #S3C2440_UFSTAT_TXFULL
+        .endm
+
+#ifndef fifo_full
+#define fifo_full fifo_full_s3c2440
+#endif
+
+        .macro  senduart,rd,rx
+                strb    \rd, [\rx, # S3C2410_UTXH ]
+        .endm
+
+        .macro  busyuart, rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
+                beq     1001f                           @
+                @ FIFO enabled...
+1003:
+                fifo_full \rd, \rx
+                bne     1003b
+                b       1002f
+
+1001:
+                @ busy waiting for non fifo
+                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                tst     \rd, #S3C2410_UTRSTAT_TXFE
+                beq     1001b
+
+1002:           @ exit busyuart
+        .endm
+
+        .macro  waituart,rd,rx
+                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
+                beq     1001f                           @
+                @ FIFO enabled...
+1003:
+                fifo_level \rd, \rx
+                teq     \rd, #0
+                bne     1003b
+                b       1002f
+1001:
+                @ idle waiting for non fifo
+                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                tst     \rd, #S3C2410_UTRSTAT_TXFE
+                beq     1001b
+
+1002:           @ exit busyuart
+        .endm
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
new file mode 100644
index 000000000000..796d24258313
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -0,0 +1,74 @@
+/* arch/arm/plat-samsung/include/plat/devs.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for s3c2410 standard platform devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/platform_device.h>
+
+struct s3c24xx_uart_resources {
+        struct resource         *resources;
+        unsigned long            nr_resources;
+};
+
+extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
+extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
+extern struct s3c24xx_uart_resources s5p_uart_resources[];
+
+extern struct platform_device *s3c24xx_uart_devs[];
+extern struct platform_device *s3c24xx_uart_src[];
+
+extern struct platform_device s3c_device_timer[];
+
+extern struct platform_device s3c64xx_device_iis0;
+extern struct platform_device s3c64xx_device_iis1;
+extern struct platform_device s3c64xx_device_iisv4;
+
+extern struct platform_device s3c64xx_device_spi0;
+extern struct platform_device s3c64xx_device_spi1;
+
+extern struct platform_device s3c64xx_device_pcm0;
+extern struct platform_device s3c64xx_device_pcm1;
+
+extern struct platform_device s3c64xx_device_ac97;
+
+extern struct platform_device s3c_device_ts;
+
+extern struct platform_device s3c_device_fb;
+extern struct platform_device s3c_device_ohci;
+extern struct platform_device s3c_device_lcd;
+extern struct platform_device s3c_device_wdt;
+extern struct platform_device s3c_device_i2c0;
+extern struct platform_device s3c_device_i2c1;
+extern struct platform_device s3c_device_rtc;
+extern struct platform_device s3c_device_adc;
+extern struct platform_device s3c_device_sdi;
+extern struct platform_device s3c_device_iis;
+extern struct platform_device s3c_device_hwmon;
+extern struct platform_device s3c_device_hsmmc0;
+extern struct platform_device s3c_device_hsmmc1;
+extern struct platform_device s3c_device_hsmmc2;
+
+extern struct platform_device s3c_device_spi0;
+extern struct platform_device s3c_device_spi1;
+
+extern struct platform_device s3c_device_hwmon;
+
+extern struct platform_device s3c_device_nand;
+
+extern struct platform_device s3c_device_usbgadget;
+extern struct platform_device s3c_device_usb_hsotg;
+
+/* s3c2440 specific devices */
+
+#ifdef CONFIG_CPU_S3C2440
+
+extern struct platform_device s3c_device_camif;
+extern struct platform_device s3c_device_ac97;
+
+#endif
diff --git a/arch/arm/plat-samsung/include/plat/dma-core.h b/arch/arm/plat-samsung/include/plat/dma-core.h
new file mode 100644
index 000000000000..32ff2a92cb3c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/dma-core.h
@@ -0,0 +1,22 @@
+/* arch/arm/plat-s3c/include/plat/dma.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung S3C DMA core support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
+
+extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
+
+/* the currently allocated channel information */
+extern struct s3c2410_dma_chan s3c2410_chans[];
+
+
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
new file mode 100644
index 000000000000..336d5ac02035
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
@@ -0,0 +1,84 @@
+/* linux/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+ *
+ * Copyright (C) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C24XX DMA support - per SoC functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <plat/dma-core.h>
+
+extern struct sysdev_class dma_sysclass;
+extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
+
+#define DMA_CH_VALID            (1<<31)
+#define DMA_CH_NEVER            (1<<30)
+
+struct s3c24xx_dma_addr {
+        unsigned long           from;
+        unsigned long           to;
+};
+
+/* struct s3c24xx_dma_map
+ *
+ * this holds the mapping information for the channel selected
+ * to be connected to the specified device
+*/
+
+struct s3c24xx_dma_map {
+        const char              *name;
+        struct s3c24xx_dma_addr  hw_addr;
+
+        unsigned long            channels[S3C_DMA_CHANNELS];
+        unsigned long            channels_rx[S3C_DMA_CHANNELS];
+};
+
+struct s3c24xx_dma_selection {
+        struct s3c24xx_dma_map  *map;
+        unsigned long            map_size;
+        unsigned long            dcon_mask;
+
+        void    (*select)(struct s3c2410_dma_chan *chan,
+                          struct s3c24xx_dma_map *map);
+
+        void    (*direction)(struct s3c2410_dma_chan *chan,
+                             struct s3c24xx_dma_map *map,
+                             enum s3c2410_dmasrc dir);
+};
+
+extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
+
+/* struct s3c24xx_dma_order_ch
+ *
+ * channel map for one of the `enum dma_ch` dma channels. the list
+ * entry contains a set of low-level channel numbers, orred with
+ * DMA_CH_VALID, which are checked in the order in the array.
+*/
+
+struct s3c24xx_dma_order_ch {
+        unsigned int    list[S3C_DMA_CHANNELS]; /* list of channels */
+        unsigned int    flags;                          /* flags */
+};
+
+/* struct s3c24xx_dma_order
+ *
+ * information provided by either the core or the board to give the
+ * dma system a hint on how to allocate channels
+*/
+
+struct s3c24xx_dma_order {
+        struct s3c24xx_dma_order_ch     channels[DMACH_MAX];
+};
+
+extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
+
+/* DMA init code, called from the cpu support code */
+
+extern int s3c2410_dma_init(void);
+
+extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
+                            unsigned int stride);
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h
new file mode 100644
index 000000000000..7584d751ed51
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/dma.h
@@ -0,0 +1,127 @@
+/* arch/arm/plat-samsung/include/plat/dma.h
+ *
+ * Copyright (C) 2003-2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C DMA support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+enum s3c2410_dma_buffresult {
+        S3C2410_RES_OK,
+        S3C2410_RES_ERR,
+        S3C2410_RES_ABORT
+};
+
+enum s3c2410_dmasrc {
+        S3C2410_DMASRC_HW,              /* source is memory */
+        S3C2410_DMASRC_MEM              /* source is hardware */
+};
+
+/* enum s3c2410_chan_op
+ *
+ * operation codes passed to the DMA code by the user, and also used
+ * to inform the current channel owner of any changes to the system state
+*/
+
+enum s3c2410_chan_op {
+        S3C2410_DMAOP_START,
+        S3C2410_DMAOP_STOP,
+        S3C2410_DMAOP_PAUSE,
+        S3C2410_DMAOP_RESUME,
+        S3C2410_DMAOP_FLUSH,
+        S3C2410_DMAOP_TIMEOUT,          /* internal signal to handler */
+        S3C2410_DMAOP_STARTED,          /* indicate channel started */
+};
+
+struct s3c2410_dma_client {
+        char                *name;
+};
+
+struct s3c2410_dma_chan;
+
+/* s3c2410_dma_cbfn_t
+ *
+ * buffer callback routine type
+*/
+
+typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
+                                   void *buf, int size,
+                                   enum s3c2410_dma_buffresult result);
+
+typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
+                                   enum s3c2410_chan_op );
+
+
+
+/* s3c2410_dma_request
+ *
+ * request a dma channel exclusivley
+*/
+
+extern int s3c2410_dma_request(unsigned int channel,
+                               struct s3c2410_dma_client *, void *dev);
+
+
+/* s3c2410_dma_ctrl
+ *
+ * change the state of the dma channel
+*/
+
+extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
+
+/* s3c2410_dma_setflags
+ *
+ * set the channel's flags to a given state
+*/
+
+extern int s3c2410_dma_setflags(unsigned int channel,
+                                unsigned int flags);
+
+/* s3c2410_dma_free
+ *
+ * free the dma channel (will also abort any outstanding operations)
+*/
+
+extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
+
+/* s3c2410_dma_enqueue
+ *
+ * place the given buffer onto the queue of operations for the channel.
+ * The buffer must be allocated from dma coherent memory, or the Dcache/WB
+ * drained before the buffer is given to the DMA system.
+*/
+
+extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
+                               dma_addr_t data, int size);
+
+/* s3c2410_dma_config
+ *
+ * configure the dma channel
+*/
+
+extern int s3c2410_dma_config(unsigned int channel, int xferunit);
+
+/* s3c2410_dma_devconfig
+ *
+ * configure the device we're talking to
+*/
+
+extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
+                                 unsigned long devaddr);
+
+/* s3c2410_dma_getposition
+ *
+ * get the position that the dma transfer is currently at
+*/
+
+extern int s3c2410_dma_getposition(unsigned int channel,
+                                   dma_addr_t *src, dma_addr_t *dest);
+
+extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
+extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
+
+
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
new file mode 100644
index 000000000000..ffc01a76b7ce
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -0,0 +1,80 @@
+/* arch/arm/plat-samsung/include/plat/fb.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - FB platform data definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C_FB_H
+#define __PLAT_S3C_FB_H __FILE__
+
+/**
+ * struct s3c_fb_pd_win - per window setup data
+ * @win_mode: The display parameters to initialise (not for window 0)
+ * @virtual_x: The virtual X size.
+ * @virtual_y: The virtual Y size.
+ */
+struct s3c_fb_pd_win {
+        struct fb_videomode     win_mode;
+
+        unsigned short          default_bpp;
+        unsigned short          max_bpp;
+        unsigned short          virtual_x;
+        unsigned short          virtual_y;
+};
+
+/**
+ * struct s3c_fb_platdata -  S3C driver platform specific information
+ * @setup_gpio: Setup the external GPIO pins to the right state to transfer
+ *              the data from the display system to the connected display
+ *              device.
+ * @vidcon0: The base vidcon0 values to control the panel data format.
+ * @vidcon1: The base vidcon1 values to control the panel data output.
+ * @win: The setup data for each hardware window, or NULL for unused.
+ * @display_mode: The LCD output display mode.
+ *
+ * The platform data supplies the video driver with all the information
+ * it requires to work with the display(s) attached to the machine. It
+ * controls the initial mode, the number of display windows (0 is always
+ * the base framebuffer) that are initialised etc.
+ *
+ */
+struct s3c_fb_platdata {
+        void    (*setup_gpio)(void);
+
+        struct s3c_fb_pd_win    *win[S3C_FB_MAX_WIN];
+
+        u32                      vidcon0;
+        u32                      vidcon1;
+};
+
+/**
+ * s3c_fb_set_platdata() - Setup the FB device with platform data.
+ * @pd: The platform data to set. The data is copied from the passed structure
+ *      so the machine data can mark the data __initdata so that any unused
+ *      machines will end up dumping their data at runtime.
+ */
+extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
+
+/**
+ * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
+ */
+extern void s3c64xx_fb_gpio_setup_24bpp(void);
+
+/**
+ * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
+ */
+extern void s5pc100_fb_gpio_setup_24bpp(void);
+
+#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
new file mode 100644
index 000000000000..dda19da037ad
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -0,0 +1,176 @@
+/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - GPIO pin configuration helper definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* This is meant for core cpu support, machine or other driver files
+ * should not be including this header.
+ */
+
+#ifndef __PLAT_GPIO_CFG_HELPERS_H
+#define __PLAT_GPIO_CFG_HELPERS_H __FILE__
+
+/* As a note, all gpio configuration functions are entered exclusively, either
+ * with the relevant lock held or the system prevented from doing anything else
+ * by disabling interrupts.
+*/
+
+static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
+                                     unsigned int off, unsigned int config)
+{
+        return (chip->config->set_config)(chip, off, config);
+}
+
+static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
+                                      unsigned int off, s3c_gpio_pull_t pull)
+{
+        return (chip->config->set_pull)(chip, off, pull);
+}
+
+/**
+ * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @cfg: The configuration value to set.
+ *
+ * This helper deal with the GPIO cases where the control register
+ * has two bits of configuration per gpio, which have the following
+ * functions:
+ *      00 = input
+ *      01 = output
+ *      1x = special function
+*/
+extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
+                                   unsigned int off, unsigned int cfg);
+
+/**
+ * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @cfg: The configuration value to set.
+ *
+ * This helper deal with the GPIO cases where the control register
+ * has one bit of configuration for the gpio, where setting the bit
+ * means the pin is in special function mode and unset means output.
+*/
+extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
+                                     unsigned int off, unsigned int cfg);
+
+/**
+ * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @cfg: The configuration value to set.
+ *
+ * This helper deal with the GPIO cases where the control register has 4 bits
+ * of control per GPIO, generally in the form of:
+ *      0000 = Input
+ *      0001 = Output
+ *      others = Special functions (dependant on bank)
+ *
+ * Note, since the code to deal with the case where there are two control
+ * registers instead of one, we do not have a separate set of functions for
+ * each case.
+*/
+extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
+                                        unsigned int off, unsigned int cfg);
+
+
+/* Pull-{up,down} resistor controls.
+ *
+ * S3C2410,S3C2440,S3C24A0 = Pull-UP,
+ * S3C2412,S3C2413 = Pull-Down
+ * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
+ * S3C2443 = Pull-Both [not same as S3C6400]
+ */
+
+/**
+ * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @param: pull: The pull mode being requested.
+ *
+ * This is a helper function for the case where we have GPIOs with one
+ * bit configuring the presence of a pull-up resistor.
+ */
+extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
+                                unsigned int off, s3c_gpio_pull_t pull);
+
+/**
+ * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
+ * @chip: The gpio chip that is being configured
+ * @off: The offset for the GPIO being configured
+ * @param: pull: The pull mode being requested
+ *
+ * This is a helper function for the case where we have GPIOs with one
+ * bit configuring the presence of a pull-down resistor.
+ */
+extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
+                                  unsigned int off, s3c_gpio_pull_t pull);
+
+/**
+ * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @param: pull: The pull mode being requested.
+ *
+ * This is a helper function for the case where we have GPIOs with two
+ * bits configuring the presence of a pull resistor, in the following
+ * order:
+ *      00 = No pull resistor connected
+ *      01 = Pull-up resistor connected
+ *      10 = Pull-down resistor connected
+ */
+extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
+                                   unsigned int off, s3c_gpio_pull_t pull);
+
+
+/**
+ * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
+ * @chip: The gpio chip that the GPIO pin belongs to
+ * @off: The offset to the pin to get the configuration of.
+ *
+ * This helper function reads the state of the pull-{up,down} resistor for the
+ * given GPIO in the same case as s3c_gpio_setpull_upown.
+*/
+extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
+                                               unsigned int off);
+
+/**
+ * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @param: pull: The pull mode being requested.
+ *
+ * This is a helper function for the case where we have GPIOs with two
+ * bits configuring the presence of a pull resistor, in the following
+ * order:
+ *      00 = Pull-up resistor connected
+ *      10 = Pull-down resistor connected
+ *      x1 = No pull up resistor
+ */
+extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
+                                    unsigned int off, s3c_gpio_pull_t pull);
+
+/**
+ * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
+ * @chip: The gpio chip that the GPIO pin belongs to.
+ * @off: The offset to the pin to get the configuration of.
+ *
+ * This helper function reads the state of the pull-{up,down} resistor for the
+ * given GPIO in the same case as s3c_gpio_setpull_upown.
+*/
+extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
+                                                unsigned int off);
+
+#endif /* __PLAT_GPIO_CFG_HELPERS_H */
+
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
new file mode 100644
index 000000000000..29cd6a86cade
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -0,0 +1,110 @@
+/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - GPIO pin configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* This file contains the necessary definitions to get the basic gpio
+ * pin configuration done such as setting a pin to input or output or
+ * changing the pull-{up,down} configurations.
+ */
+
+/* Note, this interface is being added to the s3c64xx arch first and will
+ * be added to the s3c24xx systems later.
+ */
+
+#ifndef __PLAT_GPIO_CFG_H
+#define __PLAT_GPIO_CFG_H __FILE__
+
+typedef unsigned int __bitwise__ s3c_gpio_pull_t;
+
+/* forward declaration if gpio-core.h hasn't been included */
+struct s3c_gpio_chip;
+
+/**
+ * struct s3c_gpio_cfg GPIO configuration
+ * @cfg_eint: Configuration setting when used for external interrupt source
+ * @get_pull: Read the current pull configuration for the GPIO
+ * @set_pull: Set the current pull configuraiton for the GPIO
+ * @set_config: Set the current configuration for the GPIO
+ * @get_config: Read the current configuration for the GPIO
+ *
+ * Each chip can have more than one type of GPIO bank available and some
+ * have different capabilites even when they have the same control register
+ * layouts. Provide an point to vector control routine and provide any
+ * per-bank configuration information that other systems such as the
+ * external interrupt code will need.
+ */
+struct s3c_gpio_cfg {
+        unsigned int    cfg_eint;
+
+        s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
+        int             (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
+                                    s3c_gpio_pull_t pull);
+
+        unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
+        int      (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
+                               unsigned config);
+};
+
+#define S3C_GPIO_SPECIAL_MARK   (0xfffffff0)
+#define S3C_GPIO_SPECIAL(x)     (S3C_GPIO_SPECIAL_MARK | (x))
+
+/* Defines for generic pin configurations */
+#define S3C_GPIO_INPUT  (S3C_GPIO_SPECIAL(0))
+#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
+#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
+
+#define s3c_gpio_is_cfg_special(_cfg) \
+        (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
+
+/**
+ * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
+ * @pin pin The pin number to configure.
+ * @pin to The configuration for the pin's function.
+ *
+ * Configure which function is actually connected to the external
+ * pin, such as an gpio input, output or some form of special function
+ * connected to an internal peripheral block.
+ */
+extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
+
+/* Define values for the pull-{up,down} available for each gpio pin.
+ *
+ * These values control the state of the weak pull-{up,down} resistors
+ * available on most pins on the S3C series. Not all chips support both
+ * up or down settings, and it may be dependant on the chip that is being
+ * used to whether the particular mode is available.
+ */
+#define S3C_GPIO_PULL_NONE      ((__force s3c_gpio_pull_t)0x00)
+#define S3C_GPIO_PULL_DOWN      ((__force s3c_gpio_pull_t)0x01)
+#define S3C_GPIO_PULL_UP        ((__force s3c_gpio_pull_t)0x02)
+
+/**
+ * s3c_gpio_setpull() - set the state of a gpio pin pull resistor
+ * @pin: The pin number to configure the pull resistor.
+ * @pull: The configuration for the pull resistor.
+ *
+ * This function sets the state of the pull-{up,down} resistor for the
+ * specified pin. It will return 0 if successfull, or a negative error
+ * code if the pin cannot support the requested pull setting.
+*/
+extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
+
+/**
+ * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
+ * @pin: The pin number to get the settings for
+ *
+ * Read the pull resistor value for the specified pin.
+*/
+extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
+
+#endif /* __PLAT_GPIO_CFG_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
new file mode 100644
index 000000000000..49ff406a7066
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -0,0 +1,137 @@
+/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
+ *
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - GPIO core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define GPIOCON_OFF     (0x00)
+#define GPIODAT_OFF     (0x04)
+
+#define con_4bit_shift(__off) ((__off) * 4)
+
+/* Define the core gpiolib support functions that the s3c platforms may
+ * need to extend or change depending on the hardware and the s3c chip
+ * selected at build or found at run time.
+ *
+ * These definitions are not intended for driver inclusion, there is
+ * nothing here that should not live outside the platform and core
+ * specific code.
+*/
+
+struct s3c_gpio_chip;
+
+/**
+ * struct s3c_gpio_pm - power management (suspend/resume) information
+ * @save: Routine to save the state of the GPIO block
+ * @resume: Routine to resume the GPIO block.
+ */
+struct s3c_gpio_pm {
+        void (*save)(struct s3c_gpio_chip *chip);
+        void (*resume)(struct s3c_gpio_chip *chip);
+};
+
+struct s3c_gpio_cfg;
+
+/**
+ * struct s3c_gpio_chip - wrapper for specific implementation of gpio
+ * @chip: The chip structure to be exported via gpiolib.
+ * @base: The base pointer to the gpio configuration registers.
+ * @config: special function and pull-resistor control information.
+ * @pm_save: Save information for suspend/resume support.
+ *
+ * This wrapper provides the necessary information for the Samsung
+ * specific gpios being registered with gpiolib.
+ */
+struct s3c_gpio_chip {
+        struct gpio_chip        chip;
+        struct s3c_gpio_cfg     *config;
+        struct s3c_gpio_pm      *pm;
+        void __iomem            *base;
+#ifdef CONFIG_PM
+        u32                     pm_save[4];
+#endif
+};
+
+static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
+{
+        return container_of(gpc, struct s3c_gpio_chip, chip);
+}
+
+/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
+ * @chip: The chip to register
+ *
+ * This is a wrapper to gpiochip_add() that takes our specific gpio chip
+ * information and makes the necessary alterations for the platform and
+ * notes the information for use with the configuration systems and any
+ * other parts of the system.
+ */
+extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
+
+/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
+ * for use with the configuration calls, and other parts of the s3c gpiolib
+ * support code.
+ *
+ * Not all s3c support code will need this, as some configurations of cpu
+ * may only support one or two different configuration options and have an
+ * easy gpio to s3c_gpio_chip mapping function. If this is the case, then
+ * the machine support file should provide its own s3c_gpiolib_getchip()
+ * and any other necessary functions.
+ */
+
+/**
+ * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
+ * @chip: The gpio chip that is being configured.
+ * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
+ *
+ * This helper deal with the GPIO cases where the control register has 4 bits
+ * of control per GPIO, generally in the form of:
+ * 0000 = Input
+ * 0001 = Output
+ * others = Special functions (dependant on bank)
+ *
+ * Note, since the code to deal with the case where there are two control
+ * registers instead of one, we do not have a seperate set of function
+ * (samsung_gpiolib_add_4bit2_chips)for each case.
+ */
+extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
+                                           int nr_chips);
+extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
+                                            int nr_chips);
+
+extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
+extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
+
+#ifdef CONFIG_S3C_GPIO_TRACK
+extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
+
+static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
+{
+        return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
+}
+#else
+/* machine specific code should provide s3c_gpiolib_getchip */
+
+#include <mach/gpio-track.h>
+
+static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
+#endif
+
+#ifdef CONFIG_PM
+extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
+extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
+extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
+#define __gpio_pm(x) x
+#else
+#define s3c_gpio_pm_1bit NULL
+#define s3c_gpio_pm_2bit NULL
+#define s3c_gpio_pm_4bit NULL
+#define __gpio_pm(x) NULL
+
+#endif /* CONFIG_PM */
diff --git a/arch/arm/plat-samsung/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h
new file mode 100644
index 000000000000..1ba88ea0aa31
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/hwmon.h
@@ -0,0 +1,41 @@
+/* linux/arch/arm/plat-s3c/include/plat/hwmon.h
+ *
+ * Copyright 2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C - HWMon interface for ADC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_ADC_HWMON_H
+#define __ASM_ARCH_ADC_HWMON_H __FILE__
+
+/**
+ * s3c_hwmon_chcfg - channel configuration
+ * @name: The name to give this channel.
+ * @mult: Multiply the ADC value read by this.
+ * @div: Divide the value from the ADC by this.
+ *
+ * The value read from the ADC is converted to a value that
+ * hwmon expects (mV) by result = (value_read * @mult) / @div.
+ */
+struct s3c_hwmon_chcfg {
+        const char      *name;
+        unsigned int    mult;
+        unsigned int    div;
+};
+
+/**
+ * s3c_hwmon_pdata - HWMON platform data
+ * @in: One configuration for each possible channel used.
+ */
+struct s3c_hwmon_pdata {
+        struct s3c_hwmon_chcfg  *in[8];
+};
+
+#endif /* __ASM_ARCH_ADC_HWMON_H */
+
diff --git a/arch/arm/plat-samsung/include/plat/iic-core.h b/arch/arm/plat-samsung/include/plat/iic-core.h
new file mode 100644
index 000000000000..36397ca20962
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/iic-core.h
@@ -0,0 +1,35 @@
+/* arch/arm/mach-s3c2410/include/mach/iic-core.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - I2C Controller core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IIC_CORE_H
+#define __ASM_ARCH_IIC_CORE_H __FILE__
+
+/* These functions are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void s3c_i2c0_setname(char *name)
+{
+        /* currently this device is always compiled in */
+        s3c_device_i2c0.name = name;
+}
+
+static inline void s3c_i2c1_setname(char *name)
+{
+#ifdef CONFIG_S3C_DEV_I2C1
+        s3c_device_i2c1.name = name;
+#endif
+}
+
+#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
new file mode 100644
index 000000000000..3083df00dee6
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/iic.h
@@ -0,0 +1,62 @@
+/* arch/arm/plat-s3c/include/plat/iic.h
+ *
+ * Copyright 2004-2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - I2C Controller platform_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IIC_H
+#define __ASM_ARCH_IIC_H __FILE__
+
+#define S3C_IICFLG_FILTER       (1<<0)  /* enable s3c2440 filter */
+
+/**
+ *      struct s3c2410_platform_i2c - Platform data for s3c I2C.
+ *      @bus_num: The bus number to use (if possible).
+ *      @flags: Any flags for the I2C bus (E.g. S3C_IICFLK_FILTER).
+ *      @slave_addr: The I2C address for the slave device (if enabled).
+ *      @frequency: The desired frequency in Hz of the bus.  This is
+ *                  guaranteed to not be exceeded.  If the caller does
+ *                  not care, use zero and the driver will select a
+ *                  useful default.
+ *      @sda_delay: The delay (in ns) applied to SDA edges.
+ *      @cfg_gpio: A callback to configure the pins for I2C operation.
+ */
+struct s3c2410_platform_i2c {
+        int             bus_num;
+        unsigned int    flags;
+        unsigned int    slave_addr;
+        unsigned long   frequency;
+        unsigned int    sda_delay;
+
+        void    (*cfg_gpio)(struct platform_device *dev);
+};
+
+/**
+ * s3c_i2c0_set_platdata - set platform data for i2c0 device
+ * @i2c: The platform data to set, or NULL for default data.
+ *
+ * Register the given platform data for use with the i2c0 device. This
+ * call copies the platform data, so the caller can use __initdata for
+ * their copy.
+ *
+ * This call will set cfg_gpio if is null to the default platform
+ * implementation.
+ *
+ * Any user of s3c_device_i2c0 should call this, even if it is with
+ * NULL to ensure that the device is given the default platform data
+ * as the driver will no longer carry defaults.
+ */
+extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
+
+/* defined by architecture to configure gpio */
+extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
+
+#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/irq-uart.h b/arch/arm/plat-samsung/include/plat/irq-uart.h
new file mode 100644
index 000000000000..a9331e49bea3
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/irq-uart.h
@@ -0,0 +1,20 @@
+/* arch/arm/plat-samsung/include/plat/irq-uart.h
+ *
+ * Copyright (c) 2010 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for Samsung SoC UART IRQ demux for S3C64XX and later
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct s3c_uart_irq {
+        void __iomem    *regs;
+        unsigned int     base_irq;
+        unsigned int     parent_irq;
+};
+
+extern void s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs);
+
diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
new file mode 100644
index 000000000000..a90b53431b5b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
@@ -0,0 +1,13 @@
+/* arch/arm/plat-samsung/include/plat/irq-vic-timer.h
+ *
+ * Copyright (c) 2010 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for Samsung SoC IRQ VIC timer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer);
diff --git a/arch/arm/plat-samsung/include/plat/map-base.h b/arch/arm/plat-samsung/include/plat/map-base.h
new file mode 100644
index 000000000000..250be311c85b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/map-base.h
@@ -0,0 +1,46 @@
+/* linux/include/asm-arm/plat-s3c/map.h
+ *
+ * Copyright 2003, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - Memory map definitions (virtual addresses)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_MAP_H
+#define __ASM_PLAT_MAP_H __FILE__
+
+/* Fit all our registers in at 0xF4000000 upwards, trying to use as
+ * little of the VA space as possible so vmalloc and friends have a
+ * better chance of getting memory.
+ *
+ * we try to ensure stuff like the IRQ registers are available for
+ * an single MOVS instruction (ie, only 8 bits of set data)
+ */
+
+#define S3C_ADDR_BASE   (0xF4000000)
+
+#ifndef __ASSEMBLY__
+#define S3C_ADDR(x)     ((void __iomem __force *)S3C_ADDR_BASE + (x))
+#else
+#define S3C_ADDR(x)     (S3C_ADDR_BASE + (x))
+#endif
+
+#define S3C_VA_IRQ      S3C_ADDR(0x00000000)    /* irq controller(s) */
+#define S3C_VA_SYS      S3C_ADDR(0x00100000)    /* system control */
+#define S3C_VA_MEM      S3C_ADDR(0x00200000)    /* memory control */
+#define S3C_VA_TIMER    S3C_ADDR(0x00300000)    /* timer block */
+#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000)    /* watchdog */
+#define S3C_VA_UART     S3C_ADDR(0x01000000)    /* UART */
+
+/* This is used for the CPU specific mappings that may be needed, so that
+ * they do not need to directly used S3C_ADDR() and thus make it easier to
+ * modify the space for mapping.
+ */
+#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x))
+
+#endif /* __ASM_PLAT_MAP_H */
diff --git a/arch/arm/plat-samsung/include/plat/nand.h b/arch/arm/plat-samsung/include/plat/nand.h
new file mode 100644
index 000000000000..b64115fa93a4
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/nand.h
@@ -0,0 +1,67 @@
+/* arch/arm/mach-s3c2410/include/mach/nand.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - NAND device controller platform_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/**
+ * struct s3c2410_nand_set - define a set of one or more nand chips
+ * @disable_ecc:        Entirely disable ECC - Dangerous
+ * @flash_bbt:          Openmoko u-boot can create a Bad Block Table
+ *                      Setting this flag will allow the kernel to
+ *                      look for it at boot time and also skip the NAND
+ *                      scan.
+ * @options:            Default value to set into 'struct nand_chip' options.
+ * @nr_chips:           Number of chips in this set
+ * @nr_partitions:      Number of partitions pointed to by @partitions
+ * @name:               Name of set (optional)
+ * @nr_map:             Map for low-layer logical to physical chip numbers (option)
+ * @partitions:         The mtd partition list
+ *
+ * define a set of one or more nand chips registered with an unique mtd. Also
+ * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger
+ * a warning at boot time.
+ */
+struct s3c2410_nand_set {
+        unsigned int            disable_ecc:1;
+        unsigned int            flash_bbt:1;
+
+        unsigned int            options;
+        int                     nr_chips;
+        int                     nr_partitions;
+        char                    *name;
+        int                     *nr_map;
+        struct mtd_partition    *partitions;
+        struct nand_ecclayout   *ecc_layout;
+};
+
+struct s3c2410_platform_nand {
+        /* timing information for controller, all times in nanoseconds */
+
+        int     tacls;  /* time for active CLE/ALE to nWE/nOE */
+        int     twrph0; /* active time for nWE/nOE */
+        int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
+
+        unsigned int    ignore_unset_ecc:1;
+
+        int                     nr_sets;
+        struct s3c2410_nand_set *sets;
+
+        void                    (*select_chip)(struct s3c2410_nand_set *,
+                                               int chip);
+};
+
+/**
+ * s3c_nand_set_platdata() - register NAND platform data.
+ * @nand: The NAND platform data to register with s3c_device_nand.
+ *
+ * This function copies the given NAND platform data, @nand and registers
+ * it with the s3c_device_nand. This allows @nand to be __initdata.
+*/
+extern void s3c_nand_set_platdata(struct s3c2410_platform_nand *nand);
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
new file mode 100644
index 000000000000..245836d91931
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -0,0 +1,189 @@
+/* arch/arm/plat-samsung/include/plat/pm.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Written by Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* s3c_pm_init
+ *
+ * called from board at initialisation time to setup the power
+ * management
+*/
+
+#ifdef CONFIG_PM
+
+extern __init int s3c_pm_init(void);
+
+#else
+
+static inline int s3c_pm_init(void)
+{
+        return 0;
+}
+#endif
+
+/* configuration for the IRQ mask over sleep */
+extern unsigned long s3c_irqwake_intmask;
+extern unsigned long s3c_irqwake_eintmask;
+
+/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
+extern unsigned long s3c_irqwake_intallow;
+extern unsigned long s3c_irqwake_eintallow;
+
+/* per-cpu sleep functions */
+
+extern void (*pm_cpu_prep)(void);
+extern void (*pm_cpu_sleep)(void);
+
+/* Flags for PM Control */
+
+extern unsigned long s3c_pm_flags;
+
+extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
+
+/* from sleep.S */
+
+extern int  s3c_cpu_save(unsigned long *saveblk);
+extern void s3c_cpu_resume(void);
+
+extern void s3c2410_cpu_suspend(void);
+
+extern unsigned long s3c_sleep_save_phys;
+
+/* sleep save info */
+
+/**
+ * struct sleep_save - save information for shared peripherals.
+ * @reg: Pointer to the register to save.
+ * @val: Holder for the value saved from reg.
+ *
+ * This describes a list of registers which is used by the pm core and
+ * other subsystem to save and restore register values over suspend.
+ */
+struct sleep_save {
+        void __iomem    *reg;
+        unsigned long   val;
+};
+
+#define SAVE_ITEM(x) \
+        { .reg = (x) }
+
+/**
+ * struct pm_uart_save - save block for core UART
+ * @ulcon: Save value for S3C2410_ULCON
+ * @ucon: Save value for S3C2410_UCON
+ * @ufcon: Save value for S3C2410_UFCON
+ * @umcon: Save value for S3C2410_UMCON
+ * @ubrdiv: Save value for S3C2410_UBRDIV
+ *
+ * Save block for UART registers to be held over sleep and restored if they
+ * are needed (say by debug).
+*/
+struct pm_uart_save {
+        u32     ulcon;
+        u32     ucon;
+        u32     ufcon;
+        u32     umcon;
+        u32     ubrdiv;
+        u32     udivslot;
+};
+
+/* helper functions to save/restore lists of registers. */
+
+extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
+
+#ifdef CONFIG_PM
+extern int s3c_irqext_wake(unsigned int irqno, unsigned int state);
+extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
+extern int s3c24xx_irq_resume(struct sys_device *dev);
+#else
+#define s3c_irqext_wake NULL
+#define s3c24xx_irq_suspend NULL
+#define s3c24xx_irq_resume  NULL
+#endif
+
+/* PM debug functions */
+
+#ifdef CONFIG_SAMSUNG_PM_DEBUG
+/**
+ * s3c_pm_dbg() - low level debug function for use in suspend/resume.
+ * @msg: The message to print.
+ *
+ * This function is used mainly to debug the resume process before the system
+ * can rely on printk/console output. It uses the low-level debugging output
+ * routine printascii() to do its work.
+ */
+extern void s3c_pm_dbg(const char *msg, ...);
+
+#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
+#else
+#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
+#endif
+
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+/**
+ * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
+ * @set: set bits for the state of the LEDs
+ * @clear: clear bits for the state of the LEDs.
+ */
+extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
+
+#else
+static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
+#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
+
+/* suspend memory checking */
+
+#ifdef CONFIG_SAMSUNG_PM_CHECK
+extern void s3c_pm_check_prepare(void);
+extern void s3c_pm_check_restore(void);
+extern void s3c_pm_check_cleanup(void);
+extern void s3c_pm_check_store(void);
+#else
+#define s3c_pm_check_prepare() do { } while(0)
+#define s3c_pm_check_restore() do { } while(0)
+#define s3c_pm_check_cleanup() do { } while(0)
+#define s3c_pm_check_store()   do { } while(0)
+#endif
+
+/**
+ * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
+ *
+ * Setup all the necessary GPIO pins for waking the system on external
+ * interrupt.
+ */
+extern void s3c_pm_configure_extint(void);
+
+/**
+ * s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
+ *
+ * Restore the state of the GPIO pins after sleep, which may involve ensuring
+ * that we do not glitch the state of the pins from that the bootloader's
+ * resume code has done.
+*/
+extern void s3c_pm_restore_gpios(void);
+
+/**
+ * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
+ *
+ * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios().
+ */
+extern void s3c_pm_save_gpios(void);
+
+/**
+ * s3c_pm_cb_flushcache - callback for assembly code
+ *
+ * Callback to issue flush_cache_all() as this call is
+ * not a directly callable object.
+ */
+extern void s3c_pm_cb_flushcache(void);
+
+extern void s3c_pm_save_core(void);
+extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-samsung/include/plat/regs-ac97.h b/arch/arm/plat-samsung/include/plat/regs-ac97.h
new file mode 100644
index 000000000000..c3878f7acb83
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-ac97.h
@@ -0,0 +1,67 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
+ *
+ * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440 AC97 Controller
+*/
+
+#ifndef __ASM_ARCH_REGS_AC97_H
+#define __ASM_ARCH_REGS_AC97_H __FILE__
+
+#define S3C_AC97_GLBCTRL                                (0x00)
+
+#define S3C_AC97_GLBCTRL_CODECREADYIE                   (1<<22)
+#define S3C_AC97_GLBCTRL_PCMOUTURIE                     (1<<21)
+#define S3C_AC97_GLBCTRL_PCMINORIE                      (1<<20)
+#define S3C_AC97_GLBCTRL_MICINORIE                      (1<<19)
+#define S3C_AC97_GLBCTRL_PCMOUTTIE                      (1<<18)
+#define S3C_AC97_GLBCTRL_PCMINTIE                       (1<<17)
+#define S3C_AC97_GLBCTRL_MICINTIE                       (1<<16)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF                   (0<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO                   (1<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA                   (2<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK                  (3<<12)
+#define S3C_AC97_GLBCTRL_PCMINTM_OFF                    (0<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_PIO                    (1<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_DMA                    (2<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_MASK                   (3<<10)
+#define S3C_AC97_GLBCTRL_MICINTM_OFF                    (0<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_PIO                    (1<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_DMA                    (2<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_MASK                   (3<<8)
+#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE             (1<<3)
+#define S3C_AC97_GLBCTRL_ACLINKON                       (1<<2)
+#define S3C_AC97_GLBCTRL_WARMRESET                      (1<<1)
+#define S3C_AC97_GLBCTRL_COLDRESET                      (1<<0)
+
+#define S3C_AC97_GLBSTAT                                (0x04)
+
+#define S3C_AC97_GLBSTAT_CODECREADY                     (1<<22)
+#define S3C_AC97_GLBSTAT_PCMOUTUR                       (1<<21)
+#define S3C_AC97_GLBSTAT_PCMINORI                       (1<<20)
+#define S3C_AC97_GLBSTAT_MICINORI                       (1<<19)
+#define S3C_AC97_GLBSTAT_PCMOUTTI                       (1<<18)
+#define S3C_AC97_GLBSTAT_PCMINTI                        (1<<17)
+#define S3C_AC97_GLBSTAT_MICINTI                        (1<<16)
+#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE                 (0<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_INIT                 (1<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_READY                (2<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE               (3<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_LP                   (4<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_WARM                 (5<<0)
+
+#define S3C_AC97_CODEC_CMD                              (0x08)
+
+#define S3C_AC97_CODEC_CMD_READ                         (1<<23)
+
+#define S3C_AC97_STAT                                   (0x0c)
+#define S3C_AC97_PCM_ADDR                               (0x10)
+#define S3C_AC97_PCM_DATA                               (0x18)
+#define S3C_AC97_MIC_DATA                               (0x1C)
+
+#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h
new file mode 100644
index 000000000000..7554c4fcddb9
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -0,0 +1,64 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-adc.h
+ *
+ * Copyright (c) 2004 Shannon Holland <holland@loser.net>
+ *
+ * This program is free software; yosu can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 ADC registers
+*/
+
+#ifndef __ASM_ARCH_REGS_ADC_H
+#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
+
+#define S3C2410_ADCREG(x) (x)
+
+#define S3C2410_ADCCON     S3C2410_ADCREG(0x00)
+#define S3C2410_ADCTSC     S3C2410_ADCREG(0x04)
+#define S3C2410_ADCDLY     S3C2410_ADCREG(0x08)
+#define S3C2410_ADCDAT0    S3C2410_ADCREG(0x0C)
+#define S3C2410_ADCDAT1    S3C2410_ADCREG(0x10)
+#define S3C64XX_ADCUPDN         S3C2410_ADCREG(0x14)
+#define S3C64XX_ADCCLRINT       S3C2410_ADCREG(0x18)
+#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
+
+
+/* ADCCON Register Bits */
+#define S3C64XX_ADCCON_RESSEL           (1<<16)
+#define S3C2410_ADCCON_ECFLG            (1<<15)
+#define S3C2410_ADCCON_PRSCEN           (1<<14)
+#define S3C2410_ADCCON_PRSCVL(x)        (((x)&0xFF)<<6)
+#define S3C2410_ADCCON_PRSCVLMASK       (0xFF<<6)
+#define S3C2410_ADCCON_SELMUX(x)        (((x)&0x7)<<3)
+#define S3C2410_ADCCON_MUXMASK          (0x7<<3)
+#define S3C2410_ADCCON_STDBM            (1<<2)
+#define S3C2410_ADCCON_READ_START       (1<<1)
+#define S3C2410_ADCCON_ENABLE_START     (1<<0)
+#define S3C2410_ADCCON_STARTMASK        (0x3<<0)
+
+
+/* ADCTSC Register Bits */
+#define S3C2410_ADCTSC_YM_SEN           (1<<7)
+#define S3C2410_ADCTSC_YP_SEN           (1<<6)
+#define S3C2410_ADCTSC_XM_SEN           (1<<5)
+#define S3C2410_ADCTSC_XP_SEN           (1<<4)
+#define S3C2410_ADCTSC_PULL_UP_DISABLE  (1<<3)
+#define S3C2410_ADCTSC_AUTO_PST         (1<<2)
+#define S3C2410_ADCTSC_XY_PST(x)        (((x)&0x3)<<0)
+
+/* ADCDAT0 Bits */
+#define S3C2410_ADCDAT0_UPDOWN          (1<<15)
+#define S3C2410_ADCDAT0_AUTO_PST        (1<<14)
+#define S3C2410_ADCDAT0_XY_PST          (0x3<<12)
+#define S3C2410_ADCDAT0_XPDATA_MASK     (0x03FF)
+
+/* ADCDAT1 Bits */
+#define S3C2410_ADCDAT1_UPDOWN          (1<<15)
+#define S3C2410_ADCDAT1_AUTO_PST        (1<<14)
+#define S3C2410_ADCDAT1_XY_PST          (0x3<<12)
+#define S3C2410_ADCDAT1_YPDATA_MASK     (0x03FF)
+
+#endif /* __ASM_ARCH_REGS_ADC_H */
+
+
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
new file mode 100644
index 000000000000..0f43599248ad
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
@@ -0,0 +1,235 @@
+/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - new-style framebuffer register definitions
+ *
+ * This is the register set for the new style framebuffer interface
+ * found from the S3C2443 onwards and specifically the S3C64XX series
+ * S3C6400 and S3C6410.
+ *
+ * The file contains the cpu specific items which change between whichever
+ * architecture is selected. See <plat/regs-fb.h> for the core definitions
+ * that are the same.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* include the core definitions here, in case we really do need to
+ * override them at a later date.
+*/
+
+#include <plat/regs-fb.h>
+
+#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
+#define VIDCON1_FSTATUS_EVEN    (1 << 15)
+
+/* Video timing controls */
+#define VIDTCON0                                (0x10)
+#define VIDTCON1                                (0x14)
+#define VIDTCON2                                (0x18)
+
+/* Window position controls */
+
+#define WINCON(_win)                            (0x20 + ((_win) * 4))
+
+/* OSD1 and OSD4 do not have register D */
+
+#define VIDOSD_A(_win)                          (0x40 + ((_win) * 16))
+#define VIDOSD_B(_win)                          (0x44 + ((_win) * 16))
+#define VIDOSD_C(_win)                          (0x48 + ((_win) * 16))
+#define VIDOSD_D(_win)                          (0x4C + ((_win) * 16))
+
+
+#define VIDINTCON0                              (0x130)
+
+#define WxKEYCONy(_win, _con)                   ((0x140 + ((_win) * 8)) + ((_con) * 4))
+
+/* WINCONx */
+
+#define WINCONx_CSCWIDTH_MASK                   (0x3 << 26)
+#define WINCONx_CSCWIDTH_SHIFT                  (26)
+#define WINCONx_CSCWIDTH_WIDE                   (0x0 << 26)
+#define WINCONx_CSCWIDTH_NARROW                 (0x3 << 26)
+
+#define WINCONx_ENLOCAL                         (1 << 22)
+#define WINCONx_BUFSTATUS                       (1 << 21)
+#define WINCONx_BUFSEL                          (1 << 20)
+#define WINCONx_BUFAUTOEN                       (1 << 19)
+#define WINCONx_YCbCr                           (1 << 13)
+
+#define WINCON1_LOCALSEL_CAMIF                  (1 << 23)
+
+#define WINCON2_LOCALSEL_CAMIF                  (1 << 23)
+#define WINCON2_BLD_PIX                         (1 << 6)
+
+#define WINCON2_ALPHA_SEL                       (1 << 1)
+#define WINCON2_BPPMODE_MASK                    (0xf << 2)
+#define WINCON2_BPPMODE_SHIFT                   (2)
+#define WINCON2_BPPMODE_1BPP                    (0x0 << 2)
+#define WINCON2_BPPMODE_2BPP                    (0x1 << 2)
+#define WINCON2_BPPMODE_4BPP                    (0x2 << 2)
+#define WINCON2_BPPMODE_8BPP_1232               (0x4 << 2)
+#define WINCON2_BPPMODE_16BPP_565               (0x5 << 2)
+#define WINCON2_BPPMODE_16BPP_A1555             (0x6 << 2)
+#define WINCON2_BPPMODE_16BPP_I1555             (0x7 << 2)
+#define WINCON2_BPPMODE_18BPP_666               (0x8 << 2)
+#define WINCON2_BPPMODE_18BPP_A1665             (0x9 << 2)
+#define WINCON2_BPPMODE_19BPP_A1666             (0xa << 2)
+#define WINCON2_BPPMODE_24BPP_888               (0xb << 2)
+#define WINCON2_BPPMODE_24BPP_A1887             (0xc << 2)
+#define WINCON2_BPPMODE_25BPP_A1888             (0xd << 2)
+#define WINCON2_BPPMODE_28BPP_A4888             (0xd << 2)
+
+#define WINCON3_BLD_PIX                         (1 << 6)
+
+#define WINCON3_ALPHA_SEL                       (1 << 1)
+#define WINCON3_BPPMODE_MASK                    (0xf << 2)
+#define WINCON3_BPPMODE_SHIFT                   (2)
+#define WINCON3_BPPMODE_1BPP                    (0x0 << 2)
+#define WINCON3_BPPMODE_2BPP                    (0x1 << 2)
+#define WINCON3_BPPMODE_4BPP                    (0x2 << 2)
+#define WINCON3_BPPMODE_16BPP_565               (0x5 << 2)
+#define WINCON3_BPPMODE_16BPP_A1555             (0x6 << 2)
+#define WINCON3_BPPMODE_16BPP_I1555             (0x7 << 2)
+#define WINCON3_BPPMODE_18BPP_666               (0x8 << 2)
+#define WINCON3_BPPMODE_18BPP_A1665             (0x9 << 2)
+#define WINCON3_BPPMODE_19BPP_A1666             (0xa << 2)
+#define WINCON3_BPPMODE_24BPP_888               (0xb << 2)
+#define WINCON3_BPPMODE_24BPP_A1887             (0xc << 2)
+#define WINCON3_BPPMODE_25BPP_A1888             (0xd << 2)
+#define WINCON3_BPPMODE_28BPP_A4888             (0xd << 2)
+
+#define VIDINTCON0_FIFIOSEL_WINDOW2             (0x10 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW3             (0x20 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW4             (0x40 << 5)
+
+#define DITHMODE                                (0x170)
+#define WINxMAP(_win)                           (0x180 + ((_win) * 4))
+
+
+#define DITHMODE_R_POS_MASK                     (0x3 << 5)
+#define DITHMODE_R_POS_SHIFT                    (5)
+#define DITHMODE_R_POS_8BIT                     (0x0 << 5)
+#define DITHMODE_R_POS_6BIT                     (0x1 << 5)
+#define DITHMODE_R_POS_5BIT                     (0x2 << 5)
+
+#define DITHMODE_G_POS_MASK                     (0x3 << 3)
+#define DITHMODE_G_POS_SHIFT                    (3)
+#define DITHMODE_G_POS_8BIT                     (0x0 << 3)
+#define DITHMODE_G_POS_6BIT                     (0x1 << 3)
+#define DITHMODE_G_POS_5BIT                     (0x2 << 3)
+
+#define DITHMODE_B_POS_MASK                     (0x3 << 1)
+#define DITHMODE_B_POS_SHIFT                    (1)
+#define DITHMODE_B_POS_8BIT                     (0x0 << 1)
+#define DITHMODE_B_POS_6BIT                     (0x1 << 1)
+#define DITHMODE_B_POS_5BIT                     (0x2 << 1)
+
+#define DITHMODE_DITH_EN                        (1 << 0)
+
+#define WPALCON                                 (0x1A0)
+
+/* Palette control */
+/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
+ * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
+#define WPALCON_W4PAL_16BPP_A555                (1 << 8)
+#define WPALCON_W3PAL_16BPP_A555                (1 << 7)
+#define WPALCON_W2PAL_16BPP_A555                (1 << 6)
+
+
+/* system specific implementation code for palette sizes, and other
+ * information that changes depending on which architecture is being
+ * compiled.
+*/
+
+/* return true if window _win has OSD register D */
+#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
+
+static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
+{
+        if (win < 2)
+                return 256;
+        if (win < 4)
+                return 16;
+        if (win == 4)
+                return 4;
+
+        BUG();  /* shouldn't get here */
+}
+
+static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
+{
+        /* all windows can do 1/2 bpp */
+
+        if ((bpp == 25 || bpp == 19) && win == 0)
+                return 0;       /* win 0 does not have 19 or 25bpp modes */
+
+        if (bpp == 4 && win == 4)
+                return 0;
+
+        if (bpp == 8 && (win >= 3))
+                return 0;       /* win 3/4 cannot do 8bpp in any mode */
+
+        return 1;
+}
+
+static inline int s3c_fb_pal_is16(unsigned int window)
+{
+        return window > 1;
+}
+
+struct s3c_fb_palette {
+        struct fb_bitfield      r;
+        struct fb_bitfield      g;
+        struct fb_bitfield      b;
+        struct fb_bitfield      a;
+};
+
+static inline void s3c_fb_init_palette(unsigned int window,
+                                       struct s3c_fb_palette *palette)
+{
+        if (window < 2) {
+                /* Windows 0/1 are 8/8/8 or A/8/8/8 */
+                palette->r.offset = 16;
+                palette->r.length = 8;
+                palette->g.offset = 8;
+                palette->g.length = 8;
+                palette->b.offset = 0;
+                palette->b.length = 8;
+        } else {
+                /* currently we assume RGB 5/6/5 */
+                palette->r.offset = 11;
+                palette->r.length = 5;
+                palette->g.offset = 5;
+                palette->g.length = 6;
+                palette->b.offset = 0;
+                palette->b.length = 5;
+        }
+}
+
+/* Notes on per-window bpp settings
+ *
+ * Value        Win0     Win1     Win2     Win3     Win 4
+ * 0000         1(P)     1(P)     1(P)     1(P)     1(P)
+ * 0001         2(P)     2(P)     2(P)     2(P)     2(P)
+ * 0010         4(P)     4(P)     4(P)     4(P)     -none-
+ * 0011         8(P)     8(P)     -none-   -none-   -none-
+ * 0100         -none-   8(A232)  8(A232)  -none-   -none-
+ * 0101         16(565)  16(565)  16(565)  16(565)   16(565)
+ * 0110         -none-   16(A555) 16(A555) 16(A555)  16(A555)
+ * 0111         16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
+ * 1000         18(666)  18(666)  18(666)  18(666)   18(666)
+ * 1001         -none-   18(A665) 18(A665) 18(A665)  16(A665)
+ * 1010         -none-   19(A666) 19(A666) 19(A666)  19(A666)
+ * 1011         24(888)  24(888)  24(888)  24(888)   24(888)
+ * 1100         -none-   24(A887) 24(A887) 24(A887)  24(A887)
+ * 1101         -none-   25(A888) 25(A888) 25(A888)  25(A888)
+ * 1110         -none-   -none-   -none-   -none-    -none-
+ * 1111         -none-   -none-   -none-   -none-    -none-
+*/
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
new file mode 100644
index 000000000000..0ef806e50344
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -0,0 +1,366 @@
+/* arch/arm/plat-samsung/include/plat/regs-fb.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - new-style framebuffer register definitions
+ *
+ * This is the register set for the new style framebuffer interface
+ * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
+ * S3C64XX series such as the S3C6400 and S3C6410.
+ *
+ * The file does not contain the cpu specific items which are based on
+ * whichever architecture is selected, it only contains the core of the
+ * register set. See <mach/regs-fb.h> to get the specifics.
+ *
+ * Note, we changed to using regs-fb.h as it avoids any clashes with
+ * the original regs-lcd.h so out of the way of regs-lcd.h as well as
+ * indicating the newer block is much more than just an LCD interface.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Please do not include this file directly, use <mach/regs-fb.h> to
+ * ensure all the localised SoC support is included as necessary.
+*/
+
+/* VIDCON0 */
+
+#define VIDCON0                                 (0x00)
+#define VIDCON0_INTERLACE                       (1 << 29)
+#define VIDCON0_VIDOUT_MASK                     (0x3 << 26)
+#define VIDCON0_VIDOUT_SHIFT                    (26)
+#define VIDCON0_VIDOUT_RGB                      (0x0 << 26)
+#define VIDCON0_VIDOUT_TV                       (0x1 << 26)
+#define VIDCON0_VIDOUT_I80_LDI0                 (0x2 << 26)
+#define VIDCON0_VIDOUT_I80_LDI1                 (0x3 << 26)
+
+#define VIDCON0_L1_DATA_MASK                    (0x7 << 23)
+#define VIDCON0_L1_DATA_SHIFT                   (23)
+#define VIDCON0_L1_DATA_16BPP                   (0x0 << 23)
+#define VIDCON0_L1_DATA_18BPP16                 (0x1 << 23)
+#define VIDCON0_L1_DATA_18BPP9                  (0x2 << 23)
+#define VIDCON0_L1_DATA_24BPP                   (0x3 << 23)
+#define VIDCON0_L1_DATA_18BPP                   (0x4 << 23)
+#define VIDCON0_L1_DATA_16BPP8                  (0x5 << 23)
+
+#define VIDCON0_L0_DATA_MASK                    (0x7 << 20)
+#define VIDCON0_L0_DATA_SHIFT                   (20)
+#define VIDCON0_L0_DATA_16BPP                   (0x0 << 20)
+#define VIDCON0_L0_DATA_18BPP16                 (0x1 << 20)
+#define VIDCON0_L0_DATA_18BPP9                  (0x2 << 20)
+#define VIDCON0_L0_DATA_24BPP                   (0x3 << 20)
+#define VIDCON0_L0_DATA_18BPP                   (0x4 << 20)
+#define VIDCON0_L0_DATA_16BPP8                  (0x5 << 20)
+
+#define VIDCON0_PNRMODE_MASK                    (0x3 << 17)
+#define VIDCON0_PNRMODE_SHIFT                   (17)
+#define VIDCON0_PNRMODE_RGB                     (0x0 << 17)
+#define VIDCON0_PNRMODE_BGR                     (0x1 << 17)
+#define VIDCON0_PNRMODE_SERIAL_RGB              (0x2 << 17)
+#define VIDCON0_PNRMODE_SERIAL_BGR              (0x3 << 17)
+
+#define VIDCON0_CLKVALUP                        (1 << 16)
+#define VIDCON0_CLKVAL_F_MASK                   (0xff << 6)
+#define VIDCON0_CLKVAL_F_SHIFT                  (6)
+#define VIDCON0_CLKVAL_F_LIMIT                  (0xff)
+#define VIDCON0_CLKVAL_F(_x)                    ((_x) << 6)
+#define VIDCON0_VLCKFREE                        (1 << 5)
+#define VIDCON0_CLKDIR                          (1 << 4)
+
+#define VIDCON0_CLKSEL_MASK                     (0x3 << 2)
+#define VIDCON0_CLKSEL_SHIFT                    (2)
+#define VIDCON0_CLKSEL_HCLK                     (0x0 << 2)
+#define VIDCON0_CLKSEL_LCD                      (0x1 << 2)
+#define VIDCON0_CLKSEL_27M                      (0x3 << 2)
+
+#define VIDCON0_ENVID                           (1 << 1)
+#define VIDCON0_ENVID_F                         (1 << 0)
+
+#define VIDCON1                                 (0x04)
+#define VIDCON1_LINECNT_MASK                    (0x7ff << 16)
+#define VIDCON1_LINECNT_SHIFT                   (16)
+#define VIDCON1_LINECNT_GET(_v)                 (((_v) >> 16) & 0x7ff)
+#define VIDCON1_VSTATUS_MASK                    (0x3 << 13)
+#define VIDCON1_VSTATUS_SHIFT                   (13)
+#define VIDCON1_VSTATUS_VSYNC                   (0x0 << 13)
+#define VIDCON1_VSTATUS_BACKPORCH               (0x1 << 13)
+#define VIDCON1_VSTATUS_ACTIVE                  (0x2 << 13)
+#define VIDCON1_VSTATUS_FRONTPORCH              (0x0 << 13)
+
+#define VIDCON1_INV_VCLK                        (1 << 7)
+#define VIDCON1_INV_HSYNC                       (1 << 6)
+#define VIDCON1_INV_VSYNC                       (1 << 5)
+#define VIDCON1_INV_VDEN                        (1 << 4)
+
+/* VIDCON2 */
+
+#define VIDCON2                                 (0x08)
+#define VIDCON2_EN601                           (1 << 23)
+#define VIDCON2_TVFMTSEL_SW                     (1 << 14)
+
+#define VIDCON2_TVFMTSEL1_MASK                  (0x3 << 12)
+#define VIDCON2_TVFMTSEL1_SHIFT                 (12)
+#define VIDCON2_TVFMTSEL1_RGB                   (0x0 << 12)
+#define VIDCON2_TVFMTSEL1_YUV422                (0x1 << 12)
+#define VIDCON2_TVFMTSEL1_YUV444                (0x2 << 12)
+
+#define VIDCON2_ORGYCbCr                        (1 << 8)
+#define VIDCON2_YUVORDCrCb                      (1 << 7)
+
+/* VIDTCON0 */
+
+#define VIDTCON0_VBPDE_MASK                     (0xff << 24)
+#define VIDTCON0_VBPDE_SHIFT                    (24)
+#define VIDTCON0_VBPDE_LIMIT                    (0xff)
+#define VIDTCON0_VBPDE(_x)                      ((_x) << 24)
+
+#define VIDTCON0_VBPD_MASK                      (0xff << 16)
+#define VIDTCON0_VBPD_SHIFT                     (16)
+#define VIDTCON0_VBPD_LIMIT                     (0xff)
+#define VIDTCON0_VBPD(_x)                       ((_x) << 16)
+
+#define VIDTCON0_VFPD_MASK                      (0xff << 8)
+#define VIDTCON0_VFPD_SHIFT                     (8)
+#define VIDTCON0_VFPD_LIMIT                     (0xff)
+#define VIDTCON0_VFPD(_x)                       ((_x) << 8)
+
+#define VIDTCON0_VSPW_MASK                      (0xff << 0)
+#define VIDTCON0_VSPW_SHIFT                     (0)
+#define VIDTCON0_VSPW_LIMIT                     (0xff)
+#define VIDTCON0_VSPW(_x)                       ((_x) << 0)
+
+/* VIDTCON1 */
+
+#define VIDTCON1_VFPDE_MASK                     (0xff << 24)
+#define VIDTCON1_VFPDE_SHIFT                    (24)
+#define VIDTCON1_VFPDE_LIMIT                    (0xff)
+#define VIDTCON1_VFPDE(_x)                      ((_x) << 24)
+
+#define VIDTCON1_HBPD_MASK                      (0xff << 16)
+#define VIDTCON1_HBPD_SHIFT                     (16)
+#define VIDTCON1_HBPD_LIMIT                     (0xff)
+#define VIDTCON1_HBPD(_x)                       ((_x) << 16)
+
+#define VIDTCON1_HFPD_MASK                      (0xff << 8)
+#define VIDTCON1_HFPD_SHIFT                     (8)
+#define VIDTCON1_HFPD_LIMIT                     (0xff)
+#define VIDTCON1_HFPD(_x)                       ((_x) << 8)
+
+#define VIDTCON1_HSPW_MASK                      (0xff << 0)
+#define VIDTCON1_HSPW_SHIFT                     (0)
+#define VIDTCON1_HSPW_LIMIT                     (0xff)
+#define VIDTCON1_HSPW(_x)                       ((_x) << 0)
+
+#define VIDTCON2                                (0x18)
+#define VIDTCON2_LINEVAL_MASK                   (0x7ff << 11)
+#define VIDTCON2_LINEVAL_SHIFT                  (11)
+#define VIDTCON2_LINEVAL_LIMIT                  (0x7ff)
+#define VIDTCON2_LINEVAL(_x)                    ((_x) << 11)
+
+#define VIDTCON2_HOZVAL_MASK                    (0x7ff << 0)
+#define VIDTCON2_HOZVAL_SHIFT                   (0)
+#define VIDTCON2_HOZVAL_LIMIT                   (0x7ff)
+#define VIDTCON2_HOZVAL(_x)                     ((_x) << 0)
+
+/* WINCONx */
+
+
+#define WINCONx_BITSWP                          (1 << 18)
+#define WINCONx_BYTSWP                          (1 << 17)
+#define WINCONx_HAWSWP                          (1 << 16)
+#define WINCONx_BURSTLEN_MASK                   (0x3 << 9)
+#define WINCONx_BURSTLEN_SHIFT                  (9)
+#define WINCONx_BURSTLEN_16WORD                 (0x0 << 9)
+#define WINCONx_BURSTLEN_8WORD                  (0x1 << 9)
+#define WINCONx_BURSTLEN_4WORD                  (0x2 << 9)
+
+#define WINCONx_ENWIN                           (1 << 0)
+#define WINCON0_BPPMODE_MASK                    (0xf << 2)
+#define WINCON0_BPPMODE_SHIFT                   (2)
+#define WINCON0_BPPMODE_1BPP                    (0x0 << 2)
+#define WINCON0_BPPMODE_2BPP                    (0x1 << 2)
+#define WINCON0_BPPMODE_4BPP                    (0x2 << 2)
+#define WINCON0_BPPMODE_8BPP_PALETTE            (0x3 << 2)
+#define WINCON0_BPPMODE_16BPP_565               (0x5 << 2)
+#define WINCON0_BPPMODE_16BPP_1555              (0x7 << 2)
+#define WINCON0_BPPMODE_18BPP_666               (0x8 << 2)
+#define WINCON0_BPPMODE_24BPP_888               (0xb << 2)
+
+#define WINCON1_BLD_PIX                         (1 << 6)
+
+#define WINCON1_ALPHA_SEL                       (1 << 1)
+#define WINCON1_BPPMODE_MASK                    (0xf << 2)
+#define WINCON1_BPPMODE_SHIFT                   (2)
+#define WINCON1_BPPMODE_1BPP                    (0x0 << 2)
+#define WINCON1_BPPMODE_2BPP                    (0x1 << 2)
+#define WINCON1_BPPMODE_4BPP                    (0x2 << 2)
+#define WINCON1_BPPMODE_8BPP_PALETTE            (0x3 << 2)
+#define WINCON1_BPPMODE_8BPP_1232               (0x4 << 2)
+#define WINCON1_BPPMODE_16BPP_565               (0x5 << 2)
+#define WINCON1_BPPMODE_16BPP_A1555             (0x6 << 2)
+#define WINCON1_BPPMODE_16BPP_I1555             (0x7 << 2)
+#define WINCON1_BPPMODE_18BPP_666               (0x8 << 2)
+#define WINCON1_BPPMODE_18BPP_A1665             (0x9 << 2)
+#define WINCON1_BPPMODE_19BPP_A1666             (0xa << 2)
+#define WINCON1_BPPMODE_24BPP_888               (0xb << 2)
+#define WINCON1_BPPMODE_24BPP_A1887             (0xc << 2)
+#define WINCON1_BPPMODE_25BPP_A1888             (0xd << 2)
+#define WINCON1_BPPMODE_28BPP_A4888             (0xd << 2)
+
+
+#define VIDOSDxA_TOPLEFT_X_MASK                 (0x7ff << 11)
+#define VIDOSDxA_TOPLEFT_X_SHIFT                (11)
+#define VIDOSDxA_TOPLEFT_X_LIMIT                (0x7ff)
+#define VIDOSDxA_TOPLEFT_X(_x)                  ((_x) << 11)
+
+#define VIDOSDxA_TOPLEFT_Y_MASK                 (0x7ff << 0)
+#define VIDOSDxA_TOPLEFT_Y_SHIFT                (0)
+#define VIDOSDxA_TOPLEFT_Y_LIMIT                (0x7ff)
+#define VIDOSDxA_TOPLEFT_Y(_x)                  ((_x) << 0)
+
+#define VIDOSDxB_BOTRIGHT_X_MASK                (0x7ff << 11)
+#define VIDOSDxB_BOTRIGHT_X_SHIFT               (11)
+#define VIDOSDxB_BOTRIGHT_X_LIMIT               (0x7ff)
+#define VIDOSDxB_BOTRIGHT_X(_x)                 ((_x) << 11)
+
+#define VIDOSDxB_BOTRIGHT_Y_MASK                (0x7ff << 0)
+#define VIDOSDxB_BOTRIGHT_Y_SHIFT               (0)
+#define VIDOSDxB_BOTRIGHT_Y_LIMIT               (0x7ff)
+#define VIDOSDxB_BOTRIGHT_Y(_x)                 ((_x) << 0)
+
+/* For VIDOSD[1..4]C */
+#define VIDISD14C_ALPHA0_R(_x)                  ((_x) << 20)
+#define VIDISD14C_ALPHA0_G_MASK                 (0xf << 16)
+#define VIDISD14C_ALPHA0_G_SHIFT                (16)
+#define VIDISD14C_ALPHA0_G_LIMIT                (0xf)
+#define VIDISD14C_ALPHA0_G(_x)                  ((_x) << 16)
+#define VIDISD14C_ALPHA0_B_MASK                 (0xf << 12)
+#define VIDISD14C_ALPHA0_B_SHIFT                (12)
+#define VIDISD14C_ALPHA0_B_LIMIT                (0xf)
+#define VIDISD14C_ALPHA0_B(_x)                  ((_x) << 12)
+#define VIDISD14C_ALPHA1_R_MASK                 (0xf << 8)
+#define VIDISD14C_ALPHA1_R_SHIFT                (8)
+#define VIDISD14C_ALPHA1_R_LIMIT                (0xf)
+#define VIDISD14C_ALPHA1_R(_x)                  ((_x) << 8)
+#define VIDISD14C_ALPHA1_G_MASK                 (0xf << 4)
+#define VIDISD14C_ALPHA1_G_SHIFT                (4)
+#define VIDISD14C_ALPHA1_G_LIMIT                (0xf)
+#define VIDISD14C_ALPHA1_G(_x)                  ((_x) << 4)
+#define VIDISD14C_ALPHA1_B_MASK                 (0xf << 0)
+#define VIDISD14C_ALPHA1_B_SHIFT                (0)
+#define VIDISD14C_ALPHA1_B_LIMIT                (0xf)
+#define VIDISD14C_ALPHA1_B(_x)                  ((_x) << 0)
+
+/* Video buffer addresses */
+#define VIDW_BUF_START(_buff)                   (0xA0 + ((_buff) * 8))
+#define VIDW_BUF_START1(_buff)                  (0xA4 + ((_buff) * 8))
+#define VIDW_BUF_END(_buff)                     (0xD0 + ((_buff) * 8))
+#define VIDW_BUF_END1(_buff)                    (0xD4 + ((_buff) * 8))
+#define VIDW_BUF_SIZE(_buff)                    (0x100 + ((_buff) * 4))
+
+#define VIDW_BUF_SIZE_OFFSET_MASK               (0x1fff << 13)
+#define VIDW_BUF_SIZE_OFFSET_SHIFT              (13)
+#define VIDW_BUF_SIZE_OFFSET_LIMIT              (0x1fff)
+#define VIDW_BUF_SIZE_OFFSET(_x)                ((_x) << 13)
+
+#define VIDW_BUF_SIZE_PAGEWIDTH_MASK            (0x1fff << 0)
+#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT           (0)
+#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT           (0x1fff)
+#define VIDW_BUF_SIZE_PAGEWIDTH(_x)             ((_x) << 0)
+
+/* Interrupt controls and status */
+
+#define VIDINTCON0_FIFOINTERVAL_MASK            (0x3f << 20)
+#define VIDINTCON0_FIFOINTERVAL_SHIFT           (20)
+#define VIDINTCON0_FIFOINTERVAL_LIMIT           (0x3f)
+#define VIDINTCON0_FIFOINTERVAL(_x)             ((_x) << 20)
+
+#define VIDINTCON0_INT_SYSMAINCON               (1 << 19)
+#define VIDINTCON0_INT_SYSSUBCON                (1 << 18)
+#define VIDINTCON0_INT_I80IFDONE                (1 << 17)
+
+#define VIDINTCON0_FRAMESEL0_MASK               (0x3 << 15)
+#define VIDINTCON0_FRAMESEL0_SHIFT              (15)
+#define VIDINTCON0_FRAMESEL0_BACKPORCH          (0x0 << 15)
+#define VIDINTCON0_FRAMESEL0_VSYNC              (0x1 << 15)
+#define VIDINTCON0_FRAMESEL0_ACTIVE             (0x2 << 15)
+#define VIDINTCON0_FRAMESEL0_FRONTPORCH         (0x3 << 15)
+
+#define VIDINTCON0_FRAMESEL1                    (1 << 14)
+#define VIDINTCON0_FRAMESEL1_NONE               (0x0 << 14)
+#define VIDINTCON0_FRAMESEL1_BACKPORCH          (0x1 << 14)
+#define VIDINTCON0_FRAMESEL1_VSYNC              (0x2 << 14)
+#define VIDINTCON0_FRAMESEL1_FRONTPORCH         (0x3 << 14)
+
+#define VIDINTCON0_INT_FRAME                    (1 << 12)
+#define VIDINTCON0_FIFIOSEL_MASK                (0x7f << 5)
+#define VIDINTCON0_FIFIOSEL_SHIFT               (5)
+#define VIDINTCON0_FIFIOSEL_WINDOW0             (0x1 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW1             (0x2 << 5)
+
+#define VIDINTCON0_FIFOLEVEL_MASK               (0x7 << 2)
+#define VIDINTCON0_FIFOLEVEL_SHIFT              (2)
+#define VIDINTCON0_FIFOLEVEL_TO25PC             (0x0 << 2)
+#define VIDINTCON0_FIFOLEVEL_TO50PC             (0x1 << 2)
+#define VIDINTCON0_FIFOLEVEL_TO75PC             (0x2 << 2)
+#define VIDINTCON0_FIFOLEVEL_EMPTY              (0x3 << 2)
+#define VIDINTCON0_FIFOLEVEL_FULL               (0x4 << 2)
+
+#define VIDINTCON0_INT_FIFO_MASK                (0x3 << 0)
+#define VIDINTCON0_INT_FIFO_SHIFT               (0)
+#define VIDINTCON0_INT_ENABLE                   (1 << 0)
+
+#define VIDINTCON1                              (0x134)
+#define VIDINTCON1_INT_I180                     (1 << 2)
+#define VIDINTCON1_INT_FRAME                    (1 << 1)
+#define VIDINTCON1_INT_FIFO                     (1 << 0)
+
+/* Window colour-key control registers */
+
+#define WxKEYCON0_KEYBL_EN                      (1 << 26)
+#define WxKEYCON0_KEYEN_F                       (1 << 25)
+#define WxKEYCON0_DIRCON                        (1 << 24)
+#define WxKEYCON0_COMPKEY_MASK                  (0xffffff << 0)
+#define WxKEYCON0_COMPKEY_SHIFT                 (0)
+#define WxKEYCON0_COMPKEY_LIMIT                 (0xffffff)
+#define WxKEYCON0_COMPKEY(_x)                   ((_x) << 0)
+#define WxKEYCON1_COLVAL_MASK                   (0xffffff << 0)
+#define WxKEYCON1_COLVAL_SHIFT                  (0)
+#define WxKEYCON1_COLVAL_LIMIT                  (0xffffff)
+#define WxKEYCON1_COLVAL(_x)                    ((_x) << 0)
+
+
+/* Window blanking (MAP) */
+
+#define WINxMAP_MAP                             (1 << 24)
+#define WINxMAP_MAP_COLOUR_MASK                 (0xffffff << 0)
+#define WINxMAP_MAP_COLOUR_SHIFT                (0)
+#define WINxMAP_MAP_COLOUR_LIMIT                (0xffffff)
+#define WINxMAP_MAP_COLOUR(_x)                  ((_x) << 0)
+
+#define WPALCON_PAL_UPDATE                      (1 << 9)
+#define WPALCON_W1PAL_MASK                      (0x7 << 3)
+#define WPALCON_W1PAL_SHIFT                     (3)
+#define WPALCON_W1PAL_25BPP_A888                (0x0 << 3)
+#define WPALCON_W1PAL_24BPP                     (0x1 << 3)
+#define WPALCON_W1PAL_19BPP_A666                (0x2 << 3)
+#define WPALCON_W1PAL_18BPP_A665                (0x3 << 3)
+#define WPALCON_W1PAL_18BPP                     (0x4 << 3)
+#define WPALCON_W1PAL_16BPP_A555                (0x5 << 3)
+#define WPALCON_W1PAL_16BPP_565                 (0x6 << 3)
+
+#define WPALCON_W0PAL_MASK                      (0x7 << 0)
+#define WPALCON_W0PAL_SHIFT                     (0)
+#define WPALCON_W0PAL_25BPP_A888                (0x0 << 0)
+#define WPALCON_W0PAL_24BPP                     (0x1 << 0)
+#define WPALCON_W0PAL_19BPP_A666                (0x2 << 0)
+#define WPALCON_W0PAL_18BPP_A665                (0x3 << 0)
+#define WPALCON_W0PAL_18BPP                     (0x4 << 0)
+#define WPALCON_W0PAL_16BPP_A555                (0x5 << 0)
+#define WPALCON_W0PAL_16BPP_565                 (0x6 << 0)
+
diff --git a/arch/arm/plat-samsung/include/plat/regs-iic.h b/arch/arm/plat-samsung/include/plat/regs-iic.h
new file mode 100644
index 000000000000..2f7c17de8ac8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-iic.h
@@ -0,0 +1,56 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 I2C Controller
+*/
+
+#ifndef __ASM_ARCH_REGS_IIC_H
+#define __ASM_ARCH_REGS_IIC_H __FILE__
+
+/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
+
+#define S3C2410_IICREG(x) (x)
+
+#define S3C2410_IICCON    S3C2410_IICREG(0x00)
+#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
+#define S3C2410_IICADD    S3C2410_IICREG(0x08)
+#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
+#define S3C2440_IICLC     S3C2410_IICREG(0x10)
+
+#define S3C2410_IICCON_ACKEN            (1<<7)
+#define S3C2410_IICCON_TXDIV_16         (0<<6)
+#define S3C2410_IICCON_TXDIV_512        (1<<6)
+#define S3C2410_IICCON_IRQEN            (1<<5)
+#define S3C2410_IICCON_IRQPEND          (1<<4)
+#define S3C2410_IICCON_SCALE(x)         ((x)&15)
+#define S3C2410_IICCON_SCALEMASK        (0xf)
+
+#define S3C2410_IICSTAT_MASTER_RX       (2<<6)
+#define S3C2410_IICSTAT_MASTER_TX       (3<<6)
+#define S3C2410_IICSTAT_SLAVE_RX        (0<<6)
+#define S3C2410_IICSTAT_SLAVE_TX        (1<<6)
+#define S3C2410_IICSTAT_MODEMASK        (3<<6)
+
+#define S3C2410_IICSTAT_START           (1<<5)
+#define S3C2410_IICSTAT_BUSBUSY         (1<<5)
+#define S3C2410_IICSTAT_TXRXEN          (1<<4)
+#define S3C2410_IICSTAT_ARBITR          (1<<3)
+#define S3C2410_IICSTAT_ASSLAVE         (1<<2)
+#define S3C2410_IICSTAT_ADDR0           (1<<1)
+#define S3C2410_IICSTAT_LASTBIT         (1<<0)
+
+#define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
+#define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
+#define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
+#define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
+#define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
+
+#define S3C2410_IICLC_FILTER_ON         (1<<2)
+
+#endif /* __ASM_ARCH_REGS_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-irqtype.h b/arch/arm/plat-samsung/include/plat/regs-irqtype.h
new file mode 100644
index 000000000000..c63cd3fc5ad3
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-irqtype.h
@@ -0,0 +1,21 @@
+/* arch/arm/plat-s3c/include/plat/regs-irqtype.h
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C - IRQ detection types.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including
+ * the S3C64XX
+*/
+#define S3C2410_EXTINT_LOWLEV    (0x00)
+#define S3C2410_EXTINT_HILEV     (0x01)
+#define S3C2410_EXTINT_FALLEDGE  (0x02)
+#define S3C2410_EXTINT_RISEEDGE  (0x04)
+#define S3C2410_EXTINT_BOTHEDGE  (0x06)
diff --git a/arch/arm/plat-samsung/include/plat/regs-nand.h b/arch/arm/plat-samsung/include/plat/regs-nand.h
new file mode 100644
index 000000000000..238efea7b9e4
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-nand.h
@@ -0,0 +1,123 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
+ *
+ * Copyright (c) 2004-2005 Simtec Electronics <linux@simtec.co.uk>
+ *      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 NAND register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_NAND
+#define __ASM_ARM_REGS_NAND
+
+
+#define S3C2410_NFREG(x) (x)
+
+#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
+#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
+#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
+#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
+#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
+#define S3C2410_NFECC   S3C2410_NFREG(0x14)
+
+#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
+#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
+#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
+#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
+#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
+#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
+#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
+#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
+#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
+#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
+#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
+#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
+#define S3C2440_NFSECC   S3C2410_NFREG(0x34)
+#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
+#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
+
+#define S3C2412_NFSBLK          S3C2410_NFREG(0x20)
+#define S3C2412_NFEBLK          S3C2410_NFREG(0x24)
+#define S3C2412_NFSTAT          S3C2410_NFREG(0x28)
+#define S3C2412_NFMECC_ERR0     S3C2410_NFREG(0x2C)
+#define S3C2412_NFMECC_ERR1     S3C2410_NFREG(0x30)
+#define S3C2412_NFMECC0         S3C2410_NFREG(0x34)
+#define S3C2412_NFMECC1         S3C2410_NFREG(0x38)
+#define S3C2412_NFSECC          S3C2410_NFREG(0x3C)
+
+#define S3C2410_NFCONF_EN          (1<<15)
+#define S3C2410_NFCONF_512BYTE     (1<<14)
+#define S3C2410_NFCONF_4STEP       (1<<13)
+#define S3C2410_NFCONF_INITECC     (1<<12)
+#define S3C2410_NFCONF_nFCE        (1<<11)
+#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
+#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
+#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
+
+#define S3C2410_NFSTAT_BUSY        (1<<0)
+
+#define S3C2440_NFCONF_BUSWIDTH_8       (0<<0)
+#define S3C2440_NFCONF_BUSWIDTH_16      (1<<0)
+#define S3C2440_NFCONF_ADVFLASH         (1<<3)
+#define S3C2440_NFCONF_TACLS(x)         ((x)<<12)
+#define S3C2440_NFCONF_TWRPH0(x)        ((x)<<8)
+#define S3C2440_NFCONF_TWRPH1(x)        ((x)<<4)
+
+#define S3C2440_NFCONT_LOCKTIGHT        (1<<13)
+#define S3C2440_NFCONT_SOFTLOCK         (1<<12)
+#define S3C2440_NFCONT_ILLEGALACC_EN    (1<<10)
+#define S3C2440_NFCONT_RNBINT_EN        (1<<9)
+#define S3C2440_NFCONT_RN_FALLING       (1<<8)
+#define S3C2440_NFCONT_SPARE_ECCLOCK    (1<<6)
+#define S3C2440_NFCONT_MAIN_ECCLOCK     (1<<5)
+#define S3C2440_NFCONT_INITECC          (1<<4)
+#define S3C2440_NFCONT_nFCE             (1<<1)
+#define S3C2440_NFCONT_ENABLE           (1<<0)
+
+#define S3C2440_NFSTAT_READY            (1<<0)
+#define S3C2440_NFSTAT_nCE              (1<<1)
+#define S3C2440_NFSTAT_RnB_CHANGE       (1<<2)
+#define S3C2440_NFSTAT_ILLEGAL_ACCESS   (1<<3)
+
+#define S3C2412_NFCONF_NANDBOOT         (1<<31)
+#define S3C2412_NFCONF_ECCCLKCON        (1<<30)
+#define S3C2412_NFCONF_ECC_MLC          (1<<24)
+#define S3C2412_NFCONF_TACLS_MASK       (7<<12) /* 1 extra bit of Tacls */
+
+#define S3C2412_NFCONT_ECC4_DIRWR       (1<<18)
+#define S3C2412_NFCONT_LOCKTIGHT        (1<<17)
+#define S3C2412_NFCONT_SOFTLOCK         (1<<16)
+#define S3C2412_NFCONT_ECC4_ENCINT      (1<<13)
+#define S3C2412_NFCONT_ECC4_DECINT      (1<<12)
+#define S3C2412_NFCONT_MAIN_ECC_LOCK    (1<<7)
+#define S3C2412_NFCONT_INIT_MAIN_ECC    (1<<5)
+#define S3C2412_NFCONT_nFCE1            (1<<2)
+#define S3C2412_NFCONT_nFCE0            (1<<1)
+
+#define S3C2412_NFSTAT_ECC_ENCDONE      (1<<7)
+#define S3C2412_NFSTAT_ECC_DECDONE      (1<<6)
+#define S3C2412_NFSTAT_ILLEGAL_ACCESS   (1<<5)
+#define S3C2412_NFSTAT_RnB_CHANGE       (1<<4)
+#define S3C2412_NFSTAT_nFCE1            (1<<3)
+#define S3C2412_NFSTAT_nFCE0            (1<<2)
+#define S3C2412_NFSTAT_Res1             (1<<1)
+#define S3C2412_NFSTAT_READY            (1<<0)
+
+#define S3C2412_NFECCERR_SERRDATA(x)    (((x) >> 21) & 0xf)
+#define S3C2412_NFECCERR_SERRBIT(x)     (((x) >> 18) & 0x7)
+#define S3C2412_NFECCERR_MERRDATA(x)    (((x) >> 7) & 0x3ff)
+#define S3C2412_NFECCERR_MERRBIT(x)     (((x) >> 4) & 0x7)
+#define S3C2412_NFECCERR_SPARE_ERR(x)   (((x) >> 2) & 0x3)
+#define S3C2412_NFECCERR_MAIN_ERR(x)    (((x) >> 2) & 0x3)
+#define S3C2412_NFECCERR_NONE           (0)
+#define S3C2412_NFECCERR_1BIT           (1)
+#define S3C2412_NFECCERR_MULTIBIT       (2)
+#define S3C2412_NFECCERR_ECCAREA        (3)
+
+
+
+#endif /* __ASM_ARM_REGS_NAND */
+
diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h
new file mode 100644
index 000000000000..d5837cf8e402
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h
@@ -0,0 +1,61 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Internal RTC register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_RTC_H
+#define __ASM_ARCH_REGS_RTC_H __FILE__
+
+#define S3C2410_RTCREG(x) (x)
+
+#define S3C2410_RTCCON        S3C2410_RTCREG(0x40)
+#define S3C2410_RTCCON_RTCEN  (1<<0)
+#define S3C2410_RTCCON_CLKSEL (1<<1)
+#define S3C2410_RTCCON_CNTSEL (1<<2)
+#define S3C2410_RTCCON_CLKRST (1<<3)
+
+#define S3C2410_TICNT         S3C2410_RTCREG(0x44)
+#define S3C2410_TICNT_ENABLE  (1<<7)
+
+#define S3C2410_RTCALM        S3C2410_RTCREG(0x50)
+#define S3C2410_RTCALM_ALMEN  (1<<6)
+#define S3C2410_RTCALM_YEAREN (1<<5)
+#define S3C2410_RTCALM_MONEN  (1<<4)
+#define S3C2410_RTCALM_DAYEN  (1<<3)
+#define S3C2410_RTCALM_HOUREN (1<<2)
+#define S3C2410_RTCALM_MINEN  (1<<1)
+#define S3C2410_RTCALM_SECEN  (1<<0)
+
+#define S3C2410_RTCALM_ALL \
+  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
+  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
+  S3C2410_RTCALM_SECEN
+
+
+#define S3C2410_ALMSEC        S3C2410_RTCREG(0x54)
+#define S3C2410_ALMMIN        S3C2410_RTCREG(0x58)
+#define S3C2410_ALMHOUR       S3C2410_RTCREG(0x5c)
+
+#define S3C2410_ALMDATE       S3C2410_RTCREG(0x60)
+#define S3C2410_ALMMON        S3C2410_RTCREG(0x64)
+#define S3C2410_ALMYEAR       S3C2410_RTCREG(0x68)
+
+#define S3C2410_RTCRST        S3C2410_RTCREG(0x6c)
+
+#define S3C2410_RTCSEC        S3C2410_RTCREG(0x70)
+#define S3C2410_RTCMIN        S3C2410_RTCREG(0x74)
+#define S3C2410_RTCHOUR       S3C2410_RTCREG(0x78)
+#define S3C2410_RTCDATE       S3C2410_RTCREG(0x7c)
+#define S3C2410_RTCDAY        S3C2410_RTCREG(0x80)
+#define S3C2410_RTCMON        S3C2410_RTCREG(0x84)
+#define S3C2410_RTCYEAR       S3C2410_RTCREG(0x88)
+
+
+#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h
new file mode 100644
index 000000000000..abf2fbc2eb2f
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h
@@ -0,0 +1,82 @@
+/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
+ *
+ * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2412 IIS register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
+#define __ASM_ARCH_REGS_S3C2412_IIS_H
+
+#define S3C2412_IISCON                  (0x00)
+#define S3C2412_IISMOD                  (0x04)
+#define S3C2412_IISFIC                  (0x08)
+#define S3C2412_IISPSR                  (0x0C)
+#define S3C2412_IISTXD                  (0x10)
+#define S3C2412_IISRXD                  (0x14)
+
+#define S3C2412_IISCON_LRINDEX          (1 << 11)
+#define S3C2412_IISCON_TXFIFO_EMPTY     (1 << 10)
+#define S3C2412_IISCON_RXFIFO_EMPTY     (1 << 9)
+#define S3C2412_IISCON_TXFIFO_FULL      (1 << 8)
+#define S3C2412_IISCON_RXFIFO_FULL      (1 << 7)
+#define S3C2412_IISCON_TXDMA_PAUSE      (1 << 6)
+#define S3C2412_IISCON_RXDMA_PAUSE      (1 << 5)
+#define S3C2412_IISCON_TXCH_PAUSE       (1 << 4)
+#define S3C2412_IISCON_RXCH_PAUSE       (1 << 3)
+#define S3C2412_IISCON_TXDMA_ACTIVE     (1 << 2)
+#define S3C2412_IISCON_RXDMA_ACTIVE     (1 << 1)
+#define S3C2412_IISCON_IIS_ACTIVE       (1 << 0)
+
+#define S3C64XX_IISMOD_BLC_16BIT        (0 << 13)
+#define S3C64XX_IISMOD_BLC_8BIT         (1 << 13)
+#define S3C64XX_IISMOD_BLC_24BIT        (2 << 13)
+#define S3C64XX_IISMOD_BLC_MASK         (3 << 13)
+
+#define S3C64XX_IISMOD_IMS_PCLK         (0 << 10)
+#define S3C64XX_IISMOD_IMS_SYSMUX       (1 << 10)
+
+#define S3C2412_IISMOD_MASTER_INTERNAL  (0 << 10)
+#define S3C2412_IISMOD_MASTER_EXTERNAL  (1 << 10)
+#define S3C2412_IISMOD_SLAVE            (2 << 10)
+#define S3C2412_IISMOD_MASTER_MASK      (3 << 10)
+#define S3C2412_IISMOD_MODE_TXONLY      (0 << 8)
+#define S3C2412_IISMOD_MODE_RXONLY      (1 << 8)
+#define S3C2412_IISMOD_MODE_TXRX        (2 << 8)
+#define S3C2412_IISMOD_MODE_MASK        (3 << 8)
+#define S3C2412_IISMOD_LR_LLOW          (0 << 7)
+#define S3C2412_IISMOD_LR_RLOW          (1 << 7)
+#define S3C2412_IISMOD_SDF_IIS          (0 << 5)
+#define S3C2412_IISMOD_SDF_MSB          (1 << 5)
+#define S3C2412_IISMOD_SDF_LSB          (2 << 5)
+#define S3C2412_IISMOD_SDF_MASK         (3 << 5)
+#define S3C2412_IISMOD_RCLK_256FS       (0 << 3)
+#define S3C2412_IISMOD_RCLK_512FS       (1 << 3)
+#define S3C2412_IISMOD_RCLK_384FS       (2 << 3)
+#define S3C2412_IISMOD_RCLK_768FS       (3 << 3)
+#define S3C2412_IISMOD_RCLK_MASK        (3 << 3)
+#define S3C2412_IISMOD_BCLK_32FS        (0 << 1)
+#define S3C2412_IISMOD_BCLK_48FS        (1 << 1)
+#define S3C2412_IISMOD_BCLK_16FS        (2 << 1)
+#define S3C2412_IISMOD_BCLK_24FS        (3 << 1)
+#define S3C2412_IISMOD_BCLK_MASK        (3 << 1)
+#define S3C2412_IISMOD_8BIT             (1 << 0)
+
+#define S3C64XX_IISMOD_CDCLKCON         (1 << 12)
+
+#define S3C2412_IISPSR_PSREN            (1 << 15)
+
+#define S3C2412_IISFIC_TXFLUSH          (1 << 15)
+#define S3C2412_IISFIC_RXFLUSH          (1 << 7)
+#define S3C2412_IISFIC_TXCOUNT(x)       (((x) >>  8) & 0xf)
+#define S3C2412_IISFIC_RXCOUNT(x)       (((x) >>  0) & 0xf)
+
+
+
+#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
+
diff --git a/arch/arm/plat-samsung/include/plat/regs-sdhci.h b/arch/arm/plat-samsung/include/plat/regs-sdhci.h
new file mode 100644
index 000000000000..e34049ad44cc
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-sdhci.h
@@ -0,0 +1,87 @@
+/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - SDHCI (HSMMC) register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C_SDHCI_REGS_H
+#define __PLAT_S3C_SDHCI_REGS_H __FILE__
+
+#define S3C_SDHCI_CONTROL2                      (0x80)
+#define S3C_SDHCI_CONTROL3                      (0x84)
+#define S3C64XX_SDHCI_CONTROL4                  (0x8C)
+
+#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR       (1 << 31)
+#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK         (1 << 30)
+#define S3C_SDHCI_CTRL2_CDINVRXD3               (1 << 29)
+#define S3C_SDHCI_CTRL2_SLCARDOUT               (1 << 28)
+
+#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK          (0xf << 24)
+#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT         (24)
+#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x)           ((_x) << 24)
+
+#define S3C_SDHCI_CTRL2_LVLDAT_MASK             (0xff << 16)
+#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT            (16)
+#define S3C_SDHCI_CTRL2_LVLDAT(_x)              ((_x) << 16)
+
+#define S3C_SDHCI_CTRL2_ENFBCLKTX               (1 << 15)
+#define S3C_SDHCI_CTRL2_ENFBCLKRX               (1 << 14)
+#define S3C_SDHCI_CTRL2_SDCDSEL                 (1 << 13)
+#define S3C_SDHCI_CTRL2_SDSIGPC                 (1 << 12)
+#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART        (1 << 11)
+
+#define S3C_SDHCI_CTRL2_DFCNT_MASK              (0x3 << 9)
+#define S3C_SDHCI_CTRL2_DFCNT_SHIFT             (9)
+#define S3C_SDHCI_CTRL2_DFCNT_NONE              (0x0 << 9)
+#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK            (0x1 << 9)
+#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK           (0x2 << 9)
+#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK           (0x3 << 9)
+
+#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD            (1 << 8)
+#define S3C_SDHCI_CTRL2_RWAITMODE               (1 << 7)
+#define S3C_SDHCI_CTRL2_DISBUFRD                (1 << 6)
+#define S3C_SDHCI_CTRL2_SELBASECLK_MASK         (0x3 << 4)
+#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT        (4)
+#define S3C_SDHCI_CTRL2_PWRSYNC                 (1 << 3)
+#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON          (1 << 1)
+#define S3C_SDHCI_CTRL2_HWINITFIN               (1 << 0)
+
+#define S3C_SDHCI_CTRL3_FCSEL3                  (1 << 31)
+#define S3C_SDHCI_CTRL3_FCSEL2                  (1 << 23)
+#define S3C_SDHCI_CTRL3_FCSEL1                  (1 << 15)
+#define S3C_SDHCI_CTRL3_FCSEL0                  (1 << 7)
+
+#define S3C_SDHCI_CTRL3_FIA3_MASK               (0x7f << 24)
+#define S3C_SDHCI_CTRL3_FIA3_SHIFT              (24)
+#define S3C_SDHCI_CTRL3_FIA3(_x)                ((_x) << 24)
+
+#define S3C_SDHCI_CTRL3_FIA2_MASK               (0x7f << 16)
+#define S3C_SDHCI_CTRL3_FIA2_SHIFT              (16)
+#define S3C_SDHCI_CTRL3_FIA2(_x)                ((_x) << 16)
+
+#define S3C_SDHCI_CTRL3_FIA1_MASK               (0x7f << 8)
+#define S3C_SDHCI_CTRL3_FIA1_SHIFT              (8)
+#define S3C_SDHCI_CTRL3_FIA1(_x)                ((_x) << 8)
+
+#define S3C_SDHCI_CTRL3_FIA0_MASK               (0x7f << 0)
+#define S3C_SDHCI_CTRL3_FIA0_SHIFT              (0)
+#define S3C_SDHCI_CTRL3_FIA0(_x)                ((_x) << 0)
+
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK       (0x3 << 16)
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT      (16)
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA        (0x0 << 16)
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA        (0x1 << 16)
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA        (0x2 << 16)
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA        (0x3 << 16)
+
+#define S3C64XX_SDHCI_CONTROL4_BUSY             (1)
+
+#endif /* __PLAT_S3C_SDHCI_REGS_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
new file mode 100644
index 000000000000..a6eba8496b24
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -0,0 +1,281 @@
+/* arch/arm/plat-samsung/include/plat/regs-serial.h
+ *
+ *  From linux/include/asm-arm/hardware/serial_s3c2410.h
+ *
+ *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
+ *
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ *  Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
+ *
+ *  Adapted from:
+ *
+ *  Internal header file for MX1ADS serial ports (UART1 & 2)
+ *
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef __ASM_ARM_REGS_SERIAL_H
+#define __ASM_ARM_REGS_SERIAL_H
+
+#define S3C24XX_VA_UART0      (S3C_VA_UART)
+#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
+#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
+#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )
+
+#define S3C2410_PA_UART0      (S3C24XX_PA_UART)
+#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
+#define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
+#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
+
+#define S3C2410_URXH      (0x24)
+#define S3C2410_UTXH      (0x20)
+#define S3C2410_ULCON     (0x00)
+#define S3C2410_UCON      (0x04)
+#define S3C2410_UFCON     (0x08)
+#define S3C2410_UMCON     (0x0C)
+#define S3C2410_UBRDIV    (0x28)
+#define S3C2410_UTRSTAT   (0x10)
+#define S3C2410_UERSTAT   (0x14)
+#define S3C2410_UFSTAT    (0x18)
+#define S3C2410_UMSTAT    (0x1C)
+
+#define S3C2410_LCON_CFGMASK      ((0xF<<3)|(0x3))
+
+#define S3C2410_LCON_CS5          (0x0)
+#define S3C2410_LCON_CS6          (0x1)
+#define S3C2410_LCON_CS7          (0x2)
+#define S3C2410_LCON_CS8          (0x3)
+#define S3C2410_LCON_CSMASK       (0x3)
+
+#define S3C2410_LCON_PNONE        (0x0)
+#define S3C2410_LCON_PEVEN        (0x5 << 3)
+#define S3C2410_LCON_PODD         (0x4 << 3)
+#define S3C2410_LCON_PMASK        (0x7 << 3)
+
+#define S3C2410_LCON_STOPB        (1<<2)
+#define S3C2410_LCON_IRM          (1<<6)
+
+#define S3C2440_UCON_CLKMASK      (3<<10)
+#define S3C2440_UCON_PCLK         (0<<10)
+#define S3C2440_UCON_UCLK         (1<<10)
+#define S3C2440_UCON_PCLK2        (2<<10)
+#define S3C2440_UCON_FCLK         (3<<10)
+#define S3C2443_UCON_EPLL         (3<<10)
+
+#define S3C6400_UCON_CLKMASK    (3<<10)
+#define S3C6400_UCON_PCLK       (0<<10)
+#define S3C6400_UCON_PCLK2      (2<<10)
+#define S3C6400_UCON_UCLK0      (1<<10)
+#define S3C6400_UCON_UCLK1      (3<<10)
+
+#define S3C2440_UCON2_FCLK_EN     (1<<15)
+#define S3C2440_UCON0_DIVMASK     (15 << 12)
+#define S3C2440_UCON1_DIVMASK     (15 << 12)
+#define S3C2440_UCON2_DIVMASK     (7 << 12)
+#define S3C2440_UCON_DIVSHIFT     (12)
+
+#define S3C2412_UCON_CLKMASK    (3<<10)
+#define S3C2412_UCON_UCLK       (1<<10)
+#define S3C2412_UCON_USYSCLK    (3<<10)
+#define S3C2412_UCON_PCLK       (0<<10)
+#define S3C2412_UCON_PCLK2      (2<<10)
+
+#define S3C2410_UCON_UCLK         (1<<10)
+#define S3C2410_UCON_SBREAK       (1<<4)
+
+#define S3C2410_UCON_TXILEVEL     (1<<9)
+#define S3C2410_UCON_RXILEVEL     (1<<8)
+#define S3C2410_UCON_TXIRQMODE    (1<<2)
+#define S3C2410_UCON_RXIRQMODE    (1<<0)
+#define S3C2410_UCON_RXFIFO_TOI   (1<<7)
+#define S3C2443_UCON_RXERR_IRQEN  (1<<6)
+#define S3C2443_UCON_LOOPBACK     (1<<5)
+
+#define S3C2410_UCON_DEFAULT      (S3C2410_UCON_TXILEVEL  | \
+                                   S3C2410_UCON_RXILEVEL  | \
+                                   S3C2410_UCON_TXIRQMODE | \
+                                   S3C2410_UCON_RXIRQMODE | \
+                                   S3C2410_UCON_RXFIFO_TOI)
+
+#define S3C2410_UFCON_FIFOMODE    (1<<0)
+#define S3C2410_UFCON_TXTRIG0     (0<<6)
+#define S3C2410_UFCON_RXTRIG8     (1<<4)
+#define S3C2410_UFCON_RXTRIG12    (2<<4)
+
+/* S3C2440 FIFO trigger levels */
+#define S3C2440_UFCON_RXTRIG1     (0<<4)
+#define S3C2440_UFCON_RXTRIG8     (1<<4)
+#define S3C2440_UFCON_RXTRIG16    (2<<4)
+#define S3C2440_UFCON_RXTRIG32    (3<<4)
+
+#define S3C2440_UFCON_TXTRIG0     (0<<6)
+#define S3C2440_UFCON_TXTRIG16    (1<<6)
+#define S3C2440_UFCON_TXTRIG32    (2<<6)
+#define S3C2440_UFCON_TXTRIG48    (3<<6)
+
+#define S3C2410_UFCON_RESETBOTH   (3<<1)
+#define S3C2410_UFCON_RESETTX     (1<<2)
+#define S3C2410_UFCON_RESETRX     (1<<1)
+
+#define S3C2410_UFCON_DEFAULT     (S3C2410_UFCON_FIFOMODE | \
+                                   S3C2410_UFCON_TXTRIG0  | \
+                                   S3C2410_UFCON_RXTRIG8 )
+
+#define S3C2410_UMCOM_AFC         (1<<4)
+#define S3C2410_UMCOM_RTS_LOW     (1<<0)
+
+#define S3C2412_UMCON_AFC_63    (0<<5)          /* same as s3c2443 */
+#define S3C2412_UMCON_AFC_56    (1<<5)
+#define S3C2412_UMCON_AFC_48    (2<<5)
+#define S3C2412_UMCON_AFC_40    (3<<5)
+#define S3C2412_UMCON_AFC_32    (4<<5)
+#define S3C2412_UMCON_AFC_24    (5<<5)
+#define S3C2412_UMCON_AFC_16    (6<<5)
+#define S3C2412_UMCON_AFC_8     (7<<5)
+
+#define S3C2410_UFSTAT_TXFULL     (1<<9)
+#define S3C2410_UFSTAT_RXFULL     (1<<8)
+#define S3C2410_UFSTAT_TXMASK     (15<<4)
+#define S3C2410_UFSTAT_TXSHIFT    (4)
+#define S3C2410_UFSTAT_RXMASK     (15<<0)
+#define S3C2410_UFSTAT_RXSHIFT    (0)
+
+/* UFSTAT S3C24A0 */
+#define S3C24A0_UFSTAT_TXFULL     (1 << 14)
+#define S3C24A0_UFSTAT_RXFULL     (1 << 6)
+#define S3C24A0_UFSTAT_TXMASK     (63 << 8)
+#define S3C24A0_UFSTAT_TXSHIFT    (8)
+#define S3C24A0_UFSTAT_RXMASK     (63)
+#define S3C24A0_UFSTAT_RXSHIFT    (0)
+
+/* UFSTAT S3C2443 same as S3C2440 */
+#define S3C2440_UFSTAT_TXFULL     (1<<14)
+#define S3C2440_UFSTAT_RXFULL     (1<<6)
+#define S3C2440_UFSTAT_TXSHIFT    (8)
+#define S3C2440_UFSTAT_RXSHIFT    (0)
+#define S3C2440_UFSTAT_TXMASK     (63<<8)
+#define S3C2440_UFSTAT_RXMASK     (63)
+
+#define S3C2410_UTRSTAT_TXE       (1<<2)
+#define S3C2410_UTRSTAT_TXFE      (1<<1)
+#define S3C2410_UTRSTAT_RXDR      (1<<0)
+
+#define S3C2410_UERSTAT_OVERRUN   (1<<0)
+#define S3C2410_UERSTAT_FRAME     (1<<2)
+#define S3C2410_UERSTAT_BREAK     (1<<3)
+#define S3C2443_UERSTAT_PARITY    (1<<1)
+
+#define S3C2410_UERSTAT_ANY       (S3C2410_UERSTAT_OVERRUN | \
+                                   S3C2410_UERSTAT_FRAME | \
+                                   S3C2410_UERSTAT_BREAK)
+
+#define S3C2410_UMSTAT_CTS        (1<<0)
+#define S3C2410_UMSTAT_DeltaCTS   (1<<2)
+
+#define S3C2443_DIVSLOT           (0x2C)
+
+/* S3C64XX interrupt registers. */
+#define S3C64XX_UINTP           0x30
+#define S3C64XX_UINTSP          0x34
+#define S3C64XX_UINTM           0x38
+
+/* Following are specific to S5PV210 and S5P6442 */
+#define S5PV210_UCON_CLKMASK    (1<<10)
+#define S5PV210_UCON_PCLK       (0<<10)
+#define S5PV210_UCON_UCLK       (1<<10)
+
+#define S5PV210_UFCON_TXTRIG0   (0<<8)
+#define S5PV210_UFCON_TXTRIG4   (1<<8)
+#define S5PV210_UFCON_TXTRIG8   (2<<8)
+#define S5PV210_UFCON_TXTRIG16  (3<<8)
+#define S5PV210_UFCON_TXTRIG32  (4<<8)
+#define S5PV210_UFCON_TXTRIG64  (5<<8)
+#define S5PV210_UFCON_TXTRIG128 (6<<8)
+#define S5PV210_UFCON_TXTRIG256 (7<<8)
+
+#define S5PV210_UFCON_RXTRIG1   (0<<4)
+#define S5PV210_UFCON_RXTRIG4   (1<<4)
+#define S5PV210_UFCON_RXTRIG8   (2<<4)
+#define S5PV210_UFCON_RXTRIG16  (3<<4)
+#define S5PV210_UFCON_RXTRIG32  (4<<4)
+#define S5PV210_UFCON_RXTRIG64  (5<<4)
+#define S5PV210_UFCON_RXTRIG128 (6<<4)
+#define S5PV210_UFCON_RXTRIG256 (7<<4)
+
+#define S5PV210_UFSTAT_TXFULL   (1<<24)
+#define S5PV210_UFSTAT_RXFULL   (1<<8)
+#define S5PV210_UFSTAT_TXMASK   (255<<16)
+#define S5PV210_UFSTAT_TXSHIFT  (16)
+#define S5PV210_UFSTAT_RXMASK   (255<<0)
+#define S5PV210_UFSTAT_RXSHIFT  (0)
+
+#ifndef __ASSEMBLY__
+
+/* struct s3c24xx_uart_clksrc
+ *
+ * this structure defines a named clock source that can be used for the
+ * uart, so that the best clock can be selected for the requested baud
+ * rate.
+ *
+ * min_baud and max_baud define the range of baud-rates this clock is
+ * acceptable for, if they are both zero, it is assumed any baud rate that
+ * can be generated from this clock will be used.
+ *
+ * divisor gives the divisor from the clock to the one seen by the uart
+*/
+
+struct s3c24xx_uart_clksrc {
+        const char      *name;
+        unsigned int     divisor;
+        unsigned int     min_baud;
+        unsigned int     max_baud;
+};
+
+/* configuration structure for per-machine configurations for the
+ * serial port
+ *
+ * the pointer is setup by the machine specific initialisation from the
+ * arch/arm/mach-s3c2410/ directory.
+*/
+
+struct s3c2410_uartcfg {
+        unsigned char      hwport;       /* hardware port number */
+        unsigned char      unused;
+        unsigned short     flags;
+        upf_t              uart_flags;   /* default uart flags */
+
+        unsigned long      ucon;         /* value of ucon for port */
+        unsigned long      ulcon;        /* value of ulcon for port */
+        unsigned long      ufcon;        /* value of ufcon for port */
+
+        struct s3c24xx_uart_clksrc *clocks;
+        unsigned int                clocks_size;
+};
+
+/* s3c24xx_uart_devs
+ *
+ * this is exported from the core as we cannot use driver_register(),
+ * or platform_add_device() before the console_initcall()
+*/
+
+extern struct platform_device *s3c24xx_uart_devs[4];
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_REGS_SERIAL_H */
+
diff --git a/arch/arm/plat-samsung/include/plat/regs-timer.h b/arch/arm/plat-samsung/include/plat/regs-timer.h
new file mode 100644
index 000000000000..d097d92f8cc7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-timer.h
@@ -0,0 +1,124 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Timer configuration
+*/
+
+#ifndef __ASM_ARCH_REGS_TIMER_H
+#define __ASM_ARCH_REGS_TIMER_H
+
+#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
+#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
+
+#define S3C2410_TCFG0         S3C_TIMERREG(0x00)
+#define S3C2410_TCFG1         S3C_TIMERREG(0x04)
+#define S3C2410_TCON          S3C_TIMERREG(0x08)
+
+#define S3C64XX_TINT_CSTAT    S3C_TIMERREG(0x44)
+
+#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
+#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
+#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
+#define S3C2410_TCFG_DEADZONE_MASK   (255<<16)
+#define S3C2410_TCFG_DEADZONE_SHIFT  (16)
+
+#define S3C2410_TCFG1_MUX4_DIV2   (0<<16)
+#define S3C2410_TCFG1_MUX4_DIV4   (1<<16)
+#define S3C2410_TCFG1_MUX4_DIV8   (2<<16)
+#define S3C2410_TCFG1_MUX4_DIV16  (3<<16)
+#define S3C2410_TCFG1_MUX4_TCLK1  (4<<16)
+#define S3C2410_TCFG1_MUX4_MASK   (15<<16)
+#define S3C2410_TCFG1_MUX4_SHIFT  (16)
+
+#define S3C2410_TCFG1_MUX3_DIV2   (0<<12)
+#define S3C2410_TCFG1_MUX3_DIV4   (1<<12)
+#define S3C2410_TCFG1_MUX3_DIV8   (2<<12)
+#define S3C2410_TCFG1_MUX3_DIV16  (3<<12)
+#define S3C2410_TCFG1_MUX3_TCLK1  (4<<12)
+#define S3C2410_TCFG1_MUX3_MASK   (15<<12)
+
+
+#define S3C2410_TCFG1_MUX2_DIV2   (0<<8)
+#define S3C2410_TCFG1_MUX2_DIV4   (1<<8)
+#define S3C2410_TCFG1_MUX2_DIV8   (2<<8)
+#define S3C2410_TCFG1_MUX2_DIV16  (3<<8)
+#define S3C2410_TCFG1_MUX2_TCLK1  (4<<8)
+#define S3C2410_TCFG1_MUX2_MASK   (15<<8)
+
+
+#define S3C2410_TCFG1_MUX1_DIV2   (0<<4)
+#define S3C2410_TCFG1_MUX1_DIV4   (1<<4)
+#define S3C2410_TCFG1_MUX1_DIV8   (2<<4)
+#define S3C2410_TCFG1_MUX1_DIV16  (3<<4)
+#define S3C2410_TCFG1_MUX1_TCLK0  (4<<4)
+#define S3C2410_TCFG1_MUX1_MASK   (15<<4)
+
+#define S3C2410_TCFG1_MUX0_DIV2   (0<<0)
+#define S3C2410_TCFG1_MUX0_DIV4   (1<<0)
+#define S3C2410_TCFG1_MUX0_DIV8   (2<<0)
+#define S3C2410_TCFG1_MUX0_DIV16  (3<<0)
+#define S3C2410_TCFG1_MUX0_TCLK0  (4<<0)
+#define S3C2410_TCFG1_MUX0_MASK   (15<<0)
+
+#define S3C2410_TCFG1_MUX_DIV2    (0<<0)
+#define S3C2410_TCFG1_MUX_DIV4    (1<<0)
+#define S3C2410_TCFG1_MUX_DIV8    (2<<0)
+#define S3C2410_TCFG1_MUX_DIV16   (3<<0)
+#define S3C2410_TCFG1_MUX_TCLK    (4<<0)
+#define S3C2410_TCFG1_MUX_MASK    (15<<0)
+
+#define S3C64XX_TCFG1_MUX_DIV1    (0<<0)
+#define S3C64XX_TCFG1_MUX_DIV2    (1<<0)
+#define S3C64XX_TCFG1_MUX_DIV4    (2<<0)
+#define S3C64XX_TCFG1_MUX_DIV8    (3<<0)
+#define S3C64XX_TCFG1_MUX_DIV16   (4<<0)
+#define S3C64XX_TCFG1_MUX_TCLK    (5<<0)  /* 3 sets of TCLK */
+#define S3C64XX_TCFG1_MUX_MASK    (15<<0)
+
+#define S3C2410_TCFG1_SHIFT(x)    ((x) * 4)
+
+/* for each timer, we have an count buffer, an compare buffer and
+ * an observation buffer
+*/
+
+/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
+
+#define S3C2410_TCNTB(tmr)    S3C_TIMERREG2(tmr, 0x00)
+#define S3C2410_TCMPB(tmr)    S3C_TIMERREG2(tmr, 0x04)
+#define S3C2410_TCNTO(tmr)    S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
+
+#define S3C2410_TCON_T4RELOAD     (1<<22)
+#define S3C2410_TCON_T4MANUALUPD  (1<<21)
+#define S3C2410_TCON_T4START      (1<<20)
+
+#define S3C2410_TCON_T3RELOAD     (1<<19)
+#define S3C2410_TCON_T3INVERT     (1<<18)
+#define S3C2410_TCON_T3MANUALUPD  (1<<17)
+#define S3C2410_TCON_T3START      (1<<16)
+
+#define S3C2410_TCON_T2RELOAD     (1<<15)
+#define S3C2410_TCON_T2INVERT     (1<<14)
+#define S3C2410_TCON_T2MANUALUPD  (1<<13)
+#define S3C2410_TCON_T2START      (1<<12)
+
+#define S3C2410_TCON_T1RELOAD     (1<<11)
+#define S3C2410_TCON_T1INVERT     (1<<10)
+#define S3C2410_TCON_T1MANUALUPD  (1<<9)
+#define S3C2410_TCON_T1START      (1<<8)
+
+#define S3C2410_TCON_T0DEADZONE   (1<<4)
+#define S3C2410_TCON_T0RELOAD     (1<<3)
+#define S3C2410_TCON_T0INVERT     (1<<2)
+#define S3C2410_TCON_T0MANUALUPD  (1<<1)
+#define S3C2410_TCON_T0START      (1<<0)
+
+#endif /*  __ASM_ARCH_REGS_TIMER_H */
+
+
+
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
new file mode 100644
index 000000000000..a111ad871833
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
@@ -0,0 +1,50 @@
+/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - USB2.0 Highspeed/OtG device PHY registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Note, this is a separate header file as some of the clock framework
+ * needs to touch this if the clk_48m is used as the USB OHCI or other
+ * peripheral source.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
+#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
+
+/* S3C64XX_PA_USB_HSPHY */
+
+#define S3C_HSOTG_PHYREG(x)     ((x) + S3C_VA_USB_HSPHY)
+
+#define S3C_PHYPWR                              S3C_HSOTG_PHYREG(0x00)
+#define SRC_PHYPWR_OTG_DISABLE                  (1 << 4)
+#define SRC_PHYPWR_ANALOG_POWERDOWN             (1 << 3)
+#define SRC_PHYPWR_FORCE_SUSPEND                (1 << 1)
+
+#define S3C_PHYCLK                              S3C_HSOTG_PHYREG(0x04)
+#define S3C_PHYCLK_MODE_USB11                   (1 << 6)
+#define S3C_PHYCLK_EXT_OSC                      (1 << 5)
+#define S3C_PHYCLK_CLK_FORCE                    (1 << 4)
+#define S3C_PHYCLK_ID_PULL                      (1 << 2)
+#define S3C_PHYCLK_CLKSEL_MASK                  (0x3 << 0)
+#define S3C_PHYCLK_CLKSEL_SHIFT                 (0)
+#define S3C_PHYCLK_CLKSEL_48M                   (0x0 << 0)
+#define S3C_PHYCLK_CLKSEL_12M                   (0x2 << 0)
+#define S3C_PHYCLK_CLKSEL_24M                   (0x3 << 0)
+
+#define S3C_RSTCON                              S3C_HSOTG_PHYREG(0x08)
+#define S3C_RSTCON_PHYCLK                       (1 << 2)
+#define S3C_RSTCON_HCLK                         (1 << 2)
+#define S3C_RSTCON_PHY                          (1 << 0)
+
+#define S3C_PHYTUNE                             S3C_HSOTG_PHYREG(0x20)
+
+#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
new file mode 100644
index 000000000000..8d18d9d4d148
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
@@ -0,0 +1,377 @@
+/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - USB2.0 Highspeed/OtG device block registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H
+#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__
+
+#define S3C_HSOTG_REG(x) (x)
+
+#define S3C_GOTGCTL                             S3C_HSOTG_REG(0x000)
+#define S3C_GOTGCTL_BSESVLD                     (1 << 19)
+#define S3C_GOTGCTL_ASESVLD                     (1 << 18)
+#define S3C_GOTGCTL_DBNC_SHORT                  (1 << 17)
+#define S3C_GOTGCTL_CONID_B                     (1 << 16)
+#define S3C_GOTGCTL_DEVHNPEN                    (1 << 11)
+#define S3C_GOTGCTL_HSSETHNPEN                  (1 << 10)
+#define S3C_GOTGCTL_HNPREQ                      (1 << 9)
+#define S3C_GOTGCTL_HSTNEGSCS                   (1 << 8)
+#define S3C_GOTGCTL_SESREQ                      (1 << 1)
+#define S3C_GOTGCTL_SESREQSCS                   (1 << 0)
+
+#define S3C_GOTGINT                             S3C_HSOTG_REG(0x004)
+#define S3C_GOTGINT_DbnceDone                   (1 << 19)
+#define S3C_GOTGINT_ADevTOUTChg                 (1 << 18)
+#define S3C_GOTGINT_HstNegDet                   (1 << 17)
+#define S3C_GOTGINT_HstnegSucStsChng            (1 << 9)
+#define S3C_GOTGINT_SesReqSucStsChng            (1 << 8)
+#define S3C_GOTGINT_SesEndDet                   (1 << 2)
+
+#define S3C_GAHBCFG                             S3C_HSOTG_REG(0x008)
+#define S3C_GAHBCFG_PTxFEmpLvl                  (1 << 8)
+#define S3C_GAHBCFG_NPTxFEmpLvl                 (1 << 7)
+#define S3C_GAHBCFG_DMAEn                       (1 << 5)
+#define S3C_GAHBCFG_HBstLen_MASK                (0xf << 1)
+#define S3C_GAHBCFG_HBstLen_SHIFT               (1)
+#define S3C_GAHBCFG_HBstLen_Single              (0x0 << 1)
+#define S3C_GAHBCFG_HBstLen_Incr                (0x1 << 1)
+#define S3C_GAHBCFG_HBstLen_Incr4               (0x3 << 1)
+#define S3C_GAHBCFG_HBstLen_Incr8               (0x5 << 1)
+#define S3C_GAHBCFG_HBstLen_Incr16              (0x7 << 1)
+#define S3C_GAHBCFG_GlblIntrEn                  (1 << 0)
+
+#define S3C_GUSBCFG                             S3C_HSOTG_REG(0x00C)
+#define S3C_GUSBCFG_PHYLPClkSel                 (1 << 15)
+#define S3C_GUSBCFG_HNPCap                      (1 << 9)
+#define S3C_GUSBCFG_SRPCap                      (1 << 8)
+#define S3C_GUSBCFG_PHYIf16                     (1 << 3)
+#define S3C_GUSBCFG_TOutCal_MASK                (0x7 << 0)
+#define S3C_GUSBCFG_TOutCal_SHIFT               (0)
+#define S3C_GUSBCFG_TOutCal_LIMIT               (0x7)
+#define S3C_GUSBCFG_TOutCal(_x)                 ((_x) << 0)
+
+#define S3C_GRSTCTL                             S3C_HSOTG_REG(0x010)
+
+#define S3C_GRSTCTL_AHBIdle                     (1 << 31)
+#define S3C_GRSTCTL_DMAReq                      (1 << 30)
+#define S3C_GRSTCTL_TxFNum_MASK                 (0x1f << 6)
+#define S3C_GRSTCTL_TxFNum_SHIFT                (6)
+#define S3C_GRSTCTL_TxFNum_LIMIT                (0x1f)
+#define S3C_GRSTCTL_TxFNum(_x)                  ((_x) << 6)
+#define S3C_GRSTCTL_TxFFlsh                     (1 << 5)
+#define S3C_GRSTCTL_RxFFlsh                     (1 << 4)
+#define S3C_GRSTCTL_INTknQFlsh                  (1 << 3)
+#define S3C_GRSTCTL_FrmCntrRst                  (1 << 2)
+#define S3C_GRSTCTL_HSftRst                     (1 << 1)
+#define S3C_GRSTCTL_CSftRst                     (1 << 0)
+
+#define S3C_GINTSTS                             S3C_HSOTG_REG(0x014)
+#define S3C_GINTMSK                             S3C_HSOTG_REG(0x018)
+
+#define S3C_GINTSTS_WkUpInt                     (1 << 31)
+#define S3C_GINTSTS_SessReqInt                  (1 << 30)
+#define S3C_GINTSTS_DisconnInt                  (1 << 29)
+#define S3C_GINTSTS_ConIDStsChng                (1 << 28)
+#define S3C_GINTSTS_PTxFEmp                     (1 << 26)
+#define S3C_GINTSTS_HChInt                      (1 << 25)
+#define S3C_GINTSTS_PrtInt                      (1 << 24)
+#define S3C_GINTSTS_FetSusp                     (1 << 22)
+#define S3C_GINTSTS_incompIP                    (1 << 21)
+#define S3C_GINTSTS_IncomplSOIN                 (1 << 20)
+#define S3C_GINTSTS_OEPInt                      (1 << 19)
+#define S3C_GINTSTS_IEPInt                      (1 << 18)
+#define S3C_GINTSTS_EPMis                       (1 << 17)
+#define S3C_GINTSTS_EOPF                        (1 << 15)
+#define S3C_GINTSTS_ISOutDrop                   (1 << 14)
+#define S3C_GINTSTS_EnumDone                    (1 << 13)
+#define S3C_GINTSTS_USBRst                      (1 << 12)
+#define S3C_GINTSTS_USBSusp                     (1 << 11)
+#define S3C_GINTSTS_ErlySusp                    (1 << 10)
+#define S3C_GINTSTS_GOUTNakEff                  (1 << 7)
+#define S3C_GINTSTS_GINNakEff                   (1 << 6)
+#define S3C_GINTSTS_NPTxFEmp                    (1 << 5)
+#define S3C_GINTSTS_RxFLvl                      (1 << 4)
+#define S3C_GINTSTS_SOF                         (1 << 3)
+#define S3C_GINTSTS_OTGInt                      (1 << 2)
+#define S3C_GINTSTS_ModeMis                     (1 << 1)
+#define S3C_GINTSTS_CurMod_Host                 (1 << 0)
+
+#define S3C_GRXSTSR                             S3C_HSOTG_REG(0x01C)
+#define S3C_GRXSTSP                             S3C_HSOTG_REG(0x020)
+
+#define S3C_GRXSTS_FN_MASK                      (0x7f << 25)
+#define S3C_GRXSTS_FN_SHIFT                     (25)
+
+#define S3C_GRXSTS_PktSts_MASK                  (0xf << 17)
+#define S3C_GRXSTS_PktSts_SHIFT                 (17)
+#define S3C_GRXSTS_PktSts_GlobalOutNAK          (0x1 << 17)
+#define S3C_GRXSTS_PktSts_OutRX                 (0x2 << 17)
+#define S3C_GRXSTS_PktSts_OutDone               (0x3 << 17)
+#define S3C_GRXSTS_PktSts_SetupDone             (0x4 << 17)
+#define S3C_GRXSTS_PktSts_SetupRX               (0x6 << 17)
+
+#define S3C_GRXSTS_DPID_MASK                    (0x3 << 15)
+#define S3C_GRXSTS_DPID_SHIFT                   (15)
+#define S3C_GRXSTS_ByteCnt_MASK                 (0x7ff << 4)
+#define S3C_GRXSTS_ByteCnt_SHIFT                (4)
+#define S3C_GRXSTS_EPNum_MASK                   (0xf << 0)
+#define S3C_GRXSTS_EPNum_SHIFT                  (0)
+
+#define S3C_GRXFSIZ                             S3C_HSOTG_REG(0x024)
+
+#define S3C_GNPTXFSIZ                           S3C_HSOTG_REG(0x028)
+
+#define S3C_GNPTXFSIZ_NPTxFDep_MASK             (0xffff << 16)
+#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT            (16)
+#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT            (0xffff)
+#define S3C_GNPTXFSIZ_NPTxFDep(_x)              ((_x) << 16)
+#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK          (0xffff << 0)
+#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT         (0)
+#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT         (0xffff)
+#define S3C_GNPTXFSIZ_NPTxFStAddr(_x)           ((_x) << 0)
+
+#define S3C_GNPTXSTS                            S3C_HSOTG_REG(0x02C)
+
+#define S3C_GNPTXSTS_NPtxQTop_MASK              (0x7f << 24)
+#define S3C_GNPTXSTS_NPtxQTop_SHIFT             (24)
+
+#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK         (0xff << 16)
+#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT        (16)
+#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v)      (((_v) >> 16) & 0xff)
+
+#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK         (0xffff << 0)
+#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT        (0)
+#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v)      (((_v) >> 0) & 0xffff)
+
+
+#define S3C_HPTXFSIZ                            S3C_HSOTG_REG(0x100)
+
+#define S3C_DPTXFSIZn(_a)                       S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4))
+
+#define S3C_DPTXFSIZn_DPTxFSize_MASK            (0xffff << 16)
+#define S3C_DPTXFSIZn_DPTxFSize_SHIFT           (16)
+#define S3C_DPTXFSIZn_DPTxFSize_GET(_v)         (((_v) >> 16) & 0xffff)
+#define S3C_DPTXFSIZn_DPTxFSize_LIMIT           (0xffff)
+#define S3C_DPTXFSIZn_DPTxFSize(_x)             ((_x) << 16)
+
+#define S3C_DPTXFSIZn_DPTxFStAddr_MASK          (0xffff << 0)
+#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT         (0)
+
+/* Device mode registers */
+#define S3C_DCFG                                S3C_HSOTG_REG(0x800)
+
+#define S3C_DCFG_EPMisCnt_MASK                  (0x1f << 18)
+#define S3C_DCFG_EPMisCnt_SHIFT                 (18)
+#define S3C_DCFG_EPMisCnt_LIMIT                 (0x1f)
+#define S3C_DCFG_EPMisCnt(_x)                   ((_x) << 18)
+
+#define S3C_DCFG_PerFrInt_MASK                  (0x3 << 11)
+#define S3C_DCFG_PerFrInt_SHIFT                 (11)
+#define S3C_DCFG_PerFrInt_LIMIT                 (0x3)
+#define S3C_DCFG_PerFrInt(_x)                   ((_x) << 11)
+
+#define S3C_DCFG_DevAddr_MASK                   (0x7f << 4)
+#define S3C_DCFG_DevAddr_SHIFT                  (4)
+#define S3C_DCFG_DevAddr_LIMIT                  (0x7f)
+#define S3C_DCFG_DevAddr(_x)                    ((_x) << 4)
+
+#define S3C_DCFG_NZStsOUTHShk                   (1 << 2)
+
+#define S3C_DCFG_DevSpd_MASK                    (0x3 << 0)
+#define S3C_DCFG_DevSpd_SHIFT                   (0)
+#define S3C_DCFG_DevSpd_HS                      (0x0 << 0)
+#define S3C_DCFG_DevSpd_FS                      (0x1 << 0)
+#define S3C_DCFG_DevSpd_LS                      (0x2 << 0)
+#define S3C_DCFG_DevSpd_FS48                    (0x3 << 0)
+
+#define S3C_DCTL                                S3C_HSOTG_REG(0x804)
+
+#define S3C_DCTL_PWROnPrgDone                   (1 << 11)
+#define S3C_DCTL_CGOUTNak                       (1 << 10)
+#define S3C_DCTL_SGOUTNak                       (1 << 9)
+#define S3C_DCTL_CGNPInNAK                      (1 << 8)
+#define S3C_DCTL_SGNPInNAK                      (1 << 7)
+#define S3C_DCTL_TstCtl_MASK                    (0x7 << 4)
+#define S3C_DCTL_TstCtl_SHIFT                   (4)
+#define S3C_DCTL_GOUTNakSts                     (1 << 3)
+#define S3C_DCTL_GNPINNakSts                    (1 << 2)
+#define S3C_DCTL_SftDiscon                      (1 << 1)
+#define S3C_DCTL_RmtWkUpSig                     (1 << 0)
+
+#define S3C_DSTS                                S3C_HSOTG_REG(0x808)
+
+#define S3C_DSTS_SOFFN_MASK                     (0x3fff << 8)
+#define S3C_DSTS_SOFFN_SHIFT                    (8)
+#define S3C_DSTS_SOFFN_LIMIT                    (0x3fff)
+#define S3C_DSTS_SOFFN(_x)                      ((_x) << 8)
+#define S3C_DSTS_ErraticErr                     (1 << 3)
+#define S3C_DSTS_EnumSpd_MASK                   (0x3 << 1)
+#define S3C_DSTS_EnumSpd_SHIFT                  (1)
+#define S3C_DSTS_EnumSpd_HS                     (0x0 << 1)
+#define S3C_DSTS_EnumSpd_FS                     (0x1 << 1)
+#define S3C_DSTS_EnumSpd_LS                     (0x2 << 1)
+#define S3C_DSTS_EnumSpd_FS48                   (0x3 << 1)
+
+#define S3C_DSTS_SuspSts                        (1 << 0)
+
+#define S3C_DIEPMSK                             S3C_HSOTG_REG(0x810)
+
+#define S3C_DIEPMSK_INEPNakEffMsk               (1 << 6)
+#define S3C_DIEPMSK_INTknEPMisMsk               (1 << 5)
+#define S3C_DIEPMSK_INTknTXFEmpMsk              (1 << 4)
+#define S3C_DIEPMSK_TimeOUTMsk                  (1 << 3)
+#define S3C_DIEPMSK_AHBErrMsk                   (1 << 2)
+#define S3C_DIEPMSK_EPDisbldMsk                 (1 << 1)
+#define S3C_DIEPMSK_XferComplMsk                (1 << 0)
+
+#define S3C_DOEPMSK                             S3C_HSOTG_REG(0x814)
+
+#define S3C_DOEPMSK_Back2BackSetup              (1 << 6)
+#define S3C_DOEPMSK_OUTTknEPdisMsk              (1 << 4)
+#define S3C_DOEPMSK_SetupMsk                    (1 << 3)
+#define S3C_DOEPMSK_AHBErrMsk                   (1 << 2)
+#define S3C_DOEPMSK_EPDisbldMsk                 (1 << 1)
+#define S3C_DOEPMSK_XferComplMsk                (1 << 0)
+
+#define S3C_DAINT                               S3C_HSOTG_REG(0x818)
+#define S3C_DAINTMSK                            S3C_HSOTG_REG(0x81C)
+
+#define S3C_DAINT_OutEP_SHIFT                   (16)
+#define S3C_DAINT_OutEP(x)                      (1 << ((x) + 16))
+#define S3C_DAINT_InEP(x)                       (1 << (x))
+
+#define S3C_DTKNQR1                             S3C_HSOTG_REG(0x820)
+#define S3C_DTKNQR2                             S3C_HSOTG_REG(0x824)
+#define S3C_DTKNQR3                             S3C_HSOTG_REG(0x830)
+#define S3C_DTKNQR4                             S3C_HSOTG_REG(0x834)
+
+#define S3C_DVBUSDIS                            S3C_HSOTG_REG(0x828)
+#define S3C_DVBUSPULSE                          S3C_HSOTG_REG(0x82C)
+
+#define S3C_DIEPCTL0                            S3C_HSOTG_REG(0x900)
+#define S3C_DOEPCTL0                            S3C_HSOTG_REG(0xB00)
+#define S3C_DIEPCTL(_a)                         S3C_HSOTG_REG(0x900 + ((_a) * 0x20))
+#define S3C_DOEPCTL(_a)                         S3C_HSOTG_REG(0xB00 + ((_a) * 0x20))
+
+/* EP0 specialness:
+ * bits[29..28] - reserved (no SetD0PID, SetD1PID)
+ * bits[25..22] - should always be zero, this isn't a periodic endpoint
+ * bits[10..0] - MPS setting differenct for EP0
+*/
+#define S3C_D0EPCTL_MPS_MASK                    (0x3 << 0)
+#define S3C_D0EPCTL_MPS_SHIFT                   (0)
+#define S3C_D0EPCTL_MPS_64                      (0x0 << 0)
+#define S3C_D0EPCTL_MPS_32                      (0x1 << 0)
+#define S3C_D0EPCTL_MPS_16                      (0x2 << 0)
+#define S3C_D0EPCTL_MPS_8                       (0x3 << 0)
+
+#define S3C_DxEPCTL_EPEna                       (1 << 31)
+#define S3C_DxEPCTL_EPDis                       (1 << 30)
+#define S3C_DxEPCTL_SetD1PID                    (1 << 29)
+#define S3C_DxEPCTL_SetOddFr                    (1 << 29)
+#define S3C_DxEPCTL_SetD0PID                    (1 << 28)
+#define S3C_DxEPCTL_SetEvenFr                   (1 << 28)
+#define S3C_DxEPCTL_SNAK                        (1 << 27)
+#define S3C_DxEPCTL_CNAK                        (1 << 26)
+#define S3C_DxEPCTL_TxFNum_MASK                 (0xf << 22)
+#define S3C_DxEPCTL_TxFNum_SHIFT                (22)
+#define S3C_DxEPCTL_TxFNum_LIMIT                (0xf)
+#define S3C_DxEPCTL_TxFNum(_x)                  ((_x) << 22)
+
+#define S3C_DxEPCTL_Stall                       (1 << 21)
+#define S3C_DxEPCTL_Snp                         (1 << 20)
+#define S3C_DxEPCTL_EPType_MASK                 (0x3 << 18)
+#define S3C_DxEPCTL_EPType_SHIFT                (18)
+#define S3C_DxEPCTL_EPType_Control              (0x0 << 18)
+#define S3C_DxEPCTL_EPType_Iso                  (0x1 << 18)
+#define S3C_DxEPCTL_EPType_Bulk                 (0x2 << 18)
+#define S3C_DxEPCTL_EPType_Intterupt            (0x3 << 18)
+
+#define S3C_DxEPCTL_NAKsts                      (1 << 17)
+#define S3C_DxEPCTL_DPID                        (1 << 16)
+#define S3C_DxEPCTL_EOFrNum                     (1 << 16)
+#define S3C_DxEPCTL_USBActEp                    (1 << 15)
+#define S3C_DxEPCTL_NextEp_MASK                 (0xf << 11)
+#define S3C_DxEPCTL_NextEp_SHIFT                (11)
+#define S3C_DxEPCTL_NextEp_LIMIT                (0xf)
+#define S3C_DxEPCTL_NextEp(_x)                  ((_x) << 11)
+
+#define S3C_DxEPCTL_MPS_MASK                    (0x7ff << 0)
+#define S3C_DxEPCTL_MPS_SHIFT                   (0)
+#define S3C_DxEPCTL_MPS_LIMIT                   (0x7ff)
+#define S3C_DxEPCTL_MPS(_x)                     ((_x) << 0)
+
+#define S3C_DIEPINT(_a)                         S3C_HSOTG_REG(0x908 + ((_a) * 0x20))
+#define S3C_DOEPINT(_a)                         S3C_HSOTG_REG(0xB08 + ((_a) * 0x20))
+
+#define S3C_DxEPINT_INEPNakEff                  (1 << 6)
+#define S3C_DxEPINT_Back2BackSetup              (1 << 6)
+#define S3C_DxEPINT_INTknEPMis                  (1 << 5)
+#define S3C_DxEPINT_INTknTXFEmp                 (1 << 4)
+#define S3C_DxEPINT_OUTTknEPdis                 (1 << 4)
+#define S3C_DxEPINT_Timeout                     (1 << 3)
+#define S3C_DxEPINT_Setup                       (1 << 3)
+#define S3C_DxEPINT_AHBErr                      (1 << 2)
+#define S3C_DxEPINT_EPDisbld                    (1 << 1)
+#define S3C_DxEPINT_XferCompl                   (1 << 0)
+
+#define S3C_DIEPTSIZ0                           S3C_HSOTG_REG(0x910)
+
+#define S3C_DIEPTSIZ0_PktCnt_MASK               (0x3 << 19)
+#define S3C_DIEPTSIZ0_PktCnt_SHIFT              (19)
+#define S3C_DIEPTSIZ0_PktCnt_LIMIT              (0x3)
+#define S3C_DIEPTSIZ0_PktCnt(_x)                ((_x) << 19)
+
+#define S3C_DIEPTSIZ0_XferSize_MASK             (0x7f << 0)
+#define S3C_DIEPTSIZ0_XferSize_SHIFT            (0)
+#define S3C_DIEPTSIZ0_XferSize_LIMIT            (0x7f)
+#define S3C_DIEPTSIZ0_XferSize(_x)              ((_x) << 0)
+
+
+#define DOEPTSIZ0                               S3C_HSOTG_REG(0xB10)
+#define S3C_DOEPTSIZ0_SUPCnt_MASK               (0x3 << 29)
+#define S3C_DOEPTSIZ0_SUPCnt_SHIFT              (29)
+#define S3C_DOEPTSIZ0_SUPCnt_LIMIT              (0x3)
+#define S3C_DOEPTSIZ0_SUPCnt(_x)                ((_x) << 29)
+
+#define S3C_DOEPTSIZ0_PktCnt                    (1 << 19)
+#define S3C_DOEPTSIZ0_XferSize_MASK             (0x7f << 0)
+#define S3C_DOEPTSIZ0_XferSize_SHIFT            (0)
+
+#define S3C_DIEPTSIZ(_a)                        S3C_HSOTG_REG(0x910 + ((_a) * 0x20))
+#define S3C_DOEPTSIZ(_a)                        S3C_HSOTG_REG(0xB10 + ((_a) * 0x20))
+
+#define S3C_DxEPTSIZ_MC_MASK                    (0x3 << 29)
+#define S3C_DxEPTSIZ_MC_SHIFT                   (29)
+#define S3C_DxEPTSIZ_MC_LIMIT                   (0x3)
+#define S3C_DxEPTSIZ_MC(_x)                     ((_x) << 29)
+
+#define S3C_DxEPTSIZ_PktCnt_MASK                (0x3ff << 19)
+#define S3C_DxEPTSIZ_PktCnt_SHIFT               (19)
+#define S3C_DxEPTSIZ_PktCnt_GET(_v)             (((_v) >> 19) & 0x3ff)
+#define S3C_DxEPTSIZ_PktCnt_LIMIT               (0x3ff)
+#define S3C_DxEPTSIZ_PktCnt(_x)                 ((_x) << 19)
+
+#define S3C_DxEPTSIZ_XferSize_MASK              (0x7ffff << 0)
+#define S3C_DxEPTSIZ_XferSize_SHIFT             (0)
+#define S3C_DxEPTSIZ_XferSize_GET(_v)           (((_v) >> 0) & 0x7ffff)
+#define S3C_DxEPTSIZ_XferSize_LIMIT             (0x7ffff)
+#define S3C_DxEPTSIZ_XferSize(_x)               ((_x) << 0)
+
+
+#define S3C_DIEPDMA(_a)                         S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
+#define S3C_DOEPDMA(_a)                         S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
+
+#define S3C_EPFIFO(_a)                          S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
+
+#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h
new file mode 100644
index 000000000000..4938492470f7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-watchdog.h
@@ -0,0 +1,41 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Watchdog timer control
+*/
+
+
+#ifndef __ASM_ARCH_REGS_WATCHDOG_H
+#define __ASM_ARCH_REGS_WATCHDOG_H
+
+#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
+
+#define S3C2410_WTCON      S3C_WDOGREG(0x00)
+#define S3C2410_WTDAT      S3C_WDOGREG(0x04)
+#define S3C2410_WTCNT      S3C_WDOGREG(0x08)
+
+/* the watchdog can either generate a reset pulse, or an
+ * interrupt.
+ */
+
+#define S3C2410_WTCON_RSTEN   (0x01)
+#define S3C2410_WTCON_INTEN   (1<<2)
+#define S3C2410_WTCON_ENABLE  (1<<5)
+
+#define S3C2410_WTCON_DIV16   (0<<3)
+#define S3C2410_WTCON_DIV32   (1<<3)
+#define S3C2410_WTCON_DIV64   (2<<3)
+#define S3C2410_WTCON_DIV128  (3<<3)
+
+#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
+#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
+
+#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
+
+
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
new file mode 100644
index 000000000000..d17724149315
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -0,0 +1,67 @@
+/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+ *
+ * Copyright (C) 2009 Samsung Electronics Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __S3C64XX_PLAT_SPI_H
+#define __S3C64XX_PLAT_SPI_H
+
+/**
+ * struct s3c64xx_spi_csinfo - ChipSelect description
+ * @fb_delay: Slave specific feedback delay.
+ *            Refer to FB_CLK_SEL register definition in SPI chapter.
+ * @line: Custom 'identity' of the CS line.
+ * @set_level: CS line control.
+ *
+ * This is per SPI-Slave Chipselect information.
+ * Allocate and initialize one in machine init code and make the
+ * spi_board_info.controller_data point to it.
+ */
+struct s3c64xx_spi_csinfo {
+        u8 fb_delay;
+        unsigned line;
+        void (*set_level)(unsigned line_id, int lvl);
+};
+
+/**
+ * struct s3c64xx_spi_info - SPI Controller defining structure
+ * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
+ * @src_clk_name: Platform name of the corresponding clock.
+ * @num_cs: Number of CS this controller emulates.
+ * @cfg_gpio: Configure pins for this SPI controller.
+ * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
+ * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
+ * @high_speed: If the controller supports HIGH_SPEED_EN bit
+ */
+struct s3c64xx_spi_info {
+        int src_clk_nr;
+        char *src_clk_name;
+
+        int num_cs;
+
+        int (*cfg_gpio)(struct platform_device *pdev);
+
+        /* Following two fields are for future compatibility */
+        int fifo_lvl_mask;
+        int rx_lvl_offset;
+        int high_speed;
+};
+
+/**
+ * s3c64xx_spi_set_info - SPI Controller configure callback by the board
+ *                              initialization code.
+ * @cntrlr: SPI controller number the configuration is for.
+ * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
+ * @num_cs: Number of elements in the 'cs' array.
+ *
+ * Call this from machine init code for each SPI Controller that
+ * has some chips attached to it.
+ */
+extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
+
+#endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
new file mode 100644
index 000000000000..7d07cd7aa4f2
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -0,0 +1,221 @@
+/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - SDHCI (HSMMC) platform data definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C_SDHCI_H
+#define __PLAT_S3C_SDHCI_H __FILE__
+
+struct platform_device;
+struct mmc_host;
+struct mmc_card;
+struct mmc_ios;
+
+/**
+ * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
+ * @max_width: The maximum number of data bits supported.
+ * @host_caps: Standard MMC host capabilities bit field.
+ * @cfg_gpio: Configure the GPIO for a specific card bit-width
+ * @cfg_card: Configure the interface for a specific card and speed. This
+ *            is necessary the controllers and/or GPIO blocks require the
+ *            changing of driver-strength and other controls dependant on
+ *            the card and speed of operation.
+ *
+ * Initialisation data specific to either the machine or the platform
+ * for the device driver to use or call-back when configuring gpio or
+ * card speed information.
+*/
+struct s3c_sdhci_platdata {
+        unsigned int    max_width;
+        unsigned int    host_caps;
+
+        char            **clocks;       /* set of clock sources */
+
+        void    (*cfg_gpio)(struct platform_device *dev, int width);
+        void    (*cfg_card)(struct platform_device *dev,
+                            void __iomem *regbase,
+                            struct mmc_ios *ios,
+                            struct mmc_card *card);
+};
+
+/**
+ * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
+ * @pd: Platform data to register to device.
+ *
+ * Register the given platform data for use withe S3C SDHCI device.
+ * The call will copy the platform data, so the board definitions can
+ * make the structure itself __initdata.
+ */
+extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
+extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
+extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd);
+
+/* Default platform data, exported so that per-cpu initialisation can
+ * set the correct one when there are more than one cpu type selected.
+*/
+
+extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
+extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
+extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata;
+
+/* Helper function availablity */
+
+extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+
+/* S3C6400 SDHCI setup */
+
+#ifdef CONFIG_S3C64XX_SETUP_SDHCI
+extern char *s3c64xx_hsmmc_clksrcs[4];
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
+                                         void __iomem *r,
+                                         struct mmc_ios *ios,
+                                         struct mmc_card *card);
+
+static inline void s3c6400_default_sdhci0(void)
+{
+        s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
+        s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
+}
+
+#else
+static inline void s3c6400_default_sdhci0(void) { }
+#endif  /* CONFIG_S3C_DEV_HSMMC */
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s3c6400_default_sdhci1(void)
+{
+        s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
+        s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c6400_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s3c6400_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c6400_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
+
+/* S3C6410 SDHCI setup */
+
+extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
+                                         void __iomem *r,
+                                         struct mmc_ios *ios,
+                                         struct mmc_card *card);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static inline void s3c6410_default_sdhci0(void)
+{
+        s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
+        s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c6410_default_sdhci0(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC */
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s3c6410_default_sdhci1(void)
+{
+        s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
+        s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c6410_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s3c6410_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c6410_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
+
+#else
+static inline void s3c6410_default_sdhci0(void) { }
+static inline void s3c6410_default_sdhci1(void) { }
+static inline void s3c6400_default_sdhci0(void) { }
+static inline void s3c6400_default_sdhci1(void) { }
+
+#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
+
+/* S5PC100 SDHCI setup */
+
+#ifdef CONFIG_S5PC100_SETUP_SDHCI
+extern char *s5pc100_hsmmc_clksrcs[4];
+
+extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
+                                           void __iomem *r,
+                                           struct mmc_ios *ios,
+                                           struct mmc_card *card);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static inline void s5pc100_default_sdhci0(void)
+{
+        s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
+        s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci0(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC */
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s5pc100_default_sdhci1(void)
+{
+        s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
+        s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s5pc100_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+
+
+#else
+static inline void s5pc100_default_sdhci0(void) { }
+static inline void s5pc100_default_sdhci1(void) { }
+static inline void s5pc100_default_sdhci2(void) { }
+#endif /* CONFIG_S5PC100_SETUP_SDHCI */
+
+#endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h
new file mode 100644
index 000000000000..a22a4f2eea94
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/udc-hs.h
@@ -0,0 +1,29 @@
+/* arch/arm/plat-s3c/include/plat/udc-hs.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C USB2.0 High-speed / OtG platform information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+enum s3c_hsotg_dmamode {
+        S3C_HSOTG_DMA_NONE,     /* do not use DMA at-all */
+        S3C_HSOTG_DMA_ONLY,     /* always use DMA */
+        S3C_HSOTG_DMA_DRV,      /* DMA is chosen by driver */
+};
+
+/**
+ * struct s3c_hsotg_plat - platform data for high-speed otg/udc
+ * @dma: Whether to use DMA or not.
+ * @is_osc: The clock source is an oscillator, not a crystal
+ */
+struct s3c_hsotg_plat {
+        enum s3c_hsotg_dmamode  dma;
+        unsigned int            is_osc : 1;
+};
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
new file mode 100644
index 000000000000..7d6ed7263d57
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -0,0 +1,184 @@
+/* arch/arm/plat-samsung/include/plat/uncompress.h
+ *
+ * Copyright 2003, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_UNCOMPRESS_H
+#define __ASM_PLAT_UNCOMPRESS_H
+
+typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
+
+/* uart setup */
+
+static unsigned int fifo_mask;
+static unsigned int fifo_max;
+
+/* forward declerations */
+
+static void arch_detect_cpu(void);
+
+/* defines for UART registers */
+
+#include <plat/regs-serial.h>
+#include <plat/regs-watchdog.h>
+
+/* working in physical space... */
+#undef S3C2410_WDOGREG
+#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+
+/* how many bytes we allow into the FIFO at a time in FIFO mode */
+#define FIFO_MAX         (14)
+
+#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
+
+static __inline__ void
+uart_wr(unsigned int reg, unsigned int val)
+{
+        volatile unsigned int *ptr;
+
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        *ptr = val;
+}
+
+static __inline__ unsigned int
+uart_rd(unsigned int reg)
+{
+        volatile unsigned int *ptr;
+
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        return *ptr;
+}
+
+/* we can deal with the case the UARTs are being run
+ * in FIFO mode, so that we don't hold up our execution
+ * waiting for tx to happen...
+*/
+
+static void putc(int ch)
+{
+        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
+                int level;
+
+                while (1) {
+                        level = uart_rd(S3C2410_UFSTAT);
+                        level &= fifo_mask;
+
+                        if (level < fifo_max)
+                                break;
+                }
+
+        } else {
+                /* not using fifos */
+
+                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
+                        barrier();
+        }
+
+        /* write byte to transmission register */
+        uart_wr(S3C2410_UTXH, ch);
+}
+
+static inline void flush(void)
+{
+}
+
+#define __raw_writel(d, ad)                     \
+        do {                                                    \
+                *((volatile unsigned int __force *)(ad)) = (d); \
+        } while (0)
+
+/* CONFIG_S3C_BOOT_WATCHDOG
+ *
+ * Simple boot-time watchdog setup, to reboot the system if there is
+ * any problem with the boot process
+*/
+
+#ifdef CONFIG_S3C_BOOT_WATCHDOG
+
+#define WDOG_COUNT (0xff00)
+
+static inline void arch_decomp_wdog(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+}
+
+static void arch_decomp_wdog_start(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+}
+
+#else
+#define arch_decomp_wdog_start()
+#define arch_decomp_wdog()
+#endif
+
+#ifdef CONFIG_S3C_BOOT_ERROR_RESET
+
+static void arch_decomp_error(const char *x)
+{
+        putstr("\n\n");
+        putstr(x);
+        putstr("\n\n -- System resetting\n");
+
+        __raw_writel(0x4000, S3C2410_WTDAT);
+        __raw_writel(0x4000, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+
+        while(1);
+}
+
+#define arch_error arch_decomp_error
+#endif
+
+#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
+static inline void arch_enable_uart_fifo(void)
+{
+        u32 fifocon = uart_rd(S3C2410_UFCON);
+
+        if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
+                fifocon |= S3C2410_UFCON_RESETBOTH;
+                uart_wr(S3C2410_UFCON, fifocon);
+
+                /* wait for fifo reset to complete */
+                while (1) {
+                        fifocon = uart_rd(S3C2410_UFCON);
+                        if (!(fifocon & S3C2410_UFCON_RESETBOTH))
+                                break;
+                }
+        }
+}
+#else
+#define arch_enable_uart_fifo() do { } while(0)
+#endif
+
+
+static void
+arch_decomp_setup(void)
+{
+        /* we may need to setup the uart(s) here if we are not running
+         * on an BAST... the BAST will have left the uarts configured
+         * after calling linux.
+         */
+
+        arch_detect_cpu();
+        arch_decomp_wdog_start();
+
+        /* Enable the UART FIFOs if they where not enabled and our
+         * configuration says we should turn them on.
+         */
+
+        arch_enable_uart_fifo();
+}
+
+
+#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-samsung/include/plat/usb-control.h b/arch/arm/plat-samsung/include/plat/usb-control.h
new file mode 100644
index 000000000000..7fa1fbefc3f2
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/usb-control.h
@@ -0,0 +1,43 @@
+/* arch/arm/plat-samsung/include/plat/usb-control.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - USB host port information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_USBCONTROL_H
+#define __ASM_ARCH_USBCONTROL_H
+
+#define S3C_HCDFLG_USED (1)
+
+struct s3c2410_hcd_port {
+        unsigned char   flags;
+        unsigned char   power;
+        unsigned char   oc_status;
+        unsigned char   oc_changed;
+};
+
+struct s3c2410_hcd_info {
+        struct usb_hcd          *hcd;
+        struct s3c2410_hcd_port port[2];
+
+        void            (*power_control)(int port, int to);
+        void            (*enable_oc)(struct s3c2410_hcd_info *, int on);
+        void            (*report_oc)(struct s3c2410_hcd_info *, int ports);
+};
+
+static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports)
+{
+        if (info->report_oc != NULL) {
+                (info->report_oc)(info, ports);
+        }
+}
+
+extern void s3c_ohci_set_platdata(struct s3c2410_hcd_info *info);
+
+#endif /*__ASM_ARCH_USBCONTROL_H */
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
new file mode 100644
index 000000000000..54b762acb5a0
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -0,0 +1,49 @@
+/* arch/arm/plat-s3c/include/plat/watchdog-reset.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - System define for arch_reset() function
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <plat/regs-watchdog.h>
+#include <mach/map.h>
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+static inline void arch_wdt_reset(void)
+{
+        struct clk *wdtclk;
+
+        printk("arch_reset: attempting watchdog reset\n");
+
+        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
+
+        wdtclk = clk_get(NULL, "watchdog");
+        if (!IS_ERR(wdtclk)) {
+                clk_enable(wdtclk);
+        } else
+                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
+
+        /* put initial values into count and data */
+        __raw_writel(0x80, S3C2410_WTCNT);
+        __raw_writel(0x80, S3C2410_WTDAT);
+
+        /* set the watchdog to go and reset... */
+        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
+                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
+
+        /* wait for reset to assert... */
+        mdelay(500);
+
+        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+
+        /* delay to allow the serial port to show the message */
+        mdelay(50);
+}
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
new file mode 100644
index 000000000000..6790edfaca6f
--- /dev/null
+++ b/arch/arm/plat-samsung/init.c
@@ -0,0 +1,160 @@
+/* linux/arch/arm/plat-s3c/init.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series CPU initialisation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+
+#include <plat/regs-serial.h>
+
+static struct cpu_table *cpu;
+
+static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
+                                                struct cpu_table *tab,
+                                                unsigned int count)
+{
+        for (; count != 0; count--, tab++) {
+                if ((idcode & tab->idmask) == tab->idcode)
+                        return tab;
+        }
+
+        return NULL;
+}
+
+void __init s3c_init_cpu(unsigned long idcode,
+                         struct cpu_table *cputab, unsigned int cputab_size)
+{
+        cpu = s3c_lookup_cpu(idcode, cputab, cputab_size);
+
+        if (cpu == NULL) {
+                printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
+                panic("Unknown S3C24XX CPU");
+        }
+
+        printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
+
+        if (cpu->map_io == NULL || cpu->init == NULL) {
+                printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
+                panic("Unsupported Samsung CPU");
+        }
+
+        cpu->map_io();
+}
+
+/* s3c24xx_init_clocks
+ *
+ * Initialise the clock subsystem and associated information from the
+ * given master crystal value.
+ *
+ * xtal  = 0 -> use default PLL crystal value (normally 12MHz)
+ *      != 0 -> PLL crystal value in Hz
+*/
+
+void __init s3c24xx_init_clocks(int xtal)
+{
+        if (xtal == 0)
+                xtal = 12*1000*1000;
+
+        if (cpu == NULL)
+                panic("s3c24xx_init_clocks: no cpu setup?\n");
+
+        if (cpu->init_clocks == NULL)
+                panic("s3c24xx_init_clocks: cpu has no clock init\n");
+        else
+                (cpu->init_clocks)(xtal);
+}
+
+/* uart management */
+
+static int nr_uarts __initdata = 0;
+
+static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+/* s3c24xx_init_uartdevs
+ *
+ * copy the specified platform data and configuration into our central
+ * set of devices, before the data is thrown away after the init process.
+ *
+ * This also fills in the array passed to the serial driver for the
+ * early initialisation of the console.
+*/
+
+void __init s3c24xx_init_uartdevs(char *name,
+                                  struct s3c24xx_uart_resources *res,
+                                  struct s3c2410_uartcfg *cfg, int no)
+{
+        struct platform_device *platdev;
+        struct s3c2410_uartcfg *cfgptr = uart_cfgs;
+        struct s3c24xx_uart_resources *resp;
+        int uart;
+
+        memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
+
+        for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
+                platdev = s3c24xx_uart_src[cfgptr->hwport];
+
+                resp = res + cfgptr->hwport;
+
+                s3c24xx_uart_devs[uart] = platdev;
+
+                platdev->name = name;
+                platdev->resource = resp->resources;
+                platdev->num_resources = resp->nr_resources;
+
+                platdev->dev.platform_data = cfgptr;
+        }
+
+        nr_uarts = no;
+}
+
+void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        if (cpu == NULL)
+                return;
+
+        if (cpu->init_uarts == NULL) {
+                printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
+        } else
+                (cpu->init_uarts)(cfg, no);
+}
+
+static int __init s3c_arch_init(void)
+{
+        int ret;
+
+        // do the correct init for cpu
+
+        if (cpu == NULL)
+                panic("s3c_arch_init: NULL cpu\n");
+
+        ret = (cpu->init)();
+        if (ret != 0)
+                return ret;
+
+        ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
+        return ret;
+}
+
+arch_initcall(s3c_arch_init);
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
new file mode 100644
index 000000000000..4f8c102674ae
--- /dev/null
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -0,0 +1,143 @@
+/* arch/arm/plat-samsung/irq-uart.c
+ *      originally part of arch/arm/plat-s3c64xx/irq.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung- UART Interrupt handling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/serial_core.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <plat/irq-uart.h>
+#include <plat/regs-serial.h>
+#include <plat/cpu.h>
+
+/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
+ * are consecutive when looking up the interrupt in the demux routines.
+ */
+
+static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
+{
+        struct s3c_uart_irq *uirq = get_irq_chip_data(irq);
+        return uirq->regs;
+}
+
+static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
+{
+        return irq & 3;
+}
+
+static void s3c_irq_uart_mask(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+        u32 reg;
+
+        reg = __raw_readl(regs + S3C64XX_UINTM);
+        reg |= (1 << bit);
+        __raw_writel(reg, regs + S3C64XX_UINTM);
+}
+
+static void s3c_irq_uart_maskack(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+        u32 reg;
+
+        reg = __raw_readl(regs + S3C64XX_UINTM);
+        reg |= (1 << bit);
+        __raw_writel(reg, regs + S3C64XX_UINTM);
+        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
+}
+
+static void s3c_irq_uart_unmask(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+        u32 reg;
+
+        reg = __raw_readl(regs + S3C64XX_UINTM);
+        reg &= ~(1 << bit);
+        __raw_writel(reg, regs + S3C64XX_UINTM);
+}
+
+static void s3c_irq_uart_ack(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+
+        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
+}
+
+static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
+{
+        struct s3c_uart_irq *uirq = desc->handler_data;
+        u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
+        int base = uirq->base_irq;
+
+        if (pend & (1 << 0))
+                generic_handle_irq(base);
+        if (pend & (1 << 1))
+                generic_handle_irq(base + 1);
+        if (pend & (1 << 2))
+                generic_handle_irq(base + 2);
+        if (pend & (1 << 3))
+                generic_handle_irq(base + 3);
+}
+
+static struct irq_chip s3c_irq_uart = {
+        .name           = "s3c-uart",
+        .mask           = s3c_irq_uart_mask,
+        .unmask         = s3c_irq_uart_unmask,
+        .mask_ack       = s3c_irq_uart_maskack,
+        .ack            = s3c_irq_uart_ack,
+};
+
+static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
+{
+        struct irq_desc *desc = irq_to_desc(uirq->parent_irq);
+        void __iomem *reg_base = uirq->regs;
+        unsigned int irq;
+        int offs;
+
+        /* mask all interrupts at the start. */
+        __raw_writel(0xf, reg_base + S3C64XX_UINTM);
+
+        for (offs = 0; offs < 3; offs++) {
+                irq = uirq->base_irq + offs;
+
+                set_irq_chip(irq, &s3c_irq_uart);
+                set_irq_chip_data(irq, uirq);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+
+        desc->handler_data = uirq;
+        set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
+}
+
+/**
+ * s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing
+ * @irq: The interrupt data for registering
+ * @nr_irqs: The number of interrupt descriptions in @irq.
+ *
+ * Register the UART interrupts specified by @irq including the demuxing
+ * routines. This supports the S3C6400 and newer style of devices.
+ */
+void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs)
+{
+        for (; nr_irqs > 0; nr_irqs--, irq++)
+                s3c_init_uart_irq(irq);
+}
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
new file mode 100644
index 000000000000..0270519fcabc
--- /dev/null
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -0,0 +1,86 @@
+/* arch/arm/plat-samsung/irq-vic-timer.c
+ *      originally part of arch/arm/plat-s3c64xx/irq.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - Interrupt handling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <plat/irq-vic-timer.h>
+#include <plat/regs-timer.h>
+
+static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
+{
+        generic_handle_irq((int)desc->handler_data);
+}
+
+/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
+
+static void s3c_irq_timer_mask(unsigned int irq)
+{
+        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+
+        reg &= 0x1f;  /* mask out pending interrupts */
+        reg &= ~(1 << (irq - IRQ_TIMER0));
+        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+
+static void s3c_irq_timer_unmask(unsigned int irq)
+{
+        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+
+        reg &= 0x1f;  /* mask out pending interrupts */
+        reg |= 1 << (irq - IRQ_TIMER0);
+        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+
+static void s3c_irq_timer_ack(unsigned int irq)
+{
+        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+
+        reg &= 0x1f;
+        reg |= (1 << 5) << (irq - IRQ_TIMER0);
+        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+
+static struct irq_chip s3c_irq_timer = {
+        .name           = "s3c-timer",
+        .mask           = s3c_irq_timer_mask,
+        .unmask         = s3c_irq_timer_unmask,
+        .ack            = s3c_irq_timer_ack,
+};
+
+/**
+ * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
+ * @parent_irq: The parent IRQ on the VIC for the timer.
+ * @timer_irq: The IRQ to be used for the timer.
+ *
+ * Register the necessary IRQ chaining and support for the timer IRQs
+ * chained of the VIC.
+ */
+void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
+                                   unsigned int timer_irq)
+{
+        struct irq_desc *desc = irq_to_desc(parent_irq);
+
+        set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
+
+        set_irq_chip(timer_irq, &s3c_irq_timer);
+        set_irq_handler(timer_irq, handle_level_irq);
+        set_irq_flags(timer_irq, IRQF_VALID);
+
+        desc->handler_data = (void *)timer_irq;
+}
diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c
new file mode 100644
index 000000000000..0b5bb774192a
--- /dev/null
+++ b/arch/arm/plat-samsung/pm-check.c
@@ -0,0 +1,242 @@
+/* linux/arch/arm/plat-s3c/pm-check.c
+ *  originally in linux/arch/arm/plat-s3c24xx/pm.c
+ *
+ * Copyright (c) 2004-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Power Mangament - suspend/resume memory corruptiuon check.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/init.h>
+#include <linux/crc32.h>
+#include <linux/ioport.h>
+
+#include <plat/pm.h>
+
+#if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1
+#error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value
+#endif
+
+/* suspend checking code...
+ *
+ * this next area does a set of crc checks over all the installed
+ * memory, so the system can verify if the resume was ok.
+ *
+ * CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
+ * increasing it will mean that the area corrupted will be less easy to spot,
+ * and reducing the size will cause the CRC save area to grow
+*/
+
+#define CHECK_CHUNKSIZE (CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE * 1024)
+
+static u32 crc_size;    /* size needed for the crc block */
+static u32 *crcs;       /* allocated over suspend/resume */
+
+typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
+
+/* s3c_pm_run_res
+ *
+ * go through the given resource list, and look for system ram
+*/
+
+static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
+{
+        while (ptr != NULL) {
+                if (ptr->child != NULL)
+                        s3c_pm_run_res(ptr->child, fn, arg);
+
+                if ((ptr->flags & IORESOURCE_MEM) &&
+                    strcmp(ptr->name, "System RAM") == 0) {
+                        S3C_PMDBG("Found system RAM at %08lx..%08lx\n",
+                                  (unsigned long)ptr->start,
+                                  (unsigned long)ptr->end);
+                        arg = (fn)(ptr, arg);
+                }
+
+                ptr = ptr->sibling;
+        }
+}
+
+static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg)
+{
+        s3c_pm_run_res(&iomem_resource, fn, arg);
+}
+
+static u32 *s3c_pm_countram(struct resource *res, u32 *val)
+{
+        u32 size = (u32)(res->end - res->start)+1;
+
+        size += CHECK_CHUNKSIZE-1;
+        size /= CHECK_CHUNKSIZE;
+
+        S3C_PMDBG("Area %08lx..%08lx, %d blocks\n",
+                  (unsigned long)res->start, (unsigned long)res->end, size);
+
+        *val += size * sizeof(u32);
+        return val;
+}
+
+/* s3c_pm_prepare_check
+ *
+ * prepare the necessary information for creating the CRCs. This
+ * must be done before the final save, as it will require memory
+ * allocating, and thus touching bits of the kernel we do not
+ * know about.
+*/
+
+void s3c_pm_check_prepare(void)
+{
+        crc_size = 0;
+
+        s3c_pm_run_sysram(s3c_pm_countram, &crc_size);
+
+        S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size);
+
+        crcs = kmalloc(crc_size+4, GFP_KERNEL);
+        if (crcs == NULL)
+                printk(KERN_ERR "Cannot allocated CRC save area\n");
+}
+
+static u32 *s3c_pm_makecheck(struct resource *res, u32 *val)
+{
+        unsigned long addr, left;
+
+        for (addr = res->start; addr < res->end;
+             addr += CHECK_CHUNKSIZE) {
+                left = res->end - addr;
+
+                if (left > CHECK_CHUNKSIZE)
+                        left = CHECK_CHUNKSIZE;
+
+                *val = crc32_le(~0, phys_to_virt(addr), left);
+                val++;
+        }
+
+        return val;
+}
+
+/* s3c_pm_check_store
+ *
+ * compute the CRC values for the memory blocks before the final
+ * sleep.
+*/
+
+void s3c_pm_check_store(void)
+{
+        if (crcs != NULL)
+                s3c_pm_run_sysram(s3c_pm_makecheck, crcs);
+}
+
+/* in_region
+ *
+ * return TRUE if the area defined by ptr..ptr+size contains the
+ * what..what+whatsz
+*/
+
+static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
+{
+        if ((what+whatsz) < ptr)
+                return 0;
+
+        if (what > (ptr+size))
+                return 0;
+
+        return 1;
+}
+
+/**
+ * s3c_pm_runcheck() - helper to check a resource on restore.
+ * @res: The resource to check
+ * @vak: Pointer to list of CRC32 values to check.
+ *
+ * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this
+ * function runs the given memory resource checking it against the stored
+ * CRC to ensure that memory is restored. The function tries to skip as
+ * many of the areas used during the suspend process.
+ */
+static u32 *s3c_pm_runcheck(struct resource *res, u32 *val)
+{
+        void *save_at = phys_to_virt(s3c_sleep_save_phys);
+        unsigned long addr;
+        unsigned long left;
+        void *stkpage;
+        void *ptr;
+        u32 calc;
+
+        stkpage = (void *)((u32)&calc & ~PAGE_MASK);
+
+        for (addr = res->start; addr < res->end;
+             addr += CHECK_CHUNKSIZE) {
+                left = res->end - addr;
+
+                if (left > CHECK_CHUNKSIZE)
+                        left = CHECK_CHUNKSIZE;
+
+                ptr = phys_to_virt(addr);
+
+                if (in_region(ptr, left, stkpage, 4096)) {
+                        S3C_PMDBG("skipping %08lx, has stack in\n", addr);
+                        goto skip_check;
+                }
+
+                if (in_region(ptr, left, crcs, crc_size)) {
+                        S3C_PMDBG("skipping %08lx, has crc block in\n", addr);
+                        goto skip_check;
+                }
+
+                if (in_region(ptr, left, save_at, 32*4 )) {
+                        S3C_PMDBG("skipping %08lx, has save block in\n", addr);
+                        goto skip_check;
+                }
+
+                /* calculate and check the checksum */
+
+                calc = crc32_le(~0, ptr, left);
+                if (calc != *val) {
+                        printk(KERN_ERR "Restore CRC error at "
+                               "%08lx (%08x vs %08x)\n", addr, calc, *val);
+
+                        S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n",
+                            addr, calc, *val);
+                }
+
+        skip_check:
+                val++;
+        }
+
+        return val;
+}
+
+/**
+ * s3c_pm_check_restore() - memory check called on resume
+ *
+ * check the CRCs after the restore event and free the memory used
+ * to hold them
+*/
+void s3c_pm_check_restore(void)
+{
+        if (crcs != NULL)
+                s3c_pm_run_sysram(s3c_pm_runcheck, crcs);
+}
+
+/**
+ * s3c_pm_check_cleanup() - free memory resources
+ *
+ * Free the resources that where allocated by the suspend
+ * memory check code. We do this separately from the
+ * s3c_pm_check_restore() function as we cannot call any
+ * functions that might sleep during that resume.
+ */
+void s3c_pm_check_cleanup(void)
+{
+        kfree(crcs);
+        crcs = NULL;
+}
+
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
new file mode 100644
index 000000000000..69a4c7f02e25
--- /dev/null
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -0,0 +1,380 @@
+
+/* linux/arch/arm/plat-s3c/pm-gpio.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series GPIO PM code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/sysdev.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-core.h>
+#include <plat/pm.h>
+
+/* PM GPIO helpers */
+
+#define OFFS_CON        (0x00)
+#define OFFS_DAT        (0x04)
+#define OFFS_UP         (0x08)
+
+static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
+{
+        chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+        chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+}
+
+static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
+{
+        void __iomem *base = chip->base;
+        u32 old_gpcon = __raw_readl(base + OFFS_CON);
+        u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+        u32 gps_gpcon = chip->pm_save[0];
+        u32 gps_gpdat = chip->pm_save[1];
+        u32 gpcon;
+
+        /* GPACON only has one bit per control / data and no PULLUPs.
+         * GPACON[x] = 0 => Output, 1 => SFN */
+
+        /* first set all SFN bits to SFN */
+
+        gpcon = old_gpcon | gps_gpcon;
+        __raw_writel(gpcon, base + OFFS_CON);
+
+        /* now set all the other bits */
+
+        __raw_writel(gps_gpdat, base + OFFS_DAT);
+        __raw_writel(gps_gpcon, base + OFFS_CON);
+
+        S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
+                  chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_1bit = {
+        .save   = s3c_gpio_pm_1bit_save,
+        .resume = s3c_gpio_pm_1bit_resume,
+};
+
+static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
+{
+        chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+        chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+        chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
+}
+
+/* Test whether the given masked+shifted bits of an GPIO configuration
+ * are one of the SFN (special function) modes. */
+
+static inline int is_sfn(unsigned long con)
+{
+        return con >= 2;
+}
+
+/* Test if the given masked+shifted GPIO configuration is an input */
+
+static inline int is_in(unsigned long con)
+{
+        return con == 0;
+}
+
+/* Test if the given masked+shifted GPIO configuration is an output */
+
+static inline int is_out(unsigned long con)
+{
+        return con == 1;
+}
+
+/**
+ * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
+ * @chip: The chip information to resume.
+ *
+ * Restore one of the GPIO banks that was saved during suspend. This is
+ * not as simple as once thought, due to the possibility of glitches
+ * from the order that the CON and DAT registers are set in.
+ *
+ * The three states the pin can be are {IN,OUT,SFN} which gives us 9
+ * combinations of changes to check. Three of these, if the pin stays
+ * in the same configuration can be discounted. This leaves us with
+ * the following:
+ *
+ * { IN => OUT }  Change DAT first
+ * { IN => SFN }  Change CON first
+ * { OUT => SFN } Change CON first, so new data will not glitch
+ * { OUT => IN }  Change CON first, so new data will not glitch
+ * { SFN => IN }  Change CON first
+ * { SFN => OUT } Change DAT first, so new data will not glitch [1]
+ *
+ * We do not currently deal with the UP registers as these control
+ * weak resistors, so a small delay in change should not need to bring
+ * these into the calculations.
+ *
+ * [1] this assumes that writing to a pin DAT whilst in SFN will set the
+ *     state for when it is next output.
+ */
+static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
+{
+        void __iomem *base = chip->base;
+        u32 old_gpcon = __raw_readl(base + OFFS_CON);
+        u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+        u32 gps_gpcon = chip->pm_save[0];
+        u32 gps_gpdat = chip->pm_save[1];
+        u32 gpcon, old, new, mask;
+        u32 change_mask = 0x0;
+        int nr;
+
+        /* restore GPIO pull-up settings */
+        __raw_writel(chip->pm_save[2], base + OFFS_UP);
+
+        /* Create a change_mask of all the items that need to have
+         * their CON value changed before their DAT value, so that
+         * we minimise the work between the two settings.
+         */
+
+        for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
+                old = (old_gpcon & mask) >> nr;
+                new = (gps_gpcon & mask) >> nr;
+
+                /* If there is no change, then skip */
+
+                if (old == new)
+                        continue;
+
+                /* If both are special function, then skip */
+
+                if (is_sfn(old) && is_sfn(new))
+                        continue;
+
+                /* Change is IN => OUT, do not change now */
+
+                if (is_in(old) && is_out(new))
+                        continue;
+
+                /* Change is SFN => OUT, do not change now */
+
+                if (is_sfn(old) && is_out(new))
+                        continue;
+
+                /* We should now be at the case of IN=>SFN,
+                 * OUT=>SFN, OUT=>IN, SFN=>IN. */
+
+                change_mask |= mask;
+        }
+
+
+        /* Write the new CON settings */
+
+        gpcon = old_gpcon & ~change_mask;
+        gpcon |= gps_gpcon & change_mask;
+
+        __raw_writel(gpcon, base + OFFS_CON);
+
+        /* Now change any items that require DAT,CON */
+
+        __raw_writel(gps_gpdat, base + OFFS_DAT);
+        __raw_writel(gps_gpcon, base + OFFS_CON);
+
+        S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
+                  chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_2bit = {
+        .save   = s3c_gpio_pm_2bit_save,
+        .resume = s3c_gpio_pm_2bit_resume,
+};
+
+#ifdef CONFIG_ARCH_S3C64XX
+static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
+{
+        chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
+        chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
+        chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
+
+        if (chip->chip.ngpio > 8)
+                chip->pm_save[0] = __raw_readl(chip->base - 4);
+}
+
+static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
+{
+        u32 old, new, mask;
+        u32 change_mask = 0x0;
+        int nr;
+
+        for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
+                old = (old_gpcon & mask) >> nr;
+                new = (gps_gpcon & mask) >> nr;
+
+                /* If there is no change, then skip */
+
+                if (old == new)
+                        continue;
+
+                /* If both are special function, then skip */
+
+                if (is_sfn(old) && is_sfn(new))
+                        continue;
+
+                /* Change is IN => OUT, do not change now */
+
+                if (is_in(old) && is_out(new))
+                        continue;
+
+                /* Change is SFN => OUT, do not change now */
+
+                if (is_sfn(old) && is_out(new))
+                        continue;
+
+                /* We should now be at the case of IN=>SFN,
+                 * OUT=>SFN, OUT=>IN, SFN=>IN. */
+
+                change_mask |= mask;
+        }
+
+        return change_mask;
+}
+
+static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
+{
+        void __iomem *con = chip->base + (index * 4);
+        u32 old_gpcon = __raw_readl(con);
+        u32 gps_gpcon = chip->pm_save[index + 1];
+        u32 gpcon, mask;
+
+        mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
+
+        gpcon = old_gpcon & ~mask;
+        gpcon |= gps_gpcon & mask;
+
+        __raw_writel(gpcon, con);
+}
+
+static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
+{
+        void __iomem *base = chip->base;
+        u32 old_gpcon[2];
+        u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+        u32 gps_gpdat = chip->pm_save[2];
+
+        /* First, modify the CON settings */
+
+        old_gpcon[0] = 0;
+        old_gpcon[1] = __raw_readl(base + OFFS_CON);
+
+        s3c_gpio_pm_4bit_con(chip, 0);
+        if (chip->chip.ngpio > 8) {
+                old_gpcon[0] = __raw_readl(base - 4);
+                s3c_gpio_pm_4bit_con(chip, -1);
+        }
+
+        /* Now change the configurations that require DAT,CON */
+
+        __raw_writel(chip->pm_save[2], base + OFFS_DAT);
+        __raw_writel(chip->pm_save[1], base + OFFS_CON);
+        if (chip->chip.ngpio > 8)
+                __raw_writel(chip->pm_save[0], base - 4);
+
+        __raw_writel(chip->pm_save[2], base + OFFS_DAT);
+        __raw_writel(chip->pm_save[3], base + OFFS_UP);
+
+        if (chip->chip.ngpio > 8) {
+                S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
+                          chip->chip.label, old_gpcon[0], old_gpcon[1],
+                          __raw_readl(base - 4),
+                          __raw_readl(base + OFFS_CON),
+                          old_gpdat, gps_gpdat);
+        } else
+                S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
+                          chip->chip.label, old_gpcon[1],
+                          __raw_readl(base + OFFS_CON),
+                          old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_4bit = {
+        .save   = s3c_gpio_pm_4bit_save,
+        .resume = s3c_gpio_pm_4bit_resume,
+};
+#endif /* CONFIG_ARCH_S3C64XX */
+
+/**
+ * s3c_pm_save_gpio() - save gpio chip data for suspend
+ * @ourchip: The chip for suspend.
+ */
+static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
+{
+        struct s3c_gpio_pm *pm = ourchip->pm;
+
+        if (pm == NULL || pm->save == NULL)
+                S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+        else
+                pm->save(ourchip);
+}
+
+/**
+ * s3c_pm_save_gpios() - Save the state of the GPIO banks.
+ *
+ * For all the GPIO banks, save the state of each one ready for going
+ * into a suspend mode.
+ */
+void s3c_pm_save_gpios(void)
+{
+        struct s3c_gpio_chip *ourchip;
+        unsigned int gpio_nr;
+
+        for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+                ourchip = s3c_gpiolib_getchip(gpio_nr);
+                if (!ourchip)
+                        continue;
+
+                s3c_pm_save_gpio(ourchip);
+
+                S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
+                          ourchip->chip.label,
+                          ourchip->pm_save[0],
+                          ourchip->pm_save[1],
+                          ourchip->pm_save[2],
+                          ourchip->pm_save[3]);
+
+                gpio_nr += ourchip->chip.ngpio;
+                gpio_nr += CONFIG_S3C_GPIO_SPACE;
+        }
+}
+
+/**
+ * s3c_pm_resume_gpio() - restore gpio chip data after suspend
+ * @ourchip: The suspended chip.
+ */
+static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
+{
+        struct s3c_gpio_pm *pm = ourchip->pm;
+
+        if (pm == NULL || pm->resume == NULL)
+                S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+        else
+                pm->resume(ourchip);
+}
+
+void s3c_pm_restore_gpios(void)
+{
+        struct s3c_gpio_chip *ourchip;
+        unsigned int gpio_nr;
+
+        for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+                ourchip = s3c_gpiolib_getchip(gpio_nr);
+                if (!ourchip)
+                        continue;
+
+                s3c_pm_resume_gpio(ourchip);
+
+                gpio_nr += ourchip->chip.ngpio;
+                gpio_nr += CONFIG_S3C_GPIO_SPACE;
+        }
+}
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
new file mode 100644
index 000000000000..27cfca597699
--- /dev/null
+++ b/arch/arm/plat-samsung/pm.c
@@ -0,0 +1,378 @@
+/* linux/arch/arm/plat-s3c/pm.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2004-2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C common power management (suspend to ram) support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-irq.h>
+#include <asm/irq.h>
+
+#include <plat/pm.h>
+#include <mach/pm-core.h>
+
+/* for external use */
+
+unsigned long s3c_pm_flags;
+
+/* Debug code:
+ *
+ * This code supports debug output to the low level UARTs for use on
+ * resume before the console layer is available.
+*/
+
+#ifdef CONFIG_SAMSUNG_PM_DEBUG
+extern void printascii(const char *);
+
+void s3c_pm_dbg(const char *fmt, ...)
+{
+        va_list va;
+        char buff[256];
+
+        va_start(va, fmt);
+        vsprintf(buff, fmt, va);
+        va_end(va);
+
+        printascii(buff);
+}
+
+static inline void s3c_pm_debug_init(void)
+{
+        /* restart uart clocks so we can use them to output */
+        s3c_pm_debug_init_uart();
+}
+
+#else
+#define s3c_pm_debug_init() do { } while(0)
+
+#endif /* CONFIG_SAMSUNG_PM_DEBUG */
+
+/* Save the UART configurations if we are configured for debug. */
+
+unsigned char pm_uart_udivslot;
+
+#ifdef CONFIG_SAMSUNG_PM_DEBUG
+
+struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
+{
+        void __iomem *regs = S3C_VA_UARTx(uart);
+
+        save->ulcon = __raw_readl(regs + S3C2410_ULCON);
+        save->ucon = __raw_readl(regs + S3C2410_UCON);
+        save->ufcon = __raw_readl(regs + S3C2410_UFCON);
+        save->umcon = __raw_readl(regs + S3C2410_UMCON);
+        save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
+
+        if (pm_uart_udivslot)
+                save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
+
+        S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
+                  uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
+}
+
+static void s3c_pm_save_uarts(void)
+{
+        struct pm_uart_save *save = uart_save;
+        unsigned int uart;
+
+        for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
+                s3c_pm_save_uart(uart, save);
+}
+
+static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
+{
+        void __iomem *regs = S3C_VA_UARTx(uart);
+
+        s3c_pm_arch_update_uart(regs, save);
+
+        __raw_writel(save->ulcon, regs + S3C2410_ULCON);
+        __raw_writel(save->ucon,  regs + S3C2410_UCON);
+        __raw_writel(save->ufcon, regs + S3C2410_UFCON);
+        __raw_writel(save->umcon, regs + S3C2410_UMCON);
+        __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
+
+        if (pm_uart_udivslot)
+                __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
+}
+
+static void s3c_pm_restore_uarts(void)
+{
+        struct pm_uart_save *save = uart_save;
+        unsigned int uart;
+
+        for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
+                s3c_pm_restore_uart(uart, save);
+}
+#else
+static void s3c_pm_save_uarts(void) { }
+static void s3c_pm_restore_uarts(void) { }
+#endif
+
+/* The IRQ ext-int code goes here, it is too small to currently bother
+ * with its own file. */
+
+unsigned long s3c_irqwake_intmask       = 0xffffffffL;
+unsigned long s3c_irqwake_eintmask      = 0xffffffffL;
+
+int s3c_irqext_wake(unsigned int irqno, unsigned int state)
+{
+        unsigned long bit = 1L << IRQ_EINT_BIT(irqno);
+
+        if (!(s3c_irqwake_eintallow & bit))
+                return -ENOENT;
+
+        printk(KERN_INFO "wake %s for irq %d\n",
+               state ? "enabled" : "disabled", irqno);
+
+        if (!state)
+                s3c_irqwake_eintmask |= bit;
+        else
+                s3c_irqwake_eintmask &= ~bit;
+
+        return 0;
+}
+
+/* helper functions to save and restore register state */
+
+/**
+ * s3c_pm_do_save() - save a set of registers for restoration on resume.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Run through the list of registers given, saving their contents in the
+ * array for later restoration when we wakeup.
+ */
+void s3c_pm_do_save(struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++) {
+                ptr->val = __raw_readl(ptr->reg);
+                S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
+        }
+}
+
+/**
+ * s3c_pm_do_restore() - restore register values from the save list.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Restore the register values saved from s3c_pm_do_save().
+ *
+ * Note, we do not use S3C_PMDBG() in here, as the system may not have
+ * restore the UARTs state yet
+*/
+
+void s3c_pm_do_restore(struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++) {
+                printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
+                       ptr->reg, ptr->val, __raw_readl(ptr->reg));
+
+                __raw_writel(ptr->val, ptr->reg);
+        }
+}
+
+/**
+ * s3c_pm_do_restore_core() - early restore register values from save list.
+ *
+ * This is similar to s3c_pm_do_restore() except we try and minimise the
+ * side effects of the function in case registers that hardware might need
+ * to work has been restored.
+ *
+ * WARNING: Do not put any debug in here that may effect memory or use
+ * peripherals, as things may be changing!
+*/
+
+void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++)
+                __raw_writel(ptr->val, ptr->reg);
+}
+
+/* s3c2410_pm_show_resume_irqs
+ *
+ * print any IRQs asserted at resume time (ie, we woke from)
+*/
+static void s3c_pm_show_resume_irqs(int start, unsigned long which,
+                                    unsigned long mask)
+{
+        int i;
+
+        which &= ~mask;
+
+        for (i = 0; i <= 31; i++) {
+                if (which & (1L<<i)) {
+                        S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
+                }
+        }
+}
+
+
+void (*pm_cpu_prep)(void);
+void (*pm_cpu_sleep)(void);
+
+#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
+
+/* s3c_pm_enter
+ *
+ * central control for sleep/resume process
+*/
+
+static int s3c_pm_enter(suspend_state_t state)
+{
+        static unsigned long regs_save[16];
+
+        /* ensure the debug is initialised (if enabled) */
+
+        s3c_pm_debug_init();
+
+        S3C_PMDBG("%s(%d)\n", __func__, state);
+
+        if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
+                printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
+                return -EINVAL;
+        }
+
+        /* check if we have anything to wake-up with... bad things seem
+         * to happen if you suspend with no wakeup (system will often
+         * require a full power-cycle)
+        */
+
+        if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
+            !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
+                printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
+                printk(KERN_ERR "%s: Aborting sleep\n", __func__);
+                return -EINVAL;
+        }
+
+        /* store the physical address of the register recovery block */
+
+        s3c_sleep_save_phys = virt_to_phys(regs_save);
+
+        S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
+
+        /* save all necessary core registers not covered by the drivers */
+
+        s3c_pm_save_gpios();
+        s3c_pm_save_uarts();
+        s3c_pm_save_core();
+
+        /* set the irq configuration for wake */
+
+        s3c_pm_configure_extint();
+
+        S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
+            s3c_irqwake_intmask, s3c_irqwake_eintmask);
+
+        s3c_pm_arch_prepare_irqs();
+
+        /* call cpu specific preparation */
+
+        pm_cpu_prep();
+
+        /* flush cache back to ram */
+
+        flush_cache_all();
+
+        s3c_pm_check_store();
+
+        /* send the cpu to sleep... */
+
+        s3c_pm_arch_stop_clocks();
+
+        /* s3c_cpu_save will also act as our return point from when
+         * we resume as it saves its own register state and restores it
+         * during the resume.  */
+
+        s3c_cpu_save(regs_save);
+
+        /* restore the cpu state using the kernel's cpu init code. */
+
+        cpu_init();
+
+        /* restore the system state */
+
+        s3c_pm_restore_core();
+        s3c_pm_restore_uarts();
+        s3c_pm_restore_gpios();
+
+        s3c_pm_debug_init();
+
+        /* check what irq (if any) restored the system */
+
+        s3c_pm_arch_show_resume_irqs();
+
+        S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
+
+        /* LEDs should now be 1110 */
+        s3c_pm_debug_smdkled(1 << 1, 0);
+
+        s3c_pm_check_restore();
+
+        /* ok, let's return from sleep */
+
+        S3C_PMDBG("S3C PM Resume (post-restore)\n");
+        return 0;
+}
+
+/* callback from assembly code */
+void s3c_pm_cb_flushcache(void)
+{
+        flush_cache_all();
+}
+
+static int s3c_pm_prepare(void)
+{
+        /* prepare check area if configured */
+
+        s3c_pm_check_prepare();
+        return 0;
+}
+
+static void s3c_pm_finish(void)
+{
+        s3c_pm_check_cleanup();
+}
+
+static struct platform_suspend_ops s3c_pm_ops = {
+        .enter          = s3c_pm_enter,
+        .prepare        = s3c_pm_prepare,
+        .finish         = s3c_pm_finish,
+        .valid          = suspend_valid_only_mem,
+};
+
+/* s3c_pm_init
+ *
+ * Attach the power management functions. This should be called
+ * from the board specific initialisation if the board supports
+ * it.
+*/
+
+int __init s3c_pm_init(void)
+{
+        printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
+
+        suspend_set_ops(&s3c_pm_ops);
+        return 0;
+}
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
new file mode 100644
index 000000000000..46c9381e083b
--- /dev/null
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -0,0 +1,455 @@
+/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ * Copyright (c) 2007, 2008 Ben Dooks
+ *      Ben Dooks <ben-linux@fluff.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/log2.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <asm/irq.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+#include <plat/regs-timer.h>
+#include <mach/pwm-clock.h>
+
+/* Each of the timers 0 through 5 go through the following
+ * clock tree, with the inputs depending on the timers.
+ *
+ * pclk ---- [ prescaler 0 ] -+---> timer 0
+ *                            +---> timer 1
+ *
+ * pclk ---- [ prescaler 1 ] -+---> timer 2
+ *                            +---> timer 3
+ *                            \---> timer 4
+ *
+ * Which are fed into the timers as so:
+ *
+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 0
+ * tclk 0 ------------------------------/
+ *
+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 1
+ * tclk 0 ------------------------------/
+ *
+ *
+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 2
+ * tclk 1 ------------------------------/
+ *
+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 3
+ * tclk 1 ------------------------------/
+ *
+ * prescaled 1 ---- [ div 2,4,8, 16 ] --\
+ *                                     [mux] -> timer 4
+ * tclk 1 ------------------------------/
+ *
+ * Since the mux and the divider are tied together in the
+ * same register space, it is impossible to set the parent
+ * and the rate at the same time. To avoid this, we add an
+ * intermediate 'prescaled-and-divided' clock to select
+ * as the parent for the timer input clock called tdiv.
+ *
+ * prescaled clk --> pwm-tdiv ---\
+ *                             [ mux ] --> timer X
+ * tclk -------------------------/
+*/
+
+static struct clk clk_timer_scaler[];
+
+static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
+{
+        unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
+
+        if (clk == &clk_timer_scaler[1]) {
+                tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
+                tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
+        } else {
+                tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
+        }
+
+        return clk_get_rate(clk->parent) / (tcfg0 + 1);
+}
+
+static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
+                                               unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long divisor = parent_rate / rate;
+
+        if (divisor > 256)
+                divisor = 256;
+        else if (divisor < 2)
+                divisor = 2;
+
+        return parent_rate / divisor;
+}
+
+static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
+        unsigned long tcfg0;
+        unsigned long divisor;
+        unsigned long flags;
+
+        divisor = clk_get_rate(clk->parent) / round;
+        divisor--;
+
+        local_irq_save(flags);
+        tcfg0 = __raw_readl(S3C2410_TCFG0);
+
+        if (clk == &clk_timer_scaler[1]) {
+                tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
+                tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
+        } else {
+                tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
+                tcfg0 |= divisor;
+        }
+
+        __raw_writel(tcfg0, S3C2410_TCFG0);
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static struct clk_ops clk_pwm_scaler_ops = {
+        .get_rate       = clk_pwm_scaler_get_rate,
+        .set_rate       = clk_pwm_scaler_set_rate,
+        .round_rate     = clk_pwm_scaler_round_rate,
+};
+
+static struct clk clk_timer_scaler[] = {
+        [0]     = {
+                .name           = "pwm-scaler0",
+                .id             = -1,
+                .ops            = &clk_pwm_scaler_ops,
+        },
+        [1]     = {
+                .name           = "pwm-scaler1",
+                .id             = -1,
+                .ops            = &clk_pwm_scaler_ops,
+        },
+};
+
+static struct clk clk_timer_tclk[] = {
+        [0]     = {
+                .name           = "pwm-tclk0",
+                .id             = -1,
+        },
+        [1]     = {
+                .name           = "pwm-tclk1",
+                .id             = -1,
+        },
+};
+
+struct pwm_tdiv_clk {
+        struct clk      clk;
+        unsigned int    divisor;
+};
+
+static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
+{
+        return container_of(clk, struct pwm_tdiv_clk, clk);
+}
+
+static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
+{
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned int divisor;
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        if (pwm_cfg_src_is_tclk(tcfg1))
+                divisor = to_tdiv(clk)->divisor;
+        else
+                divisor = tcfg_to_divisor(tcfg1);
+
+        return clk_get_rate(clk->parent) / divisor;
+}
+
+static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
+                                             unsigned long rate)
+{
+        unsigned long parent_rate;
+        unsigned long divisor;
+
+        parent_rate = clk_get_rate(clk->parent);
+        divisor = parent_rate / rate;
+
+        if (divisor <= 1 && pwm_tdiv_has_div1())
+                divisor = 1;
+        else if (divisor <= 2)
+                divisor = 2;
+        else if (divisor <= 4)
+                divisor = 4;
+        else if (divisor <= 8)
+                divisor = 8;
+        else
+                divisor = 16;
+
+        return parent_rate / divisor;
+}
+
+static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
+{
+        return pwm_tdiv_div_bits(divclk->divisor);
+}
+
+static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
+{
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned long bits = clk_pwm_tdiv_bits(divclk);
+        unsigned long flags;
+        unsigned long shift =  S3C2410_TCFG1_SHIFT(divclk->clk.id);
+
+        local_irq_save(flags);
+
+        tcfg1 = __raw_readl(S3C2410_TCFG1);
+        tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
+        tcfg1 |= bits << shift;
+        __raw_writel(tcfg1, S3C2410_TCFG1);
+
+        local_irq_restore(flags);
+}
+
+static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct pwm_tdiv_clk *divclk = to_tdiv(clk);
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long divisor;
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        rate = clk_round_rate(clk, rate);
+        divisor = parent_rate / rate;
+
+        if (divisor > 16)
+                return -EINVAL;
+
+        divclk->divisor = divisor;
+
+        /* Update the current MUX settings if we are currently
+         * selected as the clock source for this clock. */
+
+        if (!pwm_cfg_src_is_tclk(tcfg1))
+                clk_pwm_tdiv_update(divclk);
+
+        return 0;
+}
+
+static struct clk_ops clk_tdiv_ops = {
+        .get_rate       = clk_pwm_tdiv_get_rate,
+        .set_rate       = clk_pwm_tdiv_set_rate,
+        .round_rate     = clk_pwm_tdiv_round_rate,
+};
+
+static struct pwm_tdiv_clk clk_timer_tdiv[] = {
+        [0]     = {
+                .clk    = {
+                        .name   = "pwm-tdiv",
+                        .ops    = &clk_tdiv_ops,
+                        .parent = &clk_timer_scaler[0],
+                },
+        },
+        [1]     = {
+                .clk    = {
+                        .name   = "pwm-tdiv",
+                        .ops    = &clk_tdiv_ops,
+                        .parent = &clk_timer_scaler[0],
+                }
+        },
+        [2]     = {
+                .clk    = {
+                        .name   = "pwm-tdiv",
+                        .ops    = &clk_tdiv_ops,
+                        .parent = &clk_timer_scaler[1],
+                },
+        },
+        [3]     = {
+                .clk    = {
+                        .name   = "pwm-tdiv",
+                        .ops    = &clk_tdiv_ops,
+                        .parent = &clk_timer_scaler[1],
+                },
+        },
+        [4]     = {
+                .clk    = {
+                        .name   = "pwm-tdiv",
+                        .ops    = &clk_tdiv_ops,
+                        .parent = &clk_timer_scaler[1],
+                },
+        },
+};
+
+static int __init clk_pwm_tdiv_register(unsigned int id)
+{
+        struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        divclk->clk.id = id;
+        divclk->divisor = tcfg_to_divisor(tcfg1);
+
+        return s3c24xx_register_clock(&divclk->clk);
+}
+
+static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
+{
+        return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
+}
+
+static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
+{
+        return &clk_timer_tdiv[id].clk;
+}
+
+static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
+{
+        unsigned int id = clk->id;
+        unsigned long tcfg1;
+        unsigned long flags;
+        unsigned long bits;
+        unsigned long shift = S3C2410_TCFG1_SHIFT(id);
+
+        if (parent == s3c24xx_pwmclk_tclk(id))
+                bits = S3C_TCFG1_MUX_TCLK << shift;
+        else if (parent == s3c24xx_pwmclk_tdiv(id))
+                bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        local_irq_save(flags);
+
+        tcfg1 = __raw_readl(S3C2410_TCFG1);
+        tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
+        __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static struct clk_ops clk_tin_ops = {
+        .set_parent     = clk_pwm_tin_set_parent,
+};
+
+static struct clk clk_tin[] = {
+        [0]     = {
+                .name   = "pwm-tin",
+                .id     = 0,
+                .ops    = &clk_tin_ops,
+        },
+        [1]     = {
+                .name   = "pwm-tin",
+                .id     = 1,
+                .ops    = &clk_tin_ops,
+        },
+        [2]     = {
+                .name   = "pwm-tin",
+                .id     = 2,
+                .ops    = &clk_tin_ops,
+        },
+        [3]     = {
+                .name   = "pwm-tin",
+                .id     = 3,
+                .ops    = &clk_tin_ops,
+        },
+        [4]     = {
+                .name   = "pwm-tin",
+                .id     = 4,
+                .ops    = &clk_tin_ops,
+        },
+};
+
+static __init int clk_pwm_tin_register(struct clk *pwm)
+{
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned int id = pwm->id;
+
+        struct clk *parent;
+        int ret;
+
+        ret = s3c24xx_register_clock(pwm);
+        if (ret < 0)
+                return ret;
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        if (pwm_cfg_src_is_tclk(tcfg1))
+                parent = s3c24xx_pwmclk_tclk(id);
+        else
+                parent = s3c24xx_pwmclk_tdiv(id);
+
+        return clk_set_parent(pwm, parent);
+}
+
+/**
+ * s3c_pwmclk_init() - initialise pwm clocks
+ *
+ * Initialise and register the clocks which provide the inputs for the
+ * pwm timer blocks.
+ *
+ * Note, this call is required by the time core, so must be called after
+ * the base clocks are added and before any of the initcalls are run.
+ */
+__init void s3c_pwmclk_init(void)
+{
+        struct clk *clk_timers;
+        unsigned int clk;
+        int ret;
+
+        clk_timers = clk_get(NULL, "timers");
+        if (IS_ERR(clk_timers)) {
+                printk(KERN_ERR "%s: no parent clock\n", __func__);
+                return;
+        }
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++)
+                clk_timer_scaler[clk].parent = clk_timers;
+
+        s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler));
+        s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk));
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
+                ret = clk_pwm_tdiv_register(clk);
+
+                if (ret < 0) {
+                        printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
+                        return;
+                }
+        }
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
+                ret = clk_pwm_tin_register(&clk_tin[clk]);
+                if (ret < 0) {
+                        printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
+                        return;
+                }
+        }
+}
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c
new file mode 100644
index 000000000000..f2d11390d01c
--- /dev/null
+++ b/arch/arm/plat-samsung/pwm.c
@@ -0,0 +1,445 @@
+/* arch/arm/plat-s3c/pwm.c
+ *
+ * Copyright (c) 2007 Ben Dooks
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
+ *
+ * S3C series PWM device core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/pwm.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+#include <plat/regs-timer.h>
+
+struct pwm_device {
+        struct list_head         list;
+        struct platform_device  *pdev;
+
+        struct clk              *clk_div;
+        struct clk              *clk;
+        const char              *label;
+
+        unsigned int             period_ns;
+        unsigned int             duty_ns;
+
+        unsigned char            tcon_base;
+        unsigned char            running;
+        unsigned char            use_count;
+        unsigned char            pwm_id;
+};
+
+#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg)
+
+static struct clk *clk_scaler[2];
+
+/* Standard setup for a timer block. */
+
+#define TIMER_RESOURCE_SIZE (1)
+
+#define TIMER_RESOURCE(_tmr, _irq)                      \
+        (struct resource [TIMER_RESOURCE_SIZE]) {       \
+                [0] = {                                 \
+                        .start  = _irq,                 \
+                        .end    = _irq,                 \
+                        .flags  = IORESOURCE_IRQ        \
+                }                                       \
+        }
+
+#define DEFINE_S3C_TIMER(_tmr_no, _irq)                 \
+        .name           = "s3c24xx-pwm",                \
+        .id             = _tmr_no,                      \
+        .num_resources  = TIMER_RESOURCE_SIZE,          \
+        .resource       = TIMER_RESOURCE(_tmr_no, _irq),        \
+
+/* since we already have an static mapping for the timer, we do not
+ * bother setting any IO resource for the base.
+ */
+
+struct platform_device s3c_device_timer[] = {
+        [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
+        [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
+        [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
+        [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
+        [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
+};
+
+static inline int pwm_is_tdiv(struct pwm_device *pwm)
+{
+        return clk_get_parent(pwm->clk) == pwm->clk_div;
+}
+
+static DEFINE_MUTEX(pwm_lock);
+static LIST_HEAD(pwm_list);
+
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+        struct pwm_device *pwm;
+        int found = 0;
+
+        mutex_lock(&pwm_lock);
+
+        list_for_each_entry(pwm, &pwm_list, list) {
+                if (pwm->pwm_id == pwm_id) {
+                        found = 1;
+                        break;
+                }
+        }
+
+        if (found) {
+                if (pwm->use_count == 0) {
+                        pwm->use_count = 1;
+                        pwm->label = label;
+                } else
+                        pwm = ERR_PTR(-EBUSY);
+        } else
+                pwm = ERR_PTR(-ENOENT);
+
+        mutex_unlock(&pwm_lock);
+        return pwm;
+}
+
+EXPORT_SYMBOL(pwm_request);
+
+
+void pwm_free(struct pwm_device *pwm)
+{
+        mutex_lock(&pwm_lock);
+
+        if (pwm->use_count) {
+                pwm->use_count--;
+                pwm->label = NULL;
+        } else
+                printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id);
+
+        mutex_unlock(&pwm_lock);
+}
+
+EXPORT_SYMBOL(pwm_free);
+
+#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0))
+#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2))
+#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3))
+#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1))
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        unsigned long flags;
+        unsigned long tcon;
+
+        local_irq_save(flags);
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon |= pwm_tcon_start(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+        pwm->running = 1;
+        return 0;
+}
+
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        unsigned long flags;
+        unsigned long tcon;
+
+        local_irq_save(flags);
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon &= ~pwm_tcon_start(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+        pwm->running = 0;
+}
+
+EXPORT_SYMBOL(pwm_disable);
+
+static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
+{
+        unsigned long tin_parent_rate;
+        unsigned int div;
+
+        tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div));
+        pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate);
+
+        for (div = 2; div <= 16; div *= 2) {
+                if ((tin_parent_rate / (div << 16)) < freq)
+                        return tin_parent_rate / div;
+        }
+
+        return tin_parent_rate / 16;
+}
+
+#define NS_IN_HZ (1000000000UL)
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long tin_rate;
+        unsigned long tin_ns;
+        unsigned long period;
+        unsigned long flags;
+        unsigned long tcon;
+        unsigned long tcnt;
+        long tcmp;
+
+        /* We currently avoid using 64bit arithmetic by using the
+         * fact that anything faster than 1Hz is easily representable
+         * by 32bits. */
+
+        if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
+                return -ERANGE;
+
+        if (duty_ns > period_ns)
+                return -EINVAL;
+
+        if (period_ns == pwm->period_ns &&
+            duty_ns == pwm->duty_ns)
+                return 0;
+
+        /* The TCMP and TCNT can be read without a lock, they're not
+         * shared between the timers. */
+
+        tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id));
+        tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id));
+
+        period = NS_IN_HZ / period_ns;
+
+        pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n",
+                duty_ns, period_ns, period);
+
+        /* Check to see if we are changing the clock rate of the PWM */
+
+        if (pwm->period_ns != period_ns) {
+                if (pwm_is_tdiv(pwm)) {
+                        tin_rate = pwm_calc_tin(pwm, period);
+                        clk_set_rate(pwm->clk_div, tin_rate);
+                } else
+                        tin_rate = clk_get_rate(pwm->clk);
+
+                pwm->period_ns = period_ns;
+
+                pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate);
+
+                tin_ns = NS_IN_HZ / tin_rate;
+                tcnt = period_ns / tin_ns;
+        } else
+                tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk);
+
+        /* Note, counters count down */
+
+        tcmp = duty_ns / tin_ns;
+        tcmp = tcnt - tcmp;
+        /* the pwm hw only checks the compare register after a decrement,
+           so the pin never toggles if tcmp = tcnt */
+        if (tcmp == tcnt)
+                tcmp--;
+
+        pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
+
+        if (tcmp < 0)
+                tcmp = 0;
+
+        /* Update the PWM register block. */
+
+        local_irq_save(flags);
+
+        __raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id));
+        __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id));
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon |= pwm_tcon_manulupdate(pwm);
+        tcon |= pwm_tcon_autoreload(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        tcon &= ~pwm_tcon_manulupdate(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(pwm_config);
+
+static int pwm_register(struct pwm_device *pwm)
+{
+        pwm->duty_ns = -1;
+        pwm->period_ns = -1;
+
+        mutex_lock(&pwm_lock);
+        list_add_tail(&pwm->list, &pwm_list);
+        mutex_unlock(&pwm_lock);
+
+        return 0;
+}
+
+static int s3c_pwm_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct pwm_device *pwm;
+        unsigned long flags;
+        unsigned long tcon;
+        unsigned int id = pdev->id;
+        int ret;
+
+        if (id == 4) {
+                dev_err(dev, "TIMER4 is currently not supported\n");
+                return -ENXIO;
+        }
+
+        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+        if (pwm == NULL) {
+                dev_err(dev, "failed to allocate pwm_device\n");
+                return -ENOMEM;
+        }
+
+        pwm->pdev = pdev;
+        pwm->pwm_id = id;
+
+        /* calculate base of control bits in TCON */
+        pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4;
+
+        pwm->clk = clk_get(dev, "pwm-tin");
+        if (IS_ERR(pwm->clk)) {
+                dev_err(dev, "failed to get pwm tin clk\n");
+                ret = PTR_ERR(pwm->clk);
+                goto err_alloc;
+        }
+
+        pwm->clk_div = clk_get(dev, "pwm-tdiv");
+        if (IS_ERR(pwm->clk_div)) {
+                dev_err(dev, "failed to get pwm tdiv clk\n");
+                ret = PTR_ERR(pwm->clk_div);
+                goto err_clk_tin;
+        }
+
+        local_irq_save(flags);
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon |= pwm_tcon_invert(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+
+        ret = pwm_register(pwm);
+        if (ret) {
+                dev_err(dev, "failed to register pwm\n");
+                goto err_clk_tdiv;
+        }
+
+        pwm_dbg(pwm, "config bits %02x\n",
+                (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f);
+
+        dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
+                 clk_get_rate(pwm->clk),
+                 clk_get_rate(pwm->clk_div),
+                 pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base);
+
+        platform_set_drvdata(pdev, pwm);
+        return 0;
+
+ err_clk_tdiv:
+        clk_put(pwm->clk_div);
+
+ err_clk_tin:
+        clk_put(pwm->clk);
+
+ err_alloc:
+        kfree(pwm);
+        return ret;
+}
+
+static int __devexit s3c_pwm_remove(struct platform_device *pdev)
+{
+        struct pwm_device *pwm = platform_get_drvdata(pdev);
+
+        clk_put(pwm->clk_div);
+        clk_put(pwm->clk);
+        kfree(pwm);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        struct pwm_device *pwm = platform_get_drvdata(pdev);
+
+        /* No one preserve these values during suspend so reset them
+         * Otherwise driver leaves PWM unconfigured if same values
+         * passed to pwm_config
+         */
+        pwm->period_ns = 0;
+        pwm->duty_ns = 0;
+
+        return 0;
+}
+
+static int s3c_pwm_resume(struct platform_device *pdev)
+{
+        struct pwm_device *pwm = platform_get_drvdata(pdev);
+        unsigned long tcon;
+
+        /* Restore invertion */
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon |= pwm_tcon_invert(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        return 0;
+}
+
+#else
+#define s3c_pwm_suspend NULL
+#define s3c_pwm_resume NULL
+#endif
+
+static struct platform_driver s3c_pwm_driver = {
+        .driver         = {
+                .name   = "s3c24xx-pwm",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = s3c_pwm_probe,
+        .remove         = __devexit_p(s3c_pwm_remove),
+        .suspend        = s3c_pwm_suspend,
+        .resume         = s3c_pwm_resume,
+};
+
+static int __init pwm_init(void)
+{
+        int ret;
+
+        clk_scaler[0] = clk_get(NULL, "pwm-scaler0");
+        clk_scaler[1] = clk_get(NULL, "pwm-scaler1");
+
+        if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) {
+                printk(KERN_ERR "%s: failed to get scaler clocks\n", __func__);
+                return -EINVAL;
+        }
+
+        ret = platform_driver_register(&s3c_pwm_driver);
+        if (ret)
+                printk(KERN_ERR "%s: failed to add pwm driver\n", __func__);
+
+        return ret;
+}
+
+arch_initcall(pwm_init);
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
new file mode 100644
index 000000000000..2231d80ad817
--- /dev/null
+++ b/arch/arm/plat-samsung/time.c
@@ -0,0 +1,285 @@
+/* linux/arch/arm/plat-samsung/time.c
+ *
+ * Copyright (C) 2003-2005 Simtec Electronics
+ *      Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <asm/system.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+
+#include <asm/irq.h>
+#include <mach/map.h>
+#include <plat/regs-timer.h>
+#include <mach/regs-irq.h>
+#include <asm/mach/time.h>
+#include <mach/tick.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+static unsigned long timer_startval;
+static unsigned long timer_usec_ticks;
+
+#ifndef TICK_MAX
+#define TICK_MAX (0xffff)
+#endif
+
+#define TIMER_USEC_SHIFT 16
+
+/* we use the shifted arithmetic to work out the ratio of timer ticks
+ * to usecs, as often the peripheral clock is not a nice even multiple
+ * of 1MHz.
+ *
+ * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
+ * for the current HZ value of 200 without producing overflows.
+ *
+ * Original patch by Dimitry Andric, updated by Ben Dooks
+*/
+
+
+/* timer_mask_usec_ticks
+ *
+ * given a clock and divisor, make the value to pass into timer_ticks_to_usec
+ * to scale the ticks into usecs
+*/
+
+static inline unsigned long
+timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
+{
+        unsigned long den = pclk / 1000;
+
+        return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
+}
+
+/* timer_ticks_to_usec
+ *
+ * convert timer ticks to usec.
+*/
+
+static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
+{
+        unsigned long res;
+
+        res = ticks * timer_usec_ticks;
+        res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
+
+        return res >> TIMER_USEC_SHIFT;
+}
+
+/***
+ * Returns microsecond  since last clock interrupt.  Note that interrupts
+ * will have been disabled by do_gettimeoffset()
+ * IRQs are disabled before entering here from do_gettimeofday()
+ */
+
+static unsigned long s3c2410_gettimeoffset (void)
+{
+        unsigned long tdone;
+        unsigned long tval;
+
+        /* work out how many ticks have gone since last timer interrupt */
+
+        tval =  __raw_readl(S3C2410_TCNTO(4));
+        tdone = timer_startval - tval;
+
+        /* check to see if there is an interrupt pending */
+
+        if (s3c24xx_ostimer_pending()) {
+                /* re-read the timer, and try and fix up for the missed
+                 * interrupt. Note, the interrupt may go off before the
+                 * timer has re-loaded from wrapping.
+                 */
+
+                tval =  __raw_readl(S3C2410_TCNTO(4));
+                tdone = timer_startval - tval;
+
+                if (tval != 0)
+                        tdone += timer_startval;
+        }
+
+        return timer_ticks_to_usec(tdone);
+}
+
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t
+s3c2410_timer_interrupt(int irq, void *dev_id)
+{
+        timer_tick();
+        return IRQ_HANDLED;
+}
+
+static struct irqaction s3c2410_timer_irq = {
+        .name           = "S3C2410 Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = s3c2410_timer_interrupt,
+};
+
+#define use_tclk1_12() ( \
+        machine_is_bast()       || \
+        machine_is_vr1000()     || \
+        machine_is_anubis()     || \
+        machine_is_osiris())
+
+static struct clk *tin;
+static struct clk *tdiv;
+static struct clk *timerclk;
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ *
+ * Currently we only use timer4, as it is the only timer which has no
+ * other function that can be exploited externally
+ */
+static void s3c2410_timer_setup (void)
+{
+        unsigned long tcon;
+        unsigned long tcnt;
+        unsigned long tcfg1;
+        unsigned long tcfg0;
+
+        tcnt = TICK_MAX;  /* default value for tcnt */
+
+        /* configure the system for whichever machine is in use */
+
+        if (use_tclk1_12()) {
+                /* timer is at 12MHz, scaler is 1 */
+                timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
+                tcnt = 12000000 / HZ;
+
+                tcfg1 = __raw_readl(S3C2410_TCFG1);
+                tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
+                tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
+                __raw_writel(tcfg1, S3C2410_TCFG1);
+        } else {
+                unsigned long pclk;
+                struct clk *tscaler;
+
+                /* for the h1940 (and others), we use the pclk from the core
+                 * to generate the timer values. since values around 50 to
+                 * 70MHz are not values we can directly generate the timer
+                 * value from, we need to pre-scale and divide before using it.
+                 *
+                 * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
+                 * (8.45 ticks per usec)
+                 */
+
+                pclk = clk_get_rate(timerclk);
+
+                /* configure clock tick */
+
+                timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
+
+                tscaler = clk_get_parent(tdiv);
+
+                clk_set_rate(tscaler, pclk / 3);
+                clk_set_rate(tdiv, pclk / 6);
+                clk_set_parent(tin, tdiv);
+
+                tcnt = clk_get_rate(tin) / HZ;
+        }
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcfg0 = __raw_readl(S3C2410_TCFG0);
+        tcfg1 = __raw_readl(S3C2410_TCFG1);
+
+        /* timers reload after counting zero, so reduce the count by 1 */
+
+        tcnt--;
+
+        printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
+               tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
+
+        /* check to see if timer is within 16bit range... */
+        if (tcnt > TICK_MAX) {
+                panic("setup_timer: HZ is too small, cannot configure timer!");
+                return;
+        }
+
+        __raw_writel(tcfg1, S3C2410_TCFG1);
+        __raw_writel(tcfg0, S3C2410_TCFG0);
+
+        timer_startval = tcnt;
+        __raw_writel(tcnt, S3C2410_TCNTB(4));
+
+        /* ensure timer is stopped... */
+
+        tcon &= ~(7<<20);
+        tcon |= S3C2410_TCON_T4RELOAD;
+        tcon |= S3C2410_TCON_T4MANUALUPD;
+
+        __raw_writel(tcon, S3C2410_TCON);
+        __raw_writel(tcnt, S3C2410_TCNTB(4));
+        __raw_writel(tcnt, S3C2410_TCMPB(4));
+
+        /* start the timer running */
+        tcon |= S3C2410_TCON_T4START;
+        tcon &= ~S3C2410_TCON_T4MANUALUPD;
+        __raw_writel(tcon, S3C2410_TCON);
+}
+
+static void __init s3c2410_timer_resources(void)
+{
+        struct platform_device tmpdev;
+
+        tmpdev.dev.bus = &platform_bus_type;
+        tmpdev.id = 4;
+
+        timerclk = clk_get(NULL, "timers");
+        if (IS_ERR(timerclk))
+                panic("failed to get clock for system timer");
+
+        clk_enable(timerclk);
+
+        if (!use_tclk1_12()) {
+                tin = clk_get(&tmpdev.dev, "pwm-tin");
+                if (IS_ERR(tin))
+                        panic("failed to get pwm-tin clock for system timer");
+
+                tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
+                if (IS_ERR(tdiv))
+                        panic("failed to get pwm-tdiv clock for system timer");
+        }
+
+        clk_enable(tin);
+}
+
+static void __init s3c2410_timer_init(void)
+{
+        s3c2410_timer_resources();
+        s3c2410_timer_setup();
+        setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
+}
+
+struct sys_timer s3c24xx_timer = {
+        .init           = s3c2410_timer_init,
+        .offset         = s3c2410_gettimeoffset,
+        .resume         = s3c2410_timer_setup
+};