3 files changed, 3 insertions, 334 deletions
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index b885322717a1..9ae507270785 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -15,55 +15,7 @@
 #ifndef __PLAT_S3C_FB_H
 #define __PLAT_S3C_FB_H __FILE__
-/* S3C_FB_MAX_WIN
+#include <linux/platform_data/video_s3c.h>
- * Set to the maximum number of windows that any of the supported hardware
- * can use. Since the platform data uses this for an array size, having it
- * set to the maximum of any version of the hardware can do is safe.
- */
-#define S3C_FB_MAX_WIN  (5)
-/**
- * struct s3c_fb_pd_win - per window setup data
- * @xres     : The window X size.
- * @yres     : The window Y size.
- * @virtual_x: The virtual X size.
- * @virtual_y: The virtual Y size.
- */
-struct s3c_fb_pd_win {
-        unsigned short          default_bpp;
-        unsigned short          max_bpp;
-        unsigned short          xres;
-        unsigned short          yres;
-        unsigned short          virtual_x;
-        unsigned short          virtual_y;
-};
-/**
- * struct s3c_fb_platdata -  S3C driver platform specific information
- * @setup_gpio: Setup the external GPIO pins to the right state to transfer
- *              the data from the display system to the connected display
- *              device.
- * @vidcon0: The base vidcon0 values to control the panel data format.
- * @vidcon1: The base vidcon1 values to control the panel data output.
- * @vtiming: Video timing when connected to a RGB type panel.
- * @win: The setup data for each hardware window, or NULL for unused.
- * @display_mode: The LCD output display mode.
- *
- * The platform data supplies the video driver with all the information
- * it requires to work with the display(s) attached to the machine. It
- * controls the initial mode, the number of display windows (0 is always
- * the base framebuffer) that are initialised etc.
- *
- */
-struct s3c_fb_platdata {
-        void    (*setup_gpio)(void);
-        struct s3c_fb_pd_win    *win[S3C_FB_MAX_WIN];
-        struct fb_videomode     *vtiming;
-        u32                      vidcon0;
-        u32                      vidcon1;
-};
 /**
 * s3c_fb_set_platdata() - Setup the FB device with platform data.
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index 29c26a818842..f05f2afa440d 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -1,281 +1 @@
-/* arch/arm/plat-samsung/include/plat/regs-serial.h
+#include <linux/serial_s3c.h>
- *
- *  From linux/include/asm-arm/hardware/serial_s3c2410.h
- *
- *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
- *
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- *  Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
- *
- *  Adapted from:
- *
- *  Internal header file for MX1ADS serial ports (UART1 & 2)
- *
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-#ifndef __ASM_ARM_REGS_SERIAL_H
-#define __ASM_ARM_REGS_SERIAL_H
-#define S3C24XX_VA_UART0      (S3C_VA_UART)
-#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )
-#define S3C2410_PA_UART0      (S3C24XX_PA_UART)
-#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
-#define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
-#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
-#define S3C2410_URXH      (0x24)
-#define S3C2410_UTXH      (0x20)
-#define S3C2410_ULCON     (0x00)
-#define S3C2410_UCON      (0x04)
-#define S3C2410_UFCON     (0x08)
-#define S3C2410_UMCON     (0x0C)
-#define S3C2410_UBRDIV    (0x28)
-#define S3C2410_UTRSTAT   (0x10)
-#define S3C2410_UERSTAT   (0x14)
-#define S3C2410_UFSTAT    (0x18)
-#define S3C2410_UMSTAT    (0x1C)
-#define S3C2410_LCON_CFGMASK      ((0xF<<3)|(0x3))
-#define S3C2410_LCON_CS5          (0x0)
-#define S3C2410_LCON_CS6          (0x1)
-#define S3C2410_LCON_CS7          (0x2)
-#define S3C2410_LCON_CS8          (0x3)
-#define S3C2410_LCON_CSMASK       (0x3)
-#define S3C2410_LCON_PNONE        (0x0)
-#define S3C2410_LCON_PEVEN        (0x5 << 3)
-#define S3C2410_LCON_PODD         (0x4 << 3)
-#define S3C2410_LCON_PMASK        (0x7 << 3)
-#define S3C2410_LCON_STOPB        (1<<2)
-#define S3C2410_LCON_IRM          (1<<6)
-#define S3C2440_UCON_CLKMASK      (3<<10)
-#define S3C2440_UCON_CLKSHIFT     (10)
-#define S3C2440_UCON_PCLK         (0<<10)
-#define S3C2440_UCON_UCLK         (1<<10)
-#define S3C2440_UCON_PCLK2        (2<<10)
-#define S3C2440_UCON_FCLK         (3<<10)
-#define S3C2443_UCON_EPLL         (3<<10)
-#define S3C6400_UCON_CLKMASK    (3<<10)
-#define S3C6400_UCON_CLKSHIFT   (10)
-#define S3C6400_UCON_PCLK       (0<<10)
-#define S3C6400_UCON_PCLK2      (2<<10)
-#define S3C6400_UCON_UCLK0      (1<<10)
-#define S3C6400_UCON_UCLK1      (3<<10)
-#define S3C2440_UCON2_FCLK_EN     (1<<15)
-#define S3C2440_UCON0_DIVMASK     (15 << 12)
-#define S3C2440_UCON1_DIVMASK     (15 << 12)
-#define S3C2440_UCON2_DIVMASK     (7 << 12)
-#define S3C2440_UCON_DIVSHIFT     (12)
-#define S3C2412_UCON_CLKMASK    (3<<10)
-#define S3C2412_UCON_CLKSHIFT   (10)
-#define S3C2412_UCON_UCLK       (1<<10)
-#define S3C2412_UCON_USYSCLK    (3<<10)
-#define S3C2412_UCON_PCLK       (0<<10)
-#define S3C2412_UCON_PCLK2      (2<<10)
-#define S3C2410_UCON_CLKMASK    (1 << 10)
-#define S3C2410_UCON_CLKSHIFT   (10)
-#define S3C2410_UCON_UCLK         (1<<10)
-#define S3C2410_UCON_SBREAK       (1<<4)
-#define S3C2410_UCON_TXILEVEL     (1<<9)
-#define S3C2410_UCON_RXILEVEL     (1<<8)
-#define S3C2410_UCON_TXIRQMODE    (1<<2)
-#define S3C2410_UCON_RXIRQMODE    (1<<0)
-#define S3C2410_UCON_RXFIFO_TOI   (1<<7)
-#define S3C2443_UCON_RXERR_IRQEN  (1<<6)
-#define S3C2443_UCON_LOOPBACK     (1<<5)
-#define S3C2410_UCON_DEFAULT      (S3C2410_UCON_TXILEVEL  | \
-                                   S3C2410_UCON_RXILEVEL  | \
-                                   S3C2410_UCON_TXIRQMODE | \
-                                   S3C2410_UCON_RXIRQMODE | \
-                                   S3C2410_UCON_RXFIFO_TOI)
-#define S3C2410_UFCON_FIFOMODE    (1<<0)
-#define S3C2410_UFCON_TXTRIG0     (0<<6)
-#define S3C2410_UFCON_RXTRIG8     (1<<4)
-#define S3C2410_UFCON_RXTRIG12    (2<<4)
-/* S3C2440 FIFO trigger levels */
-#define S3C2440_UFCON_RXTRIG1     (0<<4)
-#define S3C2440_UFCON_RXTRIG8     (1<<4)
-#define S3C2440_UFCON_RXTRIG16    (2<<4)
-#define S3C2440_UFCON_RXTRIG32    (3<<4)
-#define S3C2440_UFCON_TXTRIG0     (0<<6)
-#define S3C2440_UFCON_TXTRIG16    (1<<6)
-#define S3C2440_UFCON_TXTRIG32    (2<<6)
-#define S3C2440_UFCON_TXTRIG48    (3<<6)
-#define S3C2410_UFCON_RESETBOTH   (3<<1)
-#define S3C2410_UFCON_RESETTX     (1<<2)
-#define S3C2410_UFCON_RESETRX     (1<<1)
-#define S3C2410_UFCON_DEFAULT     (S3C2410_UFCON_FIFOMODE | \
-                                   S3C2410_UFCON_TXTRIG0  | \
-                                   S3C2410_UFCON_RXTRIG8 )
-#define S3C2410_UMCOM_AFC         (1<<4)
-#define S3C2410_UMCOM_RTS_LOW     (1<<0)
-#define S3C2412_UMCON_AFC_63    (0<<5)          /* same as s3c2443 */
-#define S3C2412_UMCON_AFC_56    (1<<5)
-#define S3C2412_UMCON_AFC_48    (2<<5)
-#define S3C2412_UMCON_AFC_40    (3<<5)
-#define S3C2412_UMCON_AFC_32    (4<<5)
-#define S3C2412_UMCON_AFC_24    (5<<5)
-#define S3C2412_UMCON_AFC_16    (6<<5)
-#define S3C2412_UMCON_AFC_8     (7<<5)
-#define S3C2410_UFSTAT_TXFULL     (1<<9)
-#define S3C2410_UFSTAT_RXFULL     (1<<8)
-#define S3C2410_UFSTAT_TXMASK     (15<<4)
-#define S3C2410_UFSTAT_TXSHIFT    (4)
-#define S3C2410_UFSTAT_RXMASK     (15<<0)
-#define S3C2410_UFSTAT_RXSHIFT    (0)
-/* UFSTAT S3C2443 same as S3C2440 */
-#define S3C2440_UFSTAT_TXFULL     (1<<14)
-#define S3C2440_UFSTAT_RXFULL     (1<<6)
-#define S3C2440_UFSTAT_TXSHIFT    (8)
-#define S3C2440_UFSTAT_RXSHIFT    (0)
-#define S3C2440_UFSTAT_TXMASK     (63<<8)
-#define S3C2440_UFSTAT_RXMASK     (63)
-#define S3C2410_UTRSTAT_TXE       (1<<2)
-#define S3C2410_UTRSTAT_TXFE      (1<<1)
-#define S3C2410_UTRSTAT_RXDR      (1<<0)
-#define S3C2410_UERSTAT_OVERRUN   (1<<0)
-#define S3C2410_UERSTAT_FRAME     (1<<2)
-#define S3C2410_UERSTAT_BREAK     (1<<3)
-#define S3C2443_UERSTAT_PARITY    (1<<1)
-#define S3C2410_UERSTAT_ANY       (S3C2410_UERSTAT_OVERRUN | \
-                                   S3C2410_UERSTAT_FRAME | \
-                                   S3C2410_UERSTAT_BREAK)
-#define S3C2410_UMSTAT_CTS        (1<<0)
-#define S3C2410_UMSTAT_DeltaCTS   (1<<2)
-#define S3C2443_DIVSLOT           (0x2C)
-/* S3C64XX interrupt registers. */
-#define S3C64XX_UINTP           0x30
-#define S3C64XX_UINTSP          0x34
-#define S3C64XX_UINTM           0x38
-#define S3C64XX_UINTM_RXD       (0)
-#define S3C64XX_UINTM_TXD       (2)
-#define S3C64XX_UINTM_RXD_MSK   (1 << S3C64XX_UINTM_RXD)
-#define S3C64XX_UINTM_TXD_MSK   (1 << S3C64XX_UINTM_TXD)
-/* Following are specific to S5PV210 */
-#define S5PV210_UCON_CLKMASK    (1<<10)
-#define S5PV210_UCON_CLKSHIFT   (10)
-#define S5PV210_UCON_PCLK       (0<<10)
-#define S5PV210_UCON_UCLK       (1<<10)
-#define S5PV210_UFCON_TXTRIG0   (0<<8)
-#define S5PV210_UFCON_TXTRIG4   (1<<8)
-#define S5PV210_UFCON_TXTRIG8   (2<<8)
-#define S5PV210_UFCON_TXTRIG16  (3<<8)
-#define S5PV210_UFCON_TXTRIG32  (4<<8)
-#define S5PV210_UFCON_TXTRIG64  (5<<8)
-#define S5PV210_UFCON_TXTRIG128 (6<<8)
-#define S5PV210_UFCON_TXTRIG256 (7<<8)
-#define S5PV210_UFCON_RXTRIG1   (0<<4)
-#define S5PV210_UFCON_RXTRIG4   (1<<4)
-#define S5PV210_UFCON_RXTRIG8   (2<<4)
-#define S5PV210_UFCON_RXTRIG16  (3<<4)
-#define S5PV210_UFCON_RXTRIG32  (4<<4)
-#define S5PV210_UFCON_RXTRIG64  (5<<4)
-#define S5PV210_UFCON_RXTRIG128 (6<<4)
-#define S5PV210_UFCON_RXTRIG256 (7<<4)
-#define S5PV210_UFSTAT_TXFULL   (1<<24)
-#define S5PV210_UFSTAT_RXFULL   (1<<8)
-#define S5PV210_UFSTAT_TXMASK   (255<<16)
-#define S5PV210_UFSTAT_TXSHIFT  (16)
-#define S5PV210_UFSTAT_RXMASK   (255<<0)
-#define S5PV210_UFSTAT_RXSHIFT  (0)
-#define S3C2410_UCON_CLKSEL0    (1 << 0)
-#define S3C2410_UCON_CLKSEL1    (1 << 1)
-#define S3C2410_UCON_CLKSEL2    (1 << 2)
-#define S3C2410_UCON_CLKSEL3    (1 << 3)
-/* Default values for s5pv210 UCON and UFCON uart registers */
-#define S5PV210_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-#define S5PV210_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-#ifndef __ASSEMBLY__
-/* configuration structure for per-machine configurations for the
- * serial port
- *
- * the pointer is setup by the machine specific initialisation from the
- * arch/arm/mach-s3c2410/ directory.
-*/
-struct s3c2410_uartcfg {
-        unsigned char      hwport;       /* hardware port number */
-        unsigned char      unused;
-        unsigned short     flags;
-        upf_t              uart_flags;   /* default uart flags */
-        unsigned int       clk_sel;
-        unsigned int       has_fracval;
-        unsigned long      ucon;         /* value of ucon for port */
-        unsigned long      ulcon;        /* value of ulcon for port */
-        unsigned long      ufcon;        /* value of ufcon for port */
-};
-/* s3c24xx_uart_devs
- *
- * this is exported from the core as we cannot use driver_register(),
- * or platform_add_device() before the console_initcall()
-*/
-extern struct platform_device *s3c24xx_uart_devs[4];
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARM_REGS_SERIAL_H */
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 959bcdb03a25..ab34dfadb7f9 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -11,10 +11,7 @@
 #ifndef __PLAT_SAMSUNG_USB_PHY_H
 #define __PLAT_SAMSUNG_USB_PHY_H __FILE__
-enum s5p_usb_phy_type {
+#include <linux/usb/samsung_usb_phy.h>
-        S5P_USB_PHY_DEVICE,
-        S5P_USB_PHY_HOST,
-};
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
 extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);

diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index b885322717a1..9ae507270785 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -15,55 +15,7 @@
15	#ifndef __PLAT_S3C_FB_H	15	#ifndef __PLAT_S3C_FB_H
16	#define __PLAT_S3C_FB_H __FILE__	16	#define __PLAT_S3C_FB_H __FILE__
17		17
18	/* S3C_FB_MAX_WIN	18	#include <linux/platform_data/video_s3c.h>
19	* Set to the maximum number of windows that any of the supported hardware
20	* can use. Since the platform data uses this for an array size, having it
21	* set to the maximum of any version of the hardware can do is safe.
22	*/
23	#define S3C_FB_MAX_WIN (5)
24
25	/**
26	* struct s3c_fb_pd_win - per window setup data
27	* @xres : The window X size.
28	* @yres : The window Y size.
29	* @virtual_x: The virtual X size.
30	* @virtual_y: The virtual Y size.
31	*/
32	struct s3c_fb_pd_win {
33	unsigned short default_bpp;
34	unsigned short max_bpp;
35	unsigned short xres;
36	unsigned short yres;
37	unsigned short virtual_x;
38	unsigned short virtual_y;
39	};
40
41	/**
42	* struct s3c_fb_platdata - S3C driver platform specific information
43	* @setup_gpio: Setup the external GPIO pins to the right state to transfer
44	* the data from the display system to the connected display
45	* device.
46	* @vidcon0: The base vidcon0 values to control the panel data format.
47	* @vidcon1: The base vidcon1 values to control the panel data output.
48	* @vtiming: Video timing when connected to a RGB type panel.
49	* @win: The setup data for each hardware window, or NULL for unused.
50	* @display_mode: The LCD output display mode.
51	*
52	* The platform data supplies the video driver with all the information
53	* it requires to work with the display(s) attached to the machine. It
54	* controls the initial mode, the number of display windows (0 is always
55	* the base framebuffer) that are initialised etc.
56	*
57	*/
58	struct s3c_fb_platdata {
59	void (*setup_gpio)(void);
60
61	struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN];
62	struct fb_videomode *vtiming;
63
64	u32 vidcon0;
65	u32 vidcon1;
66	};
67		19
68	/**	20	/**
69	* s3c_fb_set_platdata() - Setup the FB device with platform data.	21	* s3c_fb_set_platdata() - Setup the FB device with platform data.


diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h index 29c26a818842..f05f2afa440d 100644 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -1,281 +1 @@
1	/* arch/arm/plat-samsung/include/plat/regs-serial.h		#include <linux/serial_s3c.h>
2	*
3	* From linux/include/asm-arm/hardware/serial_s3c2410.h
4	*
5	* Internal header file for Samsung S3C2410 serial ports (UART0-2)
6	*
7	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
8	*
9	* Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
10	*
11	* Adapted from:
12	*
13	* Internal header file for MX1ADS serial ports (UART1 & 2)
14	*
15	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
16	*
17	* This program is free software; you can redistribute it and/or modify
18	* it under the terms of the GNU General Public License as published by
19	* the Free Software Foundation; either version 2 of the License, or
20	* (at your option) any later version.
21	*
22	* This program is distributed in the hope that it will be useful,
23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25	* GNU General Public License for more details.
26	*
27	* You should have received a copy of the GNU General Public License
28	* along with this program; if not, write to the Free Software
29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30	*/
31
32	#ifndef __ASM_ARM_REGS_SERIAL_H
33	#define __ASM_ARM_REGS_SERIAL_H
34
35	#define S3C24XX_VA_UART0 (S3C_VA_UART)
36	#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
37	#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
38	#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
39
40	#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
41	#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
42	#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
43	#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
44
45	#define S3C2410_URXH (0x24)
46	#define S3C2410_UTXH (0x20)
47	#define S3C2410_ULCON (0x00)
48	#define S3C2410_UCON (0x04)
49	#define S3C2410_UFCON (0x08)
50	#define S3C2410_UMCON (0x0C)
51	#define S3C2410_UBRDIV (0x28)
52	#define S3C2410_UTRSTAT (0x10)
53	#define S3C2410_UERSTAT (0x14)
54	#define S3C2410_UFSTAT (0x18)
55	#define S3C2410_UMSTAT (0x1C)
56
57	#define S3C2410_LCON_CFGMASK ((0xF<<3)\|(0x3))
58
59	#define S3C2410_LCON_CS5 (0x0)
60	#define S3C2410_LCON_CS6 (0x1)
61	#define S3C2410_LCON_CS7 (0x2)
62	#define S3C2410_LCON_CS8 (0x3)
63	#define S3C2410_LCON_CSMASK (0x3)
64
65	#define S3C2410_LCON_PNONE (0x0)
66	#define S3C2410_LCON_PEVEN (0x5 << 3)
67	#define S3C2410_LCON_PODD (0x4 << 3)
68	#define S3C2410_LCON_PMASK (0x7 << 3)
69
70	#define S3C2410_LCON_STOPB (1<<2)
71	#define S3C2410_LCON_IRM (1<<6)
72
73	#define S3C2440_UCON_CLKMASK (3<<10)
74	#define S3C2440_UCON_CLKSHIFT (10)
75	#define S3C2440_UCON_PCLK (0<<10)
76	#define S3C2440_UCON_UCLK (1<<10)
77	#define S3C2440_UCON_PCLK2 (2<<10)
78	#define S3C2440_UCON_FCLK (3<<10)
79	#define S3C2443_UCON_EPLL (3<<10)
80
81	#define S3C6400_UCON_CLKMASK (3<<10)
82	#define S3C6400_UCON_CLKSHIFT (10)
83	#define S3C6400_UCON_PCLK (0<<10)
84	#define S3C6400_UCON_PCLK2 (2<<10)
85	#define S3C6400_UCON_UCLK0 (1<<10)
86	#define S3C6400_UCON_UCLK1 (3<<10)
87
88	#define S3C2440_UCON2_FCLK_EN (1<<15)
89	#define S3C2440_UCON0_DIVMASK (15 << 12)
90	#define S3C2440_UCON1_DIVMASK (15 << 12)
91	#define S3C2440_UCON2_DIVMASK (7 << 12)
92	#define S3C2440_UCON_DIVSHIFT (12)
93
94	#define S3C2412_UCON_CLKMASK (3<<10)
95	#define S3C2412_UCON_CLKSHIFT (10)
96	#define S3C2412_UCON_UCLK (1<<10)
97	#define S3C2412_UCON_USYSCLK (3<<10)
98	#define S3C2412_UCON_PCLK (0<<10)
99	#define S3C2412_UCON_PCLK2 (2<<10)
100
101	#define S3C2410_UCON_CLKMASK (1 << 10)
102	#define S3C2410_UCON_CLKSHIFT (10)
103	#define S3C2410_UCON_UCLK (1<<10)
104	#define S3C2410_UCON_SBREAK (1<<4)
105
106	#define S3C2410_UCON_TXILEVEL (1<<9)
107	#define S3C2410_UCON_RXILEVEL (1<<8)
108	#define S3C2410_UCON_TXIRQMODE (1<<2)
109	#define S3C2410_UCON_RXIRQMODE (1<<0)
110	#define S3C2410_UCON_RXFIFO_TOI (1<<7)
111	#define S3C2443_UCON_RXERR_IRQEN (1<<6)
112	#define S3C2443_UCON_LOOPBACK (1<<5)
113
114	#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL \| \
115	S3C2410_UCON_RXILEVEL \| \
116	S3C2410_UCON_TXIRQMODE \| \
117	S3C2410_UCON_RXIRQMODE \| \
118	S3C2410_UCON_RXFIFO_TOI)
119
120	#define S3C2410_UFCON_FIFOMODE (1<<0)
121	#define S3C2410_UFCON_TXTRIG0 (0<<6)
122	#define S3C2410_UFCON_RXTRIG8 (1<<4)
123	#define S3C2410_UFCON_RXTRIG12 (2<<4)
124
125	/* S3C2440 FIFO trigger levels */
126	#define S3C2440_UFCON_RXTRIG1 (0<<4)
127	#define S3C2440_UFCON_RXTRIG8 (1<<4)
128	#define S3C2440_UFCON_RXTRIG16 (2<<4)
129	#define S3C2440_UFCON_RXTRIG32 (3<<4)
130
131	#define S3C2440_UFCON_TXTRIG0 (0<<6)
132	#define S3C2440_UFCON_TXTRIG16 (1<<6)
133	#define S3C2440_UFCON_TXTRIG32 (2<<6)
134	#define S3C2440_UFCON_TXTRIG48 (3<<6)
135
136	#define S3C2410_UFCON_RESETBOTH (3<<1)
137	#define S3C2410_UFCON_RESETTX (1<<2)
138	#define S3C2410_UFCON_RESETRX (1<<1)
139
140	#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE \| \
141	S3C2410_UFCON_TXTRIG0 \| \
142	S3C2410_UFCON_RXTRIG8 )
143
144	#define S3C2410_UMCOM_AFC (1<<4)
145	#define S3C2410_UMCOM_RTS_LOW (1<<0)
146
147	#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
148	#define S3C2412_UMCON_AFC_56 (1<<5)
149	#define S3C2412_UMCON_AFC_48 (2<<5)
150	#define S3C2412_UMCON_AFC_40 (3<<5)
151	#define S3C2412_UMCON_AFC_32 (4<<5)
152	#define S3C2412_UMCON_AFC_24 (5<<5)
153	#define S3C2412_UMCON_AFC_16 (6<<5)
154	#define S3C2412_UMCON_AFC_8 (7<<5)
155
156	#define S3C2410_UFSTAT_TXFULL (1<<9)
157	#define S3C2410_UFSTAT_RXFULL (1<<8)
158	#define S3C2410_UFSTAT_TXMASK (15<<4)
159	#define S3C2410_UFSTAT_TXSHIFT (4)
160	#define S3C2410_UFSTAT_RXMASK (15<<0)
161	#define S3C2410_UFSTAT_RXSHIFT (0)
162
163	/* UFSTAT S3C2443 same as S3C2440 */
164	#define S3C2440_UFSTAT_TXFULL (1<<14)
165	#define S3C2440_UFSTAT_RXFULL (1<<6)
166	#define S3C2440_UFSTAT_TXSHIFT (8)
167	#define S3C2440_UFSTAT_RXSHIFT (0)
168	#define S3C2440_UFSTAT_TXMASK (63<<8)
169	#define S3C2440_UFSTAT_RXMASK (63)
170
171	#define S3C2410_UTRSTAT_TXE (1<<2)
172	#define S3C2410_UTRSTAT_TXFE (1<<1)
173	#define S3C2410_UTRSTAT_RXDR (1<<0)
174
175	#define S3C2410_UERSTAT_OVERRUN (1<<0)
176	#define S3C2410_UERSTAT_FRAME (1<<2)
177	#define S3C2410_UERSTAT_BREAK (1<<3)
178	#define S3C2443_UERSTAT_PARITY (1<<1)
179
180	#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN \| \
181	S3C2410_UERSTAT_FRAME \| \
182	S3C2410_UERSTAT_BREAK)
183
184	#define S3C2410_UMSTAT_CTS (1<<0)
185	#define S3C2410_UMSTAT_DeltaCTS (1<<2)
186
187	#define S3C2443_DIVSLOT (0x2C)
188
189	/* S3C64XX interrupt registers. */
190	#define S3C64XX_UINTP 0x30
191	#define S3C64XX_UINTSP 0x34
192	#define S3C64XX_UINTM 0x38
193
194	#define S3C64XX_UINTM_RXD (0)
195	#define S3C64XX_UINTM_TXD (2)
196	#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
197	#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)
198
199	/* Following are specific to S5PV210 */
200	#define S5PV210_UCON_CLKMASK (1<<10)
201	#define S5PV210_UCON_CLKSHIFT (10)
202	#define S5PV210_UCON_PCLK (0<<10)
203	#define S5PV210_UCON_UCLK (1<<10)
204
205	#define S5PV210_UFCON_TXTRIG0 (0<<8)
206	#define S5PV210_UFCON_TXTRIG4 (1<<8)
207	#define S5PV210_UFCON_TXTRIG8 (2<<8)
208	#define S5PV210_UFCON_TXTRIG16 (3<<8)
209	#define S5PV210_UFCON_TXTRIG32 (4<<8)
210	#define S5PV210_UFCON_TXTRIG64 (5<<8)
211	#define S5PV210_UFCON_TXTRIG128 (6<<8)
212	#define S5PV210_UFCON_TXTRIG256 (7<<8)
213
214	#define S5PV210_UFCON_RXTRIG1 (0<<4)
215	#define S5PV210_UFCON_RXTRIG4 (1<<4)
216	#define S5PV210_UFCON_RXTRIG8 (2<<4)
217	#define S5PV210_UFCON_RXTRIG16 (3<<4)
218	#define S5PV210_UFCON_RXTRIG32 (4<<4)
219	#define S5PV210_UFCON_RXTRIG64 (5<<4)
220	#define S5PV210_UFCON_RXTRIG128 (6<<4)
221	#define S5PV210_UFCON_RXTRIG256 (7<<4)
222
223	#define S5PV210_UFSTAT_TXFULL (1<<24)
224	#define S5PV210_UFSTAT_RXFULL (1<<8)
225	#define S5PV210_UFSTAT_TXMASK (255<<16)
226	#define S5PV210_UFSTAT_TXSHIFT (16)
227	#define S5PV210_UFSTAT_RXMASK (255<<0)
228	#define S5PV210_UFSTAT_RXSHIFT (0)
229
230	#define S3C2410_UCON_CLKSEL0 (1 << 0)
231	#define S3C2410_UCON_CLKSEL1 (1 << 1)
232	#define S3C2410_UCON_CLKSEL2 (1 << 2)
233	#define S3C2410_UCON_CLKSEL3 (1 << 3)
234
235	/* Default values for s5pv210 UCON and UFCON uart registers */
236	#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL \| \
237	S3C2410_UCON_RXILEVEL \| \
238	S3C2410_UCON_TXIRQMODE \| \
239	S3C2410_UCON_RXIRQMODE \| \
240	S3C2410_UCON_RXFIFO_TOI \| \
241	S3C2443_UCON_RXERR_IRQEN)
242
243	#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE \| \
244	S5PV210_UFCON_TXTRIG4 \| \
245	S5PV210_UFCON_RXTRIG4)
246
247	#ifndef __ASSEMBLY__
248
249	/* configuration structure for per-machine configurations for the
250	* serial port
251	*
252	* the pointer is setup by the machine specific initialisation from the
253	* arch/arm/mach-s3c2410/ directory.
254	*/
255
256	struct s3c2410_uartcfg {
257	unsigned char hwport; /* hardware port number */
258	unsigned char unused;
259	unsigned short flags;
260	upf_t uart_flags; /* default uart flags */
261	unsigned int clk_sel;
262
263	unsigned int has_fracval;
264
265	unsigned long ucon; /* value of ucon for port */
266	unsigned long ulcon; /* value of ulcon for port */
267	unsigned long ufcon; /* value of ufcon for port */
268	};
269
270	/* s3c24xx_uart_devs
271	*
272	* this is exported from the core as we cannot use driver_register(),
273	* or platform_add_device() before the console_initcall()
274	*/
275
276	extern struct platform_device *s3c24xx_uart_devs[4];
277
278	#endif /* __ASSEMBLY__ */
279
280	#endif /* __ASM_ARM_REGS_SERIAL_H */
281


diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h index 959bcdb03a25..ab34dfadb7f9 100644 --- a/arch/arm/plat-samsung/include/plat/usb-phy.h +++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -11,10 +11,7 @@
11	#ifndef __PLAT_SAMSUNG_USB_PHY_H	11	#ifndef __PLAT_SAMSUNG_USB_PHY_H
12	#define __PLAT_SAMSUNG_USB_PHY_H __FILE__	12	#define __PLAT_SAMSUNG_USB_PHY_H __FILE__
13		13
14	enum s5p_usb_phy_type {	14	#include <linux/usb/samsung_usb_phy.h>
15	S5P_USB_PHY_DEVICE,
16	S5P_USB_PHY_HOST,
17	};
18		15
19	extern int s5p_usb_phy_init(struct platform_device *pdev, int type);	16	extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
20	extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);	17	extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);