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-rw-r--r--arch/arm/plat-samsung/include/plat/regs-fb-v4.h159
1 files changed, 0 insertions, 159 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
deleted file mode 100644
index 4c3647f80057..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+++ /dev/null
@@ -1,159 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards and specifically the S3C64XX series
12 * S3C6400 and S3C6410.
13 *
14 * The file contains the cpu specific items which change between whichever
15 * architecture is selected. See <plat/regs-fb.h> for the core definitions
16 * that are the same.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21*/
22
23/* include the core definitions here, in case we really do need to
24 * override them at a later date.
25*/
26
27#include <plat/regs-fb.h>
28
29#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
30#define VIDCON1_FSTATUS_EVEN (1 << 15)
31
32/* Video timing controls */
33#define VIDTCON0 (0x10)
34#define VIDTCON1 (0x14)
35#define VIDTCON2 (0x18)
36
37/* Window position controls */
38
39#define WINCON(_win) (0x20 + ((_win) * 4))
40
41/* OSD1 and OSD4 do not have register D */
42
43#define VIDOSD_BASE (0x40)
44
45#define VIDINTCON0 (0x130)
46
47/* WINCONx */
48
49#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
50#define WINCONx_CSCWIDTH_SHIFT (26)
51#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
52#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
53
54#define WINCONx_ENLOCAL (1 << 22)
55#define WINCONx_BUFSTATUS (1 << 21)
56#define WINCONx_BUFSEL (1 << 20)
57#define WINCONx_BUFAUTOEN (1 << 19)
58#define WINCONx_YCbCr (1 << 13)
59
60#define WINCON1_LOCALSEL_CAMIF (1 << 23)
61
62#define WINCON2_LOCALSEL_CAMIF (1 << 23)
63#define WINCON2_BLD_PIX (1 << 6)
64
65#define WINCON2_ALPHA_SEL (1 << 1)
66#define WINCON2_BPPMODE_MASK (0xf << 2)
67#define WINCON2_BPPMODE_SHIFT (2)
68#define WINCON2_BPPMODE_1BPP (0x0 << 2)
69#define WINCON2_BPPMODE_2BPP (0x1 << 2)
70#define WINCON2_BPPMODE_4BPP (0x2 << 2)
71#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
72#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
73#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
74#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
75#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
76#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
77#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
78#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
79#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
80#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
81#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
82
83#define WINCON3_BLD_PIX (1 << 6)
84
85#define WINCON3_ALPHA_SEL (1 << 1)
86#define WINCON3_BPPMODE_MASK (0xf << 2)
87#define WINCON3_BPPMODE_SHIFT (2)
88#define WINCON3_BPPMODE_1BPP (0x0 << 2)
89#define WINCON3_BPPMODE_2BPP (0x1 << 2)
90#define WINCON3_BPPMODE_4BPP (0x2 << 2)
91#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
92#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
93#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
94#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
95#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
96#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
97#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
98#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
99#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
100#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
101
102#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
103#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
104#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
105
106#define DITHMODE (0x170)
107#define WINxMAP(_win) (0x180 + ((_win) * 4))
108
109
110#define DITHMODE_R_POS_MASK (0x3 << 5)
111#define DITHMODE_R_POS_SHIFT (5)
112#define DITHMODE_R_POS_8BIT (0x0 << 5)
113#define DITHMODE_R_POS_6BIT (0x1 << 5)
114#define DITHMODE_R_POS_5BIT (0x2 << 5)
115
116#define DITHMODE_G_POS_MASK (0x3 << 3)
117#define DITHMODE_G_POS_SHIFT (3)
118#define DITHMODE_G_POS_8BIT (0x0 << 3)
119#define DITHMODE_G_POS_6BIT (0x1 << 3)
120#define DITHMODE_G_POS_5BIT (0x2 << 3)
121
122#define DITHMODE_B_POS_MASK (0x3 << 1)
123#define DITHMODE_B_POS_SHIFT (1)
124#define DITHMODE_B_POS_8BIT (0x0 << 1)
125#define DITHMODE_B_POS_6BIT (0x1 << 1)
126#define DITHMODE_B_POS_5BIT (0x2 << 1)
127
128#define DITHMODE_DITH_EN (1 << 0)
129
130#define WPALCON (0x1A0)
131
132/* Palette control */
133/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
134 * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
135#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
136#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
137#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
138
139
140/* Notes on per-window bpp settings
141 *
142 * Value Win0 Win1 Win2 Win3 Win 4
143 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
144 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
145 * 0010 4(P) 4(P) 4(P) 4(P) -none-
146 * 0011 8(P) 8(P) -none- -none- -none-
147 * 0100 -none- 8(A232) 8(A232) -none- -none-
148 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
149 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
150 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
151 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
152 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
153 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
154 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
155 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
156 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
157 * 1110 -none- -none- -none- -none- -none-
158 * 1111 -none- -none- -none- -none- -none-
159*/
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