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Diffstat (limited to 'arch/arm/plat-s5pc1xx/s5pc100-clock.c')
-rw-r--r--arch/arm/plat-s5pc1xx/s5pc100-clock.c126
1 files changed, 54 insertions, 72 deletions
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
index b436d44510c8..16f0b9077390 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -111,7 +111,9 @@ static struct clk clk_dout_apll = {
111 .name = "dout_apll", 111 .name = "dout_apll",
112 .id = -1, 112 .id = -1,
113 .parent = &clk_mout_apll.clk, 113 .parent = &clk_mout_apll.clk,
114 .get_rate = s5pc100_clk_dout_apll_get_rate, 114 .ops = &(struct clk_ops) {
115 .get_rate = s5pc100_clk_dout_apll_get_rate,
116 },
115}; 117};
116 118
117static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) 119static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
@@ -165,9 +167,11 @@ static struct clk clk_arm = {
165 .name = "armclk", 167 .name = "armclk",
166 .id = -1, 168 .id = -1,
167 .parent = &clk_dout_apll, 169 .parent = &clk_dout_apll,
168 .get_rate = s5pc100_clk_arm_get_rate, 170 .ops = &(struct clk_ops) {
169 .set_rate = s5pc100_clk_arm_set_rate, 171 .get_rate = s5pc100_clk_arm_get_rate,
170 .round_rate = s5pc100_clk_arm_round_rate, 172 .set_rate = s5pc100_clk_arm_set_rate,
173 .round_rate = s5pc100_clk_arm_round_rate,
174 },
171}; 175};
172 176
173static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) 177static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
@@ -185,7 +189,9 @@ static struct clk clk_dout_d0_bus = {
185 .name = "dout_d0_bus", 189 .name = "dout_d0_bus",
186 .id = -1, 190 .id = -1,
187 .parent = &clk_arm, 191 .parent = &clk_arm,
188 .get_rate = s5pc100_clk_dout_d0_bus_get_rate, 192 .ops = &(struct clk_ops) {
193 .get_rate = s5pc100_clk_dout_d0_bus_get_rate,
194 },
189}; 195};
190 196
191static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) 197static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
@@ -203,7 +209,9 @@ static struct clk clk_dout_pclkd0 = {
203 .name = "dout_pclkd0", 209 .name = "dout_pclkd0",
204 .id = -1, 210 .id = -1,
205 .parent = &clk_dout_d0_bus, 211 .parent = &clk_dout_d0_bus,
206 .get_rate = s5pc100_clk_dout_pclkd0_get_rate, 212 .ops = &(struct clk_ops) {
213 .get_rate = s5pc100_clk_dout_pclkd0_get_rate,
214 },
207}; 215};
208 216
209static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) 217static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
@@ -221,7 +229,9 @@ static struct clk clk_dout_apll2 = {
221 .name = "dout_apll2", 229 .name = "dout_apll2",
222 .id = -1, 230 .id = -1,
223 .parent = &clk_mout_apll.clk, 231 .parent = &clk_mout_apll.clk,
224 .get_rate = s5pc100_clk_dout_apll2_get_rate, 232 .ops = &(struct clk_ops) {
233 .get_rate = s5pc100_clk_dout_apll2_get_rate,
234 },
225}; 235};
226 236
227/* MPLL */ 237/* MPLL */
@@ -284,7 +294,9 @@ static struct clk clk_dout_d1_bus = {
284 .name = "dout_d1_bus", 294 .name = "dout_d1_bus",
285 .id = -1, 295 .id = -1,
286 .parent = &clk_mout_am.clk, 296 .parent = &clk_mout_am.clk,
287 .get_rate = s5pc100_clk_dout_d1_bus_get_rate, 297 .ops = &(struct clk_ops) {
298 .get_rate = s5pc100_clk_dout_d1_bus_get_rate,
299 },
288}; 300};
289 301
290static struct clk *clkset_onenand_list[] = { 302static struct clk *clkset_onenand_list[] = {
@@ -325,7 +337,9 @@ static struct clk clk_dout_pclkd1 = {
325 .name = "dout_pclkd1", 337 .name = "dout_pclkd1",
326 .id = -1, 338 .id = -1,
327 .parent = &clk_dout_d1_bus, 339 .parent = &clk_dout_d1_bus,
328 .get_rate = s5pc100_clk_dout_pclkd1_get_rate, 340 .ops = &(struct clk_ops) {
341 .get_rate = s5pc100_clk_dout_pclkd1_get_rate,
342 },
329}; 343};
330 344
331static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) 345static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
@@ -345,7 +359,9 @@ static struct clk clk_dout_mpll2 = {
345 .name = "dout_mpll2", 359 .name = "dout_mpll2",
346 .id = -1, 360 .id = -1,
347 .parent = &clk_mout_am.clk, 361 .parent = &clk_mout_am.clk,
348 .get_rate = s5pc100_clk_dout_mpll2_get_rate, 362 .ops = &(struct clk_ops) {
363 .get_rate = s5pc100_clk_dout_mpll2_get_rate,
364 },
349}; 365};
350 366
351static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) 367static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
@@ -365,7 +381,9 @@ static struct clk clk_dout_cam = {
365 .name = "dout_cam", 381 .name = "dout_cam",
366 .id = -1, 382 .id = -1,
367 .parent = &clk_dout_mpll2, 383 .parent = &clk_dout_mpll2,
368 .get_rate = s5pc100_clk_dout_cam_get_rate, 384 .ops = &(struct clk_ops) {
385 .get_rate = s5pc100_clk_dout_cam_get_rate,
386 },
369}; 387};
370 388
371static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) 389static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
@@ -385,7 +403,9 @@ static struct clk clk_dout_mpll = {
385 .name = "dout_mpll", 403 .name = "dout_mpll",
386 .id = -1, 404 .id = -1,
387 .parent = &clk_mout_am.clk, 405 .parent = &clk_mout_am.clk,
388 .get_rate = s5pc100_clk_dout_mpll_get_rate, 406 .ops = &(struct clk_ops) {
407 .get_rate = s5pc100_clk_dout_mpll_get_rate,
408 },
389}; 409};
390 410
391/* EPLL */ 411/* EPLL */
@@ -540,6 +560,13 @@ static unsigned long s5pc100_roundrate_clksrc(struct clk *clk,
540 return rate; 560 return rate;
541} 561}
542 562
563static struct clk_ops s5pc100_clksrc_ops = {
564 .set_parent = s5pc100_setparent_clksrc,
565 .get_rate = s5pc100_getrate_clksrc,
566 .set_rate = s5pc100_setrate_clksrc,
567 .round_rate = s5pc100_roundrate_clksrc,
568};
569
543static struct clk *clkset_spi_list[] = { 570static struct clk *clkset_spi_list[] = {
544 &clk_mout_epll.clk, 571 &clk_mout_epll.clk,
545 &clk_dout_mpll2, 572 &clk_dout_mpll2,
@@ -558,10 +585,7 @@ static struct clksrc_clk clk_spi0 = {
558 .id = 0, 585 .id = 0,
559 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, 586 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
560 .enable = s5pc100_sclk0_ctrl, 587 .enable = s5pc100_sclk0_ctrl,
561 .set_parent = s5pc100_setparent_clksrc, 588
562 .get_rate = s5pc100_getrate_clksrc,
563 .set_rate = s5pc100_setrate_clksrc,
564 .round_rate = s5pc100_roundrate_clksrc,
565 }, 589 },
566 .shift = S5PC100_CLKSRC1_SPI0_SHIFT, 590 .shift = S5PC100_CLKSRC1_SPI0_SHIFT,
567 .mask = S5PC100_CLKSRC1_SPI0_MASK, 591 .mask = S5PC100_CLKSRC1_SPI0_MASK,
@@ -577,10 +601,7 @@ static struct clksrc_clk clk_spi1 = {
577 .id = 1, 601 .id = 1,
578 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, 602 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
579 .enable = s5pc100_sclk0_ctrl, 603 .enable = s5pc100_sclk0_ctrl,
580 .set_parent = s5pc100_setparent_clksrc, 604 .ops = &s5pc100_clksrc_ops,
581 .get_rate = s5pc100_getrate_clksrc,
582 .set_rate = s5pc100_setrate_clksrc,
583 .round_rate = s5pc100_roundrate_clksrc,
584 }, 605 },
585 .shift = S5PC100_CLKSRC1_SPI1_SHIFT, 606 .shift = S5PC100_CLKSRC1_SPI1_SHIFT,
586 .mask = S5PC100_CLKSRC1_SPI1_MASK, 607 .mask = S5PC100_CLKSRC1_SPI1_MASK,
@@ -596,10 +617,7 @@ static struct clksrc_clk clk_spi2 = {
596 .id = 2, 617 .id = 2,
597 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, 618 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
598 .enable = s5pc100_sclk0_ctrl, 619 .enable = s5pc100_sclk0_ctrl,
599 .set_parent = s5pc100_setparent_clksrc, 620 .ops = &s5pc100_clksrc_ops,
600 .get_rate = s5pc100_getrate_clksrc,
601 .set_rate = s5pc100_setrate_clksrc,
602 .round_rate = s5pc100_roundrate_clksrc,
603 }, 621 },
604 .shift = S5PC100_CLKSRC1_SPI2_SHIFT, 622 .shift = S5PC100_CLKSRC1_SPI2_SHIFT,
605 .mask = S5PC100_CLKSRC1_SPI2_MASK, 623 .mask = S5PC100_CLKSRC1_SPI2_MASK,
@@ -625,10 +643,7 @@ static struct clksrc_clk clk_uart_uclk1 = {
625 .id = -1, 643 .id = -1,
626 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, 644 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
627 .enable = s5pc100_sclk0_ctrl, 645 .enable = s5pc100_sclk0_ctrl,
628 .set_parent = s5pc100_setparent_clksrc, 646 .ops = &s5pc100_clksrc_ops,
629 .get_rate = s5pc100_getrate_clksrc,
630 .set_rate = s5pc100_setrate_clksrc,
631 .round_rate = s5pc100_roundrate_clksrc,
632 }, 647 },
633 .shift = S5PC100_CLKSRC1_UART_SHIFT, 648 .shift = S5PC100_CLKSRC1_UART_SHIFT,
634 .mask = S5PC100_CLKSRC1_UART_MASK, 649 .mask = S5PC100_CLKSRC1_UART_MASK,
@@ -683,10 +698,7 @@ static struct clksrc_clk clk_audio0 = {
683 .id = 0, 698 .id = 0,
684 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, 699 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
685 .enable = s5pc100_sclk1_ctrl, 700 .enable = s5pc100_sclk1_ctrl,
686 .set_parent = s5pc100_setparent_clksrc, 701 .ops = &s5pc100_clksrc_ops,
687 .get_rate = s5pc100_getrate_clksrc,
688 .set_rate = s5pc100_setrate_clksrc,
689 .round_rate = s5pc100_roundrate_clksrc,
690 }, 702 },
691 .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT, 703 .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT,
692 .mask = S5PC100_CLKSRC3_AUDIO0_MASK, 704 .mask = S5PC100_CLKSRC3_AUDIO0_MASK,
@@ -716,10 +728,7 @@ static struct clksrc_clk clk_audio1 = {
716 .id = 1, 728 .id = 1,
717 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, 729 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
718 .enable = s5pc100_sclk1_ctrl, 730 .enable = s5pc100_sclk1_ctrl,
719 .set_parent = s5pc100_setparent_clksrc, 731 .ops = &s5pc100_clksrc_ops,
720 .get_rate = s5pc100_getrate_clksrc,
721 .set_rate = s5pc100_setrate_clksrc,
722 .round_rate = s5pc100_roundrate_clksrc,
723 }, 732 },
724 .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT, 733 .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT,
725 .mask = S5PC100_CLKSRC3_AUDIO1_MASK, 734 .mask = S5PC100_CLKSRC3_AUDIO1_MASK,
@@ -748,10 +757,7 @@ static struct clksrc_clk clk_audio2 = {
748 .id = 2, 757 .id = 2,
749 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, 758 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
750 .enable = s5pc100_sclk1_ctrl, 759 .enable = s5pc100_sclk1_ctrl,
751 .set_parent = s5pc100_setparent_clksrc, 760 .ops = &s5pc100_clksrc_ops,
752 .get_rate = s5pc100_getrate_clksrc,
753 .set_rate = s5pc100_setrate_clksrc,
754 .round_rate = s5pc100_roundrate_clksrc,
755 }, 761 },
756 .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT, 762 .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT,
757 .mask = S5PC100_CLKSRC3_AUDIO2_MASK, 763 .mask = S5PC100_CLKSRC3_AUDIO2_MASK,
@@ -801,10 +807,7 @@ static struct clksrc_clk clk_lcd = {
801 .id = -1, 807 .id = -1,
802 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, 808 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
803 .enable = s5pc100_sclk1_ctrl, 809 .enable = s5pc100_sclk1_ctrl,
804 .set_parent = s5pc100_setparent_clksrc, 810 .ops = &s5pc100_clksrc_ops,
805 .get_rate = s5pc100_getrate_clksrc,
806 .set_rate = s5pc100_setrate_clksrc,
807 .round_rate = s5pc100_roundrate_clksrc,
808 }, 811 },
809 .shift = S5PC100_CLKSRC2_LCD_SHIFT, 812 .shift = S5PC100_CLKSRC2_LCD_SHIFT,
810 .mask = S5PC100_CLKSRC2_LCD_MASK, 813 .mask = S5PC100_CLKSRC2_LCD_MASK,
@@ -820,10 +823,7 @@ static struct clksrc_clk clk_fimc0 = {
820 .id = 0, 823 .id = 0,
821 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, 824 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
822 .enable = s5pc100_sclk1_ctrl, 825 .enable = s5pc100_sclk1_ctrl,
823 .set_parent = s5pc100_setparent_clksrc, 826 .ops = &s5pc100_clksrc_ops,
824 .get_rate = s5pc100_getrate_clksrc,
825 .set_rate = s5pc100_setrate_clksrc,
826 .round_rate = s5pc100_roundrate_clksrc,
827 }, 827 },
828 .shift = S5PC100_CLKSRC2_FIMC0_SHIFT, 828 .shift = S5PC100_CLKSRC2_FIMC0_SHIFT,
829 .mask = S5PC100_CLKSRC2_FIMC0_MASK, 829 .mask = S5PC100_CLKSRC2_FIMC0_MASK,
@@ -839,10 +839,7 @@ static struct clksrc_clk clk_fimc1 = {
839 .id = 1, 839 .id = 1,
840 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, 840 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
841 .enable = s5pc100_sclk1_ctrl, 841 .enable = s5pc100_sclk1_ctrl,
842 .set_parent = s5pc100_setparent_clksrc, 842 .ops = &s5pc100_clksrc_ops,
843 .get_rate = s5pc100_getrate_clksrc,
844 .set_rate = s5pc100_setrate_clksrc,
845 .round_rate = s5pc100_roundrate_clksrc,
846 }, 843 },
847 .shift = S5PC100_CLKSRC2_FIMC1_SHIFT, 844 .shift = S5PC100_CLKSRC2_FIMC1_SHIFT,
848 .mask = S5PC100_CLKSRC2_FIMC1_MASK, 845 .mask = S5PC100_CLKSRC2_FIMC1_MASK,
@@ -858,10 +855,7 @@ static struct clksrc_clk clk_fimc2 = {
858 .id = 2, 855 .id = 2,
859 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, 856 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
860 .enable = s5pc100_sclk1_ctrl, 857 .enable = s5pc100_sclk1_ctrl,
861 .set_parent = s5pc100_setparent_clksrc, 858 .ops = &s5pc100_clksrc_ops,
862 .get_rate = s5pc100_getrate_clksrc,
863 .set_rate = s5pc100_setrate_clksrc,
864 .round_rate = s5pc100_roundrate_clksrc,
865 }, 859 },
866 .shift = S5PC100_CLKSRC2_FIMC2_SHIFT, 860 .shift = S5PC100_CLKSRC2_FIMC2_SHIFT,
867 .mask = S5PC100_CLKSRC2_FIMC2_MASK, 861 .mask = S5PC100_CLKSRC2_FIMC2_MASK,
@@ -889,10 +883,7 @@ static struct clksrc_clk clk_mmc0 = {
889 .id = 0, 883 .id = 0,
890 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, 884 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
891 .enable = s5pc100_sclk0_ctrl, 885 .enable = s5pc100_sclk0_ctrl,
892 .set_parent = s5pc100_setparent_clksrc, 886 .ops = &s5pc100_clksrc_ops,
893 .get_rate = s5pc100_getrate_clksrc,
894 .set_rate = s5pc100_setrate_clksrc,
895 .round_rate = s5pc100_roundrate_clksrc,
896 }, 887 },
897 .shift = S5PC100_CLKSRC2_MMC0_SHIFT, 888 .shift = S5PC100_CLKSRC2_MMC0_SHIFT,
898 .mask = S5PC100_CLKSRC2_MMC0_MASK, 889 .mask = S5PC100_CLKSRC2_MMC0_MASK,
@@ -908,10 +899,7 @@ static struct clksrc_clk clk_mmc1 = {
908 .id = 1, 899 .id = 1,
909 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, 900 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
910 .enable = s5pc100_sclk0_ctrl, 901 .enable = s5pc100_sclk0_ctrl,
911 .set_parent = s5pc100_setparent_clksrc, 902 .ops = &s5pc100_clksrc_ops,
912 .get_rate = s5pc100_getrate_clksrc,
913 .set_rate = s5pc100_setrate_clksrc,
914 .round_rate = s5pc100_roundrate_clksrc,
915 }, 903 },
916 .shift = S5PC100_CLKSRC2_MMC1_SHIFT, 904 .shift = S5PC100_CLKSRC2_MMC1_SHIFT,
917 .mask = S5PC100_CLKSRC2_MMC1_MASK, 905 .mask = S5PC100_CLKSRC2_MMC1_MASK,
@@ -927,10 +915,7 @@ static struct clksrc_clk clk_mmc2 = {
927 .id = 2, 915 .id = 2,
928 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, 916 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
929 .enable = s5pc100_sclk0_ctrl, 917 .enable = s5pc100_sclk0_ctrl,
930 .set_parent = s5pc100_setparent_clksrc, 918 .ops = &s5pc100_clksrc_ops,
931 .get_rate = s5pc100_getrate_clksrc,
932 .set_rate = s5pc100_setrate_clksrc,
933 .round_rate = s5pc100_roundrate_clksrc,
934 }, 919 },
935 .shift = S5PC100_CLKSRC2_MMC2_SHIFT, 920 .shift = S5PC100_CLKSRC2_MMC2_SHIFT,
936 .mask = S5PC100_CLKSRC2_MMC2_MASK, 921 .mask = S5PC100_CLKSRC2_MMC2_MASK,
@@ -959,10 +944,7 @@ static struct clksrc_clk clk_usbhost = {
959 .id = -1, 944 .id = -1,
960 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, 945 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
961 .enable = s5pc100_sclk0_ctrl, 946 .enable = s5pc100_sclk0_ctrl,
962 .set_parent = s5pc100_setparent_clksrc, 947 .ops = &s5pc100_clksrc_ops,
963 .get_rate = s5pc100_getrate_clksrc,
964 .set_rate = s5pc100_setrate_clksrc,
965 .round_rate = s5pc100_roundrate_clksrc,
966 }, 948 },
967 .shift = S5PC100_CLKSRC1_UHOST_SHIFT, 949 .shift = S5PC100_CLKSRC1_UHOST_SHIFT,
968 .mask = S5PC100_CLKSRC1_UHOST_MASK, 950 .mask = S5PC100_CLKSRC1_UHOST_MASK,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 03:37:47 -0500