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-rw-r--r--arch/arm/plat-s5pc1xx/s5pc100-clock.c416
1 files changed, 179 insertions, 237 deletions
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
index a9e37302f82f..2bf6c57a96a2 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -534,14 +534,44 @@ static struct clksrc_sources clkset_audio2 = {
534 .nr_sources = ARRAY_SIZE(clkset_audio2_list), 534 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
535}; 535};
536 536
537static struct clksrc_clk clk_audio0; 537static struct clksrc_clk clksrc_audio[] = {
538static struct clksrc_clk clk_audio1; 538 {
539static struct clksrc_clk clk_audio2; 539 .clk = {
540 .name = "audio-bus",
541 .id = 0,
542 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
543 .enable = s5pc100_sclk1_ctrl,
544 },
545 .sources = &clkset_audio0,
546 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, },
547 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, },
548 }, {
549 .clk = {
550 .name = "audio-bus",
551 .id = 1,
552 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
553 .enable = s5pc100_sclk1_ctrl,
554 },
555 .sources = &clkset_audio1,
556 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, },
557 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, },
558 }, {
559 .clk = {
560 .name = "audio-bus",
561 .id = 2,
562 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
563 .enable = s5pc100_sclk1_ctrl,
564 },
565 .sources = &clkset_audio2,
566 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, },
567 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, },
568 },
569};
540 570
541static struct clk *clkset_spdif_list[] = { 571static struct clk *clkset_spdif_list[] = {
542 &clk_audio0.clk, 572 &clksrc_audio[0].clk,
543 &clk_audio1.clk, 573 &clksrc_audio[1].clk,
544 &clk_audio2.clk, 574 &clksrc_audio[2].clk,
545}; 575};
546 576
547static struct clksrc_sources clkset_spdif = { 577static struct clksrc_sources clkset_spdif = {
@@ -585,195 +615,136 @@ static struct clksrc_sources clkset_usbhost = {
585 .nr_sources = ARRAY_SIZE(clkset_usbhost_list), 615 .nr_sources = ARRAY_SIZE(clkset_usbhost_list),
586}; 616};
587 617
588static struct clksrc_clk clk_spi0 = { 618static struct clksrc_clk clksrc_clks[] = {
589 .clk = { 619 {
590 .name = "spi_bus", 620 .clk = {
591 .id = 0, 621 .name = "spi_bus",
592 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, 622 .id = 0,
593 .enable = s5pc100_sclk0_ctrl, 623 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
594 624 .enable = s5pc100_sclk0_ctrl,
595 }, 625
596 .sources = &clkset_spi, 626 },
597 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, }, 627 .sources = &clkset_spi,
598 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, }, 628 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, },
599}; 629 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, },
600 630 }, {
601static struct clksrc_clk clk_spi1 = { 631 .clk = {
602 .clk = { 632 .name = "spi_bus",
603 .name = "spi_bus", 633 .id = 1,
604 .id = 1, 634 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
605 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, 635 .enable = s5pc100_sclk0_ctrl,
606 .enable = s5pc100_sclk0_ctrl, 636 },
607 }, 637 .sources = &clkset_spi,
608 .sources = &clkset_spi, 638 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, },
609 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, }, 639 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, },
610 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, }, 640 }, {
611}; 641 .clk = {
612 642 .name = "spi_bus",
613static struct clksrc_clk clk_spi2 = { 643 .id = 2,
614 .clk = { 644 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
615 .name = "spi_bus", 645 .enable = s5pc100_sclk0_ctrl,
616 .id = 2, 646 },
617 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, 647 .sources = &clkset_spi,
618 .enable = s5pc100_sclk0_ctrl, 648 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, },
619 }, 649 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, },
620 .sources = &clkset_spi, 650 }, {
621 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, }, 651 .clk = {
622 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, }, 652 .name = "uclk1",
623}; 653 .id = -1,
624 654 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
625static struct clksrc_clk clk_uart_uclk1 = { 655 .enable = s5pc100_sclk0_ctrl,
626 .clk = { 656 },
627 .name = "uclk1", 657 .sources = &clkset_uart,
628 .id = -1, 658 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, },
629 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, 659 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, },
630 .enable = s5pc100_sclk0_ctrl, 660 }, {
631 }, 661 .clk = {
632 .sources = &clkset_uart, 662 .name = "spdif",
633 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, }, 663 .id = -1,
634 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, }, 664 },
635}; 665 .sources = &clkset_spdif,
636 666 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, },
637static struct clksrc_clk clk_audio0 = { 667 }, {
638 .clk = { 668 .clk = {
639 .name = "audio-bus", 669 .name = "lcd",
640 .id = 0, 670 .id = -1,
641 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, 671 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
642 .enable = s5pc100_sclk1_ctrl, 672 .enable = s5pc100_sclk1_ctrl,
643 }, 673 },
644 .sources = &clkset_audio0, 674 .sources = &clkset_lcd_fimc,
645 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, }, 675 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, },
646 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, }, 676 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, },
647}; 677 }, {
648 678 .clk = {
649static struct clksrc_clk clk_audio1 = { 679 .name = "fimc",
650 .clk = { 680 .id = 0,
651 .name = "audio-bus", 681 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
652 .id = 1, 682 .enable = s5pc100_sclk1_ctrl,
653 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, 683 },
654 .enable = s5pc100_sclk1_ctrl, 684 .sources = &clkset_lcd_fimc,
655 }, 685 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, },
656 .sources = &clkset_audio1, 686 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, },
657 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, }, 687 }, {
658 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, }, 688 .clk = {
659}; 689 .name = "fimc",
660 690 .id = 1,
661 691 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
662static struct clksrc_clk clk_audio2 = { 692 .enable = s5pc100_sclk1_ctrl,
663 .clk = { 693 },
664 .name = "audio-bus", 694 .sources = &clkset_lcd_fimc,
665 .id = 2, 695 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, },
666 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, 696 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, },
667 .enable = s5pc100_sclk1_ctrl, 697 }, {
668 }, 698 .clk = {
669 .sources = &clkset_audio2, 699 .name = "fimc",
670 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, }, 700 .id = 2,
671 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, }, 701 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
672}; 702 .enable = s5pc100_sclk1_ctrl,
673 703 },
674static struct clksrc_clk clk_spdif = { 704 .sources = &clkset_lcd_fimc,
675 .clk = { 705 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, },
676 .name = "spdif", 706 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, },
677 .id = -1, 707 }, {
678 }, 708 .clk = {
679 .sources = &clkset_spdif, 709 .name = "mmc_bus",
680 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, }, 710 .id = 0,
681}; 711 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
682 712 .enable = s5pc100_sclk0_ctrl,
683static struct clksrc_clk clk_lcd = { 713 },
684 .clk = { 714 .sources = &clkset_mmc,
685 .name = "lcd", 715 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, },
686 .id = -1, 716 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, },
687 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, 717 }, {
688 .enable = s5pc100_sclk1_ctrl, 718 .clk = {
689 }, 719 .name = "mmc_bus",
690 .sources = &clkset_lcd_fimc, 720 .id = 1,
691 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, }, 721 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
692 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, }, 722 .enable = s5pc100_sclk0_ctrl,
693}; 723 },
694 724 .sources = &clkset_mmc,
695static struct clksrc_clk clk_fimc0 = { 725 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, },
696 .clk = { 726 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, },
697 .name = "fimc", 727 }, {
698 .id = 0, 728 .clk = {
699 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, 729 .name = "mmc_bus",
700 .enable = s5pc100_sclk1_ctrl, 730 .id = 2,
701 }, 731 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
702 .sources = &clkset_lcd_fimc, 732 .enable = s5pc100_sclk0_ctrl,
703 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, }, 733 },
704 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, }, 734 .sources = &clkset_mmc,
705}; 735 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, },
706 736 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, },
707static struct clksrc_clk clk_fimc1 = { 737 }, {
708 .clk = { 738 .clk = {
709 .name = "fimc", 739 .name = "usbhost",
710 .id = 1, 740 .id = -1,
711 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, 741 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
712 .enable = s5pc100_sclk1_ctrl, 742 .enable = s5pc100_sclk0_ctrl,
713 }, 743 },
714 .sources = &clkset_lcd_fimc, 744 .sources = &clkset_usbhost,
715 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, }, 745 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, },
716 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, }, 746 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, },
717}; 747 }
718
719static struct clksrc_clk clk_fimc2 = {
720 .clk = {
721 .name = "fimc",
722 .id = 2,
723 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
724 .enable = s5pc100_sclk1_ctrl,
725 },
726 .sources = &clkset_lcd_fimc,
727 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, },
728 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, },
729};
730
731static struct clksrc_clk clk_mmc0 = {
732 .clk = {
733 .name = "mmc_bus",
734 .id = 0,
735 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
736 .enable = s5pc100_sclk0_ctrl,
737 },
738 .sources = &clkset_mmc,
739 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, },
740 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, },
741};
742
743static struct clksrc_clk clk_mmc1 = {
744 .clk = {
745 .name = "mmc_bus",
746 .id = 1,
747 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
748 .enable = s5pc100_sclk0_ctrl,
749 },
750 .sources = &clkset_mmc,
751 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, },
752 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, },
753};
754
755static struct clksrc_clk clk_mmc2 = {
756 .clk = {
757 .name = "mmc_bus",
758 .id = 2,
759 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
760 .enable = s5pc100_sclk0_ctrl,
761 },
762 .sources = &clkset_mmc,
763 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, },
764 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, },
765};
766
767static struct clksrc_clk clk_usbhost = {
768 .clk = {
769 .name = "usbhost",
770 .id = -1,
771 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
772 .enable = s5pc100_sclk0_ctrl,
773 },
774 .sources = &clkset_usbhost,
775 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, },
776 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, },
777}; 748};
778 749
779/* Clock initialisation code */ 750/* Clock initialisation code */
@@ -785,22 +756,6 @@ static struct clksrc_clk *init_parents[] = {
785 &clk_mout_onenand, 756 &clk_mout_onenand,
786 &clk_mout_epll, 757 &clk_mout_epll,
787 &clk_mout_hpll, 758 &clk_mout_hpll,
788 &clk_spi0,
789 &clk_spi1,
790 &clk_spi2,
791 &clk_uart_uclk1,
792 &clk_audio0,
793 &clk_audio1,
794 &clk_audio2,
795 &clk_spdif,
796 &clk_lcd,
797 &clk_fimc0,
798 &clk_fimc1,
799 &clk_fimc2,
800 &clk_mmc0,
801 &clk_mmc1,
802 &clk_mmc2,
803 &clk_usbhost,
804}; 759};
805 760
806#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 761#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -867,6 +822,12 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
867 822
868 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) 823 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
869 s3c_set_clksrc(init_parents[ptr], true); 824 s3c_set_clksrc(init_parents[ptr], true);
825
826 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++)
827 s3c_set_clksrc(clksrc_audio + ptr, true);
828
829 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
830 s3c_set_clksrc(clksrc_clks + ptr, true);
870} 831}
871 832
872static struct clk *clks[] __initdata = { 833static struct clk *clks[] __initdata = {
@@ -875,8 +836,13 @@ static struct clk *clks[] __initdata = {
875 &clk_dout_d0_bus, 836 &clk_dout_d0_bus,
876 &clk_dout_pclkd0, 837 &clk_dout_pclkd0,
877 &clk_dout_apll2, 838 &clk_dout_apll2,
839 &clk_mout_apll.clk,
840 &clk_mout_mpll.clk,
841 &clk_mout_epll.clk,
842 &clk_mout_hpll.clk,
878 &clk_mout_am.clk, 843 &clk_mout_am.clk,
879 &clk_dout_d1_bus, 844 &clk_dout_d1_bus,
845 &clk_mout_onenand.clk,
880 &clk_dout_pclkd1, 846 &clk_dout_pclkd1,
881 &clk_dout_mpll2, 847 &clk_dout_mpll2,
882 &clk_dout_cam, 848 &clk_dout_cam,
@@ -890,30 +856,6 @@ static struct clk *clks[] __initdata = {
890 &clk_arm, 856 &clk_arm,
891}; 857};
892 858
893/* simplest change - will aggregate clocks later */
894static struct clksrc_clk *clks_src[] = {
895 &clk_mout_apll,
896 &clk_mout_mpll,
897 &clk_mout_onenand,
898 &clk_mout_epll,
899 &clk_spi0,
900 &clk_spi1,
901 &clk_spi2,
902 &clk_uart_uclk1,
903 &clk_audio0,
904 &clk_audio1,
905 &clk_audio2,
906 &clk_spdif,
907 &clk_lcd,
908 &clk_fimc0,
909 &clk_fimc1,
910 &clk_fimc2,
911 &clk_mmc0,
912 &clk_mmc1,
913 &clk_mmc2,
914 &clk_usbhost,
915};
916
917void __init s5pc100_register_clocks(void) 859void __init s5pc100_register_clocks(void)
918{ 860{
919 struct clk *clkp; 861 struct clk *clkp;
@@ -929,6 +871,6 @@ void __init s5pc100_register_clocks(void)
929 } 871 }
930 } 872 }
931 873
932 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++) 874 s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio));
933 s3c_register_clksrc(clks_src[ptr], 1); 875 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
934} 876}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 20:57:44 -0400