diff options
Diffstat (limited to 'arch/arm/plat-s5pc1xx/irq.c')
-rw-r--r-- | arch/arm/plat-s5pc1xx/irq.c | 88 |
1 files changed, 7 insertions, 81 deletions
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c index e44fd04ef333..ae233bdeb7e2 100644 --- a/arch/arm/plat-s5pc1xx/irq.c +++ b/arch/arm/plat-s5pc1xx/irq.c | |||
@@ -20,77 +20,9 @@ | |||
20 | #include <asm/hardware/vic.h> | 20 | #include <asm/hardware/vic.h> |
21 | 21 | ||
22 | #include <mach/map.h> | 22 | #include <mach/map.h> |
23 | #include <plat/regs-timer.h> | 23 | #include <plat/irq-vic-timer.h> |
24 | #include <plat/cpu.h> | 24 | #include <plat/cpu.h> |
25 | 25 | ||
26 | /* Timer interrupt handling */ | ||
27 | |||
28 | static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) | ||
29 | { | ||
30 | generic_handle_irq(sub_irq); | ||
31 | } | ||
32 | |||
33 | static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) | ||
34 | { | ||
35 | s3c_irq_demux_timer(irq, IRQ_TIMER0); | ||
36 | } | ||
37 | |||
38 | static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) | ||
39 | { | ||
40 | s3c_irq_demux_timer(irq, IRQ_TIMER1); | ||
41 | } | ||
42 | |||
43 | static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) | ||
44 | { | ||
45 | s3c_irq_demux_timer(irq, IRQ_TIMER2); | ||
46 | } | ||
47 | |||
48 | static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) | ||
49 | { | ||
50 | s3c_irq_demux_timer(irq, IRQ_TIMER3); | ||
51 | } | ||
52 | |||
53 | static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) | ||
54 | { | ||
55 | s3c_irq_demux_timer(irq, IRQ_TIMER4); | ||
56 | } | ||
57 | |||
58 | /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ | ||
59 | |||
60 | static void s3c_irq_timer_mask(unsigned int irq) | ||
61 | { | ||
62 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
63 | |||
64 | reg &= 0x1f; /* mask out pending interrupts */ | ||
65 | reg &= ~(1 << (irq - IRQ_TIMER0)); | ||
66 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
67 | } | ||
68 | |||
69 | static void s3c_irq_timer_unmask(unsigned int irq) | ||
70 | { | ||
71 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
72 | |||
73 | reg &= 0x1f; /* mask out pending interrupts */ | ||
74 | reg |= 1 << (irq - IRQ_TIMER0); | ||
75 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
76 | } | ||
77 | |||
78 | static void s3c_irq_timer_ack(unsigned int irq) | ||
79 | { | ||
80 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
81 | |||
82 | reg &= 0x1f; /* mask out pending interrupts */ | ||
83 | reg |= (1 << 5) << (irq - IRQ_TIMER0); | ||
84 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
85 | } | ||
86 | |||
87 | static struct irq_chip s3c_irq_timer = { | ||
88 | .name = "s3c-timer", | ||
89 | .mask = s3c_irq_timer_mask, | ||
90 | .unmask = s3c_irq_timer_unmask, | ||
91 | .ack = s3c_irq_timer_ack, | ||
92 | }; | ||
93 | |||
94 | struct uart_irq { | 26 | struct uart_irq { |
95 | void __iomem *regs; | 27 | void __iomem *regs; |
96 | unsigned int base_irq; | 28 | unsigned int base_irq; |
@@ -229,7 +161,7 @@ static void __init s5pc1xx_uart_irq(struct uart_irq *uirq) | |||
229 | void __init s5pc1xx_init_irq(u32 *vic_valid, int num) | 161 | void __init s5pc1xx_init_irq(u32 *vic_valid, int num) |
230 | { | 162 | { |
231 | int i; | 163 | int i; |
232 | int uart, irq; | 164 | int uart; |
233 | 165 | ||
234 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); | 166 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); |
235 | 167 | ||
@@ -240,17 +172,11 @@ void __init s5pc1xx_init_irq(u32 *vic_valid, int num) | |||
240 | 172 | ||
241 | /* add the timer sub-irqs */ | 173 | /* add the timer sub-irqs */ |
242 | 174 | ||
243 | set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0); | 175 | s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); |
244 | set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1); | 176 | s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); |
245 | set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2); | 177 | s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); |
246 | set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3); | 178 | s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); |
247 | set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4); | 179 | s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); |
248 | |||
249 | for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { | ||
250 | set_irq_chip(irq, &s3c_irq_timer); | ||
251 | set_irq_handler(irq, handle_level_irq); | ||
252 | set_irq_flags(irq, IRQF_VALID); | ||
253 | } | ||
254 | 180 | ||
255 | for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) | 181 | for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) |
256 | s5pc1xx_uart_irq(&uart_irqs[uart]); | 182 | s5pc1xx_uart_irq(&uart_irqs[uart]); |