diff options
Diffstat (limited to 'arch/arm/plat-s5pc1xx/clock.c')
-rw-r--r-- | arch/arm/plat-s5pc1xx/clock.c | 31 |
1 files changed, 6 insertions, 25 deletions
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c index 26c21d849790..387f23190c3c 100644 --- a/arch/arm/plat-s5pc1xx/clock.c +++ b/arch/arm/plat-s5pc1xx/clock.c | |||
@@ -64,25 +64,13 @@ struct clk clk_54m = { | |||
64 | .rate = 54000000, | 64 | .rate = 54000000, |
65 | }; | 65 | }; |
66 | 66 | ||
67 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | ||
68 | { | ||
69 | clk->rate = rate; | ||
70 | return 0; | ||
71 | } | ||
72 | |||
73 | static int clk_dummy_enable(struct clk *clk, int enable) | ||
74 | { | ||
75 | return 0; | ||
76 | } | ||
77 | |||
78 | struct clk clk_hd0 = { | 67 | struct clk clk_hd0 = { |
79 | .name = "hclkd0", | 68 | .name = "hclkd0", |
80 | .id = -1, | 69 | .id = -1, |
81 | .rate = 0, | 70 | .rate = 0, |
82 | .parent = NULL, | 71 | .parent = NULL, |
83 | .ctrlbit = 0, | 72 | .ctrlbit = 0, |
84 | .set_rate = clk_default_setrate, | 73 | .ops = &clk_ops_def_setrate, |
85 | .enable = clk_dummy_enable, | ||
86 | }; | 74 | }; |
87 | 75 | ||
88 | struct clk clk_pd0 = { | 76 | struct clk clk_pd0 = { |
@@ -91,8 +79,7 @@ struct clk clk_pd0 = { | |||
91 | .rate = 0, | 79 | .rate = 0, |
92 | .parent = NULL, | 80 | .parent = NULL, |
93 | .ctrlbit = 0, | 81 | .ctrlbit = 0, |
94 | .set_rate = clk_default_setrate, | 82 | .ops = &clk_ops_def_setrate, |
95 | .enable = clk_dummy_enable, | ||
96 | }; | 83 | }; |
97 | 84 | ||
98 | static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) | 85 | static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) |
@@ -686,6 +673,8 @@ static struct clk s5pc100_init_clocks[] = { | |||
686 | static struct clk *clks[] __initdata = { | 673 | static struct clk *clks[] __initdata = { |
687 | &clk_ext, | 674 | &clk_ext, |
688 | &clk_epll, | 675 | &clk_epll, |
676 | &clk_pd0, | ||
677 | &clk_hd0, | ||
689 | &clk_27m, | 678 | &clk_27m, |
690 | &clk_48m, | 679 | &clk_48m, |
691 | &clk_54m, | 680 | &clk_54m, |
@@ -700,16 +689,8 @@ void __init s5pc1xx_register_clocks(void) | |||
700 | 689 | ||
701 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | 690 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
702 | 691 | ||
703 | clkp = s5pc100_init_clocks; | 692 | s3c_register_clocks(s5pc100_init_clocks, |
704 | size = ARRAY_SIZE(s5pc100_init_clocks); | 693 | ARRAY_SIZE(s5pc100_init_clocks)); |
705 | |||
706 | for (ptr = 0; ptr < size; ptr++, clkp++) { | ||
707 | ret = s3c24xx_register_clock(clkp); | ||
708 | if (ret < 0) { | ||
709 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
710 | clkp->name, ret); | ||
711 | } | ||
712 | } | ||
713 | 694 | ||
714 | clkp = s5pc100_init_clocks_disable; | 695 | clkp = s5pc100_init_clocks_disable; |
715 | size = ARRAY_SIZE(s5pc100_init_clocks_disable); | 696 | size = ARRAY_SIZE(s5pc100_init_clocks_disable); |