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Diffstat (limited to 'arch/arm/plat-s5pc1xx/clock.c')
-rw-r--r--arch/arm/plat-s5pc1xx/clock.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
index 26c21d849790..2f4d8d4c4e1c 100644
--- a/arch/arm/plat-s5pc1xx/clock.c
+++ b/arch/arm/plat-s5pc1xx/clock.c
@@ -70,6 +70,10 @@ static int clk_default_setrate(struct clk *clk, unsigned long rate)
70 return 0; 70 return 0;
71} 71}
72 72
73static struct clk_ops clk_ops_default_setrate = {
74 .set_rate = clk_default_setrate,
75};
76
73static int clk_dummy_enable(struct clk *clk, int enable) 77static int clk_dummy_enable(struct clk *clk, int enable)
74{ 78{
75 return 0; 79 return 0;
@@ -81,8 +85,8 @@ struct clk clk_hd0 = {
81 .rate = 0, 85 .rate = 0,
82 .parent = NULL, 86 .parent = NULL,
83 .ctrlbit = 0, 87 .ctrlbit = 0,
84 .set_rate = clk_default_setrate,
85 .enable = clk_dummy_enable, 88 .enable = clk_dummy_enable,
89 .ops = &clk_ops_default_setrate,
86}; 90};
87 91
88struct clk clk_pd0 = { 92struct clk clk_pd0 = {
@@ -91,7 +95,7 @@ struct clk clk_pd0 = {
91 .rate = 0, 95 .rate = 0,
92 .parent = NULL, 96 .parent = NULL,
93 .ctrlbit = 0, 97 .ctrlbit = 0,
94 .set_rate = clk_default_setrate, 98 .ops = &clk_ops_default_setrate,
95 .enable = clk_dummy_enable, 99 .enable = clk_dummy_enable,
96}; 100};
97 101