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-rw-r--r--arch/arm/plat-s5pc1xx/clock.c728
1 files changed, 728 insertions, 0 deletions
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
new file mode 100644
index 000000000000..26c21d849790
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+++ b/arch/arm/plat-s5pc1xx/clock.c
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1/* linux/arch/arm/plat-s5pc1xx/clock.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 *
5 * S5PC1XX Base clock support
6 *
7 * Based on plat-s3c64xx/clock.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/hardware.h>
22#include <mach/map.h>
23
24#include <plat/regs-clock.h>
25#include <plat/devs.h>
26#include <plat/clock.h>
27
28struct clk clk_27m = {
29 .name = "clk_27m",
30 .id = -1,
31 .rate = 27000000,
32};
33
34static int clk_48m_ctrl(struct clk *clk, int enable)
35{
36 unsigned long flags;
37 u32 val;
38
39 /* can't rely on clock lock, this register has other usages */
40 local_irq_save(flags);
41
42 val = __raw_readl(S5PC100_CLKSRC1);
43 if (enable)
44 val |= S5PC100_CLKSRC1_CLK48M_MASK;
45 else
46 val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
47
48 __raw_writel(val, S5PC100_CLKSRC1);
49 local_irq_restore(flags);
50
51 return 0;
52}
53
54struct clk clk_48m = {
55 .name = "clk_48m",
56 .id = -1,
57 .rate = 48000000,
58 .enable = clk_48m_ctrl,
59};
60
61struct clk clk_54m = {
62 .name = "clk_54m",
63 .id = -1,
64 .rate = 54000000,
65};
66
67static int clk_default_setrate(struct clk *clk, unsigned long rate)
68{
69 clk->rate = rate;
70 return 0;
71}
72
73static int clk_dummy_enable(struct clk *clk, int enable)
74{
75 return 0;
76}
77
78struct clk clk_hd0 = {
79 .name = "hclkd0",
80 .id = -1,
81 .rate = 0,
82 .parent = NULL,
83 .ctrlbit = 0,
84 .set_rate = clk_default_setrate,
85 .enable = clk_dummy_enable,
86};
87
88struct clk clk_pd0 = {
89 .name = "pclkd0",
90 .id = -1,
91 .rate = 0,
92 .parent = NULL,
93 .ctrlbit = 0,
94 .set_rate = clk_default_setrate,
95 .enable = clk_dummy_enable,
96};
97
98static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
99{
100 unsigned int ctrlbit = clk->ctrlbit;
101 u32 con;
102
103 con = __raw_readl(reg);
104 if (enable)
105 con |= ctrlbit;
106 else
107 con &= ~ctrlbit;
108 __raw_writel(con, reg);
109
110 return 0;
111}
112
113static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
114{
115 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
116}
117
118static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
119{
120 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
121}
122
123static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
124{
125 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
126}
127
128static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
129{
130 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
131}
132
133static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
134{
135 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
136}
137
138static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
139{
140 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
141}
142
143static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
144{
145 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
146}
147
148static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
149{
150 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
151}
152
153static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
154{
155 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
156}
157
158static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
159{
160 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
161}
162
163int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
164{
165 return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
166}
167
168int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
169{
170 return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
171}
172
173static struct clk s5pc100_init_clocks_disable[] = {
174 {
175 .name = "dsi",
176 .id = -1,
177 .parent = &clk_p,
178 .enable = s5pc100_clk_d11_ctrl,
179 .ctrlbit = S5PC100_CLKGATE_D11_DSI,
180 }, {
181 .name = "csi",
182 .id = -1,
183 .parent = &clk_h,
184 .enable = s5pc100_clk_d11_ctrl,
185 .ctrlbit = S5PC100_CLKGATE_D11_CSI,
186 }, {
187 .name = "ccan",
188 .id = 0,
189 .parent = &clk_p,
190 .enable = s5pc100_clk_d14_ctrl,
191 .ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
192 }, {
193 .name = "ccan",
194 .id = 1,
195 .parent = &clk_p,
196 .enable = s5pc100_clk_d14_ctrl,
197 .ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
198 }, {
199 .name = "keypad",
200 .id = -1,
201 .parent = &clk_p,
202 .enable = s5pc100_clk_d15_ctrl,
203 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
204 }, {
205 .name = "hclkd2",
206 .id = -1,
207 .parent = NULL,
208 .enable = s5pc100_clk_d20_ctrl,
209 .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
210 }, {
211 .name = "iis-d2",
212 .id = -1,
213 .parent = NULL,
214 .enable = s5pc100_clk_d20_ctrl,
215 .ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
216 },
217};
218
219static struct clk s5pc100_init_clocks[] = {
220 /* System1 (D0_0) devices */
221 {
222 .name = "intc",
223 .id = -1,
224 .parent = &clk_hd0,
225 .enable = s5pc100_clk_d00_ctrl,
226 .ctrlbit = S5PC100_CLKGATE_D00_INTC,
227 }, {
228 .name = "tzic",
229 .id = -1,
230 .parent = &clk_hd0,
231 .enable = s5pc100_clk_d00_ctrl,
232 .ctrlbit = S5PC100_CLKGATE_D00_TZIC,
233 }, {
234 .name = "cf-ata",
235 .id = -1,
236 .parent = &clk_hd0,
237 .enable = s5pc100_clk_d00_ctrl,
238 .ctrlbit = S5PC100_CLKGATE_D00_CFCON,
239 }, {
240 .name = "mdma",
241 .id = -1,
242 .parent = &clk_hd0,
243 .enable = s5pc100_clk_d00_ctrl,
244 .ctrlbit = S5PC100_CLKGATE_D00_MDMA,
245 }, {
246 .name = "g2d",
247 .id = -1,
248 .parent = &clk_hd0,
249 .enable = s5pc100_clk_d00_ctrl,
250 .ctrlbit = S5PC100_CLKGATE_D00_G2D,
251 }, {
252 .name = "secss",
253 .id = -1,
254 .parent = &clk_hd0,
255 .enable = s5pc100_clk_d00_ctrl,
256 .ctrlbit = S5PC100_CLKGATE_D00_SECSS,
257 }, {
258 .name = "cssys",
259 .id = -1,
260 .parent = &clk_hd0,
261 .enable = s5pc100_clk_d00_ctrl,
262 .ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
263 },
264
265 /* Memory (D0_1) devices */
266 {
267 .name = "dmc",
268 .id = -1,
269 .parent = &clk_hd0,
270 .enable = s5pc100_clk_d01_ctrl,
271 .ctrlbit = S5PC100_CLKGATE_D01_DMC,
272 }, {
273 .name = "sromc",
274 .id = -1,
275 .parent = &clk_hd0,
276 .enable = s5pc100_clk_d01_ctrl,
277 .ctrlbit = S5PC100_CLKGATE_D01_SROMC,
278 }, {
279 .name = "onenand",
280 .id = -1,
281 .parent = &clk_hd0,
282 .enable = s5pc100_clk_d01_ctrl,
283 .ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
284 }, {
285 .name = "nand",
286 .id = -1,
287 .parent = &clk_hd0,
288 .enable = s5pc100_clk_d01_ctrl,
289 .ctrlbit = S5PC100_CLKGATE_D01_NFCON,
290 }, {
291 .name = "intmem",
292 .id = -1,
293 .parent = &clk_hd0,
294 .enable = s5pc100_clk_d01_ctrl,
295 .ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
296 }, {
297 .name = "ebi",
298 .id = -1,
299 .parent = &clk_hd0,
300 .enable = s5pc100_clk_d01_ctrl,
301 .ctrlbit = S5PC100_CLKGATE_D01_EBI,
302 },
303
304 /* System2 (D0_2) devices */
305 {
306 .name = "seckey",
307 .id = -1,
308 .parent = &clk_pd0,
309 .enable = s5pc100_clk_d02_ctrl,
310 .ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
311 }, {
312 .name = "sdm",
313 .id = -1,
314 .parent = &clk_hd0,
315 .enable = s5pc100_clk_d02_ctrl,
316 .ctrlbit = S5PC100_CLKGATE_D02_SDM,
317 },
318
319 /* File (D1_0) devices */
320 {
321 .name = "pdma",
322 .id = 0,
323 .parent = &clk_h,
324 .enable = s5pc100_clk_d10_ctrl,
325 .ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
326 }, {
327 .name = "pdma",
328 .id = 1,
329 .parent = &clk_h,
330 .enable = s5pc100_clk_d10_ctrl,
331 .ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
332 }, {
333 .name = "usb-host",
334 .id = -1,
335 .parent = &clk_h,
336 .enable = s5pc100_clk_d10_ctrl,
337 .ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
338 }, {
339 .name = "otg",
340 .id = -1,
341 .parent = &clk_h,
342 .enable = s5pc100_clk_d10_ctrl,
343 .ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
344 }, {
345 .name = "modem",
346 .id = -1,
347 .parent = &clk_h,
348 .enable = s5pc100_clk_d10_ctrl,
349 .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
350 }, {
351 .name = "hsmmc",
352 .id = 0,
353 .parent = &clk_48m,
354 .enable = s5pc100_clk_d10_ctrl,
355 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
356 }, {
357 .name = "hsmmc",
358 .id = 1,
359 .parent = &clk_48m,
360 .enable = s5pc100_clk_d10_ctrl,
361 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
362 }, {
363 .name = "hsmmc",
364 .id = 2,
365 .parent = &clk_48m,
366 .enable = s5pc100_clk_d10_ctrl,
367 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
368 },
369
370 /* Multimedia1 (D1_1) devices */
371 {
372 .name = "lcd",
373 .id = -1,
374 .parent = &clk_p,
375 .enable = s5pc100_clk_d11_ctrl,
376 .ctrlbit = S5PC100_CLKGATE_D11_LCD,
377 }, {
378 .name = "rotator",
379 .id = -1,
380 .parent = &clk_p,
381 .enable = s5pc100_clk_d11_ctrl,
382 .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
383 }, {
384 .name = "fimc",
385 .id = -1,
386 .parent = &clk_p,
387 .enable = s5pc100_clk_d11_ctrl,
388 .ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
389 }, {
390 .name = "fimc",
391 .id = -1,
392 .parent = &clk_p,
393 .enable = s5pc100_clk_d11_ctrl,
394 .ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
395 }, {
396 .name = "fimc",
397 .id = -1,
398 .parent = &clk_p,
399 .enable = s5pc100_clk_d11_ctrl,
400 .ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
401 }, {
402 .name = "jpeg",
403 .id = -1,
404 .parent = &clk_p,
405 .enable = s5pc100_clk_d11_ctrl,
406 .ctrlbit = S5PC100_CLKGATE_D11_JPEG,
407 }, {
408 .name = "g3d",
409 .id = -1,
410 .parent = &clk_p,
411 .enable = s5pc100_clk_d11_ctrl,
412 .ctrlbit = S5PC100_CLKGATE_D11_G3D,
413 },
414
415 /* Multimedia2 (D1_2) devices */
416 {
417 .name = "tv",
418 .id = -1,
419 .parent = &clk_p,
420 .enable = s5pc100_clk_d12_ctrl,
421 .ctrlbit = S5PC100_CLKGATE_D12_TV,
422 }, {
423 .name = "vp",
424 .id = -1,
425 .parent = &clk_p,
426 .enable = s5pc100_clk_d12_ctrl,
427 .ctrlbit = S5PC100_CLKGATE_D12_VP,
428 }, {
429 .name = "mixer",
430 .id = -1,
431 .parent = &clk_p,
432 .enable = s5pc100_clk_d12_ctrl,
433 .ctrlbit = S5PC100_CLKGATE_D12_MIXER,
434 }, {
435 .name = "hdmi",
436 .id = -1,
437 .parent = &clk_p,
438 .enable = s5pc100_clk_d12_ctrl,
439 .ctrlbit = S5PC100_CLKGATE_D12_HDMI,
440 }, {
441 .name = "mfc",
442 .id = -1,
443 .parent = &clk_p,
444 .enable = s5pc100_clk_d12_ctrl,
445 .ctrlbit = S5PC100_CLKGATE_D12_MFC,
446 },
447
448 /* System (D1_3) devices */
449 {
450 .name = "chipid",
451 .id = -1,
452 .parent = &clk_p,
453 .enable = s5pc100_clk_d13_ctrl,
454 .ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
455 }, {
456 .name = "gpio",
457 .id = -1,
458 .parent = &clk_p,
459 .enable = s5pc100_clk_d13_ctrl,
460 .ctrlbit = S5PC100_CLKGATE_D13_GPIO,
461 }, {
462 .name = "apc",
463 .id = -1,
464 .parent = &clk_p,
465 .enable = s5pc100_clk_d13_ctrl,
466 .ctrlbit = S5PC100_CLKGATE_D13_APC,
467 }, {
468 .name = "iec",
469 .id = -1,
470 .parent = &clk_p,
471 .enable = s5pc100_clk_d13_ctrl,
472 .ctrlbit = S5PC100_CLKGATE_D13_IEC,
473 }, {
474 .name = "timers",
475 .id = -1,
476 .parent = &clk_p,
477 .enable = s5pc100_clk_d13_ctrl,
478 .ctrlbit = S5PC100_CLKGATE_D13_PWM,
479 }, {
480 .name = "systimer",
481 .id = -1,
482 .parent = &clk_p,
483 .enable = s5pc100_clk_d13_ctrl,
484 .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
485 }, {
486 .name = "watchdog",
487 .id = -1,
488 .parent = &clk_p,
489 .enable = s5pc100_clk_d13_ctrl,
490 .ctrlbit = S5PC100_CLKGATE_D13_WDT,
491 }, {
492 .name = "rtc",
493 .id = -1,
494 .parent = &clk_p,
495 .enable = s5pc100_clk_d13_ctrl,
496 .ctrlbit = S5PC100_CLKGATE_D13_RTC,
497 },
498
499 /* Connectivity (D1_4) devices */
500 {
501 .name = "uart",
502 .id = 0,
503 .parent = &clk_p,
504 .enable = s5pc100_clk_d14_ctrl,
505 .ctrlbit = S5PC100_CLKGATE_D14_UART0,
506 }, {
507 .name = "uart",
508 .id = 1,
509 .parent = &clk_p,
510 .enable = s5pc100_clk_d14_ctrl,
511 .ctrlbit = S5PC100_CLKGATE_D14_UART1,
512 }, {
513 .name = "uart",
514 .id = 2,
515 .parent = &clk_p,
516 .enable = s5pc100_clk_d14_ctrl,
517 .ctrlbit = S5PC100_CLKGATE_D14_UART2,
518 }, {
519 .name = "uart",
520 .id = 3,
521 .parent = &clk_p,
522 .enable = s5pc100_clk_d14_ctrl,
523 .ctrlbit = S5PC100_CLKGATE_D14_UART3,
524 }, {
525 .name = "i2c",
526 .id = -1,
527 .parent = &clk_p,
528 .enable = s5pc100_clk_d14_ctrl,
529 .ctrlbit = S5PC100_CLKGATE_D14_IIC,
530 }, {
531 .name = "hdmi-i2c",
532 .id = -1,
533 .parent = &clk_p,
534 .enable = s5pc100_clk_d14_ctrl,
535 .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
536 }, {
537 .name = "spi",
538 .id = 0,
539 .parent = &clk_p,
540 .enable = s5pc100_clk_d14_ctrl,
541 .ctrlbit = S5PC100_CLKGATE_D14_SPI0,
542 }, {
543 .name = "spi",
544 .id = 1,
545 .parent = &clk_p,
546 .enable = s5pc100_clk_d14_ctrl,
547 .ctrlbit = S5PC100_CLKGATE_D14_SPI1,
548 }, {
549 .name = "spi",
550 .id = 2,
551 .parent = &clk_p,
552 .enable = s5pc100_clk_d14_ctrl,
553 .ctrlbit = S5PC100_CLKGATE_D14_SPI2,
554 }, {
555 .name = "irda",
556 .id = -1,
557 .parent = &clk_p,
558 .enable = s5pc100_clk_d14_ctrl,
559 .ctrlbit = S5PC100_CLKGATE_D14_IRDA,
560 }, {
561 .name = "hsitx",
562 .id = -1,
563 .parent = &clk_p,
564 .enable = s5pc100_clk_d14_ctrl,
565 .ctrlbit = S5PC100_CLKGATE_D14_HSITX,
566 }, {
567 .name = "hsirx",
568 .id = -1,
569 .parent = &clk_p,
570 .enable = s5pc100_clk_d14_ctrl,
571 .ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
572 },
573
574 /* Audio (D1_5) devices */
575 {
576 .name = "iis",
577 .id = 0,
578 .parent = &clk_p,
579 .enable = s5pc100_clk_d15_ctrl,
580 .ctrlbit = S5PC100_CLKGATE_D15_IIS0,
581 }, {
582 .name = "iis",
583 .id = 1,
584 .parent = &clk_p,
585 .enable = s5pc100_clk_d15_ctrl,
586 .ctrlbit = S5PC100_CLKGATE_D15_IIS1,
587 }, {
588 .name = "iis",
589 .id = 2,
590 .parent = &clk_p,
591 .enable = s5pc100_clk_d15_ctrl,
592 .ctrlbit = S5PC100_CLKGATE_D15_IIS2,
593 }, {
594 .name = "ac97",
595 .id = -1,
596 .parent = &clk_p,
597 .enable = s5pc100_clk_d15_ctrl,
598 .ctrlbit = S5PC100_CLKGATE_D15_AC97,
599 }, {
600 .name = "pcm",
601 .id = 0,
602 .parent = &clk_p,
603 .enable = s5pc100_clk_d15_ctrl,
604 .ctrlbit = S5PC100_CLKGATE_D15_PCM0,
605 }, {
606 .name = "pcm",
607 .id = 1,
608 .parent = &clk_p,
609 .enable = s5pc100_clk_d15_ctrl,
610 .ctrlbit = S5PC100_CLKGATE_D15_PCM1,
611 }, {
612 .name = "spdif",
613 .id = -1,
614 .parent = &clk_p,
615 .enable = s5pc100_clk_d15_ctrl,
616 .ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
617 }, {
618 .name = "adc",
619 .id = -1,
620 .parent = &clk_p,
621 .enable = s5pc100_clk_d15_ctrl,
622 .ctrlbit = S5PC100_CLKGATE_D15_TSADC,
623 }, {
624 .name = "cg",
625 .id = -1,
626 .parent = &clk_p,
627 .enable = s5pc100_clk_d15_ctrl,
628 .ctrlbit = S5PC100_CLKGATE_D15_CG,
629 },
630
631 /* Audio (D2_0) devices: all disabled */
632
633 /* Special Clocks 0 */
634 {
635 .name = "sclk_hpm",
636 .id = -1,
637 .parent = NULL,
638 .enable = s5pc100_sclk0_ctrl,
639 .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
640 }, {
641 .name = "sclk_onenand",
642 .id = -1,
643 .parent = NULL,
644 .enable = s5pc100_sclk0_ctrl,
645 .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
646 }, {
647 .name = "spi_48",
648 .id = 0,
649 .parent = &clk_48m,
650 .enable = s5pc100_sclk0_ctrl,
651 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
652 }, {
653 .name = "spi_48",
654 .id = 1,
655 .parent = &clk_48m,
656 .enable = s5pc100_sclk0_ctrl,
657 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
658 }, {
659 .name = "spi_48",
660 .id = 2,
661 .parent = &clk_48m,
662 .enable = s5pc100_sclk0_ctrl,
663 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
664 }, {
665 .name = "mmc_48",
666 .id = 0,
667 .parent = &clk_48m,
668 .enable = s5pc100_sclk0_ctrl,
669 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
670 }, {
671 .name = "mmc_48",
672 .id = 1,
673 .parent = &clk_48m,
674 .enable = s5pc100_sclk0_ctrl,
675 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
676 }, {
677 .name = "mmc_48",
678 .id = 2,
679 .parent = &clk_48m,
680 .enable = s5pc100_sclk0_ctrl,
681 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
682 },
683 /* Special Clocks 1 */
684};
685
686static struct clk *clks[] __initdata = {
687 &clk_ext,
688 &clk_epll,
689 &clk_27m,
690 &clk_48m,
691 &clk_54m,
692};
693
694void __init s5pc1xx_register_clocks(void)
695{
696 struct clk *clkp;
697 int ret;
698 int ptr;
699 int size;
700
701 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
702
703 clkp = s5pc100_init_clocks;
704 size = ARRAY_SIZE(s5pc100_init_clocks);
705
706 for (ptr = 0; ptr < size; ptr++, clkp++) {
707 ret = s3c24xx_register_clock(clkp);
708 if (ret < 0) {
709 printk(KERN_ERR "Failed to register clock %s (%d)\n",
710 clkp->name, ret);
711 }
712 }
713
714 clkp = s5pc100_init_clocks_disable;
715 size = ARRAY_SIZE(s5pc100_init_clocks_disable);
716
717 for (ptr = 0; ptr < size; ptr++, clkp++) {
718 ret = s3c24xx_register_clock(clkp);
719 if (ret < 0) {
720 printk(KERN_ERR "Failed to register clock %s (%d)\n",
721 clkp->name, ret);
722 }
723
724 (clkp->enable)(clkp, 0);
725 }
726
727 s3c_pwmclk_init();
728}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 08:34:40 -0400