aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-s5p
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-s5p')
-rw-r--r--arch/arm/plat-s5p/Kconfig5
-rw-r--r--arch/arm/plat-s5p/Makefile3
-rw-r--r--arch/arm/plat-s5p/clock.c29
-rw-r--r--arch/arm/plat-s5p/include/plat/irqs.h18
-rw-r--r--arch/arm/plat-s5p/include/plat/map-s5p.h40
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p-clock.h4
-rw-r--r--arch/arm/plat-s5p/irq-eint.c10
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c237
-rw-r--r--arch/arm/plat-s5p/irq-pm.c93
-rw-r--r--arch/arm/plat-s5p/pm.c52
10 files changed, 461 insertions, 30 deletions
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 25960966af7c..65dbfa8e0a86 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -32,6 +32,11 @@ config S5P_EXT_INT
32 Use the external interrupts (other than GPIO interrupts.) 32 Use the external interrupts (other than GPIO interrupts.)
33 Note: Do not choose this for S5P6440 and S5P6450. 33 Note: Do not choose this for S5P6440 and S5P6450.
34 34
35config S5P_GPIO_INT
36 bool
37 help
38 Common code for the GPIO interrupts (other than external interrupts.)
39
35config S5P_DEV_FIMC0 40config S5P_DEV_FIMC0
36 bool 41 bool
37 help 42 help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index f3e917e27da8..de65238a7aef 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -18,6 +18,9 @@ obj-y += cpu.o
18obj-y += clock.o 18obj-y += clock.o
19obj-y += irq.o 19obj-y += irq.o
20obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o 20obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
21obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o
22obj-$(CONFIG_PM) += pm.o
23obj-$(CONFIG_PM) += irq-pm.o
21 24
22# devices 25# devices
23 26
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 8aaf4e6b60c3..8d081d968c58 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -21,6 +21,8 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <asm/div64.h> 22#include <asm/div64.h>
23 23
24#include <mach/regs-clock.h>
25
24#include <plat/clock.h> 26#include <plat/clock.h>
25#include <plat/clock-clksrc.h> 27#include <plat/clock-clksrc.h>
26#include <plat/s5p-clock.h> 28#include <plat/s5p-clock.h>
@@ -88,14 +90,6 @@ struct clk clk_fout_vpll = {
88 .ctrlbit = (1 << 31), 90 .ctrlbit = (1 << 31),
89}; 91};
90 92
91/* ARM clock */
92struct clk clk_arm = {
93 .name = "armclk",
94 .id = -1,
95 .rate = 0,
96 .ctrlbit = 0,
97};
98
99/* Possible clock sources for APLL Mux */ 93/* Possible clock sources for APLL Mux */
100static struct clk *clk_src_apll_list[] = { 94static struct clk *clk_src_apll_list[] = {
101 [0] = &clk_fin_apll, 95 [0] = &clk_fin_apll,
@@ -156,6 +150,24 @@ int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
156 return 0; 150 return 0;
157} 151}
158 152
153int s5p_epll_enable(struct clk *clk, int enable)
154{
155 unsigned int ctrlbit = clk->ctrlbit;
156 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
157
158 if (enable)
159 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
160 else
161 __raw_writel(epll_con, S5P_EPLL_CON);
162
163 return 0;
164}
165
166unsigned long s5p_epll_get_rate(struct clk *clk)
167{
168 return clk->rate;
169}
170
159static struct clk *s5p_clks[] __initdata = { 171static struct clk *s5p_clks[] __initdata = {
160 &clk_ext_xtal_mux, 172 &clk_ext_xtal_mux,
161 &clk_48m, 173 &clk_48m,
@@ -165,7 +177,6 @@ static struct clk *s5p_clks[] __initdata = {
165 &clk_fout_epll, 177 &clk_fout_epll,
166 &clk_fout_dpll, 178 &clk_fout_dpll,
167 &clk_fout_vpll, 179 &clk_fout_vpll,
168 &clk_arm,
169 &clk_vpll, 180 &clk_vpll,
170 &clk_xusbxti, 181 &clk_xusbxti,
171}; 182};
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
index 3fb3a3a17465..ba9121c60a2a 100644
--- a/arch/arm/plat-s5p/include/plat/irqs.h
+++ b/arch/arm/plat-s5p/include/plat/irqs.h
@@ -94,4 +94,22 @@
94 ((irq) - S5P_EINT_BASE1) : \ 94 ((irq) - S5P_EINT_BASE1) : \
95 ((irq) + 16 - S5P_EINT_BASE2)) 95 ((irq) + 16 - S5P_EINT_BASE2))
96 96
97#define IRQ_EINT_BIT(x) EINT_OFFSET(x)
98
99/* Typically only a few gpio chips require gpio interrupt support.
100 To avoid memory waste irq descriptors are allocated only for
101 S5P_GPIOINT_GROUP_COUNT chips, each with total number of
102 S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
103 to any gpio chip with the s5p_register_gpio_interrupt() function */
104#define S5P_GPIOINT_GROUP_COUNT 4
105#define S5P_GPIOINT_GROUP_SIZE 8
106#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
107
108/* IRQ types common for all s5p platforms */
109#define S5P_IRQ_TYPE_LEVEL_LOW (0x00)
110#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01)
111#define S5P_IRQ_TYPE_EDGE_FALLING (0x02)
112#define S5P_IRQ_TYPE_EDGE_RISING (0x03)
113#define S5P_IRQ_TYPE_EDGE_BOTH (0x04)
114
97#endif /* __ASM_PLAT_S5P_IRQS_H */ 115#endif /* __ASM_PLAT_S5P_IRQS_H */
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index c4ff88bf6477..fef353d44513 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -13,24 +13,38 @@
13#ifndef __ASM_PLAT_MAP_S5P_H 13#ifndef __ASM_PLAT_MAP_S5P_H
14#define __ASM_PLAT_MAP_S5P_H __FILE__ 14#define __ASM_PLAT_MAP_S5P_H __FILE__
15 15
16#define S5P_VA_CHIPID S3C_ADDR(0x00700000) 16#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
17#define S5P_VA_GPIO S3C_ADDR(0x00500000) 17#define S5P_VA_CMU S3C_ADDR(0x02100000)
18#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000) 18#define S5P_VA_GPIO S3C_ADDR(0x02200000)
19#define S5P_VA_SROMC S3C_ADDR(0x01100000) 19#define S5P_VA_GPIO1 S5P_VA_GPIO
20#define S5P_VA_SYSRAM S3C_ADDR(0x01180000) 20#define S5P_VA_GPIO2 S3C_ADDR(0x02240000)
21 21#define S5P_VA_GPIO3 S3C_ADDR(0x02280000)
22#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000) 22
23#define S5P_VA_SYSRAM S3C_ADDR(0x02400000)
24#define S5P_VA_DMC0 S3C_ADDR(0x02440000)
25#define S5P_VA_DMC1 S3C_ADDR(0x02480000)
26#define S5P_VA_SROMC S3C_ADDR(0x024C0000)
27
28#define S5P_VA_SYSTIMER S3C_ADDR(0x02500000)
29#define S5P_VA_L2CC S3C_ADDR(0x02600000)
30
31#define S5P_VA_COMBINER_BASE S3C_ADDR(0x02700000)
23#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10) 32#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
24 33
25#define S5P_VA_COREPERI_BASE S3C_ADDR(0x00800000) 34#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
26#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x)) 35#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
27#define S5P_VA_SCU S5P_VA_COREPERI(0x0) 36#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
28#define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100) 37#define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100)
29#define S5P_VA_TWD S5P_VA_COREPERI(0x600) 38#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
30#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000) 39#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
31 40
32#define S5P_VA_L2CC S3C_ADDR(0x00900000) 41#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)
33#define S5P_VA_CMU S3C_ADDR(0x00920000) 42
43#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
44#define VA_VIC0 VA_VIC(0)
45#define VA_VIC1 VA_VIC(1)
46#define VA_VIC2 VA_VIC(2)
47#define VA_VIC3 VA_VIC(3)
34 48
35#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 49#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
36#define S5P_VA_UART0 S5P_VA_UART(0) 50#define S5P_VA_UART0 S5P_VA_UART(0)
@@ -42,10 +56,4 @@
42#define S3C_UART_OFFSET (0x400) 56#define S3C_UART_OFFSET (0x400)
43#endif 57#endif
44 58
45#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
46#define VA_VIC0 VA_VIC(0)
47#define VA_VIC1 VA_VIC(1)
48#define VA_VIC2 VA_VIC(2)
49#define VA_VIC3 VA_VIC(3)
50
51#endif /* __ASM_PLAT_MAP_S5P_H */ 59#endif /* __ASM_PLAT_MAP_S5P_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 17036c898409..2b6dcff8ab2b 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -43,4 +43,8 @@ extern struct clksrc_sources clk_src_dpll;
43 43
44extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); 44extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
45 45
46/* Common EPLL operations for S5P platform */
47extern int s5p_epll_enable(struct clk *clk, int enable);
48extern unsigned long s5p_epll_get_rate(struct clk *clk);
49
46#endif /* __ASM_PLAT_S5P_CLOCK_H */ 50#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index f36cd3327025..752f1a645f9d 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -67,23 +67,23 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
67 67
68 switch (type) { 68 switch (type) {
69 case IRQ_TYPE_EDGE_RISING: 69 case IRQ_TYPE_EDGE_RISING:
70 newvalue = S5P_EXTINT_RISEEDGE; 70 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
71 break; 71 break;
72 72
73 case IRQ_TYPE_EDGE_FALLING: 73 case IRQ_TYPE_EDGE_FALLING:
74 newvalue = S5P_EXTINT_FALLEDGE; 74 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
75 break; 75 break;
76 76
77 case IRQ_TYPE_EDGE_BOTH: 77 case IRQ_TYPE_EDGE_BOTH:
78 newvalue = S5P_EXTINT_BOTHEDGE; 78 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
79 break; 79 break;
80 80
81 case IRQ_TYPE_LEVEL_LOW: 81 case IRQ_TYPE_LEVEL_LOW:
82 newvalue = S5P_EXTINT_LOWLEV; 82 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
83 break; 83 break;
84 84
85 case IRQ_TYPE_LEVEL_HIGH: 85 case IRQ_TYPE_LEVEL_HIGH:
86 newvalue = S5P_EXTINT_HILEV; 86 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
87 break; 87 break;
88 88
89 default: 89 default:
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
new file mode 100644
index 000000000000..0e5dc8cbf5e3
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -0,0 +1,237 @@
1/* linux/arch/arm/plat-s5p/irq-gpioint.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * Author: Kyungmin Park <kyungmin.park@samsung.com>
5 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
6 * Author: Marek Szyprowski <m.szyprowski@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19#include <linux/gpio.h>
20
21#include <mach/map.h>
22#include <plat/gpio-core.h>
23#include <plat/gpio-cfg.h>
24
25#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x))
26
27#define GPIOINT_CON_OFFSET 0x700
28#define GPIOINT_MASK_OFFSET 0x900
29#define GPIOINT_PEND_OFFSET 0xA00
30
31static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR];
32
33static int s5p_gpioint_get_group(unsigned int irq)
34{
35 struct gpio_chip *chip = get_irq_data(irq);
36 struct s3c_gpio_chip *s3c_chip = container_of(chip,
37 struct s3c_gpio_chip, chip);
38 int group;
39
40 for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++)
41 if (s3c_chip == irq_chips[group])
42 break;
43
44 return group;
45}
46
47static int s5p_gpioint_get_offset(unsigned int irq)
48{
49 struct gpio_chip *chip = get_irq_data(irq);
50 struct s3c_gpio_chip *s3c_chip = container_of(chip,
51 struct s3c_gpio_chip, chip);
52
53 return irq - s3c_chip->irq_base;
54}
55
56static void s5p_gpioint_ack(unsigned int irq)
57{
58 int group, offset, pend_offset;
59 unsigned int value;
60
61 group = s5p_gpioint_get_group(irq);
62 offset = s5p_gpioint_get_offset(irq);
63 pend_offset = group << 2;
64
65 value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
66 value |= 1 << offset;
67 __raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
68}
69
70static void s5p_gpioint_mask(unsigned int irq)
71{
72 int group, offset, mask_offset;
73 unsigned int value;
74
75 group = s5p_gpioint_get_group(irq);
76 offset = s5p_gpioint_get_offset(irq);
77 mask_offset = group << 2;
78
79 value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
80 value |= 1 << offset;
81 __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
82}
83
84static void s5p_gpioint_unmask(unsigned int irq)
85{
86 int group, offset, mask_offset;
87 unsigned int value;
88
89 group = s5p_gpioint_get_group(irq);
90 offset = s5p_gpioint_get_offset(irq);
91 mask_offset = group << 2;
92
93 value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
94 value &= ~(1 << offset);
95 __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
96}
97
98static void s5p_gpioint_mask_ack(unsigned int irq)
99{
100 s5p_gpioint_mask(irq);
101 s5p_gpioint_ack(irq);
102}
103
104static int s5p_gpioint_set_type(unsigned int irq, unsigned int type)
105{
106 int group, offset, con_offset;
107 unsigned int value;
108
109 group = s5p_gpioint_get_group(irq);
110 offset = s5p_gpioint_get_offset(irq);
111 con_offset = group << 2;
112
113 switch (type) {
114 case IRQ_TYPE_EDGE_RISING:
115 type = S5P_IRQ_TYPE_EDGE_RISING;
116 break;
117 case IRQ_TYPE_EDGE_FALLING:
118 type = S5P_IRQ_TYPE_EDGE_FALLING;
119 break;
120 case IRQ_TYPE_EDGE_BOTH:
121 type = S5P_IRQ_TYPE_EDGE_BOTH;
122 break;
123 case IRQ_TYPE_LEVEL_HIGH:
124 type = S5P_IRQ_TYPE_LEVEL_HIGH;
125 break;
126 case IRQ_TYPE_LEVEL_LOW:
127 type = S5P_IRQ_TYPE_LEVEL_LOW;
128 break;
129 case IRQ_TYPE_NONE:
130 default:
131 printk(KERN_WARNING "No irq type\n");
132 return -EINVAL;
133 }
134
135 value = __raw_readl(S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
136 value &= ~(0x7 << (offset * 0x4));
137 value |= (type << (offset * 0x4));
138 __raw_writel(value, S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
139
140 return 0;
141}
142
143struct irq_chip s5p_gpioint = {
144 .name = "s5p_gpioint",
145 .ack = s5p_gpioint_ack,
146 .mask = s5p_gpioint_mask,
147 .mask_ack = s5p_gpioint_mask_ack,
148 .unmask = s5p_gpioint_unmask,
149 .set_type = s5p_gpioint_set_type,
150};
151
152static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
153{
154 int group, offset, pend_offset, mask_offset;
155 int real_irq;
156 unsigned int pend, mask;
157
158 for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++) {
159 pend_offset = group << 2;
160 pend = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) +
161 pend_offset);
162 if (!pend)
163 continue;
164
165 mask_offset = group << 2;
166 mask = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) +
167 mask_offset);
168 pend &= ~mask;
169
170 for (offset = 0; offset < 8; offset++) {
171 if (pend & (1 << offset)) {
172 struct s3c_gpio_chip *chip = irq_chips[group];
173 if (chip) {
174 real_irq = chip->irq_base + offset;
175 generic_handle_irq(real_irq);
176 }
177 }
178 }
179 }
180}
181
182static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
183{
184 static int used_gpioint_groups = 0;
185 static bool handler_registered = 0;
186 int irq, group = chip->group;
187 int i;
188
189 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
190 return -ENOMEM;
191
192 chip->irq_base = S5P_GPIOINT_BASE +
193 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
194 used_gpioint_groups++;
195
196 if (!handler_registered) {
197 set_irq_chained_handler(IRQ_GPIOINT, s5p_gpioint_handler);
198 handler_registered = 1;
199 }
200
201 irq_chips[group] = chip;
202 for (i = 0; i < chip->chip.ngpio; i++) {
203 irq = chip->irq_base + i;
204 set_irq_chip(irq, &s5p_gpioint);
205 set_irq_data(irq, &chip->chip);
206 set_irq_handler(irq, handle_level_irq);
207 set_irq_flags(irq, IRQF_VALID);
208 }
209 return 0;
210}
211
212int __init s5p_register_gpio_interrupt(int pin)
213{
214 struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin);
215 int offset, group;
216 int ret;
217
218 if (!my_chip)
219 return -EINVAL;
220
221 offset = pin - my_chip->chip.base;
222 group = my_chip->group;
223
224 /* check if the group has been already registered */
225 if (my_chip->irq_base)
226 return my_chip->irq_base + offset;
227
228 /* register gpio group */
229 ret = s5p_gpioint_add(my_chip);
230 if (ret == 0) {
231 my_chip->chip.to_irq = samsung_gpiolib_to_irq;
232 printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
233 group);
234 return my_chip->irq_base + offset;
235 }
236 return ret;
237}
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
new file mode 100644
index 000000000000..dc33b9ecda45
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-pm.c
@@ -0,0 +1,93 @@
1/* linux/arch/arm/plat-s5p/irq-pm.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/plat-s3c24xx/irq-pm.c,
7 * Copyright (c) 2003,2004 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19#include <linux/sysdev.h>
20
21#include <plat/cpu.h>
22#include <plat/irqs.h>
23#include <plat/pm.h>
24#include <mach/map.h>
25
26#include <mach/regs-gpio.h>
27#include <mach/regs-irq.h>
28
29/* state for IRQs over sleep */
30
31/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
32 * as wakeup sources
33 *
34 * set bit to 1 in allow bitfield to enable the wakeup settings on it
35*/
36
37unsigned long s3c_irqwake_intallow = 0x00000006L;
38unsigned long s3c_irqwake_eintallow = 0xffffffffL;
39
40int s3c_irq_wake(unsigned int irqno, unsigned int state)
41{
42 unsigned long irqbit;
43
44 switch (irqno) {
45 case IRQ_RTC_TIC:
46 case IRQ_RTC_ALARM:
47 irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
48 if (!state)
49 s3c_irqwake_intmask |= irqbit;
50 else
51 s3c_irqwake_intmask &= ~irqbit;
52 break;
53 default:
54 return -ENOENT;
55 }
56 return 0;
57}
58
59static struct sleep_save eint_save[] = {
60 SAVE_ITEM(S5P_EINT_CON(0)),
61 SAVE_ITEM(S5P_EINT_CON(1)),
62 SAVE_ITEM(S5P_EINT_CON(2)),
63 SAVE_ITEM(S5P_EINT_CON(3)),
64
65 SAVE_ITEM(S5P_EINT_FLTCON(0)),
66 SAVE_ITEM(S5P_EINT_FLTCON(1)),
67 SAVE_ITEM(S5P_EINT_FLTCON(2)),
68 SAVE_ITEM(S5P_EINT_FLTCON(3)),
69 SAVE_ITEM(S5P_EINT_FLTCON(4)),
70 SAVE_ITEM(S5P_EINT_FLTCON(5)),
71 SAVE_ITEM(S5P_EINT_FLTCON(6)),
72 SAVE_ITEM(S5P_EINT_FLTCON(7)),
73
74 SAVE_ITEM(S5P_EINT_MASK(0)),
75 SAVE_ITEM(S5P_EINT_MASK(1)),
76 SAVE_ITEM(S5P_EINT_MASK(2)),
77 SAVE_ITEM(S5P_EINT_MASK(3)),
78};
79
80int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
81{
82 s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
83
84 return 0;
85}
86
87int s3c24xx_irq_resume(struct sys_device *dev)
88{
89 s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
90
91 return 0;
92}
93
diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c
new file mode 100644
index 000000000000..d592b6304b48
--- /dev/null
+++ b/arch/arm/plat-s5p/pm.c
@@ -0,0 +1,52 @@
1/* linux/arch/arm/plat-s5p/pm.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P Power Manager (Suspend-To-RAM) support
7 *
8 * Based on arch/arm/plat-s3c24xx/pm.c
9 * Copyright (c) 2004,2006 Simtec Electronics
10 * Ben Dooks <ben@simtec.co.uk>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17#include <linux/suspend.h>
18#include <plat/pm.h>
19
20#define PFX "s5p pm: "
21
22/* s3c_pm_check_resume_pin
23 *
24 * check to see if the pin is configured correctly for sleep mode, and
25 * make any necessary adjustments if it is not
26*/
27
28static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
29{
30 /* nothing here yet */
31}
32
33/* s3c_pm_configure_extint
34 *
35 * configure all external interrupt pins
36*/
37
38void s3c_pm_configure_extint(void)
39{
40 /* nothing here yet */
41}
42
43void s3c_pm_restore_core(void)
44{
45 /* nothing here yet */
46}
47
48void s3c_pm_save_core(void)
49{
50 /* nothing here yet */
51}
52
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 12:14:36 -0500