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-rw-r--r--arch/arm/plat-s5p/Kconfig1
-rw-r--r--arch/arm/plat-s5p/Makefile1
-rw-r--r--arch/arm/plat-s5p/cpu.c144
-rw-r--r--arch/arm/plat-s5p/s5p-time.c19
4 files changed, 4 insertions, 161 deletions
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 9b9968fa8695..8167ce66188c 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -11,6 +11,7 @@ config PLAT_S5P
11 default y 11 default y
12 select ARM_VIC if !ARCH_EXYNOS4 12 select ARM_VIC if !ARCH_EXYNOS4
13 select ARM_GIC if ARCH_EXYNOS4 13 select ARM_GIC if ARCH_EXYNOS4
14 select GIC_NON_BANKED if ARCH_EXYNOS4
14 select NO_IOPORT 15 select NO_IOPORT
15 select ARCH_REQUIRE_GPIOLIB 16 select ARCH_REQUIRE_GPIOLIB
16 select S3C_GPIO_TRACK 17 select S3C_GPIO_TRACK
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 876344038b8d..30d8c3016e6b 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -13,7 +13,6 @@ obj- :=
13# Core files 13# Core files
14 14
15obj-y += dev-uart.o 15obj-y += dev-uart.o
16obj-y += cpu.o
17obj-y += clock.o 16obj-y += clock.o
18obj-y += irq.o 17obj-y += irq.o
19obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o 18obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
deleted file mode 100644
index a56959e83516..000000000000
--- a/arch/arm/plat-s5p/cpu.c
+++ /dev/null
@@ -1,144 +0,0 @@
1/* linux/arch/arm/plat-s5p/cpu.c
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P CPU Support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15
16#include <asm/mach/arch.h>
17#include <asm/mach/map.h>
18
19#include <mach/map.h>
20#include <mach/regs-clock.h>
21
22#include <plat/cpu.h>
23#include <plat/s5p6440.h>
24#include <plat/s5p6450.h>
25#include <plat/s5pc100.h>
26#include <plat/s5pv210.h>
27#include <plat/exynos4.h>
28
29/* table of supported CPUs */
30
31static const char name_s5p6440[] = "S5P6440";
32static const char name_s5p6450[] = "S5P6450";
33static const char name_s5pc100[] = "S5PC100";
34static const char name_s5pv210[] = "S5PV210/S5PC110";
35static const char name_exynos4210[] = "EXYNOS4210";
36static const char name_exynos4212[] = "EXYNOS4212";
37static const char name_exynos4412[] = "EXYNOS4412";
38
39static struct cpu_table cpu_ids[] __initdata = {
40 {
41 .idcode = S5P6440_CPU_ID,
42 .idmask = S5P64XX_CPU_MASK,
43 .map_io = s5p6440_map_io,
44 .init_clocks = s5p6440_init_clocks,
45 .init_uarts = s5p6440_init_uarts,
46 .init = s5p64x0_init,
47 .name = name_s5p6440,
48 }, {
49 .idcode = S5P6450_CPU_ID,
50 .idmask = S5P64XX_CPU_MASK,
51 .map_io = s5p6450_map_io,
52 .init_clocks = s5p6450_init_clocks,
53 .init_uarts = s5p6450_init_uarts,
54 .init = s5p64x0_init,
55 .name = name_s5p6450,
56 }, {
57 .idcode = S5PC100_CPU_ID,
58 .idmask = S5PC100_CPU_MASK,
59 .map_io = s5pc100_map_io,
60 .init_clocks = s5pc100_init_clocks,
61 .init_uarts = s5pc100_init_uarts,
62 .init = s5pc100_init,
63 .name = name_s5pc100,
64 }, {
65 .idcode = S5PV210_CPU_ID,
66 .idmask = S5PV210_CPU_MASK,
67 .map_io = s5pv210_map_io,
68 .init_clocks = s5pv210_init_clocks,
69 .init_uarts = s5pv210_init_uarts,
70 .init = s5pv210_init,
71 .name = name_s5pv210,
72 }, {
73 .idcode = EXYNOS4210_CPU_ID,
74 .idmask = EXYNOS4_CPU_MASK,
75 .map_io = exynos4_map_io,
76 .init_clocks = exynos4_init_clocks,
77 .init_uarts = exynos4_init_uarts,
78 .init = exynos_init,
79 .name = name_exynos4210,
80 }, {
81 .idcode = EXYNOS4212_CPU_ID,
82 .idmask = EXYNOS4_CPU_MASK,
83 .map_io = exynos4_map_io,
84 .init_clocks = exynos4_init_clocks,
85 .init_uarts = exynos4_init_uarts,
86 .init = exynos_init,
87 .name = name_exynos4212,
88 }, {
89 .idcode = EXYNOS4412_CPU_ID,
90 .idmask = EXYNOS4_CPU_MASK,
91 .map_io = exynos4_map_io,
92 .init_clocks = exynos4_init_clocks,
93 .init_uarts = exynos4_init_uarts,
94 .init = exynos_init,
95 .name = name_exynos4412,
96 },
97};
98
99/* minimal IO mapping */
100
101static struct map_desc s5p_iodesc[] __initdata = {
102 {
103 .virtual = (unsigned long)S5P_VA_CHIPID,
104 .pfn = __phys_to_pfn(S5P_PA_CHIPID),
105 .length = SZ_4K,
106 .type = MT_DEVICE,
107 }, {
108 .virtual = (unsigned long)S3C_VA_SYS,
109 .pfn = __phys_to_pfn(S5P_PA_SYSCON),
110 .length = SZ_64K,
111 .type = MT_DEVICE,
112 }, {
113 .virtual = (unsigned long)S3C_VA_TIMER,
114 .pfn = __phys_to_pfn(S5P_PA_TIMER),
115 .length = SZ_16K,
116 .type = MT_DEVICE,
117 }, {
118 .virtual = (unsigned long)S3C_VA_WATCHDOG,
119 .pfn = __phys_to_pfn(S3C_PA_WDT),
120 .length = SZ_4K,
121 .type = MT_DEVICE,
122 }, {
123 .virtual = (unsigned long)S5P_VA_SROMC,
124 .pfn = __phys_to_pfn(S5P_PA_SROMC),
125 .length = SZ_4K,
126 .type = MT_DEVICE,
127 },
128};
129
130/* read cpu identification code */
131
132void __init s5p_init_io(struct map_desc *mach_desc,
133 int size, void __iomem *cpuid_addr)
134{
135 /* initialize the io descriptors we need for initialization */
136 iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc));
137 if (mach_desc)
138 iotable_init(mach_desc, size);
139
140 /* detect cpu id and rev. */
141 s5p_init_cpu(cpuid_addr);
142
143 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
144}
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index c833e7b57599..17c0a2c58dfd 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -10,7 +10,6 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#include <linux/sched.h>
14#include <linux/interrupt.h> 13#include <linux/interrupt.h>
15#include <linux/irq.h> 14#include <linux/irq.h>
16#include <linux/err.h> 15#include <linux/err.h>
@@ -321,26 +320,14 @@ static void __iomem *s5p_timer_reg(void)
321 * this wraps around for now, since it is just a relative time 320 * this wraps around for now, since it is just a relative time
322 * stamp. (Inspired by U300 implementation.) 321 * stamp. (Inspired by U300 implementation.)
323 */ 322 */
324static DEFINE_CLOCK_DATA(cd); 323static u32 notrace s5p_read_sched_clock(void)
325
326unsigned long long notrace sched_clock(void)
327{ 324{
328 void __iomem *reg = s5p_timer_reg(); 325 void __iomem *reg = s5p_timer_reg();
329 326
330 if (!reg) 327 if (!reg)
331 return 0; 328 return 0;
332 329
333 return cyc_to_sched_clock(&cd, ~__raw_readl(reg), (u32)~0); 330 return ~__raw_readl(reg);
334}
335
336static void notrace s5p_update_sched_clock(void)
337{
338 void __iomem *reg = s5p_timer_reg();
339
340 if (!reg)
341 return;
342
343 update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
344} 331}
345 332
346static void __init s5p_clocksource_init(void) 333static void __init s5p_clocksource_init(void)
@@ -358,7 +345,7 @@ static void __init s5p_clocksource_init(void)
358 s5p_time_setup(timer_source.source_id, TCNT_MAX); 345 s5p_time_setup(timer_source.source_id, TCNT_MAX);
359 s5p_time_start(timer_source.source_id, PERIODIC); 346 s5p_time_start(timer_source.source_id, PERIODIC);
360 347
361 init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate); 348 setup_sched_clock(s5p_read_sched_clock, 32, clock_rate);
362 349
363 if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer", 350 if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
364 clock_rate, 250, 32, clocksource_mmio_readl_down)) 351 clock_rate, 250, 32, clocksource_mmio_readl_down))
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 08:11:36 -0500