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-rw-r--r--arch/arm/plat-s5p/include/plat/mipi_csis.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/plat-s5p/include/plat/mipi_csis.h b/arch/arm/plat-s5p/include/plat/mipi_csis.h
index 8b3ada88df7a..9bd254c5ed22 100644
--- a/arch/arm/plat-s5p/include/plat/mipi_csis.h
+++ b/arch/arm/plat-s5p/include/plat/mipi_csis.h
@@ -11,18 +11,33 @@
11#ifndef PLAT_S5P_MIPI_CSIS_H_ 11#ifndef PLAT_S5P_MIPI_CSIS_H_
12#define PLAT_S5P_MIPI_CSIS_H_ __FILE__ 12#define PLAT_S5P_MIPI_CSIS_H_ __FILE__
13 13
14struct platform_device;
15
14/** 16/**
15 * struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver 17 * struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver
16 * @clk_rate: bus clock frequency 18 * @clk_rate: bus clock frequency
17 * @lanes: number of data lanes used 19 * @lanes: number of data lanes used
18 * @alignment: data alignment in bits 20 * @alignment: data alignment in bits
19 * @hs_settle: HS-RX settle time 21 * @hs_settle: HS-RX settle time
22 * @fixed_phy_vdd: false to enable external D-PHY regulator management in the
23 * driver or true in case this regulator has no enable function
24 * @phy_enable: pointer to a callback controlling D-PHY enable/reset
20 */ 25 */
21struct s5p_platform_mipi_csis { 26struct s5p_platform_mipi_csis {
22 unsigned long clk_rate; 27 unsigned long clk_rate;
23 u8 lanes; 28 u8 lanes;
24 u8 alignment; 29 u8 alignment;
25 u8 hs_settle; 30 u8 hs_settle;
31 bool fixed_phy_vdd;
32 int (*phy_enable)(struct platform_device *pdev, bool on);
26}; 33};
27 34
35/**
36 * s5p_csis_phy_enable - global MIPI-CSI receiver D-PHY control
37 * @pdev: MIPI-CSIS platform device
38 * @on: true to enable D-PHY and deassert its reset
39 * false to disable D-PHY
40 */
41int s5p_csis_phy_enable(struct platform_device *pdev, bool on);
42
28#endif /* PLAT_S5P_MIPI_CSIS_H_ */ 43#endif /* PLAT_S5P_MIPI_CSIS_H_ */