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-rw-r--r--arch/arm/plat-s3c/include/plat/audio.h17
-rw-r--r--arch/arm/plat-s3c/include/plat/cpu-freq.h145
-rw-r--r--arch/arm/plat-s3c/include/plat/cpu.h84
-rw-r--r--arch/arm/plat-s3c/include/plat/debug-macro.S75
-rw-r--r--arch/arm/plat-s3c/include/plat/devs.h71
-rw-r--r--arch/arm/plat-s3c/include/plat/fb.h80
-rw-r--r--arch/arm/plat-s3c/include/plat/pm.h189
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-fb-v4.h235
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-fb.h366
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-serial.h281
-rw-r--r--arch/arm/plat-s3c/include/plat/uncompress.h186
-rw-r--r--arch/arm/plat-s3c/include/plat/usb-control.h43
12 files changed, 0 insertions, 1772 deletions
diff --git a/arch/arm/plat-s3c/include/plat/audio.h b/arch/arm/plat-s3c/include/plat/audio.h
deleted file mode 100644
index f22d23bb6271..000000000000
--- a/arch/arm/plat-s3c/include/plat/audio.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* arch/arm/plat-s3c/include/plat/audio.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co. Ltd
4 * Author: Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/**
12 * struct s3c_audio_pdata - common platform data for audio device drivers
13 * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
14 */
15struct s3c_audio_pdata {
16 int (*cfg_gpio)(struct platform_device *);
17};
diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h
deleted file mode 100644
index 94eb06a2ea5c..000000000000
--- a/arch/arm/plat-s3c/include/plat/cpu-freq.h
+++ /dev/null
@@ -1,145 +0,0 @@
1/* arch/arm/plat-s3c/include/plat/cpu-freq.h
2 *
3 * Copyright (c) 2006-2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C CPU frequency scaling support - driver and board
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/cpufreq.h>
15
16struct s3c_cpufreq_info;
17struct s3c_cpufreq_board;
18struct s3c_iotimings;
19
20/**
21 * struct s3c_freq - frequency information (mainly for core drivers)
22 * @fclk: The FCLK frequency in Hz.
23 * @armclk: The ARMCLK frequency in Hz.
24 * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
25 * @hclk: The HCLK frequency in Hz.
26 * @pclk: The PCLK frequency in Hz.
27 *
28 * This contains the frequency information about the current configuration
29 * mainly for the core drivers to ensure we do not end up passing about
30 * a large number of parameters.
31 *
32 * The @hclk_tns field is a useful cache for the parts of the drivers that
33 * need to calculate IO timings and suchlike.
34 */
35struct s3c_freq {
36 unsigned long fclk;
37 unsigned long armclk;
38 unsigned long hclk_tns; /* in 10ths of ns */
39 unsigned long hclk;
40 unsigned long pclk;
41};
42
43/**
44 * struct s3c_cpufreq_freqs - s3c cpufreq notification information.
45 * @freqs: The cpufreq setting information.
46 * @old: The old clock settings.
47 * @new: The new clock settings.
48 * @pll_changing: Set if the PLL is changing.
49 *
50 * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the
51 * notification can use this information that is not provided by just
52 * having the core frequency alone.
53 *
54 * The pll_changing flag is used to indicate if the PLL itself is
55 * being set during this change. This is important as the clocks
56 * will temporarily be set to the XTAL clock during this time, so
57 * drivers may want to close down their output during this time.
58 *
59 * Note, this is not being used by any current drivers and therefore
60 * may be removed in the future.
61 */
62struct s3c_cpufreq_freqs {
63 struct cpufreq_freqs freqs;
64 struct s3c_freq old;
65 struct s3c_freq new;
66
67 unsigned int pll_changing:1;
68};
69
70#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
71
72/**
73 * struct s3c_clkdivs - clock divisor information
74 * @p_divisor: Divisor from FCLK to PCLK.
75 * @h_divisor: Divisor from FCLK to HCLK.
76 * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
77 * @dvs: Non-zero if using DVS mode for ARMCLK.
78 *
79 * Divisor settings for the core clocks.
80 */
81struct s3c_clkdivs {
82 int p_divisor;
83 int h_divisor;
84 int arm_divisor;
85 unsigned char dvs;
86};
87
88#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
89
90/**
91 * struct s3c_pllval - PLL value entry.
92 * @freq: The frequency for this entry in Hz.
93 * @pll_reg: The PLL register setting for this PLL value.
94 */
95struct s3c_pllval {
96 unsigned long freq;
97 unsigned long pll_reg;
98};
99
100/**
101 * struct s3c_cpufreq_board - per-board cpu frequency informatin
102 * @refresh: The SDRAM refresh period in nanoseconds.
103 * @auto_io: Set if the IO timing settings should be generated from the
104 * initialisation time hardware registers.
105 * @need_io: Set if the board has external IO on any of the chipselect
106 * lines that will require the hardware timing registers to be
107 * updated on a clock change.
108 * @max: The maxium frequency limits for the system. Any field that
109 * is left at zero will use the CPU's settings.
110 *
111 * This contains the board specific settings that affect how the CPU
112 * drivers chose settings. These include the memory refresh and IO
113 * timing information.
114 *
115 * Registration depends on the driver being used, the ARMCLK only
116 * implementation does not currently need this but the older style
117 * driver requires this to be available.
118 */
119struct s3c_cpufreq_board {
120 unsigned int refresh;
121 unsigned int auto_io:1; /* automatically init io timings. */
122 unsigned int need_io:1; /* set if needs io timing support. */
123
124 /* any non-zero field in here is taken as an upper limit. */
125 struct s3c_freq max; /* frequency limits */
126};
127
128/* Things depending on frequency scaling. */
129#ifdef CONFIG_CPU_FREQ_S3C
130#define __init_or_cpufreq
131#else
132#define __init_or_cpufreq __init
133#endif
134
135/* Board functions */
136
137#ifdef CONFIG_CPU_FREQ_S3C
138extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
139#else
140
141static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
142{
143 return 0;
144}
145#endif /* CONFIG_CPU_FREQ_S3C */
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h
deleted file mode 100644
index 676db9465674..000000000000
--- a/arch/arm/plat-s3c/include/plat/cpu.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/* linux/arch/arm/plat-s3c/include/plat/cpu.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* todo - fix when rmk changes iodescs to use `void __iomem *` */
14
15#ifndef __SAMSUNG_PLAT_CPU_H
16#define __SAMSUNG_PLAT_CPU_H
17
18#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
19
20#ifndef MHZ
21#define MHZ (1000*1000)
22#endif
23
24#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
25
26/* forward declaration */
27struct s3c24xx_uart_resources;
28struct platform_device;
29struct s3c2410_uartcfg;
30struct map_desc;
31
32/* per-cpu initialisation function table. */
33
34struct cpu_table {
35 unsigned long idcode;
36 unsigned long idmask;
37 void (*map_io)(void);
38 void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
39 void (*init_clocks)(int xtal);
40 int (*init)(void);
41 const char *name;
42};
43
44extern void s3c_init_cpu(unsigned long idcode,
45 struct cpu_table *cpus, unsigned int cputab_size);
46
47/* core initialisation functions */
48
49extern void s3c24xx_init_irq(void);
50extern void s3c64xx_init_irq(u32 vic0, u32 vic1);
51extern void s5p_init_irq(u32 *vic, u32 num_vic);
52
53extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
54extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
55extern void s5p_init_io(struct map_desc *mach_desc,
56 int size, void __iomem *cpuid_addr);
57
58extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
59
60extern void s3c24xx_init_clocks(int xtal);
61
62extern void s3c24xx_init_uartdevs(char *name,
63 struct s3c24xx_uart_resources *res,
64 struct s3c2410_uartcfg *cfg, int no);
65
66/* timer for 2410/2440 */
67
68struct sys_timer;
69extern struct sys_timer s3c24xx_timer;
70
71/* system device classes */
72
73extern struct sysdev_class s3c2410_sysclass;
74extern struct sysdev_class s3c2410a_sysclass;
75extern struct sysdev_class s3c2412_sysclass;
76extern struct sysdev_class s3c2440_sysclass;
77extern struct sysdev_class s3c2442_sysclass;
78extern struct sysdev_class s3c2443_sysclass;
79extern struct sysdev_class s3c6410_sysclass;
80extern struct sysdev_class s3c64xx_sysclass;
81
82extern void (*s5pc1xx_idle)(void);
83
84#endif
diff --git a/arch/arm/plat-s3c/include/plat/debug-macro.S b/arch/arm/plat-s3c/include/plat/debug-macro.S
deleted file mode 100644
index 3634d4e3708b..000000000000
--- a/arch/arm/plat-s3c/include/plat/debug-macro.S
+++ /dev/null
@@ -1,75 +0,0 @@
1/* linux/include/asm-arm/plat-s3c/debug-macro.S
2 *
3 * Copyright 2005, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <plat/regs-serial.h>
13
14/* The S3C2440 implementations are used by default as they are the
15 * most widely re-used */
16
17 .macro fifo_level_s3c2440 rd, rx
18 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
19 and \rd, \rd, #S3C2440_UFSTAT_TXMASK
20 .endm
21
22#ifndef fifo_level
23#define fifo_level fifo_level_s3c2440
24#endif
25
26 .macro fifo_full_s3c2440 rd, rx
27 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
28 tst \rd, #S3C2440_UFSTAT_TXFULL
29 .endm
30
31#ifndef fifo_full
32#define fifo_full fifo_full_s3c2440
33#endif
34
35 .macro senduart,rd,rx
36 strb \rd, [\rx, # S3C2410_UTXH ]
37 .endm
38
39 .macro busyuart, rd, rx
40 ldr \rd, [ \rx, # S3C2410_UFCON ]
41 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
42 beq 1001f @
43 @ FIFO enabled...
441003:
45 fifo_full \rd, \rx
46 bne 1003b
47 b 1002f
48
491001:
50 @ busy waiting for non fifo
51 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
52 tst \rd, #S3C2410_UTRSTAT_TXFE
53 beq 1001b
54
551002: @ exit busyuart
56 .endm
57
58 .macro waituart,rd,rx
59 ldr \rd, [ \rx, # S3C2410_UFCON ]
60 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
61 beq 1001f @
62 @ FIFO enabled...
631003:
64 fifo_level \rd, \rx
65 teq \rd, #0
66 bne 1003b
67 b 1002f
681001:
69 @ idle waiting for non fifo
70 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
71 tst \rd, #S3C2410_UTRSTAT_TXFE
72 beq 1001b
73
741002: @ exit busyuart
75 .endm
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h
deleted file mode 100644
index c6f9b7310490..000000000000
--- a/arch/arm/plat-s3c/include/plat/devs.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/devs.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2410 standard platform devices
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12#include <linux/platform_device.h>
13
14struct s3c24xx_uart_resources {
15 struct resource *resources;
16 unsigned long nr_resources;
17};
18
19extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
20extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
21extern struct s3c24xx_uart_resources s5p_uart_resources[];
22
23extern struct platform_device *s3c24xx_uart_devs[];
24extern struct platform_device *s3c24xx_uart_src[];
25
26extern struct platform_device s3c_device_timer[];
27
28extern struct platform_device s3c64xx_device_iis0;
29extern struct platform_device s3c64xx_device_iis1;
30extern struct platform_device s3c64xx_device_iisv4;
31
32extern struct platform_device s3c64xx_device_spi0;
33extern struct platform_device s3c64xx_device_spi1;
34
35extern struct platform_device s3c64xx_device_pcm0;
36extern struct platform_device s3c64xx_device_pcm1;
37
38extern struct platform_device s3c_device_ts;
39extern struct platform_device s3c_device_fb;
40extern struct platform_device s3c_device_ohci;
41extern struct platform_device s3c_device_lcd;
42extern struct platform_device s3c_device_wdt;
43extern struct platform_device s3c_device_i2c0;
44extern struct platform_device s3c_device_i2c1;
45extern struct platform_device s3c_device_rtc;
46extern struct platform_device s3c_device_adc;
47extern struct platform_device s3c_device_sdi;
48extern struct platform_device s3c_device_iis;
49extern struct platform_device s3c_device_hwmon;
50extern struct platform_device s3c_device_hsmmc0;
51extern struct platform_device s3c_device_hsmmc1;
52extern struct platform_device s3c_device_hsmmc2;
53
54extern struct platform_device s3c_device_spi0;
55extern struct platform_device s3c_device_spi1;
56
57extern struct platform_device s3c_device_hwmon;
58
59extern struct platform_device s3c_device_nand;
60
61extern struct platform_device s3c_device_usbgadget;
62extern struct platform_device s3c_device_usb_hsotg;
63
64/* s3c2440 specific devices */
65
66#ifdef CONFIG_CPU_S3C2440
67
68extern struct platform_device s3c_device_camif;
69extern struct platform_device s3c_device_ac97;
70
71#endif
diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h
deleted file mode 100644
index f8db87930f8b..000000000000
--- a/arch/arm/plat-s3c/include/plat/fb.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/* linux/arch/arm/plat-s3c/include/plat/fb.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - FB platform data definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_FB_H
16#define __PLAT_S3C_FB_H __FILE__
17
18/**
19 * struct s3c_fb_pd_win - per window setup data
20 * @win_mode: The display parameters to initialise (not for window 0)
21 * @virtual_x: The virtual X size.
22 * @virtual_y: The virtual Y size.
23 */
24struct s3c_fb_pd_win {
25 struct fb_videomode win_mode;
26
27 unsigned short default_bpp;
28 unsigned short max_bpp;
29 unsigned short virtual_x;
30 unsigned short virtual_y;
31};
32
33/**
34 * struct s3c_fb_platdata - S3C driver platform specific information
35 * @setup_gpio: Setup the external GPIO pins to the right state to transfer
36 * the data from the display system to the connected display
37 * device.
38 * @vidcon0: The base vidcon0 values to control the panel data format.
39 * @vidcon1: The base vidcon1 values to control the panel data output.
40 * @win: The setup data for each hardware window, or NULL for unused.
41 * @display_mode: The LCD output display mode.
42 *
43 * The platform data supplies the video driver with all the information
44 * it requires to work with the display(s) attached to the machine. It
45 * controls the initial mode, the number of display windows (0 is always
46 * the base framebuffer) that are initialised etc.
47 *
48 */
49struct s3c_fb_platdata {
50 void (*setup_gpio)(void);
51
52 struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN];
53
54 u32 vidcon0;
55 u32 vidcon1;
56};
57
58/**
59 * s3c_fb_set_platdata() - Setup the FB device with platform data.
60 * @pd: The platform data to set. The data is copied from the passed structure
61 * so the machine data can mark the data __initdata so that any unused
62 * machines will end up dumping their data at runtime.
63 */
64extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
65
66/**
67 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
68 *
69 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
70 */
71extern void s3c64xx_fb_gpio_setup_24bpp(void);
72
73/**
74 * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD
75 *
76 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
77 */
78extern void s5pc100_fb_gpio_setup_24bpp(void);
79
80#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h
deleted file mode 100644
index 2543bd227f2d..000000000000
--- a/arch/arm/plat-s3c/include/plat/pm.h
+++ /dev/null
@@ -1,189 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/pm.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Written by Ben Dooks, <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* s3c_pm_init
13 *
14 * called from board at initialisation time to setup the power
15 * management
16*/
17
18#ifdef CONFIG_PM
19
20extern __init int s3c_pm_init(void);
21
22#else
23
24static inline int s3c_pm_init(void)
25{
26 return 0;
27}
28#endif
29
30/* configuration for the IRQ mask over sleep */
31extern unsigned long s3c_irqwake_intmask;
32extern unsigned long s3c_irqwake_eintmask;
33
34/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
35extern unsigned long s3c_irqwake_intallow;
36extern unsigned long s3c_irqwake_eintallow;
37
38/* per-cpu sleep functions */
39
40extern void (*pm_cpu_prep)(void);
41extern void (*pm_cpu_sleep)(void);
42
43/* Flags for PM Control */
44
45extern unsigned long s3c_pm_flags;
46
47extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */
48
49/* from sleep.S */
50
51extern int s3c_cpu_save(unsigned long *saveblk);
52extern void s3c_cpu_resume(void);
53
54extern void s3c2410_cpu_suspend(void);
55
56extern unsigned long s3c_sleep_save_phys;
57
58/* sleep save info */
59
60/**
61 * struct sleep_save - save information for shared peripherals.
62 * @reg: Pointer to the register to save.
63 * @val: Holder for the value saved from reg.
64 *
65 * This describes a list of registers which is used by the pm core and
66 * other subsystem to save and restore register values over suspend.
67 */
68struct sleep_save {
69 void __iomem *reg;
70 unsigned long val;
71};
72
73#define SAVE_ITEM(x) \
74 { .reg = (x) }
75
76/**
77 * struct pm_uart_save - save block for core UART
78 * @ulcon: Save value for S3C2410_ULCON
79 * @ucon: Save value for S3C2410_UCON
80 * @ufcon: Save value for S3C2410_UFCON
81 * @umcon: Save value for S3C2410_UMCON
82 * @ubrdiv: Save value for S3C2410_UBRDIV
83 *
84 * Save block for UART registers to be held over sleep and restored if they
85 * are needed (say by debug).
86*/
87struct pm_uart_save {
88 u32 ulcon;
89 u32 ucon;
90 u32 ufcon;
91 u32 umcon;
92 u32 ubrdiv;
93 u32 udivslot;
94};
95
96/* helper functions to save/restore lists of registers. */
97
98extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
99extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
100extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
101
102#ifdef CONFIG_PM
103extern int s3c_irqext_wake(unsigned int irqno, unsigned int state);
104extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
105extern int s3c24xx_irq_resume(struct sys_device *dev);
106#else
107#define s3c_irqext_wake NULL
108#define s3c24xx_irq_suspend NULL
109#define s3c24xx_irq_resume NULL
110#endif
111
112/* PM debug functions */
113
114#ifdef CONFIG_SAMSUNG_PM_DEBUG
115/**
116 * s3c_pm_dbg() - low level debug function for use in suspend/resume.
117 * @msg: The message to print.
118 *
119 * This function is used mainly to debug the resume process before the system
120 * can rely on printk/console output. It uses the low-level debugging output
121 * routine printascii() to do its work.
122 */
123extern void s3c_pm_dbg(const char *msg, ...);
124
125#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
126#else
127#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
128#endif
129
130#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
131/**
132 * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
133 * @set: set bits for the state of the LEDs
134 * @clear: clear bits for the state of the LEDs.
135 */
136extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
137
138#else
139static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
140#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
141
142/* suspend memory checking */
143
144#ifdef CONFIG_SAMSUNG_PM_CHECK
145extern void s3c_pm_check_prepare(void);
146extern void s3c_pm_check_restore(void);
147extern void s3c_pm_check_cleanup(void);
148extern void s3c_pm_check_store(void);
149#else
150#define s3c_pm_check_prepare() do { } while(0)
151#define s3c_pm_check_restore() do { } while(0)
152#define s3c_pm_check_cleanup() do { } while(0)
153#define s3c_pm_check_store() do { } while(0)
154#endif
155
156/**
157 * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
158 *
159 * Setup all the necessary GPIO pins for waking the system on external
160 * interrupt.
161 */
162extern void s3c_pm_configure_extint(void);
163
164/**
165 * s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
166 *
167 * Restore the state of the GPIO pins after sleep, which may involve ensuring
168 * that we do not glitch the state of the pins from that the bootloader's
169 * resume code has done.
170*/
171extern void s3c_pm_restore_gpios(void);
172
173/**
174 * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
175 *
176 * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios().
177 */
178extern void s3c_pm_save_gpios(void);
179
180/**
181 * s3c_pm_cb_flushcache - callback for assembly code
182 *
183 * Callback to issue flush_cache_all() as this call is
184 * not a directly callable object.
185 */
186extern void s3c_pm_cb_flushcache(void);
187
188extern void s3c_pm_save_core(void);
189extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-s3c/include/plat/regs-fb-v4.h b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h
deleted file mode 100644
index a60ed0d06c94..000000000000
--- a/arch/arm/plat-s3c/include/plat/regs-fb-v4.h
+++ /dev/null
@@ -1,235 +0,0 @@
1/* arch/arm/plat-s3c/include/plat/regs-fb-v4.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards and specifically the S3C64XX series
12 * S3C6400 and S3C6410.
13 *
14 * The file contains the cpu specific items which change between whichever
15 * architecture is selected. See <plat/regs-fb.h> for the core definitions
16 * that are the same.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21*/
22
23/* include the core definitions here, in case we really do need to
24 * override them at a later date.
25*/
26
27#include <plat/regs-fb.h>
28
29#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
30#define VIDCON1_FSTATUS_EVEN (1 << 15)
31
32/* Video timing controls */
33#define VIDTCON0 (0x10)
34#define VIDTCON1 (0x14)
35#define VIDTCON2 (0x18)
36
37/* Window position controls */
38
39#define WINCON(_win) (0x20 + ((_win) * 4))
40
41/* OSD1 and OSD4 do not have register D */
42
43#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
44#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
45#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
46#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
47
48
49#define VIDINTCON0 (0x130)
50
51#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
52
53/* WINCONx */
54
55#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
56#define WINCONx_CSCWIDTH_SHIFT (26)
57#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
58#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
59
60#define WINCONx_ENLOCAL (1 << 22)
61#define WINCONx_BUFSTATUS (1 << 21)
62#define WINCONx_BUFSEL (1 << 20)
63#define WINCONx_BUFAUTOEN (1 << 19)
64#define WINCONx_YCbCr (1 << 13)
65
66#define WINCON1_LOCALSEL_CAMIF (1 << 23)
67
68#define WINCON2_LOCALSEL_CAMIF (1 << 23)
69#define WINCON2_BLD_PIX (1 << 6)
70
71#define WINCON2_ALPHA_SEL (1 << 1)
72#define WINCON2_BPPMODE_MASK (0xf << 2)
73#define WINCON2_BPPMODE_SHIFT (2)
74#define WINCON2_BPPMODE_1BPP (0x0 << 2)
75#define WINCON2_BPPMODE_2BPP (0x1 << 2)
76#define WINCON2_BPPMODE_4BPP (0x2 << 2)
77#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
78#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
79#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
80#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
81#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
82#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
83#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
84#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
85#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
86#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
87#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
88
89#define WINCON3_BLD_PIX (1 << 6)
90
91#define WINCON3_ALPHA_SEL (1 << 1)
92#define WINCON3_BPPMODE_MASK (0xf << 2)
93#define WINCON3_BPPMODE_SHIFT (2)
94#define WINCON3_BPPMODE_1BPP (0x0 << 2)
95#define WINCON3_BPPMODE_2BPP (0x1 << 2)
96#define WINCON3_BPPMODE_4BPP (0x2 << 2)
97#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
98#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
99#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
100#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
101#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
102#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
103#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
104#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
105#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
106#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
107
108#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
109#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
110#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
111
112#define DITHMODE (0x170)
113#define WINxMAP(_win) (0x180 + ((_win) * 4))
114
115
116#define DITHMODE_R_POS_MASK (0x3 << 5)
117#define DITHMODE_R_POS_SHIFT (5)
118#define DITHMODE_R_POS_8BIT (0x0 << 5)
119#define DITHMODE_R_POS_6BIT (0x1 << 5)
120#define DITHMODE_R_POS_5BIT (0x2 << 5)
121
122#define DITHMODE_G_POS_MASK (0x3 << 3)
123#define DITHMODE_G_POS_SHIFT (3)
124#define DITHMODE_G_POS_8BIT (0x0 << 3)
125#define DITHMODE_G_POS_6BIT (0x1 << 3)
126#define DITHMODE_G_POS_5BIT (0x2 << 3)
127
128#define DITHMODE_B_POS_MASK (0x3 << 1)
129#define DITHMODE_B_POS_SHIFT (1)
130#define DITHMODE_B_POS_8BIT (0x0 << 1)
131#define DITHMODE_B_POS_6BIT (0x1 << 1)
132#define DITHMODE_B_POS_5BIT (0x2 << 1)
133
134#define DITHMODE_DITH_EN (1 << 0)
135
136#define WPALCON (0x1A0)
137
138/* Palette control */
139/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
140 * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
141#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
142#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
143#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
144
145
146/* system specific implementation code for palette sizes, and other
147 * information that changes depending on which architecture is being
148 * compiled.
149*/
150
151/* return true if window _win has OSD register D */
152#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
153
154static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
155{
156 if (win < 2)
157 return 256;
158 if (win < 4)
159 return 16;
160 if (win == 4)
161 return 4;
162
163 BUG(); /* shouldn't get here */
164}
165
166static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
167{
168 /* all windows can do 1/2 bpp */
169
170 if ((bpp == 25 || bpp == 19) && win == 0)
171 return 0; /* win 0 does not have 19 or 25bpp modes */
172
173 if (bpp == 4 && win == 4)
174 return 0;
175
176 if (bpp == 8 && (win >= 3))
177 return 0; /* win 3/4 cannot do 8bpp in any mode */
178
179 return 1;
180}
181
182static inline int s3c_fb_pal_is16(unsigned int window)
183{
184 return window > 1;
185}
186
187struct s3c_fb_palette {
188 struct fb_bitfield r;
189 struct fb_bitfield g;
190 struct fb_bitfield b;
191 struct fb_bitfield a;
192};
193
194static inline void s3c_fb_init_palette(unsigned int window,
195 struct s3c_fb_palette *palette)
196{
197 if (window < 2) {
198 /* Windows 0/1 are 8/8/8 or A/8/8/8 */
199 palette->r.offset = 16;
200 palette->r.length = 8;
201 palette->g.offset = 8;
202 palette->g.length = 8;
203 palette->b.offset = 0;
204 palette->b.length = 8;
205 } else {
206 /* currently we assume RGB 5/6/5 */
207 palette->r.offset = 11;
208 palette->r.length = 5;
209 palette->g.offset = 5;
210 palette->g.length = 6;
211 palette->b.offset = 0;
212 palette->b.length = 5;
213 }
214}
215
216/* Notes on per-window bpp settings
217 *
218 * Value Win0 Win1 Win2 Win3 Win 4
219 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
220 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
221 * 0010 4(P) 4(P) 4(P) 4(P) -none-
222 * 0011 8(P) 8(P) -none- -none- -none-
223 * 0100 -none- 8(A232) 8(A232) -none- -none-
224 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
225 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
226 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
227 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
228 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
229 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
230 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
231 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
232 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
233 * 1110 -none- -none- -none- -none- -none-
234 * 1111 -none- -none- -none- -none- -none-
235*/
diff --git a/arch/arm/plat-s3c/include/plat/regs-fb.h b/arch/arm/plat-s3c/include/plat/regs-fb.h
deleted file mode 100644
index e9ee599d430e..000000000000
--- a/arch/arm/plat-s3c/include/plat/regs-fb.h
+++ /dev/null
@@ -1,366 +0,0 @@
1/* arch/arm/plat-s3c/include/plat/regs-fb.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
12 * S3C64XX series such as the S3C6400 and S3C6410.
13 *
14 * The file does not contain the cpu specific items which are based on
15 * whichever architecture is selected, it only contains the core of the
16 * register set. See <mach/regs-fb.h> to get the specifics.
17 *
18 * Note, we changed to using regs-fb.h as it avoids any clashes with
19 * the original regs-lcd.h so out of the way of regs-lcd.h as well as
20 * indicating the newer block is much more than just an LCD interface.
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25*/
26
27/* Please do not include this file directly, use <mach/regs-fb.h> to
28 * ensure all the localised SoC support is included as necessary.
29*/
30
31/* VIDCON0 */
32
33#define VIDCON0 (0x00)
34#define VIDCON0_INTERLACE (1 << 29)
35#define VIDCON0_VIDOUT_MASK (0x3 << 26)
36#define VIDCON0_VIDOUT_SHIFT (26)
37#define VIDCON0_VIDOUT_RGB (0x0 << 26)
38#define VIDCON0_VIDOUT_TV (0x1 << 26)
39#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
40#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
41
42#define VIDCON0_L1_DATA_MASK (0x7 << 23)
43#define VIDCON0_L1_DATA_SHIFT (23)
44#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
45#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
46#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
47#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
48#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
49#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
50
51#define VIDCON0_L0_DATA_MASK (0x7 << 20)
52#define VIDCON0_L0_DATA_SHIFT (20)
53#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
54#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
55#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
56#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
57#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
58#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
59
60#define VIDCON0_PNRMODE_MASK (0x3 << 17)
61#define VIDCON0_PNRMODE_SHIFT (17)
62#define VIDCON0_PNRMODE_RGB (0x0 << 17)
63#define VIDCON0_PNRMODE_BGR (0x1 << 17)
64#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
65#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
66
67#define VIDCON0_CLKVALUP (1 << 16)
68#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
69#define VIDCON0_CLKVAL_F_SHIFT (6)
70#define VIDCON0_CLKVAL_F_LIMIT (0xff)
71#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
72#define VIDCON0_VLCKFREE (1 << 5)
73#define VIDCON0_CLKDIR (1 << 4)
74
75#define VIDCON0_CLKSEL_MASK (0x3 << 2)
76#define VIDCON0_CLKSEL_SHIFT (2)
77#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
78#define VIDCON0_CLKSEL_LCD (0x1 << 2)
79#define VIDCON0_CLKSEL_27M (0x3 << 2)
80
81#define VIDCON0_ENVID (1 << 1)
82#define VIDCON0_ENVID_F (1 << 0)
83
84#define VIDCON1 (0x04)
85#define VIDCON1_LINECNT_MASK (0x7ff << 16)
86#define VIDCON1_LINECNT_SHIFT (16)
87#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
88#define VIDCON1_VSTATUS_MASK (0x3 << 13)
89#define VIDCON1_VSTATUS_SHIFT (13)
90#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
91#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
92#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
93#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
94
95#define VIDCON1_INV_VCLK (1 << 7)
96#define VIDCON1_INV_HSYNC (1 << 6)
97#define VIDCON1_INV_VSYNC (1 << 5)
98#define VIDCON1_INV_VDEN (1 << 4)
99
100/* VIDCON2 */
101
102#define VIDCON2 (0x08)
103#define VIDCON2_EN601 (1 << 23)
104#define VIDCON2_TVFMTSEL_SW (1 << 14)
105
106#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
107#define VIDCON2_TVFMTSEL1_SHIFT (12)
108#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
109#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
110#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
111
112#define VIDCON2_ORGYCbCr (1 << 8)
113#define VIDCON2_YUVORDCrCb (1 << 7)
114
115/* VIDTCON0 */
116
117#define VIDTCON0_VBPDE_MASK (0xff << 24)
118#define VIDTCON0_VBPDE_SHIFT (24)
119#define VIDTCON0_VBPDE_LIMIT (0xff)
120#define VIDTCON0_VBPDE(_x) ((_x) << 24)
121
122#define VIDTCON0_VBPD_MASK (0xff << 16)
123#define VIDTCON0_VBPD_SHIFT (16)
124#define VIDTCON0_VBPD_LIMIT (0xff)
125#define VIDTCON0_VBPD(_x) ((_x) << 16)
126
127#define VIDTCON0_VFPD_MASK (0xff << 8)
128#define VIDTCON0_VFPD_SHIFT (8)
129#define VIDTCON0_VFPD_LIMIT (0xff)
130#define VIDTCON0_VFPD(_x) ((_x) << 8)
131
132#define VIDTCON0_VSPW_MASK (0xff << 0)
133#define VIDTCON0_VSPW_SHIFT (0)
134#define VIDTCON0_VSPW_LIMIT (0xff)
135#define VIDTCON0_VSPW(_x) ((_x) << 0)
136
137/* VIDTCON1 */
138
139#define VIDTCON1_VFPDE_MASK (0xff << 24)
140#define VIDTCON1_VFPDE_SHIFT (24)
141#define VIDTCON1_VFPDE_LIMIT (0xff)
142#define VIDTCON1_VFPDE(_x) ((_x) << 24)
143
144#define VIDTCON1_HBPD_MASK (0xff << 16)
145#define VIDTCON1_HBPD_SHIFT (16)
146#define VIDTCON1_HBPD_LIMIT (0xff)
147#define VIDTCON1_HBPD(_x) ((_x) << 16)
148
149#define VIDTCON1_HFPD_MASK (0xff << 8)
150#define VIDTCON1_HFPD_SHIFT (8)
151#define VIDTCON1_HFPD_LIMIT (0xff)
152#define VIDTCON1_HFPD(_x) ((_x) << 8)
153
154#define VIDTCON1_HSPW_MASK (0xff << 0)
155#define VIDTCON1_HSPW_SHIFT (0)
156#define VIDTCON1_HSPW_LIMIT (0xff)
157#define VIDTCON1_HSPW(_x) ((_x) << 0)
158
159#define VIDTCON2 (0x18)
160#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
161#define VIDTCON2_LINEVAL_SHIFT (11)
162#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
163#define VIDTCON2_LINEVAL(_x) ((_x) << 11)
164
165#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
166#define VIDTCON2_HOZVAL_SHIFT (0)
167#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
168#define VIDTCON2_HOZVAL(_x) ((_x) << 0)
169
170/* WINCONx */
171
172
173#define WINCONx_BITSWP (1 << 18)
174#define WINCONx_BYTSWP (1 << 17)
175#define WINCONx_HAWSWP (1 << 16)
176#define WINCONx_BURSTLEN_MASK (0x3 << 9)
177#define WINCONx_BURSTLEN_SHIFT (9)
178#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
179#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
180#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
181
182#define WINCONx_ENWIN (1 << 0)
183#define WINCON0_BPPMODE_MASK (0xf << 2)
184#define WINCON0_BPPMODE_SHIFT (2)
185#define WINCON0_BPPMODE_1BPP (0x0 << 2)
186#define WINCON0_BPPMODE_2BPP (0x1 << 2)
187#define WINCON0_BPPMODE_4BPP (0x2 << 2)
188#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
189#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
190#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
191#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
192#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
193
194#define WINCON1_BLD_PIX (1 << 6)
195
196#define WINCON1_ALPHA_SEL (1 << 1)
197#define WINCON1_BPPMODE_MASK (0xf << 2)
198#define WINCON1_BPPMODE_SHIFT (2)
199#define WINCON1_BPPMODE_1BPP (0x0 << 2)
200#define WINCON1_BPPMODE_2BPP (0x1 << 2)
201#define WINCON1_BPPMODE_4BPP (0x2 << 2)
202#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
203#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
204#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
205#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
206#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
207#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
208#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
209#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
210#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
211#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
212#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
213#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
214
215
216#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
217#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
218#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
219#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11)
220
221#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
222#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
223#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
224#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0)
225
226#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
227#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
228#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
229#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11)
230
231#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
232#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
233#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
234#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0)
235
236/* For VIDOSD[1..4]C */
237#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
238#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
239#define VIDISD14C_ALPHA0_G_SHIFT (16)
240#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
241#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
242#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
243#define VIDISD14C_ALPHA0_B_SHIFT (12)
244#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
245#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
246#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
247#define VIDISD14C_ALPHA1_R_SHIFT (8)
248#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
249#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
250#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
251#define VIDISD14C_ALPHA1_G_SHIFT (4)
252#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
253#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
254#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
255#define VIDISD14C_ALPHA1_B_SHIFT (0)
256#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
257#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
258
259/* Video buffer addresses */
260#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
261#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
262#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
263#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
264#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
265
266#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
267#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
268#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
269#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13)
270
271#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
272#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
273#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
274#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0)
275
276/* Interrupt controls and status */
277
278#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
279#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
280#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
281#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
282
283#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
284#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
285#define VIDINTCON0_INT_I80IFDONE (1 << 17)
286
287#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
288#define VIDINTCON0_FRAMESEL0_SHIFT (15)
289#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
290#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
291#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
292#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
293
294#define VIDINTCON0_FRAMESEL1 (1 << 14)
295#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14)
296#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14)
297#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14)
298#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14)
299
300#define VIDINTCON0_INT_FRAME (1 << 12)
301#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
302#define VIDINTCON0_FIFIOSEL_SHIFT (5)
303#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
304#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
305
306#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
307#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
308#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
309#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
310#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
311#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
312#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
313
314#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
315#define VIDINTCON0_INT_FIFO_SHIFT (0)
316#define VIDINTCON0_INT_ENABLE (1 << 0)
317
318#define VIDINTCON1 (0x134)
319#define VIDINTCON1_INT_I180 (1 << 2)
320#define VIDINTCON1_INT_FRAME (1 << 1)
321#define VIDINTCON1_INT_FIFO (1 << 0)
322
323/* Window colour-key control registers */
324
325#define WxKEYCON0_KEYBL_EN (1 << 26)
326#define WxKEYCON0_KEYEN_F (1 << 25)
327#define WxKEYCON0_DIRCON (1 << 24)
328#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
329#define WxKEYCON0_COMPKEY_SHIFT (0)
330#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
331#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
332#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
333#define WxKEYCON1_COLVAL_SHIFT (0)
334#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
335#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
336
337
338/* Window blanking (MAP) */
339
340#define WINxMAP_MAP (1 << 24)
341#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
342#define WINxMAP_MAP_COLOUR_SHIFT (0)
343#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
344#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
345
346#define WPALCON_PAL_UPDATE (1 << 9)
347#define WPALCON_W1PAL_MASK (0x7 << 3)
348#define WPALCON_W1PAL_SHIFT (3)
349#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
350#define WPALCON_W1PAL_24BPP (0x1 << 3)
351#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
352#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
353#define WPALCON_W1PAL_18BPP (0x4 << 3)
354#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
355#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
356
357#define WPALCON_W0PAL_MASK (0x7 << 0)
358#define WPALCON_W0PAL_SHIFT (0)
359#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
360#define WPALCON_W0PAL_24BPP (0x1 << 0)
361#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
362#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
363#define WPALCON_W0PAL_18BPP (0x4 << 0)
364#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
365#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
366
diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
deleted file mode 100644
index 60d6604185ea..000000000000
--- a/arch/arm/plat-s3c/include/plat/regs-serial.h
+++ /dev/null
@@ -1,281 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-serial.h
2 *
3 * From linux/include/asm-arm/hardware/serial_s3c2410.h
4 *
5 * Internal header file for Samsung S3C2410 serial ports (UART0-2)
6 *
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 *
9 * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
10 *
11 * Adapted from:
12 *
13 * Internal header file for MX1ADS serial ports (UART1 & 2)
14 *
15 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30*/
31
32#ifndef __ASM_ARM_REGS_SERIAL_H
33#define __ASM_ARM_REGS_SERIAL_H
34
35#define S3C24XX_VA_UART0 (S3C_VA_UART)
36#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
37#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
38#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
39
40#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
41#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
42#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
43#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
44
45#define S3C2410_URXH (0x24)
46#define S3C2410_UTXH (0x20)
47#define S3C2410_ULCON (0x00)
48#define S3C2410_UCON (0x04)
49#define S3C2410_UFCON (0x08)
50#define S3C2410_UMCON (0x0C)
51#define S3C2410_UBRDIV (0x28)
52#define S3C2410_UTRSTAT (0x10)
53#define S3C2410_UERSTAT (0x14)
54#define S3C2410_UFSTAT (0x18)
55#define S3C2410_UMSTAT (0x1C)
56
57#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
58
59#define S3C2410_LCON_CS5 (0x0)
60#define S3C2410_LCON_CS6 (0x1)
61#define S3C2410_LCON_CS7 (0x2)
62#define S3C2410_LCON_CS8 (0x3)
63#define S3C2410_LCON_CSMASK (0x3)
64
65#define S3C2410_LCON_PNONE (0x0)
66#define S3C2410_LCON_PEVEN (0x5 << 3)
67#define S3C2410_LCON_PODD (0x4 << 3)
68#define S3C2410_LCON_PMASK (0x7 << 3)
69
70#define S3C2410_LCON_STOPB (1<<2)
71#define S3C2410_LCON_IRM (1<<6)
72
73#define S3C2440_UCON_CLKMASK (3<<10)
74#define S3C2440_UCON_PCLK (0<<10)
75#define S3C2440_UCON_UCLK (1<<10)
76#define S3C2440_UCON_PCLK2 (2<<10)
77#define S3C2440_UCON_FCLK (3<<10)
78#define S3C2443_UCON_EPLL (3<<10)
79
80#define S3C6400_UCON_CLKMASK (3<<10)
81#define S3C6400_UCON_PCLK (0<<10)
82#define S3C6400_UCON_PCLK2 (2<<10)
83#define S3C6400_UCON_UCLK0 (1<<10)
84#define S3C6400_UCON_UCLK1 (3<<10)
85
86#define S3C2440_UCON2_FCLK_EN (1<<15)
87#define S3C2440_UCON0_DIVMASK (15 << 12)
88#define S3C2440_UCON1_DIVMASK (15 << 12)
89#define S3C2440_UCON2_DIVMASK (7 << 12)
90#define S3C2440_UCON_DIVSHIFT (12)
91
92#define S3C2412_UCON_CLKMASK (3<<10)
93#define S3C2412_UCON_UCLK (1<<10)
94#define S3C2412_UCON_USYSCLK (3<<10)
95#define S3C2412_UCON_PCLK (0<<10)
96#define S3C2412_UCON_PCLK2 (2<<10)
97
98#define S3C2410_UCON_UCLK (1<<10)
99#define S3C2410_UCON_SBREAK (1<<4)
100
101#define S3C2410_UCON_TXILEVEL (1<<9)
102#define S3C2410_UCON_RXILEVEL (1<<8)
103#define S3C2410_UCON_TXIRQMODE (1<<2)
104#define S3C2410_UCON_RXIRQMODE (1<<0)
105#define S3C2410_UCON_RXFIFO_TOI (1<<7)
106#define S3C2443_UCON_RXERR_IRQEN (1<<6)
107#define S3C2443_UCON_LOOPBACK (1<<5)
108
109#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
110 S3C2410_UCON_RXILEVEL | \
111 S3C2410_UCON_TXIRQMODE | \
112 S3C2410_UCON_RXIRQMODE | \
113 S3C2410_UCON_RXFIFO_TOI)
114
115#define S3C2410_UFCON_FIFOMODE (1<<0)
116#define S3C2410_UFCON_TXTRIG0 (0<<6)
117#define S3C2410_UFCON_RXTRIG8 (1<<4)
118#define S3C2410_UFCON_RXTRIG12 (2<<4)
119
120/* S3C2440 FIFO trigger levels */
121#define S3C2440_UFCON_RXTRIG1 (0<<4)
122#define S3C2440_UFCON_RXTRIG8 (1<<4)
123#define S3C2440_UFCON_RXTRIG16 (2<<4)
124#define S3C2440_UFCON_RXTRIG32 (3<<4)
125
126#define S3C2440_UFCON_TXTRIG0 (0<<6)
127#define S3C2440_UFCON_TXTRIG16 (1<<6)
128#define S3C2440_UFCON_TXTRIG32 (2<<6)
129#define S3C2440_UFCON_TXTRIG48 (3<<6)
130
131#define S3C2410_UFCON_RESETBOTH (3<<1)
132#define S3C2410_UFCON_RESETTX (1<<2)
133#define S3C2410_UFCON_RESETRX (1<<1)
134
135#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
136 S3C2410_UFCON_TXTRIG0 | \
137 S3C2410_UFCON_RXTRIG8 )
138
139#define S3C2410_UMCOM_AFC (1<<4)
140#define S3C2410_UMCOM_RTS_LOW (1<<0)
141
142#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
143#define S3C2412_UMCON_AFC_56 (1<<5)
144#define S3C2412_UMCON_AFC_48 (2<<5)
145#define S3C2412_UMCON_AFC_40 (3<<5)
146#define S3C2412_UMCON_AFC_32 (4<<5)
147#define S3C2412_UMCON_AFC_24 (5<<5)
148#define S3C2412_UMCON_AFC_16 (6<<5)
149#define S3C2412_UMCON_AFC_8 (7<<5)
150
151#define S3C2410_UFSTAT_TXFULL (1<<9)
152#define S3C2410_UFSTAT_RXFULL (1<<8)
153#define S3C2410_UFSTAT_TXMASK (15<<4)
154#define S3C2410_UFSTAT_TXSHIFT (4)
155#define S3C2410_UFSTAT_RXMASK (15<<0)
156#define S3C2410_UFSTAT_RXSHIFT (0)
157
158/* UFSTAT S3C24A0 */
159#define S3C24A0_UFSTAT_TXFULL (1 << 14)
160#define S3C24A0_UFSTAT_RXFULL (1 << 6)
161#define S3C24A0_UFSTAT_TXMASK (63 << 8)
162#define S3C24A0_UFSTAT_TXSHIFT (8)
163#define S3C24A0_UFSTAT_RXMASK (63)
164#define S3C24A0_UFSTAT_RXSHIFT (0)
165
166/* UFSTAT S3C2443 same as S3C2440 */
167#define S3C2440_UFSTAT_TXFULL (1<<14)
168#define S3C2440_UFSTAT_RXFULL (1<<6)
169#define S3C2440_UFSTAT_TXSHIFT (8)
170#define S3C2440_UFSTAT_RXSHIFT (0)
171#define S3C2440_UFSTAT_TXMASK (63<<8)
172#define S3C2440_UFSTAT_RXMASK (63)
173
174#define S3C2410_UTRSTAT_TXE (1<<2)
175#define S3C2410_UTRSTAT_TXFE (1<<1)
176#define S3C2410_UTRSTAT_RXDR (1<<0)
177
178#define S3C2410_UERSTAT_OVERRUN (1<<0)
179#define S3C2410_UERSTAT_FRAME (1<<2)
180#define S3C2410_UERSTAT_BREAK (1<<3)
181#define S3C2443_UERSTAT_PARITY (1<<1)
182
183#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
184 S3C2410_UERSTAT_FRAME | \
185 S3C2410_UERSTAT_BREAK)
186
187#define S3C2410_UMSTAT_CTS (1<<0)
188#define S3C2410_UMSTAT_DeltaCTS (1<<2)
189
190#define S3C2443_DIVSLOT (0x2C)
191
192/* S3C64XX interrupt registers. */
193#define S3C64XX_UINTP 0x30
194#define S3C64XX_UINTSP 0x34
195#define S3C64XX_UINTM 0x38
196
197/* Following are specific to S5PV210 and S5P6442 */
198#define S5PV210_UCON_CLKMASK (1<<10)
199#define S5PV210_UCON_PCLK (0<<10)
200#define S5PV210_UCON_UCLK (1<<10)
201
202#define S5PV210_UFCON_TXTRIG0 (0<<8)
203#define S5PV210_UFCON_TXTRIG4 (1<<8)
204#define S5PV210_UFCON_TXTRIG8 (2<<8)
205#define S5PV210_UFCON_TXTRIG16 (3<<8)
206#define S5PV210_UFCON_TXTRIG32 (4<<8)
207#define S5PV210_UFCON_TXTRIG64 (5<<8)
208#define S5PV210_UFCON_TXTRIG128 (6<<8)
209#define S5PV210_UFCON_TXTRIG256 (7<<8)
210
211#define S5PV210_UFCON_RXTRIG1 (0<<4)
212#define S5PV210_UFCON_RXTRIG4 (1<<4)
213#define S5PV210_UFCON_RXTRIG8 (2<<4)
214#define S5PV210_UFCON_RXTRIG16 (3<<4)
215#define S5PV210_UFCON_RXTRIG32 (4<<4)
216#define S5PV210_UFCON_RXTRIG64 (5<<4)
217#define S5PV210_UFCON_RXTRIG128 (6<<4)
218#define S5PV210_UFCON_RXTRIG256 (7<<4)
219
220#define S5PV210_UFSTAT_TXFULL (1<<24)
221#define S5PV210_UFSTAT_RXFULL (1<<8)
222#define S5PV210_UFSTAT_TXMASK (255<<16)
223#define S5PV210_UFSTAT_TXSHIFT (16)
224#define S5PV210_UFSTAT_RXMASK (255<<0)
225#define S5PV210_UFSTAT_RXSHIFT (0)
226
227#ifndef __ASSEMBLY__
228
229/* struct s3c24xx_uart_clksrc
230 *
231 * this structure defines a named clock source that can be used for the
232 * uart, so that the best clock can be selected for the requested baud
233 * rate.
234 *
235 * min_baud and max_baud define the range of baud-rates this clock is
236 * acceptable for, if they are both zero, it is assumed any baud rate that
237 * can be generated from this clock will be used.
238 *
239 * divisor gives the divisor from the clock to the one seen by the uart
240*/
241
242struct s3c24xx_uart_clksrc {
243 const char *name;
244 unsigned int divisor;
245 unsigned int min_baud;
246 unsigned int max_baud;
247};
248
249/* configuration structure for per-machine configurations for the
250 * serial port
251 *
252 * the pointer is setup by the machine specific initialisation from the
253 * arch/arm/mach-s3c2410/ directory.
254*/
255
256struct s3c2410_uartcfg {
257 unsigned char hwport; /* hardware port number */
258 unsigned char unused;
259 unsigned short flags;
260 upf_t uart_flags; /* default uart flags */
261
262 unsigned long ucon; /* value of ucon for port */
263 unsigned long ulcon; /* value of ulcon for port */
264 unsigned long ufcon; /* value of ufcon for port */
265
266 struct s3c24xx_uart_clksrc *clocks;
267 unsigned int clocks_size;
268};
269
270/* s3c24xx_uart_devs
271 *
272 * this is exported from the core as we cannot use driver_register(),
273 * or platform_add_device() before the console_initcall()
274*/
275
276extern struct platform_device *s3c24xx_uart_devs[4];
277
278#endif /* __ASSEMBLY__ */
279
280#endif /* __ASM_ARM_REGS_SERIAL_H */
281
diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h
deleted file mode 100644
index dc66a477f62e..000000000000
--- a/arch/arm/plat-s3c/include/plat/uncompress.h
+++ /dev/null
@@ -1,186 +0,0 @@
1/* linux/include/asm-arm/plat-s3c/uncompress.h
2 *
3 * Copyright 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - uncompress code
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_PLAT_UNCOMPRESS_H
15#define __ASM_PLAT_UNCOMPRESS_H
16
17typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
18
19/* uart setup */
20
21static unsigned int fifo_mask;
22static unsigned int fifo_max;
23
24/* forward declerations */
25
26static void arch_detect_cpu(void);
27
28/* defines for UART registers */
29
30#include <plat/regs-serial.h>
31#include <plat/regs-watchdog.h>
32
33/* working in physical space... */
34#undef S3C2410_WDOGREG
35#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
36
37/* how many bytes we allow into the FIFO at a time in FIFO mode */
38#define FIFO_MAX (14)
39
40#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
41
42static __inline__ void
43uart_wr(unsigned int reg, unsigned int val)
44{
45 volatile unsigned int *ptr;
46
47 ptr = (volatile unsigned int *)(reg + uart_base);
48 *ptr = val;
49}
50
51static __inline__ unsigned int
52uart_rd(unsigned int reg)
53{
54 volatile unsigned int *ptr;
55
56 ptr = (volatile unsigned int *)(reg + uart_base);
57 return *ptr;
58}
59
60/* we can deal with the case the UARTs are being run
61 * in FIFO mode, so that we don't hold up our execution
62 * waiting for tx to happen...
63*/
64
65static void putc(int ch)
66{
67 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
68 int level;
69
70 while (1) {
71 level = uart_rd(S3C2410_UFSTAT);
72 level &= fifo_mask;
73
74 if (level < fifo_max)
75 break;
76 }
77
78 } else {
79 /* not using fifos */
80
81 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
82 barrier();
83 }
84
85 /* write byte to transmission register */
86 uart_wr(S3C2410_UTXH, ch);
87}
88
89static inline void flush(void)
90{
91}
92
93#define __raw_writel(d, ad) \
94 do { \
95 *((volatile unsigned int __force *)(ad)) = (d); \
96 } while (0)
97
98/* CONFIG_S3C_BOOT_WATCHDOG
99 *
100 * Simple boot-time watchdog setup, to reboot the system if there is
101 * any problem with the boot process
102*/
103
104#ifdef CONFIG_S3C_BOOT_WATCHDOG
105
106#define WDOG_COUNT (0xff00)
107
108static inline void arch_decomp_wdog(void)
109{
110 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
111}
112
113static void arch_decomp_wdog_start(void)
114{
115 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
116 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
117 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
118}
119
120#else
121#define arch_decomp_wdog_start()
122#define arch_decomp_wdog()
123#endif
124
125#ifdef CONFIG_S3C_BOOT_ERROR_RESET
126
127static void arch_decomp_error(const char *x)
128{
129 putstr("\n\n");
130 putstr(x);
131 putstr("\n\n -- System resetting\n");
132
133 __raw_writel(0x4000, S3C2410_WTDAT);
134 __raw_writel(0x4000, S3C2410_WTCNT);
135 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
136
137 while(1);
138}
139
140#define arch_error arch_decomp_error
141#endif
142
143static void error(char *err);
144
145#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
146static inline void arch_enable_uart_fifo(void)
147{
148 u32 fifocon = uart_rd(S3C2410_UFCON);
149
150 if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
151 fifocon |= S3C2410_UFCON_RESETBOTH;
152 uart_wr(S3C2410_UFCON, fifocon);
153
154 /* wait for fifo reset to complete */
155 while (1) {
156 fifocon = uart_rd(S3C2410_UFCON);
157 if (!(fifocon & S3C2410_UFCON_RESETBOTH))
158 break;
159 }
160 }
161}
162#else
163#define arch_enable_uart_fifo() do { } while(0)
164#endif
165
166
167static void
168arch_decomp_setup(void)
169{
170 /* we may need to setup the uart(s) here if we are not running
171 * on an BAST... the BAST will have left the uarts configured
172 * after calling linux.
173 */
174
175 arch_detect_cpu();
176 arch_decomp_wdog_start();
177
178 /* Enable the UART FIFOs if they where not enabled and our
179 * configuration says we should turn them on.
180 */
181
182 arch_enable_uart_fifo();
183}
184
185
186#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-s3c/include/plat/usb-control.h b/arch/arm/plat-s3c/include/plat/usb-control.h
deleted file mode 100644
index a6a57bf796bd..000000000000
--- a/arch/arm/plat-s3c/include/plat/usb-control.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/* arch/arm/plat-s3c/include/plat/usb-control.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C - USB host port information
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_USBCONTROL_H
14#define __ASM_ARCH_USBCONTROL_H
15
16#define S3C_HCDFLG_USED (1)
17
18struct s3c2410_hcd_port {
19 unsigned char flags;
20 unsigned char power;
21 unsigned char oc_status;
22 unsigned char oc_changed;
23};
24
25struct s3c2410_hcd_info {
26 struct usb_hcd *hcd;
27 struct s3c2410_hcd_port port[2];
28
29 void (*power_control)(int port, int to);
30 void (*enable_oc)(struct s3c2410_hcd_info *, int on);
31 void (*report_oc)(struct s3c2410_hcd_info *, int ports);
32};
33
34static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports)
35{
36 if (info->report_oc != NULL) {
37 (info->report_oc)(info, ports);
38 }
39}
40
41extern void s3c_ohci_set_platdata(struct s3c2410_hcd_info *info);
42
43#endif /*__ASM_ARCH_USBCONTROL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 16:57:49 -0500