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-rw-r--r--arch/arm/plat-s3c/Kconfig26
-rw-r--r--arch/arm/plat-s3c/Makefile8
-rw-r--r--arch/arm/plat-s3c/dev-audio.c68
-rw-r--r--arch/arm/plat-s3c/dev-usb-hsotg.c41
-rw-r--r--arch/arm/plat-s3c/dev-usb.c50
-rw-r--r--arch/arm/plat-s3c/dma.c86
-rw-r--r--arch/arm/plat-s3c/gpio-config.c2
-rw-r--r--arch/arm/plat-s3c/gpio.c11
-rw-r--r--arch/arm/plat-s3c/include/plat/adc.h10
-rw-r--r--arch/arm/plat-s3c/include/plat/clock.h1
-rw-r--r--arch/arm/plat-s3c/include/plat/cpu.h3
-rw-r--r--arch/arm/plat-s3c/include/plat/devs.h6
-rw-r--r--arch/arm/plat-s3c/include/plat/dma-core.h22
-rw-r--r--arch/arm/plat-s3c/include/plat/dma.h127
-rw-r--r--arch/arm/plat-s3c/include/plat/gpio-core.h30
-rw-r--r--arch/arm/plat-s3c/include/plat/nand.h31
-rw-r--r--arch/arm/plat-s3c/include/plat/pm.h15
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-serial.h5
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h50
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h377
-rw-r--r--arch/arm/plat-s3c/include/plat/sdhci.h50
-rw-r--r--arch/arm/plat-s3c/include/plat/udc-hs.h29
-rw-r--r--arch/arm/plat-s3c/include/plat/watchdog-reset.h49
-rw-r--r--arch/arm/plat-s3c/pm-gpio.c380
-rw-r--r--arch/arm/plat-s3c/pm.c19
25 files changed, 1470 insertions, 26 deletions
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index de9383814e5e..935c7558469b 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -71,6 +71,15 @@ config S3C2410_PM_DEBUG
71 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> 71 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
72 for more information. 72 for more information.
73 73
74config S3C_PM_DEBUG_LED_SMDK
75 bool "SMDK LED suspend/resume debugging"
76 depends on PM && (MACH_SMDK6410)
77 help
78 Say Y here to enable the use of the SMDK LEDs on the baseboard
79 for debugging of the state of the suspend and resume process.
80
81 Note, this currently only works for S3C64XX based SMDK boards.
82
74config S3C2410_PM_CHECK 83config S3C2410_PM_CHECK
75 bool "S3C2410 PM Suspend Memory CRC" 84 bool "S3C2410 PM Suspend Memory CRC"
76 depends on PM && CRC32 85 depends on PM && CRC32
@@ -150,6 +159,13 @@ config S3C_GPIO_CFG_S3C64XX
150 Internal configuration to enable S3C64XX style GPIO configuration 159 Internal configuration to enable S3C64XX style GPIO configuration
151 functions. 160 functions.
152 161
162# DMA
163
164config S3C_DMA
165 bool
166 help
167 Internal configuration for S3C DMA core
168
153# device definitions to compile in 169# device definitions to compile in
154 170
155config S3C_DEV_HSMMC 171config S3C_DEV_HSMMC
@@ -172,4 +188,14 @@ config S3C_DEV_FB
172 help 188 help
173 Compile in platform device definition for framebuffer 189 Compile in platform device definition for framebuffer
174 190
191config S3C_DEV_USB_HOST
192 bool
193 help
194 Compile in platform device definition for USB host.
195
196config S3C_DEV_USB_HSOTG
197 bool
198 help
199 Compile in platform device definition for USB high-speed OtG
200
175endif 201endif
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 8d7815d25a51..74bb7cb5da49 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -18,9 +18,14 @@ obj-y += pwm-clock.o
18obj-y += gpio.o 18obj-y += gpio.o
19obj-y += gpio-config.o 19obj-y += gpio-config.o
20 20
21# DMA support
22
23obj-$(CONFIG_S3C_DMA) += dma.o
24
21# PM support 25# PM support
22 26
23obj-$(CONFIG_PM) += pm.o 27obj-$(CONFIG_PM) += pm.o
28obj-$(CONFIG_PM) += pm-gpio.o
24obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o 29obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o
25 30
26# devices 31# devices
@@ -29,4 +34,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
29obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o 34obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
30obj-y += dev-i2c0.o 35obj-y += dev-i2c0.o
31obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o 36obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
37obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o
32obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o 38obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
39obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o
40obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
diff --git a/arch/arm/plat-s3c/dev-audio.c b/arch/arm/plat-s3c/dev-audio.c
new file mode 100644
index 000000000000..1322beb40dd7
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-audio.c
@@ -0,0 +1,68 @@
1/* linux/arch/arm/plat-s3c/dev-audio.c
2 *
3 * Copyright 2009 Wolfson Microelectronics
4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 *
6
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/platform_device.h>
15
16#include <mach/irqs.h>
17#include <mach/map.h>
18
19#include <plat/devs.h>
20
21
22static struct resource s3c64xx_iis0_resource[] = {
23 [0] = {
24 .start = S3C64XX_PA_IIS0,
25 .end = S3C64XX_PA_IIS0 + 0x100 - 1,
26 .flags = IORESOURCE_MEM,
27 },
28};
29
30struct platform_device s3c64xx_device_iis0 = {
31 .name = "s3c64xx-iis",
32 .id = 0,
33 .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource),
34 .resource = s3c64xx_iis0_resource,
35};
36EXPORT_SYMBOL(s3c64xx_device_iis0);
37
38static struct resource s3c64xx_iis1_resource[] = {
39 [0] = {
40 .start = S3C64XX_PA_IIS1,
41 .end = S3C64XX_PA_IIS1 + 0x100 - 1,
42 .flags = IORESOURCE_MEM,
43 },
44};
45
46struct platform_device s3c64xx_device_iis1 = {
47 .name = "s3c64xx-iis",
48 .id = 1,
49 .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource),
50 .resource = s3c64xx_iis1_resource,
51};
52EXPORT_SYMBOL(s3c64xx_device_iis1);
53
54static struct resource s3c64xx_iisv4_resource[] = {
55 [0] = {
56 .start = S3C64XX_PA_IISV4,
57 .end = S3C64XX_PA_IISV4 + 0x100 - 1,
58 .flags = IORESOURCE_MEM,
59 },
60};
61
62struct platform_device s3c64xx_device_iisv4 = {
63 .name = "s3c64xx-iis-v4",
64 .id = -1,
65 .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource),
66 .resource = s3c64xx_iisv4_resource,
67};
68EXPORT_SYMBOL(s3c64xx_device_iisv4);
diff --git a/arch/arm/plat-s3c/dev-usb-hsotg.c b/arch/arm/plat-s3c/dev-usb-hsotg.c
new file mode 100644
index 000000000000..e2f604b51c86
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-usb-hsotg.c
@@ -0,0 +1,41 @@
1/* linux/arch/arm/plat-s3c/dev-usb-hsotg.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for USB high-speed UDC/OtG block
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20
21#include <plat/devs.h>
22
23static struct resource s3c_usb_hsotg_resources[] = {
24 [0] = {
25 .start = S3C_PA_USB_HSOTG,
26 .end = S3C_PA_USB_HSOTG + 0x10000 - 1,
27 .flags = IORESOURCE_MEM,
28 },
29 [1] = {
30 .start = IRQ_OTG,
31 .end = IRQ_OTG,
32 .flags = IORESOURCE_IRQ,
33 },
34};
35
36struct platform_device s3c_device_usb_hsotg = {
37 .name = "s3c-hsotg",
38 .id = -1,
39 .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
40 .resource = s3c_usb_hsotg_resources,
41};
diff --git a/arch/arm/plat-s3c/dev-usb.c b/arch/arm/plat-s3c/dev-usb.c
new file mode 100644
index 000000000000..2ee85abed6d9
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-usb.c
@@ -0,0 +1,50 @@
1/* linux/arch/arm/plat-s3c/dev-usb.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for USB host
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20
21#include <plat/devs.h>
22
23
24static struct resource s3c_usb_resource[] = {
25 [0] = {
26 .start = S3C_PA_USBHOST,
27 .end = S3C_PA_USBHOST + 0x100 - 1,
28 .flags = IORESOURCE_MEM,
29 },
30 [1] = {
31 .start = IRQ_USBH,
32 .end = IRQ_USBH,
33 .flags = IORESOURCE_IRQ,
34 }
35};
36
37static u64 s3c_device_usb_dmamask = 0xffffffffUL;
38
39struct platform_device s3c_device_usb = {
40 .name = "s3c2410-ohci",
41 .id = -1,
42 .num_resources = ARRAY_SIZE(s3c_usb_resource),
43 .resource = s3c_usb_resource,
44 .dev = {
45 .dma_mask = &s3c_device_usb_dmamask,
46 .coherent_dma_mask = 0xffffffffUL
47 }
48};
49
50EXPORT_SYMBOL(s3c_device_usb);
diff --git a/arch/arm/plat-s3c/dma.c b/arch/arm/plat-s3c/dma.c
new file mode 100644
index 000000000000..c9db75c06af5
--- /dev/null
+++ b/arch/arm/plat-s3c/dma.c
@@ -0,0 +1,86 @@
1/* linux/arch/arm/plat-s3c/dma.c
2 *
3 * Copyright (c) 2003-2005,2006,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C DMA core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14struct s3c2410_dma_buf;
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/errno.h>
19
20#include <mach/dma.h>
21#include <mach/irqs.h>
22
23#include <plat/dma-plat.h>
24
25/* dma channel state information */
26struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
27struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
28
29/* s3c_dma_lookup_channel
30 *
31 * change the dma channel number given into a real dma channel id
32*/
33
34struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
35{
36 if (channel & DMACH_LOW_LEVEL)
37 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
38 else
39 return s3c_dma_chan_map[channel];
40}
41
42/* do we need to protect the settings of the fields from
43 * irq?
44*/
45
46int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
47{
48 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
49
50 if (chan == NULL)
51 return -EINVAL;
52
53 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
54
55 chan->op_fn = rtn;
56
57 return 0;
58}
59EXPORT_SYMBOL(s3c2410_dma_set_opfn);
60
61int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
62{
63 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
64
65 if (chan == NULL)
66 return -EINVAL;
67
68 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
69
70 chan->callback_fn = rtn;
71
72 return 0;
73}
74EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
75
76int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
77{
78 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
79
80 if (chan == NULL)
81 return -EINVAL;
82
83 chan->flags = flags;
84 return 0;
85}
86EXPORT_SYMBOL(s3c2410_dma_setflags);
diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-s3c/gpio-config.c
index 08044dec9731..456969b6fa0d 100644
--- a/arch/arm/plat-s3c/gpio-config.c
+++ b/arch/arm/plat-s3c/gpio-config.c
@@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
119 unsigned int shift = (off & 7) * 4; 119 unsigned int shift = (off & 7) * 4;
120 u32 con; 120 u32 con;
121 121
122 if (off < 8 && chip->chip.ngpio >= 8) 122 if (off < 8 && chip->chip.ngpio > 8)
123 reg -= 4; 123 reg -= 4;
124 124
125 if (s3c_gpio_is_cfg_special(cfg)) { 125 if (s3c_gpio_is_cfg_special(cfg)) {
diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c
index d71dd6d9ce5c..260fdc6ad685 100644
--- a/arch/arm/plat-s3c/gpio.c
+++ b/arch/arm/plat-s3c/gpio.c
@@ -16,7 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18 18
19#include <plat/gpio-core.h> 19#include <mach/gpio-core.h>
20 20
21#ifdef CONFIG_S3C_GPIO_TRACK 21#ifdef CONFIG_S3C_GPIO_TRACK
22struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; 22struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
@@ -140,6 +140,15 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
140 if (!gc->get) 140 if (!gc->get)
141 gc->get = s3c_gpiolib_get; 141 gc->get = s3c_gpiolib_get;
142 142
143#ifdef CONFIG_PM
144 if (chip->pm != NULL) {
145 if (!chip->pm->save || !chip->pm->resume)
146 printk(KERN_ERR "gpio: %s has missing PM functions\n",
147 gc->label);
148 } else
149 printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
150#endif
151
143 /* gpiochip_add() prints own failure message on error. */ 152 /* gpiochip_add() prints own failure message on error. */
144 ret = gpiochip_add(gc); 153 ret = gpiochip_add(gc);
145 if (ret >= 0) 154 if (ret >= 0)
diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h
index 43df2a404b0b..d847bd476b6c 100644
--- a/arch/arm/plat-s3c/include/plat/adc.h
+++ b/arch/arm/plat-s3c/include/plat/adc.h
@@ -19,10 +19,12 @@ struct s3c_adc_client;
19extern int s3c_adc_start(struct s3c_adc_client *client, 19extern int s3c_adc_start(struct s3c_adc_client *client,
20 unsigned int channel, unsigned int nr_samples); 20 unsigned int channel, unsigned int nr_samples);
21 21
22extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, 22extern struct s3c_adc_client *
23 void (*select)(unsigned selected), 23 s3c_adc_register(struct platform_device *pdev,
24 void (*conv)(unsigned d0, unsigned d1), 24 void (*select)(unsigned selected),
25 unsigned int is_ts); 25 void (*conv)(unsigned d0, unsigned d1,
26 unsigned *samples_left),
27 unsigned int is_ts);
26 28
27extern void s3c_adc_release(struct s3c_adc_client *client); 29extern void s3c_adc_release(struct s3c_adc_client *client);
28 30
diff --git a/arch/arm/plat-s3c/include/plat/clock.h b/arch/arm/plat-s3c/include/plat/clock.h
index a10622eed43a..d86af84b5b8c 100644
--- a/arch/arm/plat-s3c/include/plat/clock.h
+++ b/arch/arm/plat-s3c/include/plat/clock.h
@@ -50,6 +50,7 @@ extern struct clk clk_xtal;
50extern struct clk clk_ext; 50extern struct clk clk_ext;
51 51
52/* S3C64XX specific clocks */ 52/* S3C64XX specific clocks */
53extern struct clk clk_h2;
53extern struct clk clk_27m; 54extern struct clk clk_27m;
54extern struct clk clk_48m; 55extern struct clk clk_48m;
55 56
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h
index e62ae0fcfe56..be541cbba070 100644
--- a/arch/arm/plat-s3c/include/plat/cpu.h
+++ b/arch/arm/plat-s3c/include/plat/cpu.h
@@ -69,3 +69,6 @@ extern struct sysdev_class s3c2412_sysclass;
69extern struct sysdev_class s3c2440_sysclass; 69extern struct sysdev_class s3c2440_sysclass;
70extern struct sysdev_class s3c2442_sysclass; 70extern struct sysdev_class s3c2442_sysclass;
71extern struct sysdev_class s3c2443_sysclass; 71extern struct sysdev_class s3c2443_sysclass;
72extern struct sysdev_class s3c6410_sysclass;
73extern struct sysdev_class s3c64xx_sysclass;
74
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h
index 26f0cec3ac04..b5b9c4d46e9a 100644
--- a/arch/arm/plat-s3c/include/plat/devs.h
+++ b/arch/arm/plat-s3c/include/plat/devs.h
@@ -24,13 +24,16 @@ extern struct platform_device *s3c24xx_uart_src[];
24 24
25extern struct platform_device s3c_device_timer[]; 25extern struct platform_device s3c_device_timer[];
26 26
27extern struct platform_device s3c64xx_device_iis0;
28extern struct platform_device s3c64xx_device_iis1;
29extern struct platform_device s3c64xx_device_iisv4;
30
27extern struct platform_device s3c_device_fb; 31extern struct platform_device s3c_device_fb;
28extern struct platform_device s3c_device_usb; 32extern struct platform_device s3c_device_usb;
29extern struct platform_device s3c_device_lcd; 33extern struct platform_device s3c_device_lcd;
30extern struct platform_device s3c_device_wdt; 34extern struct platform_device s3c_device_wdt;
31extern struct platform_device s3c_device_i2c0; 35extern struct platform_device s3c_device_i2c0;
32extern struct platform_device s3c_device_i2c1; 36extern struct platform_device s3c_device_i2c1;
33extern struct platform_device s3c_device_iis;
34extern struct platform_device s3c_device_rtc; 37extern struct platform_device s3c_device_rtc;
35extern struct platform_device s3c_device_adc; 38extern struct platform_device s3c_device_adc;
36extern struct platform_device s3c_device_sdi; 39extern struct platform_device s3c_device_sdi;
@@ -45,6 +48,7 @@ extern struct platform_device s3c_device_spi1;
45extern struct platform_device s3c_device_nand; 48extern struct platform_device s3c_device_nand;
46 49
47extern struct platform_device s3c_device_usbgadget; 50extern struct platform_device s3c_device_usbgadget;
51extern struct platform_device s3c_device_usb_hsotg;
48 52
49/* s3c2440 specific devices */ 53/* s3c2440 specific devices */
50 54
diff --git a/arch/arm/plat-s3c/include/plat/dma-core.h b/arch/arm/plat-s3c/include/plat/dma-core.h
new file mode 100644
index 000000000000..32ff2a92cb3c
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/dma-core.h
@@ -0,0 +1,22 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Samsung S3C DMA core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
16
17extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
18
19/* the currently allocated channel information */
20extern struct s3c2410_dma_chan s3c2410_chans[];
21
22
diff --git a/arch/arm/plat-s3c/include/plat/dma.h b/arch/arm/plat-s3c/include/plat/dma.h
new file mode 100644
index 000000000000..34dba98f08e1
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/dma.h
@@ -0,0 +1,127 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13enum s3c2410_dma_buffresult {
14 S3C2410_RES_OK,
15 S3C2410_RES_ERR,
16 S3C2410_RES_ABORT
17};
18
19enum s3c2410_dmasrc {
20 S3C2410_DMASRC_HW, /* source is memory */
21 S3C2410_DMASRC_MEM /* source is hardware */
22};
23
24/* enum s3c2410_chan_op
25 *
26 * operation codes passed to the DMA code by the user, and also used
27 * to inform the current channel owner of any changes to the system state
28*/
29
30enum s3c2410_chan_op {
31 S3C2410_DMAOP_START,
32 S3C2410_DMAOP_STOP,
33 S3C2410_DMAOP_PAUSE,
34 S3C2410_DMAOP_RESUME,
35 S3C2410_DMAOP_FLUSH,
36 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
37 S3C2410_DMAOP_STARTED, /* indicate channel started */
38};
39
40struct s3c2410_dma_client {
41 char *name;
42};
43
44struct s3c2410_dma_chan;
45
46/* s3c2410_dma_cbfn_t
47 *
48 * buffer callback routine type
49*/
50
51typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
52 void *buf, int size,
53 enum s3c2410_dma_buffresult result);
54
55typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
56 enum s3c2410_chan_op );
57
58
59
60/* s3c2410_dma_request
61 *
62 * request a dma channel exclusivley
63*/
64
65extern int s3c2410_dma_request(unsigned int channel,
66 struct s3c2410_dma_client *, void *dev);
67
68
69/* s3c2410_dma_ctrl
70 *
71 * change the state of the dma channel
72*/
73
74extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
75
76/* s3c2410_dma_setflags
77 *
78 * set the channel's flags to a given state
79*/
80
81extern int s3c2410_dma_setflags(unsigned int channel,
82 unsigned int flags);
83
84/* s3c2410_dma_free
85 *
86 * free the dma channel (will also abort any outstanding operations)
87*/
88
89extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
90
91/* s3c2410_dma_enqueue
92 *
93 * place the given buffer onto the queue of operations for the channel.
94 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
95 * drained before the buffer is given to the DMA system.
96*/
97
98extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
99 dma_addr_t data, int size);
100
101/* s3c2410_dma_config
102 *
103 * configure the dma channel
104*/
105
106extern int s3c2410_dma_config(unsigned int channel, int xferunit);
107
108/* s3c2410_dma_devconfig
109 *
110 * configure the device we're talking to
111*/
112
113extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
114 unsigned long devaddr);
115
116/* s3c2410_dma_getposition
117 *
118 * get the position that the dma transfer is currently at
119*/
120
121extern int s3c2410_dma_getposition(unsigned int channel,
122 dma_addr_t *src, dma_addr_t *dest);
123
124extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
125extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
126
127
diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h
index 2fc60a580ac8..32af612767aa 100644
--- a/arch/arm/plat-s3c/include/plat/gpio-core.h
+++ b/arch/arm/plat-s3c/include/plat/gpio-core.h
@@ -20,6 +20,18 @@
20 * specific code. 20 * specific code.
21*/ 21*/
22 22
23struct s3c_gpio_chip;
24
25/**
26 * struct s3c_gpio_pm - power management (suspend/resume) information
27 * @save: Routine to save the state of the GPIO block
28 * @resume: Routine to resume the GPIO block.
29 */
30struct s3c_gpio_pm {
31 void (*save)(struct s3c_gpio_chip *chip);
32 void (*resume)(struct s3c_gpio_chip *chip);
33};
34
23struct s3c_gpio_cfg; 35struct s3c_gpio_cfg;
24 36
25/** 37/**
@@ -27,6 +39,7 @@ struct s3c_gpio_cfg;
27 * @chip: The chip structure to be exported via gpiolib. 39 * @chip: The chip structure to be exported via gpiolib.
28 * @base: The base pointer to the gpio configuration registers. 40 * @base: The base pointer to the gpio configuration registers.
29 * @config: special function and pull-resistor control information. 41 * @config: special function and pull-resistor control information.
42 * @pm_save: Save information for suspend/resume support.
30 * 43 *
31 * This wrapper provides the necessary information for the Samsung 44 * This wrapper provides the necessary information for the Samsung
32 * specific gpios being registered with gpiolib. 45 * specific gpios being registered with gpiolib.
@@ -34,7 +47,11 @@ struct s3c_gpio_cfg;
34struct s3c_gpio_chip { 47struct s3c_gpio_chip {
35 struct gpio_chip chip; 48 struct gpio_chip chip;
36 struct s3c_gpio_cfg *config; 49 struct s3c_gpio_cfg *config;
50 struct s3c_gpio_pm *pm;
37 void __iomem *base; 51 void __iomem *base;
52#ifdef CONFIG_PM
53 u32 pm_save[4];
54#endif
38}; 55};
39 56
40static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) 57static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
@@ -75,3 +92,16 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
75 92
76static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } 93static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
77#endif 94#endif
95
96#ifdef CONFIG_PM
97extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
98extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
99extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
100#define __gpio_pm(x) x
101#else
102#define s3c_gpio_pm_1bit NULL
103#define s3c_gpio_pm_2bit NULL
104#define s3c_gpio_pm_4bit NULL
105#define __gpio_pm(x) NULL
106
107#endif /* CONFIG_PM */
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h
index f4dcd14af059..18f958801e64 100644
--- a/arch/arm/plat-s3c/include/plat/nand.h
+++ b/arch/arm/plat-s3c/include/plat/nand.h
@@ -10,19 +10,26 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13/* struct s3c2410_nand_set 13/**
14 * struct s3c2410_nand_set - define a set of one or more nand chips
15 * @disable_ecc: Entirely disable ECC - Dangerous
16 * @flash_bbt: Openmoko u-boot can create a Bad Block Table
17 * Setting this flag will allow the kernel to
18 * look for it at boot time and also skip the NAND
19 * scan.
20 * @nr_chips: Number of chips in this set
21 * @nr_partitions: Number of partitions pointed to by @partitions
22 * @name: Name of set (optional)
23 * @nr_map: Map for low-layer logical to physical chip numbers (option)
24 * @partitions: The mtd partition list
14 * 25 *
15 * define an set of one or more nand chips registered with an unique mtd 26 * define a set of one or more nand chips registered with an unique mtd. Also
16 * 27 * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger
17 * nr_chips = number of chips in this set 28 * a warning at boot time.
18 * nr_partitions = number of partitions pointed to be partitoons (or zero) 29 */
19 * name = name of set (optional)
20 * nr_map = map for low-layer logical to physical chip numbers (option)
21 * partitions = mtd partition list
22*/
23
24struct s3c2410_nand_set { 30struct s3c2410_nand_set {
25 unsigned int disable_ecc : 1; 31 unsigned int disable_ecc:1;
32 unsigned int flash_bbt:1;
26 33
27 int nr_chips; 34 int nr_chips;
28 int nr_partitions; 35 int nr_partitions;
@@ -39,7 +46,7 @@ struct s3c2410_platform_nand {
39 int twrph0; /* active time for nWE/nOE */ 46 int twrph0; /* active time for nWE/nOE */
40 int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ 47 int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
41 48
42 unsigned int ignore_unset_ecc : 1; 49 unsigned int ignore_unset_ecc:1;
43 50
44 int nr_sets; 51 int nr_sets;
45 struct s3c2410_nand_set *sets; 52 struct s3c2410_nand_set *sets;
diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h
index 3779775133a9..7a797192fcf3 100644
--- a/arch/arm/plat-s3c/include/plat/pm.h
+++ b/arch/arm/plat-s3c/include/plat/pm.h
@@ -44,6 +44,8 @@ extern void (*pm_cpu_sleep)(void);
44 44
45extern unsigned long s3c_pm_flags; 45extern unsigned long s3c_pm_flags;
46 46
47extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */
48
47/* from sleep.S */ 49/* from sleep.S */
48 50
49extern int s3c_cpu_save(unsigned long *saveblk); 51extern int s3c_cpu_save(unsigned long *saveblk);
@@ -88,6 +90,7 @@ struct pm_uart_save {
88 u32 ufcon; 90 u32 ufcon;
89 u32 umcon; 91 u32 umcon;
90 u32 ubrdiv; 92 u32 ubrdiv;
93 u32 udivslot;
91}; 94};
92 95
93/* helper functions to save/restore lists of registers. */ 96/* helper functions to save/restore lists of registers. */
@@ -124,6 +127,18 @@ extern void s3c_pm_dbg(const char *msg, ...);
124#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) 127#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
125#endif 128#endif
126 129
130#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
131/**
132 * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
133 * @set: set bits for the state of the LEDs
134 * @clear: clear bits for the state of the LEDs.
135 */
136extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
137
138#else
139static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
140#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
141
127/* suspend memory checking */ 142/* suspend memory checking */
128 143
129#ifdef CONFIG_S3C2410_PM_CHECK 144#ifdef CONFIG_S3C2410_PM_CHECK
diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
index 487d7d2a7e1d..66af75a5cdd1 100644
--- a/arch/arm/plat-s3c/include/plat/regs-serial.h
+++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
@@ -189,6 +189,11 @@
189 189
190#define S3C2443_DIVSLOT (0x2C) 190#define S3C2443_DIVSLOT (0x2C)
191 191
192/* S3C64XX interrupt registers. */
193#define S3C64XX_UINTP 0x30
194#define S3C64XX_UINTSP 0x34
195#define S3C64XX_UINTM 0x38
196
192#ifndef __ASSEMBLY__ 197#ifndef __ASSEMBLY__
193 198
194/* struct s3c24xx_uart_clksrc 199/* struct s3c24xx_uart_clksrc
diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
new file mode 100644
index 000000000000..36a85f5000c8
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
@@ -0,0 +1,50 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device PHY registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, this is a seperate header file as some of the clock framework
16 * needs to touch this if the clk_48m is used as the USB OHCI or other
17 * peripheral source.
18*/
19
20#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
21#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
22
23/* S3C64XX_PA_USB_HSPHY */
24
25#define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
26
27#define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00)
28#define SRC_PHYPWR_OTG_DISABLE (1 << 4)
29#define SRC_PHYPWR_ANALOG_POWERDOWN (1 << 3)
30#define SRC_PHYPWR_FORCE_SUSPEND (1 << 1)
31
32#define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04)
33#define S3C_PHYCLK_MODE_USB11 (1 << 6)
34#define S3C_PHYCLK_EXT_OSC (1 << 5)
35#define S3C_PHYCLK_CLK_FORCE (1 << 4)
36#define S3C_PHYCLK_ID_PULL (1 << 2)
37#define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0)
38#define S3C_PHYCLK_CLKSEL_SHIFT (0)
39#define S3C_PHYCLK_CLKSEL_48M (0x0 << 0)
40#define S3C_PHYCLK_CLKSEL_12M (0x2 << 0)
41#define S3C_PHYCLK_CLKSEL_24M (0x3 << 0)
42
43#define S3C_RSTCON S3C_HSOTG_PHYREG(0x08)
44#define S3C_RSTCON_PHYCLK (1 << 2)
45#define S3C_RSTCON_HCLK (1 << 2)
46#define S3C_RSTCON_PHY (1 << 0)
47
48#define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20)
49
50#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
new file mode 100644
index 000000000000..8d18d9d4d148
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
@@ -0,0 +1,377 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device block registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H
16#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__
17
18#define S3C_HSOTG_REG(x) (x)
19
20#define S3C_GOTGCTL S3C_HSOTG_REG(0x000)
21#define S3C_GOTGCTL_BSESVLD (1 << 19)
22#define S3C_GOTGCTL_ASESVLD (1 << 18)
23#define S3C_GOTGCTL_DBNC_SHORT (1 << 17)
24#define S3C_GOTGCTL_CONID_B (1 << 16)
25#define S3C_GOTGCTL_DEVHNPEN (1 << 11)
26#define S3C_GOTGCTL_HSSETHNPEN (1 << 10)
27#define S3C_GOTGCTL_HNPREQ (1 << 9)
28#define S3C_GOTGCTL_HSTNEGSCS (1 << 8)
29#define S3C_GOTGCTL_SESREQ (1 << 1)
30#define S3C_GOTGCTL_SESREQSCS (1 << 0)
31
32#define S3C_GOTGINT S3C_HSOTG_REG(0x004)
33#define S3C_GOTGINT_DbnceDone (1 << 19)
34#define S3C_GOTGINT_ADevTOUTChg (1 << 18)
35#define S3C_GOTGINT_HstNegDet (1 << 17)
36#define S3C_GOTGINT_HstnegSucStsChng (1 << 9)
37#define S3C_GOTGINT_SesReqSucStsChng (1 << 8)
38#define S3C_GOTGINT_SesEndDet (1 << 2)
39
40#define S3C_GAHBCFG S3C_HSOTG_REG(0x008)
41#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8)
42#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7)
43#define S3C_GAHBCFG_DMAEn (1 << 5)
44#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1)
45#define S3C_GAHBCFG_HBstLen_SHIFT (1)
46#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1)
47#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1)
48#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1)
49#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1)
50#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1)
51#define S3C_GAHBCFG_GlblIntrEn (1 << 0)
52
53#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C)
54#define S3C_GUSBCFG_PHYLPClkSel (1 << 15)
55#define S3C_GUSBCFG_HNPCap (1 << 9)
56#define S3C_GUSBCFG_SRPCap (1 << 8)
57#define S3C_GUSBCFG_PHYIf16 (1 << 3)
58#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0)
59#define S3C_GUSBCFG_TOutCal_SHIFT (0)
60#define S3C_GUSBCFG_TOutCal_LIMIT (0x7)
61#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0)
62
63#define S3C_GRSTCTL S3C_HSOTG_REG(0x010)
64
65#define S3C_GRSTCTL_AHBIdle (1 << 31)
66#define S3C_GRSTCTL_DMAReq (1 << 30)
67#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6)
68#define S3C_GRSTCTL_TxFNum_SHIFT (6)
69#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f)
70#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6)
71#define S3C_GRSTCTL_TxFFlsh (1 << 5)
72#define S3C_GRSTCTL_RxFFlsh (1 << 4)
73#define S3C_GRSTCTL_INTknQFlsh (1 << 3)
74#define S3C_GRSTCTL_FrmCntrRst (1 << 2)
75#define S3C_GRSTCTL_HSftRst (1 << 1)
76#define S3C_GRSTCTL_CSftRst (1 << 0)
77
78#define S3C_GINTSTS S3C_HSOTG_REG(0x014)
79#define S3C_GINTMSK S3C_HSOTG_REG(0x018)
80
81#define S3C_GINTSTS_WkUpInt (1 << 31)
82#define S3C_GINTSTS_SessReqInt (1 << 30)
83#define S3C_GINTSTS_DisconnInt (1 << 29)
84#define S3C_GINTSTS_ConIDStsChng (1 << 28)
85#define S3C_GINTSTS_PTxFEmp (1 << 26)
86#define S3C_GINTSTS_HChInt (1 << 25)
87#define S3C_GINTSTS_PrtInt (1 << 24)
88#define S3C_GINTSTS_FetSusp (1 << 22)
89#define S3C_GINTSTS_incompIP (1 << 21)
90#define S3C_GINTSTS_IncomplSOIN (1 << 20)
91#define S3C_GINTSTS_OEPInt (1 << 19)
92#define S3C_GINTSTS_IEPInt (1 << 18)
93#define S3C_GINTSTS_EPMis (1 << 17)
94#define S3C_GINTSTS_EOPF (1 << 15)
95#define S3C_GINTSTS_ISOutDrop (1 << 14)
96#define S3C_GINTSTS_EnumDone (1 << 13)
97#define S3C_GINTSTS_USBRst (1 << 12)
98#define S3C_GINTSTS_USBSusp (1 << 11)
99#define S3C_GINTSTS_ErlySusp (1 << 10)
100#define S3C_GINTSTS_GOUTNakEff (1 << 7)
101#define S3C_GINTSTS_GINNakEff (1 << 6)
102#define S3C_GINTSTS_NPTxFEmp (1 << 5)
103#define S3C_GINTSTS_RxFLvl (1 << 4)
104#define S3C_GINTSTS_SOF (1 << 3)
105#define S3C_GINTSTS_OTGInt (1 << 2)
106#define S3C_GINTSTS_ModeMis (1 << 1)
107#define S3C_GINTSTS_CurMod_Host (1 << 0)
108
109#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C)
110#define S3C_GRXSTSP S3C_HSOTG_REG(0x020)
111
112#define S3C_GRXSTS_FN_MASK (0x7f << 25)
113#define S3C_GRXSTS_FN_SHIFT (25)
114
115#define S3C_GRXSTS_PktSts_MASK (0xf << 17)
116#define S3C_GRXSTS_PktSts_SHIFT (17)
117#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
118#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17)
119#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17)
120#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17)
121#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17)
122
123#define S3C_GRXSTS_DPID_MASK (0x3 << 15)
124#define S3C_GRXSTS_DPID_SHIFT (15)
125#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4)
126#define S3C_GRXSTS_ByteCnt_SHIFT (4)
127#define S3C_GRXSTS_EPNum_MASK (0xf << 0)
128#define S3C_GRXSTS_EPNum_SHIFT (0)
129
130#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024)
131
132#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028)
133
134#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
135#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16)
136#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
137#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
138#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
139#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
140#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
141#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
142
143#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C)
144
145#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
146#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24)
147
148#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
149#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
150#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
151
152#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
153#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
154#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
155
156
157#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100)
158
159#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4))
160
161#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
162#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16)
163#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
164#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
165#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
166
167#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
168#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0)
169
170/* Device mode registers */
171#define S3C_DCFG S3C_HSOTG_REG(0x800)
172
173#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18)
174#define S3C_DCFG_EPMisCnt_SHIFT (18)
175#define S3C_DCFG_EPMisCnt_LIMIT (0x1f)
176#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18)
177
178#define S3C_DCFG_PerFrInt_MASK (0x3 << 11)
179#define S3C_DCFG_PerFrInt_SHIFT (11)
180#define S3C_DCFG_PerFrInt_LIMIT (0x3)
181#define S3C_DCFG_PerFrInt(_x) ((_x) << 11)
182
183#define S3C_DCFG_DevAddr_MASK (0x7f << 4)
184#define S3C_DCFG_DevAddr_SHIFT (4)
185#define S3C_DCFG_DevAddr_LIMIT (0x7f)
186#define S3C_DCFG_DevAddr(_x) ((_x) << 4)
187
188#define S3C_DCFG_NZStsOUTHShk (1 << 2)
189
190#define S3C_DCFG_DevSpd_MASK (0x3 << 0)
191#define S3C_DCFG_DevSpd_SHIFT (0)
192#define S3C_DCFG_DevSpd_HS (0x0 << 0)
193#define S3C_DCFG_DevSpd_FS (0x1 << 0)
194#define S3C_DCFG_DevSpd_LS (0x2 << 0)
195#define S3C_DCFG_DevSpd_FS48 (0x3 << 0)
196
197#define S3C_DCTL S3C_HSOTG_REG(0x804)
198
199#define S3C_DCTL_PWROnPrgDone (1 << 11)
200#define S3C_DCTL_CGOUTNak (1 << 10)
201#define S3C_DCTL_SGOUTNak (1 << 9)
202#define S3C_DCTL_CGNPInNAK (1 << 8)
203#define S3C_DCTL_SGNPInNAK (1 << 7)
204#define S3C_DCTL_TstCtl_MASK (0x7 << 4)
205#define S3C_DCTL_TstCtl_SHIFT (4)
206#define S3C_DCTL_GOUTNakSts (1 << 3)
207#define S3C_DCTL_GNPINNakSts (1 << 2)
208#define S3C_DCTL_SftDiscon (1 << 1)
209#define S3C_DCTL_RmtWkUpSig (1 << 0)
210
211#define S3C_DSTS S3C_HSOTG_REG(0x808)
212
213#define S3C_DSTS_SOFFN_MASK (0x3fff << 8)
214#define S3C_DSTS_SOFFN_SHIFT (8)
215#define S3C_DSTS_SOFFN_LIMIT (0x3fff)
216#define S3C_DSTS_SOFFN(_x) ((_x) << 8)
217#define S3C_DSTS_ErraticErr (1 << 3)
218#define S3C_DSTS_EnumSpd_MASK (0x3 << 1)
219#define S3C_DSTS_EnumSpd_SHIFT (1)
220#define S3C_DSTS_EnumSpd_HS (0x0 << 1)
221#define S3C_DSTS_EnumSpd_FS (0x1 << 1)
222#define S3C_DSTS_EnumSpd_LS (0x2 << 1)
223#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1)
224
225#define S3C_DSTS_SuspSts (1 << 0)
226
227#define S3C_DIEPMSK S3C_HSOTG_REG(0x810)
228
229#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6)
230#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5)
231#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4)
232#define S3C_DIEPMSK_TimeOUTMsk (1 << 3)
233#define S3C_DIEPMSK_AHBErrMsk (1 << 2)
234#define S3C_DIEPMSK_EPDisbldMsk (1 << 1)
235#define S3C_DIEPMSK_XferComplMsk (1 << 0)
236
237#define S3C_DOEPMSK S3C_HSOTG_REG(0x814)
238
239#define S3C_DOEPMSK_Back2BackSetup (1 << 6)
240#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4)
241#define S3C_DOEPMSK_SetupMsk (1 << 3)
242#define S3C_DOEPMSK_AHBErrMsk (1 << 2)
243#define S3C_DOEPMSK_EPDisbldMsk (1 << 1)
244#define S3C_DOEPMSK_XferComplMsk (1 << 0)
245
246#define S3C_DAINT S3C_HSOTG_REG(0x818)
247#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C)
248
249#define S3C_DAINT_OutEP_SHIFT (16)
250#define S3C_DAINT_OutEP(x) (1 << ((x) + 16))
251#define S3C_DAINT_InEP(x) (1 << (x))
252
253#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820)
254#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824)
255#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830)
256#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834)
257
258#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828)
259#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C)
260
261#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900)
262#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00)
263#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20))
264#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20))
265
266/* EP0 specialness:
267 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
268 * bits[25..22] - should always be zero, this isn't a periodic endpoint
269 * bits[10..0] - MPS setting differenct for EP0
270*/
271#define S3C_D0EPCTL_MPS_MASK (0x3 << 0)
272#define S3C_D0EPCTL_MPS_SHIFT (0)
273#define S3C_D0EPCTL_MPS_64 (0x0 << 0)
274#define S3C_D0EPCTL_MPS_32 (0x1 << 0)
275#define S3C_D0EPCTL_MPS_16 (0x2 << 0)
276#define S3C_D0EPCTL_MPS_8 (0x3 << 0)
277
278#define S3C_DxEPCTL_EPEna (1 << 31)
279#define S3C_DxEPCTL_EPDis (1 << 30)
280#define S3C_DxEPCTL_SetD1PID (1 << 29)
281#define S3C_DxEPCTL_SetOddFr (1 << 29)
282#define S3C_DxEPCTL_SetD0PID (1 << 28)
283#define S3C_DxEPCTL_SetEvenFr (1 << 28)
284#define S3C_DxEPCTL_SNAK (1 << 27)
285#define S3C_DxEPCTL_CNAK (1 << 26)
286#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22)
287#define S3C_DxEPCTL_TxFNum_SHIFT (22)
288#define S3C_DxEPCTL_TxFNum_LIMIT (0xf)
289#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22)
290
291#define S3C_DxEPCTL_Stall (1 << 21)
292#define S3C_DxEPCTL_Snp (1 << 20)
293#define S3C_DxEPCTL_EPType_MASK (0x3 << 18)
294#define S3C_DxEPCTL_EPType_SHIFT (18)
295#define S3C_DxEPCTL_EPType_Control (0x0 << 18)
296#define S3C_DxEPCTL_EPType_Iso (0x1 << 18)
297#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18)
298#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18)
299
300#define S3C_DxEPCTL_NAKsts (1 << 17)
301#define S3C_DxEPCTL_DPID (1 << 16)
302#define S3C_DxEPCTL_EOFrNum (1 << 16)
303#define S3C_DxEPCTL_USBActEp (1 << 15)
304#define S3C_DxEPCTL_NextEp_MASK (0xf << 11)
305#define S3C_DxEPCTL_NextEp_SHIFT (11)
306#define S3C_DxEPCTL_NextEp_LIMIT (0xf)
307#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11)
308
309#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0)
310#define S3C_DxEPCTL_MPS_SHIFT (0)
311#define S3C_DxEPCTL_MPS_LIMIT (0x7ff)
312#define S3C_DxEPCTL_MPS(_x) ((_x) << 0)
313
314#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20))
315#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20))
316
317#define S3C_DxEPINT_INEPNakEff (1 << 6)
318#define S3C_DxEPINT_Back2BackSetup (1 << 6)
319#define S3C_DxEPINT_INTknEPMis (1 << 5)
320#define S3C_DxEPINT_INTknTXFEmp (1 << 4)
321#define S3C_DxEPINT_OUTTknEPdis (1 << 4)
322#define S3C_DxEPINT_Timeout (1 << 3)
323#define S3C_DxEPINT_Setup (1 << 3)
324#define S3C_DxEPINT_AHBErr (1 << 2)
325#define S3C_DxEPINT_EPDisbld (1 << 1)
326#define S3C_DxEPINT_XferCompl (1 << 0)
327
328#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910)
329
330#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
331#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19)
332#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3)
333#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
334
335#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0)
336#define S3C_DIEPTSIZ0_XferSize_SHIFT (0)
337#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f)
338#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0)
339
340
341#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10)
342#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
343#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29)
344#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3)
345#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
346
347#define S3C_DOEPTSIZ0_PktCnt (1 << 19)
348#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0)
349#define S3C_DOEPTSIZ0_XferSize_SHIFT (0)
350
351#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20))
352#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20))
353
354#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29)
355#define S3C_DxEPTSIZ_MC_SHIFT (29)
356#define S3C_DxEPTSIZ_MC_LIMIT (0x3)
357#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29)
358
359#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
360#define S3C_DxEPTSIZ_PktCnt_SHIFT (19)
361#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
362#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff)
363#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19)
364
365#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
366#define S3C_DxEPTSIZ_XferSize_SHIFT (0)
367#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
368#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff)
369#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0)
370
371
372#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
373#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
374
375#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
376
377#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h
index c4ca3920ca4b..f615308ccdfb 100644
--- a/arch/arm/plat-s3c/include/plat/sdhci.h
+++ b/arch/arm/plat-s3c/include/plat/sdhci.h
@@ -67,12 +67,52 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
67 67
68/* Helper function availablity */ 68/* Helper function availablity */
69 69
70extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
71extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
72
73/* S3C6400 SDHCI setup */
74
75#ifdef CONFIG_S3C6400_SETUP_SDHCI
76extern char *s3c6400_hsmmc_clksrcs[4];
77
78#ifdef CONFIG_S3C_DEV_HSMMC
79extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
80 void __iomem *r,
81 struct mmc_ios *ios,
82 struct mmc_card *card);
83
84static inline void s3c6400_default_sdhci0(void)
85{
86 s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
87 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
88 s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
89}
90
91#else
92static inline void s3c6400_default_sdhci0(void) { }
93#endif /* CONFIG_S3C_DEV_HSMMC */
94
95#ifdef CONFIG_S3C_DEV_HSMMC1
96static inline void s3c6400_default_sdhci1(void)
97{
98 s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
99 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
100 s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
101}
102#else
103static inline void s3c6400_default_sdhci1(void) { }
104#endif /* CONFIG_S3C_DEV_HSMMC1 */
105
106#else
107static inline void s3c6400_default_sdhci0(void) { }
108static inline void s3c6400_default_sdhci1(void) { }
109#endif /* CONFIG_S3C6400_SETUP_SDHCI */
110
111/* S3C6410 SDHCI setup */
112
70#ifdef CONFIG_S3C6410_SETUP_SDHCI 113#ifdef CONFIG_S3C6410_SETUP_SDHCI
71extern char *s3c6410_hsmmc_clksrcs[4]; 114extern char *s3c6410_hsmmc_clksrcs[4];
72 115
73extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
74extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
75
76extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, 116extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
77 void __iomem *r, 117 void __iomem *r,
78 struct mmc_ios *ios, 118 struct mmc_ios *ios,
@@ -82,7 +122,7 @@ extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
82static inline void s3c6410_default_sdhci0(void) 122static inline void s3c6410_default_sdhci0(void)
83{ 123{
84 s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs; 124 s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
85 s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio; 125 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
86 s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; 126 s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
87} 127}
88#else 128#else
@@ -93,7 +133,7 @@ static inline void s3c6410_default_sdhci0(void) { }
93static inline void s3c6410_default_sdhci1(void) 133static inline void s3c6410_default_sdhci1(void)
94{ 134{
95 s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs; 135 s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
96 s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio; 136 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
97 s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; 137 s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
98} 138}
99#else 139#else
diff --git a/arch/arm/plat-s3c/include/plat/udc-hs.h b/arch/arm/plat-s3c/include/plat/udc-hs.h
new file mode 100644
index 000000000000..dd04db043109
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/udc-hs.h
@@ -0,0 +1,29 @@
1/* arch/arm/plat-s3c/include/plat/udc-hs.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C USB2.0 High-speed / OtG platform information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15enum s3c_hostg_dmamode {
16 S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */
17 S3C_HSOTG_DMA_ONLY, /* always use DMA */
18 S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */
19};
20
21/**
22 * struct s3c_hsotg_plat - platform data for high-speed otg/udc
23 * @dma: Whether to use DMA or not.
24 * @is_osc: The clock source is an oscillator, not a crystal
25 */
26struct s3c_hsotg_plat {
27 enum s3c_hostg_dmamode dma;
28 unsigned int is_osc : 1;
29};
diff --git a/arch/arm/plat-s3c/include/plat/watchdog-reset.h b/arch/arm/plat-s3c/include/plat/watchdog-reset.h
new file mode 100644
index 000000000000..54b762acb5a0
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/watchdog-reset.h
@@ -0,0 +1,49 @@
1/* arch/arm/plat-s3c/include/plat/watchdog-reset.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - System define for arch_reset() function
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <plat/regs-watchdog.h>
14#include <mach/map.h>
15
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/io.h>
19
20static inline void arch_wdt_reset(void)
21{
22 struct clk *wdtclk;
23
24 printk("arch_reset: attempting watchdog reset\n");
25
26 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
27
28 wdtclk = clk_get(NULL, "watchdog");
29 if (!IS_ERR(wdtclk)) {
30 clk_enable(wdtclk);
31 } else
32 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
33
34 /* put initial values into count and data */
35 __raw_writel(0x80, S3C2410_WTCNT);
36 __raw_writel(0x80, S3C2410_WTDAT);
37
38 /* set the watchdog to go and reset... */
39 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
40 S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
41
42 /* wait for reset to assert... */
43 mdelay(500);
44
45 printk(KERN_ERR "Watchdog reset failed to assert reset\n");
46
47 /* delay to allow the serial port to show the message */
48 mdelay(50);
49}
diff --git a/arch/arm/plat-s3c/pm-gpio.c b/arch/arm/plat-s3c/pm-gpio.c
new file mode 100644
index 000000000000..cfd326a8b693
--- /dev/null
+++ b/arch/arm/plat-s3c/pm-gpio.c
@@ -0,0 +1,380 @@
1
2/* linux/arch/arm/plat-s3c/pm-gpio.c
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * S3C series GPIO PM code
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/kernel.h>
17#include <linux/sysdev.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21
22#include <mach/gpio-core.h>
23#include <plat/pm.h>
24
25/* PM GPIO helpers */
26
27#define OFFS_CON (0x00)
28#define OFFS_DAT (0x04)
29#define OFFS_UP (0x08)
30
31static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
32{
33 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
34 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
35}
36
37static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
38{
39 void __iomem *base = chip->base;
40 u32 old_gpcon = __raw_readl(base + OFFS_CON);
41 u32 old_gpdat = __raw_readl(base + OFFS_DAT);
42 u32 gps_gpcon = chip->pm_save[0];
43 u32 gps_gpdat = chip->pm_save[1];
44 u32 gpcon;
45
46 /* GPACON only has one bit per control / data and no PULLUPs.
47 * GPACON[x] = 0 => Output, 1 => SFN */
48
49 /* first set all SFN bits to SFN */
50
51 gpcon = old_gpcon | gps_gpcon;
52 __raw_writel(gpcon, base + OFFS_CON);
53
54 /* now set all the other bits */
55
56 __raw_writel(gps_gpdat, base + OFFS_DAT);
57 __raw_writel(gps_gpcon, base + OFFS_CON);
58
59 S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
60 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
61}
62
63struct s3c_gpio_pm s3c_gpio_pm_1bit = {
64 .save = s3c_gpio_pm_1bit_save,
65 .resume = s3c_gpio_pm_1bit_resume,
66};
67
68static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
69{
70 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
71 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
72 chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
73}
74
75/* Test whether the given masked+shifted bits of an GPIO configuration
76 * are one of the SFN (special function) modes. */
77
78static inline int is_sfn(unsigned long con)
79{
80 return con >= 2;
81}
82
83/* Test if the given masked+shifted GPIO configuration is an input */
84
85static inline int is_in(unsigned long con)
86{
87 return con == 0;
88}
89
90/* Test if the given masked+shifted GPIO configuration is an output */
91
92static inline int is_out(unsigned long con)
93{
94 return con == 1;
95}
96
97/**
98 * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
99 * @chip: The chip information to resume.
100 *
101 * Restore one of the GPIO banks that was saved during suspend. This is
102 * not as simple as once thought, due to the possibility of glitches
103 * from the order that the CON and DAT registers are set in.
104 *
105 * The three states the pin can be are {IN,OUT,SFN} which gives us 9
106 * combinations of changes to check. Three of these, if the pin stays
107 * in the same configuration can be discounted. This leaves us with
108 * the following:
109 *
110 * { IN => OUT } Change DAT first
111 * { IN => SFN } Change CON first
112 * { OUT => SFN } Change CON first, so new data will not glitch
113 * { OUT => IN } Change CON first, so new data will not glitch
114 * { SFN => IN } Change CON first
115 * { SFN => OUT } Change DAT first, so new data will not glitch [1]
116 *
117 * We do not currently deal with the UP registers as these control
118 * weak resistors, so a small delay in change should not need to bring
119 * these into the calculations.
120 *
121 * [1] this assumes that writing to a pin DAT whilst in SFN will set the
122 * state for when it is next output.
123 */
124static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
125{
126 void __iomem *base = chip->base;
127 u32 old_gpcon = __raw_readl(base + OFFS_CON);
128 u32 old_gpdat = __raw_readl(base + OFFS_DAT);
129 u32 gps_gpcon = chip->pm_save[0];
130 u32 gps_gpdat = chip->pm_save[1];
131 u32 gpcon, old, new, mask;
132 u32 change_mask = 0x0;
133 int nr;
134
135 /* restore GPIO pull-up settings */
136 __raw_writel(chip->pm_save[2], base + OFFS_UP);
137
138 /* Create a change_mask of all the items that need to have
139 * their CON value changed before their DAT value, so that
140 * we minimise the work between the two settings.
141 */
142
143 for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
144 old = (old_gpcon & mask) >> nr;
145 new = (gps_gpcon & mask) >> nr;
146
147 /* If there is no change, then skip */
148
149 if (old == new)
150 continue;
151
152 /* If both are special function, then skip */
153
154 if (is_sfn(old) && is_sfn(new))
155 continue;
156
157 /* Change is IN => OUT, do not change now */
158
159 if (is_in(old) && is_out(new))
160 continue;
161
162 /* Change is SFN => OUT, do not change now */
163
164 if (is_sfn(old) && is_out(new))
165 continue;
166
167 /* We should now be at the case of IN=>SFN,
168 * OUT=>SFN, OUT=>IN, SFN=>IN. */
169
170 change_mask |= mask;
171 }
172
173
174 /* Write the new CON settings */
175
176 gpcon = old_gpcon & ~change_mask;
177 gpcon |= gps_gpcon & change_mask;
178
179 __raw_writel(gpcon, base + OFFS_CON);
180
181 /* Now change any items that require DAT,CON */
182
183 __raw_writel(gps_gpdat, base + OFFS_DAT);
184 __raw_writel(gps_gpcon, base + OFFS_CON);
185
186 S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
187 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
188}
189
190struct s3c_gpio_pm s3c_gpio_pm_2bit = {
191 .save = s3c_gpio_pm_2bit_save,
192 .resume = s3c_gpio_pm_2bit_resume,
193};
194
195#ifdef CONFIG_ARCH_S3C64XX
196static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
197{
198 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
199 chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
200 chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
201
202 if (chip->chip.ngpio > 8)
203 chip->pm_save[0] = __raw_readl(chip->base - 4);
204}
205
206static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
207{
208 u32 old, new, mask;
209 u32 change_mask = 0x0;
210 int nr;
211
212 for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
213 old = (old_gpcon & mask) >> nr;
214 new = (gps_gpcon & mask) >> nr;
215
216 /* If there is no change, then skip */
217
218 if (old == new)
219 continue;
220
221 /* If both are special function, then skip */
222
223 if (is_sfn(old) && is_sfn(new))
224 continue;
225
226 /* Change is IN => OUT, do not change now */
227
228 if (is_in(old) && is_out(new))
229 continue;
230
231 /* Change is SFN => OUT, do not change now */
232
233 if (is_sfn(old) && is_out(new))
234 continue;
235
236 /* We should now be at the case of IN=>SFN,
237 * OUT=>SFN, OUT=>IN, SFN=>IN. */
238
239 change_mask |= mask;
240 }
241
242 return change_mask;
243}
244
245static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
246{
247 void __iomem *con = chip->base + (index * 4);
248 u32 old_gpcon = __raw_readl(con);
249 u32 gps_gpcon = chip->pm_save[index + 1];
250 u32 gpcon, mask;
251
252 mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
253
254 gpcon = old_gpcon & ~mask;
255 gpcon |= gps_gpcon & mask;
256
257 __raw_writel(gpcon, con);
258}
259
260static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
261{
262 void __iomem *base = chip->base;
263 u32 old_gpcon[2];
264 u32 old_gpdat = __raw_readl(base + OFFS_DAT);
265 u32 gps_gpdat = chip->pm_save[2];
266
267 /* First, modify the CON settings */
268
269 old_gpcon[0] = 0;
270 old_gpcon[1] = __raw_readl(base + OFFS_CON);
271
272 s3c_gpio_pm_4bit_con(chip, 0);
273 if (chip->chip.ngpio > 8) {
274 old_gpcon[0] = __raw_readl(base - 4);
275 s3c_gpio_pm_4bit_con(chip, -1);
276 }
277
278 /* Now change the configurations that require DAT,CON */
279
280 __raw_writel(chip->pm_save[2], base + OFFS_DAT);
281 __raw_writel(chip->pm_save[1], base + OFFS_CON);
282 if (chip->chip.ngpio > 8)
283 __raw_writel(chip->pm_save[0], base - 4);
284
285 __raw_writel(chip->pm_save[2], base + OFFS_DAT);
286 __raw_writel(chip->pm_save[3], base + OFFS_UP);
287
288 if (chip->chip.ngpio > 8) {
289 S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
290 chip->chip.label, old_gpcon[0], old_gpcon[1],
291 __raw_readl(base - 4),
292 __raw_readl(base + OFFS_CON),
293 old_gpdat, gps_gpdat);
294 } else
295 S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
296 chip->chip.label, old_gpcon[1],
297 __raw_readl(base + OFFS_CON),
298 old_gpdat, gps_gpdat);
299}
300
301struct s3c_gpio_pm s3c_gpio_pm_4bit = {
302 .save = s3c_gpio_pm_4bit_save,
303 .resume = s3c_gpio_pm_4bit_resume,
304};
305#endif /* CONFIG_ARCH_S3C64XX */
306
307/**
308 * s3c_pm_save_gpio() - save gpio chip data for suspend
309 * @ourchip: The chip for suspend.
310 */
311static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
312{
313 struct s3c_gpio_pm *pm = ourchip->pm;
314
315 if (pm == NULL || pm->save == NULL)
316 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
317 else
318 pm->save(ourchip);
319}
320
321/**
322 * s3c_pm_save_gpios() - Save the state of the GPIO banks.
323 *
324 * For all the GPIO banks, save the state of each one ready for going
325 * into a suspend mode.
326 */
327void s3c_pm_save_gpios(void)
328{
329 struct s3c_gpio_chip *ourchip;
330 unsigned int gpio_nr;
331
332 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
333 ourchip = s3c_gpiolib_getchip(gpio_nr);
334 if (!ourchip)
335 continue;
336
337 s3c_pm_save_gpio(ourchip);
338
339 S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
340 ourchip->chip.label,
341 ourchip->pm_save[0],
342 ourchip->pm_save[1],
343 ourchip->pm_save[2],
344 ourchip->pm_save[3]);
345
346 gpio_nr += ourchip->chip.ngpio;
347 gpio_nr += CONFIG_S3C_GPIO_SPACE;
348 }
349}
350
351/**
352 * s3c_pm_resume_gpio() - restore gpio chip data after suspend
353 * @ourchip: The suspended chip.
354 */
355static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
356{
357 struct s3c_gpio_pm *pm = ourchip->pm;
358
359 if (pm == NULL || pm->resume == NULL)
360 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
361 else
362 pm->resume(ourchip);
363}
364
365void s3c_pm_restore_gpios(void)
366{
367 struct s3c_gpio_chip *ourchip;
368 unsigned int gpio_nr;
369
370 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
371 ourchip = s3c_gpiolib_getchip(gpio_nr);
372 if (!ourchip)
373 continue;
374
375 s3c_pm_resume_gpio(ourchip);
376
377 gpio_nr += ourchip->chip.ngpio;
378 gpio_nr += CONFIG_S3C_GPIO_SPACE;
379 }
380}
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c
index 061182ca66e3..8d97db2c7a0d 100644
--- a/arch/arm/plat-s3c/pm.c
+++ b/arch/arm/plat-s3c/pm.c
@@ -21,11 +21,10 @@
21 21
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/map.h>
24 25
25#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
26#include <mach/regs-clock.h> 27#include <mach/regs-clock.h>
27#include <mach/regs-gpio.h>
28#include <mach/regs-mem.h>
29#include <mach/regs-irq.h> 28#include <mach/regs-irq.h>
30#include <asm/irq.h> 29#include <asm/irq.h>
31 30
@@ -70,6 +69,8 @@ static inline void s3c_pm_debug_init(void)
70 69
71/* Save the UART configurations if we are configured for debug. */ 70/* Save the UART configurations if we are configured for debug. */
72 71
72unsigned char pm_uart_udivslot;
73
73#ifdef CONFIG_S3C2410_PM_DEBUG 74#ifdef CONFIG_S3C2410_PM_DEBUG
74 75
75struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; 76struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
@@ -83,6 +84,12 @@ static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
83 save->ufcon = __raw_readl(regs + S3C2410_UFCON); 84 save->ufcon = __raw_readl(regs + S3C2410_UFCON);
84 save->umcon = __raw_readl(regs + S3C2410_UMCON); 85 save->umcon = __raw_readl(regs + S3C2410_UMCON);
85 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); 86 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
87
88 if (pm_uart_udivslot)
89 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
90
91 S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
92 uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
86} 93}
87 94
88static void s3c_pm_save_uarts(void) 95static void s3c_pm_save_uarts(void)
@@ -98,11 +105,16 @@ static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
98{ 105{
99 void __iomem *regs = S3C_VA_UARTx(uart); 106 void __iomem *regs = S3C_VA_UARTx(uart);
100 107
108 s3c_pm_arch_update_uart(regs, save);
109
101 __raw_writel(save->ulcon, regs + S3C2410_ULCON); 110 __raw_writel(save->ulcon, regs + S3C2410_ULCON);
102 __raw_writel(save->ucon, regs + S3C2410_UCON); 111 __raw_writel(save->ucon, regs + S3C2410_UCON);
103 __raw_writel(save->ufcon, regs + S3C2410_UFCON); 112 __raw_writel(save->ufcon, regs + S3C2410_UFCON);
104 __raw_writel(save->umcon, regs + S3C2410_UMCON); 113 __raw_writel(save->umcon, regs + S3C2410_UMCON);
105 __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); 114 __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
115
116 if (pm_uart_udivslot)
117 __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
106} 118}
107 119
108static void s3c_pm_restore_uarts(void) 120static void s3c_pm_restore_uarts(void)
@@ -313,6 +325,9 @@ static int s3c_pm_enter(suspend_state_t state)
313 325
314 S3C_PMDBG("%s: post sleep, preparing to return\n", __func__); 326 S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
315 327
328 /* LEDs should now be 1110 */
329 s3c_pm_debug_smdkled(1 << 1, 0);
330
316 s3c_pm_check_restore(); 331 s3c_pm_check_restore();
317 332
318 /* ok, let's return from sleep */ 333 /* ok, let's return from sleep */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-19 03:18:47 -0500