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-rw-r--r--arch/arm/plat-s3c/Makefile3
-rw-r--r--arch/arm/plat-s3c/include/plat/debug-macro.S75
-rw-r--r--arch/arm/plat-s3c/include/plat/map.h40
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-adc.h60
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-serial.h232
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-timer.h115
-rw-r--r--arch/arm/plat-s3c/include/plat/uncompress.h155
7 files changed, 680 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
new file mode 100644
index 000000000000..f03d7b35ba37
--- /dev/null
+++ b/arch/arm/plat-s3c/Makefile
@@ -0,0 +1,3 @@
1# dummy makefile, currently just including asm/arm/plat-s3c/include/plat
2
3obj-n := dummy.o
diff --git a/arch/arm/plat-s3c/include/plat/debug-macro.S b/arch/arm/plat-s3c/include/plat/debug-macro.S
new file mode 100644
index 000000000000..4aa7e2e6c001
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/debug-macro.S
@@ -0,0 +1,75 @@
1/* linux/include/asm-arm/plat-s3c/debug-macro.S
2 *
3 * Copyright 2005, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <plat/regs-serial.h>
13
14/* The S3C2440 implementations are used by default as they are the
15 * most widely re-used */
16
17 .macro fifo_level_s3c2440 rd, rx
18 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
19 and \rd, \rd, #S3C2440_UFSTAT_TXMASK
20 .endm
21
22#ifndef fifo_level
23#define fifo_level fifo_level_s3c2410
24#endif
25
26 .macro fifo_full_s3c2440 rd, rx
27 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
28 tst \rd, #S3C2440_UFSTAT_TXFULL
29 .endm
30
31#ifndef fifo_full
32#define fifo_full fifo_full_s3c2440
33#endif
34
35 .macro senduart,rd,rx
36 strb \rd, [\rx, # S3C2410_UTXH ]
37 .endm
38
39 .macro busyuart, rd, rx
40 ldr \rd, [ \rx, # S3C2410_UFCON ]
41 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
42 beq 1001f @
43 @ FIFO enabled...
441003:
45 fifo_full \rd, \rx
46 bne 1003b
47 b 1002f
48
491001:
50 @ busy waiting for non fifo
51 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
52 tst \rd, #S3C2410_UTRSTAT_TXFE
53 beq 1001b
54
551002: @ exit busyuart
56 .endm
57
58 .macro waituart,rd,rx
59 ldr \rd, [ \rx, # S3C2410_UFCON ]
60 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
61 beq 1001f @
62 @ FIFO enabled...
631003:
64 fifo_level \rd, \rx
65 teq \rd, #0
66 bne 1003b
67 b 1002f
681001:
69 @ idle waiting for non fifo
70 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
71 tst \rd, #S3C2410_UTRSTAT_TXFE
72 beq 1001b
73
741002: @ exit busyuart
75 .endm
diff --git a/arch/arm/plat-s3c/include/plat/map.h b/arch/arm/plat-s3c/include/plat/map.h
new file mode 100644
index 000000000000..b84289d32a54
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/map.h
@@ -0,0 +1,40 @@
1/* linux/include/asm-arm/plat-s3c/map.h
2 *
3 * Copyright 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - Memory map definitions (virtual addresses)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_PLAT_MAP_H
15#define __ASM_PLAT_MAP_H __FILE__
16
17/* Fit all our registers in at 0xF4000000 upwards, trying to use as
18 * little of the VA space as possible so vmalloc and friends have a
19 * better chance of getting memory.
20 *
21 * we try to ensure stuff like the IRQ registers are available for
22 * an single MOVS instruction (ie, only 8 bits of set data)
23 */
24
25#define S3C_ADDR_BASE (0xF4000000)
26
27#ifndef __ASSEMBLY__
28#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
29#else
30#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
31#endif
32
33#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
34#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
35#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */
36#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
37#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
38#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
39
40#endif /* __ASM_PLAT_MAP_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-adc.h b/arch/arm/plat-s3c/include/plat/regs-adc.h
new file mode 100644
index 000000000000..4323cccc86cd
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-adc.h
@@ -0,0 +1,60 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-adc.h
2 *
3 * Copyright (c) 2004 Shannon Holland <holland@loser.net>
4 *
5 * This program is free software; yosu can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 ADC registers
10*/
11
12#ifndef __ASM_ARCH_REGS_ADC_H
13#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
14
15#define S3C2410_ADCREG(x) (x)
16
17#define S3C2410_ADCCON S3C2410_ADCREG(0x00)
18#define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
19#define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
20#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
21#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
22
23
24/* ADCCON Register Bits */
25#define S3C2410_ADCCON_ECFLG (1<<15)
26#define S3C2410_ADCCON_PRSCEN (1<<14)
27#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
28#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
29#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
30#define S3C2410_ADCCON_MUXMASK (0x7<<3)
31#define S3C2410_ADCCON_STDBM (1<<2)
32#define S3C2410_ADCCON_READ_START (1<<1)
33#define S3C2410_ADCCON_ENABLE_START (1<<0)
34#define S3C2410_ADCCON_STARTMASK (0x3<<0)
35
36
37/* ADCTSC Register Bits */
38#define S3C2410_ADCTSC_YM_SEN (1<<7)
39#define S3C2410_ADCTSC_YP_SEN (1<<6)
40#define S3C2410_ADCTSC_XM_SEN (1<<5)
41#define S3C2410_ADCTSC_XP_SEN (1<<4)
42#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
43#define S3C2410_ADCTSC_AUTO_PST (1<<2)
44#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
45
46/* ADCDAT0 Bits */
47#define S3C2410_ADCDAT0_UPDOWN (1<<15)
48#define S3C2410_ADCDAT0_AUTO_PST (1<<14)
49#define S3C2410_ADCDAT0_XY_PST (0x3<<12)
50#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
51
52/* ADCDAT1 Bits */
53#define S3C2410_ADCDAT1_UPDOWN (1<<15)
54#define S3C2410_ADCDAT1_AUTO_PST (1<<14)
55#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
56#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
57
58#endif /* __ASM_ARCH_REGS_ADC_H */
59
60
diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
new file mode 100644
index 000000000000..a0daa647b92c
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
@@ -0,0 +1,232 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-serial.h
2 *
3 * From linux/include/asm-arm/hardware/serial_s3c2410.h
4 *
5 * Internal header file for Samsung S3C2410 serial ports (UART0-2)
6 *
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 *
9 * Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
10 *
11 * Adapted from:
12 *
13 * Internal header file for MX1ADS serial ports (UART1 & 2)
14 *
15 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30*/
31
32#ifndef __ASM_ARM_REGS_SERIAL_H
33#define __ASM_ARM_REGS_SERIAL_H
34
35#define S3C24XX_VA_UART0 (S3C_VA_UART)
36#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
37#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
38#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
39
40#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
41#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
42#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
43#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
44
45#define S3C2410_URXH (0x24)
46#define S3C2410_UTXH (0x20)
47#define S3C2410_ULCON (0x00)
48#define S3C2410_UCON (0x04)
49#define S3C2410_UFCON (0x08)
50#define S3C2410_UMCON (0x0C)
51#define S3C2410_UBRDIV (0x28)
52#define S3C2410_UTRSTAT (0x10)
53#define S3C2410_UERSTAT (0x14)
54#define S3C2410_UFSTAT (0x18)
55#define S3C2410_UMSTAT (0x1C)
56
57#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
58
59#define S3C2410_LCON_CS5 (0x0)
60#define S3C2410_LCON_CS6 (0x1)
61#define S3C2410_LCON_CS7 (0x2)
62#define S3C2410_LCON_CS8 (0x3)
63#define S3C2410_LCON_CSMASK (0x3)
64
65#define S3C2410_LCON_PNONE (0x0)
66#define S3C2410_LCON_PEVEN (0x5 << 3)
67#define S3C2410_LCON_PODD (0x4 << 3)
68#define S3C2410_LCON_PMASK (0x7 << 3)
69
70#define S3C2410_LCON_STOPB (1<<2)
71#define S3C2410_LCON_IRM (1<<6)
72
73#define S3C2440_UCON_CLKMASK (3<<10)
74#define S3C2440_UCON_PCLK (0<<10)
75#define S3C2440_UCON_UCLK (1<<10)
76#define S3C2440_UCON_PCLK2 (2<<10)
77#define S3C2440_UCON_FCLK (3<<10)
78#define S3C2443_UCON_EPLL (3<<10)
79
80#define S3C2440_UCON2_FCLK_EN (1<<15)
81#define S3C2440_UCON0_DIVMASK (15 << 12)
82#define S3C2440_UCON1_DIVMASK (15 << 12)
83#define S3C2440_UCON2_DIVMASK (7 << 12)
84#define S3C2440_UCON_DIVSHIFT (12)
85
86#define S3C2412_UCON_CLKMASK (3<<10)
87#define S3C2412_UCON_UCLK (1<<10)
88#define S3C2412_UCON_USYSCLK (3<<10)
89#define S3C2412_UCON_PCLK (0<<10)
90#define S3C2412_UCON_PCLK2 (2<<10)
91
92#define S3C2410_UCON_UCLK (1<<10)
93#define S3C2410_UCON_SBREAK (1<<4)
94
95#define S3C2410_UCON_TXILEVEL (1<<9)
96#define S3C2410_UCON_RXILEVEL (1<<8)
97#define S3C2410_UCON_TXIRQMODE (1<<2)
98#define S3C2410_UCON_RXIRQMODE (1<<0)
99#define S3C2410_UCON_RXFIFO_TOI (1<<7)
100#define S3C2443_UCON_RXERR_IRQEN (1<<6)
101#define S3C2443_UCON_LOOPBACK (1<<5)
102
103#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
104 S3C2410_UCON_RXILEVEL | \
105 S3C2410_UCON_TXIRQMODE | \
106 S3C2410_UCON_RXIRQMODE | \
107 S3C2410_UCON_RXFIFO_TOI)
108
109#define S3C2410_UFCON_FIFOMODE (1<<0)
110#define S3C2410_UFCON_TXTRIG0 (0<<6)
111#define S3C2410_UFCON_RXTRIG8 (1<<4)
112#define S3C2410_UFCON_RXTRIG12 (2<<4)
113
114/* S3C2440 FIFO trigger levels */
115#define S3C2440_UFCON_RXTRIG1 (0<<4)
116#define S3C2440_UFCON_RXTRIG8 (1<<4)
117#define S3C2440_UFCON_RXTRIG16 (2<<4)
118#define S3C2440_UFCON_RXTRIG32 (3<<4)
119
120#define S3C2440_UFCON_TXTRIG0 (0<<6)
121#define S3C2440_UFCON_TXTRIG16 (1<<6)
122#define S3C2440_UFCON_TXTRIG32 (2<<6)
123#define S3C2440_UFCON_TXTRIG48 (3<<6)
124
125#define S3C2410_UFCON_RESETBOTH (3<<1)
126#define S3C2410_UFCON_RESETTX (1<<2)
127#define S3C2410_UFCON_RESETRX (1<<1)
128
129#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
130 S3C2410_UFCON_TXTRIG0 | \
131 S3C2410_UFCON_RXTRIG8 )
132
133#define S3C2410_UMCOM_AFC (1<<4)
134#define S3C2410_UMCOM_RTS_LOW (1<<0)
135
136#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
137#define S3C2412_UMCON_AFC_56 (1<<5)
138#define S3C2412_UMCON_AFC_48 (2<<5)
139#define S3C2412_UMCON_AFC_40 (3<<5)
140#define S3C2412_UMCON_AFC_32 (4<<5)
141#define S3C2412_UMCON_AFC_24 (5<<5)
142#define S3C2412_UMCON_AFC_16 (6<<5)
143#define S3C2412_UMCON_AFC_8 (7<<5)
144
145#define S3C2410_UFSTAT_TXFULL (1<<9)
146#define S3C2410_UFSTAT_RXFULL (1<<8)
147#define S3C2410_UFSTAT_TXMASK (15<<4)
148#define S3C2410_UFSTAT_TXSHIFT (4)
149#define S3C2410_UFSTAT_RXMASK (15<<0)
150#define S3C2410_UFSTAT_RXSHIFT (0)
151
152/* UFSTAT S3C2443 same as S3C2440 */
153#define S3C2440_UFSTAT_TXFULL (1<<14)
154#define S3C2440_UFSTAT_RXFULL (1<<6)
155#define S3C2440_UFSTAT_TXSHIFT (8)
156#define S3C2440_UFSTAT_RXSHIFT (0)
157#define S3C2440_UFSTAT_TXMASK (63<<8)
158#define S3C2440_UFSTAT_RXMASK (63)
159
160#define S3C2410_UTRSTAT_TXE (1<<2)
161#define S3C2410_UTRSTAT_TXFE (1<<1)
162#define S3C2410_UTRSTAT_RXDR (1<<0)
163
164#define S3C2410_UERSTAT_OVERRUN (1<<0)
165#define S3C2410_UERSTAT_FRAME (1<<2)
166#define S3C2410_UERSTAT_BREAK (1<<3)
167#define S3C2443_UERSTAT_PARITY (1<<1)
168
169#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
170 S3C2410_UERSTAT_FRAME | \
171 S3C2410_UERSTAT_BREAK)
172
173#define S3C2410_UMSTAT_CTS (1<<0)
174#define S3C2410_UMSTAT_DeltaCTS (1<<2)
175
176#define S3C2443_DIVSLOT (0x2C)
177
178#ifndef __ASSEMBLY__
179
180/* struct s3c24xx_uart_clksrc
181 *
182 * this structure defines a named clock source that can be used for the
183 * uart, so that the best clock can be selected for the requested baud
184 * rate.
185 *
186 * min_baud and max_baud define the range of baud-rates this clock is
187 * acceptable for, if they are both zero, it is assumed any baud rate that
188 * can be generated from this clock will be used.
189 *
190 * divisor gives the divisor from the clock to the one seen by the uart
191*/
192
193struct s3c24xx_uart_clksrc {
194 const char *name;
195 unsigned int divisor;
196 unsigned int min_baud;
197 unsigned int max_baud;
198};
199
200/* configuration structure for per-machine configurations for the
201 * serial port
202 *
203 * the pointer is setup by the machine specific initialisation from the
204 * arch/arm/mach-s3c2410/ directory.
205*/
206
207struct s3c2410_uartcfg {
208 unsigned char hwport; /* hardware port number */
209 unsigned char unused;
210 unsigned short flags;
211 upf_t uart_flags; /* default uart flags */
212
213 unsigned long ucon; /* value of ucon for port */
214 unsigned long ulcon; /* value of ulcon for port */
215 unsigned long ufcon; /* value of ufcon for port */
216
217 struct s3c24xx_uart_clksrc *clocks;
218 unsigned int clocks_size;
219};
220
221/* s3c24xx_uart_devs
222 *
223 * this is exported from the core as we cannot use driver_register(),
224 * or platform_add_device() before the console_initcall()
225*/
226
227extern struct platform_device *s3c24xx_uart_devs[3];
228
229#endif /* __ASSEMBLY__ */
230
231#endif /* __ASM_ARM_REGS_SERIAL_H */
232
diff --git a/arch/arm/plat-s3c/include/plat/regs-timer.h b/arch/arm/plat-s3c/include/plat/regs-timer.h
new file mode 100644
index 000000000000..cc0eedd53e38
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-timer.h
@@ -0,0 +1,115 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Timer configuration
11*/
12
13
14#ifndef __ASM_ARCH_REGS_TIMER_H
15#define __ASM_ARCH_REGS_TIMER_H
16
17#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
18#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
19
20#define S3C2410_TCFG0 S3C_TIMERREG(0x00)
21#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
22#define S3C2410_TCON S3C_TIMERREG(0x08)
23
24#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
25#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
26#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
27#define S3C2410_TCFG_DEADZONE_MASK (255<<16)
28#define S3C2410_TCFG_DEADZONE_SHIFT (16)
29
30#define S3C2410_TCFG1_MUX4_DIV2 (0<<16)
31#define S3C2410_TCFG1_MUX4_DIV4 (1<<16)
32#define S3C2410_TCFG1_MUX4_DIV8 (2<<16)
33#define S3C2410_TCFG1_MUX4_DIV16 (3<<16)
34#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16)
35#define S3C2410_TCFG1_MUX4_MASK (15<<16)
36#define S3C2410_TCFG1_MUX4_SHIFT (16)
37
38#define S3C2410_TCFG1_MUX3_DIV2 (0<<12)
39#define S3C2410_TCFG1_MUX3_DIV4 (1<<12)
40#define S3C2410_TCFG1_MUX3_DIV8 (2<<12)
41#define S3C2410_TCFG1_MUX3_DIV16 (3<<12)
42#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12)
43#define S3C2410_TCFG1_MUX3_MASK (15<<12)
44
45
46#define S3C2410_TCFG1_MUX2_DIV2 (0<<8)
47#define S3C2410_TCFG1_MUX2_DIV4 (1<<8)
48#define S3C2410_TCFG1_MUX2_DIV8 (2<<8)
49#define S3C2410_TCFG1_MUX2_DIV16 (3<<8)
50#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8)
51#define S3C2410_TCFG1_MUX2_MASK (15<<8)
52
53
54#define S3C2410_TCFG1_MUX1_DIV2 (0<<4)
55#define S3C2410_TCFG1_MUX1_DIV4 (1<<4)
56#define S3C2410_TCFG1_MUX1_DIV8 (2<<4)
57#define S3C2410_TCFG1_MUX1_DIV16 (3<<4)
58#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4)
59#define S3C2410_TCFG1_MUX1_MASK (15<<4)
60
61#define S3C2410_TCFG1_MUX0_DIV2 (0<<0)
62#define S3C2410_TCFG1_MUX0_DIV4 (1<<0)
63#define S3C2410_TCFG1_MUX0_DIV8 (2<<0)
64#define S3C2410_TCFG1_MUX0_DIV16 (3<<0)
65#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
66#define S3C2410_TCFG1_MUX0_MASK (15<<0)
67
68#define S3C2410_TCFG1_MUX_DIV2 (0<<0)
69#define S3C2410_TCFG1_MUX_DIV4 (1<<0)
70#define S3C2410_TCFG1_MUX_DIV8 (2<<0)
71#define S3C2410_TCFG1_MUX_DIV16 (3<<0)
72#define S3C2410_TCFG1_MUX_TCLK (4<<0)
73#define S3C2410_TCFG1_MUX_MASK (15<<0)
74
75#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
76
77/* for each timer, we have an count buffer, an compare buffer and
78 * an observation buffer
79*/
80
81/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
82
83#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
84#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
85#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
86
87#define S3C2410_TCON_T4RELOAD (1<<22)
88#define S3C2410_TCON_T4MANUALUPD (1<<21)
89#define S3C2410_TCON_T4START (1<<20)
90
91#define S3C2410_TCON_T3RELOAD (1<<19)
92#define S3C2410_TCON_T3INVERT (1<<18)
93#define S3C2410_TCON_T3MANUALUPD (1<<17)
94#define S3C2410_TCON_T3START (1<<16)
95
96#define S3C2410_TCON_T2RELOAD (1<<15)
97#define S3C2410_TCON_T2INVERT (1<<14)
98#define S3C2410_TCON_T2MANUALUPD (1<<13)
99#define S3C2410_TCON_T2START (1<<12)
100
101#define S3C2410_TCON_T1RELOAD (1<<11)
102#define S3C2410_TCON_T1INVERT (1<<10)
103#define S3C2410_TCON_T1MANUALUPD (1<<9)
104#define S3C2410_TCON_T1START (1<<8)
105
106#define S3C2410_TCON_T0DEADZONE (1<<4)
107#define S3C2410_TCON_T0RELOAD (1<<3)
108#define S3C2410_TCON_T0INVERT (1<<2)
109#define S3C2410_TCON_T0MANUALUPD (1<<1)
110#define S3C2410_TCON_T0START (1<<0)
111
112#endif /* __ASM_ARCH_REGS_TIMER_H */
113
114
115
diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h
new file mode 100644
index 000000000000..4df006b9cc10
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/uncompress.h
@@ -0,0 +1,155 @@
1/* linux/include/asm-arm/plat-s3c/uncompress.h
2 *
3 * Copyright 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - uncompress code
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_PLAT_UNCOMPRESS_H
15#define __ASM_PLAT_UNCOMPRESS_H
16
17typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
18
19/* uart setup */
20
21static unsigned int fifo_mask;
22static unsigned int fifo_max;
23
24/* forward declerations */
25
26static void arch_detect_cpu(void);
27
28/* defines for UART registers */
29
30#include <plat/regs-serial.h>
31#include <asm/plat-s3c/regs-watchdog.h>
32
33/* working in physical space... */
34#undef S3C2410_WDOGREG
35#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
36
37/* how many bytes we allow into the FIFO at a time in FIFO mode */
38#define FIFO_MAX (14)
39
40#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
41
42static __inline__ void
43uart_wr(unsigned int reg, unsigned int val)
44{
45 volatile unsigned int *ptr;
46
47 ptr = (volatile unsigned int *)(reg + uart_base);
48 *ptr = val;
49}
50
51static __inline__ unsigned int
52uart_rd(unsigned int reg)
53{
54 volatile unsigned int *ptr;
55
56 ptr = (volatile unsigned int *)(reg + uart_base);
57 return *ptr;
58}
59
60/* we can deal with the case the UARTs are being run
61 * in FIFO mode, so that we don't hold up our execution
62 * waiting for tx to happen...
63*/
64
65static void putc(int ch)
66{
67 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
68 int level;
69
70 while (1) {
71 level = uart_rd(S3C2410_UFSTAT);
72 level &= fifo_mask;
73
74 if (level < fifo_max)
75 break;
76 }
77
78 } else {
79 /* not using fifos */
80
81 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
82 barrier();
83 }
84
85 /* write byte to transmission register */
86 uart_wr(S3C2410_UTXH, ch);
87}
88
89static inline void flush(void)
90{
91}
92
93#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
94
95/* CONFIG_S3C_BOOT_WATCHDOG
96 *
97 * Simple boot-time watchdog setup, to reboot the system if there is
98 * any problem with the boot process
99*/
100
101#ifdef CONFIG_S3C_BOOT_WATCHDOG
102
103#define WDOG_COUNT (0xff00)
104
105static inline void arch_decomp_wdog(void)
106{
107 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
108}
109
110static void arch_decomp_wdog_start(void)
111{
112 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
113 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
114 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
115}
116
117#else
118#define arch_decomp_wdog_start()
119#define arch_decomp_wdog()
120#endif
121
122#ifdef CONFIG_S3C_BOOT_ERROR_RESET
123
124static void arch_decomp_error(const char *x)
125{
126 putstr("\n\n");
127 putstr(x);
128 putstr("\n\n -- System resetting\n");
129
130 __raw_writel(0x4000, S3C2410_WTDAT);
131 __raw_writel(0x4000, S3C2410_WTCNT);
132 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
133
134 while(1);
135}
136
137#define arch_error arch_decomp_error
138#endif
139
140static void error(char *err);
141
142static void
143arch_decomp_setup(void)
144{
145 /* we may need to setup the uart(s) here if we are not running
146 * on an BAST... the BAST will have left the uarts configured
147 * after calling linux.
148 */
149
150 arch_detect_cpu();
151 arch_decomp_wdog_start();
152}
153
154
155#endif /* __ASM_PLAT_UNCOMPRESS_H */
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