9 files changed, 459 insertions, 1 deletions

diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index b85b4359e935..80255a5e1789 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -13,6 +13,7 @@ obj-				:=
 # Core files
 
 obj-y                           += dev-uart.o
+obj-y                           += dev-rtc.o
 obj-y                           += cpu.o
 obj-y                           += irq.o
 obj-y                           += irq-eint.o
@@ -35,6 +36,10 @@ obj-$(CONFIG_PM)		+= irq-pm.o
 
 obj-$(CONFIG_S3C64XX_DMA)       += dma.o
 
+# ADC support
+
+obj-$(CONFIG_S3C_ADC)           += dev-adc.o
+
 # Device setup
 
 obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
@@ -42,3 +47,4 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
 obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
 obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o
+obj-$(CONFIG_SPI_S3C64XX) += dev-spi.o
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
index ae5883c00e7a..2989c3a2e94d 100644
--- a/arch/arm/plat-s3c64xx/clock.c
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -141,6 +141,18 @@ static struct clk init_clocks_disable[] = {
                 .enable         = s3c64xx_pclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
         }, {
+                .name           = "spi_48m",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
+        }, {
+                .name           = "spi_48m",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
+        }, {
                 .name           = "48m",
                 .id             = 0,
                 .parent         = &clk_48m,
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c
index c0e6f2a45154..bc7ca1812e32 100644
--- a/arch/arm/plat-s3c64xx/cpu.c
+++ b/arch/arm/plat-s3c64xx/cpu.c
@@ -73,6 +73,11 @@ static struct map_desc s3c_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S3C_VA_MEM,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_SROM),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)(S3C_VA_UART + UART_OFFS),
                 .pfn            = __phys_to_pfn(S3C_PA_UART),
                 .length         = SZ_4K,
diff --git a/arch/arm/plat-s3c64xx/dev-adc.c b/arch/arm/plat-s3c64xx/dev-adc.c
new file mode 100644
index 000000000000..fafef9b6bcfa
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/dev-adc.c
@@ -0,0 +1,46 @@
+/* linux/arch/arm/plat-s3c64xx/dev-adc.c
+ *
+ * Copyright 2010 Maurus Cuelenaere
+ *
+ * S3C64xx series device definition for ADC device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/adc.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_adc_resource[] = {
+        [0] = {
+                .start = S3C64XX_PA_ADC,
+                .end   = S3C64XX_PA_ADC + SZ_256 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TC,
+                .end   = IRQ_TC,
+                .flags = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start = IRQ_ADC,
+                .end   = IRQ_ADC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_adc = {
+        .name           = "s3c64xx-adc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s3c_adc_resource),
+        .resource       = s3c_adc_resource,
+};
diff --git a/arch/arm/plat-s3c64xx/dev-audio.c b/arch/arm/plat-s3c64xx/dev-audio.c
index a21a88fbb7e3..cdba3a77ea19 100644
--- a/arch/arm/plat-s3c64xx/dev-audio.c
+++ b/arch/arm/plat-s3c64xx/dev-audio.c
@@ -3,7 +3,6 @@
  * Copyright 2009 Wolfson Microelectronics
  *      Mark Brown <broonie@opensource.wolfsonmicro.com>
  *
-
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -20,16 +19,69 @@
 
 #include <plat/devs.h>
 #include <plat/audio.h>
+#include <plat/gpio-bank-c.h>
 #include <plat/gpio-bank-d.h>
 #include <plat/gpio-bank-e.h>
+#include <plat/gpio-bank-h.h>
 #include <plat/gpio-cfg.h>
 
+static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
+                s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
+                s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
+                s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
+                s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
+                break;
+        case 1:
+                s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
+                s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
+                s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
+                s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
+                s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
+        default:
+                printk(KERN_DEBUG "Invalid I2S Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev)
+{
+        s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S0_V40_DO);
+        s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S1_V40_DO);
+        s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S2_V40_DO);
+        s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
+        s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
+        s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
+        s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
+
+        return 0;
+}
+
 static struct resource s3c64xx_iis0_resource[] = {
         [0] = {
                 .start = S3C64XX_PA_IIS0,
                 .end   = S3C64XX_PA_IIS0 + 0x100 - 1,
                 .flags = IORESOURCE_MEM,
         },
+        [1] = {
+                .start = DMACH_I2S0_OUT,
+                .end   = DMACH_I2S0_OUT,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_I2S0_IN,
+                .end   = DMACH_I2S0_IN,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct s3c_audio_pdata s3c_i2s0_pdata = {
+        .cfg_gpio = s3c64xx_i2sv3_cfg_gpio,
 };
 
 struct platform_device s3c64xx_device_iis0 = {
@@ -37,6 +89,9 @@ struct platform_device s3c64xx_device_iis0 = {
         .id               = 0,
         .num_resources    = ARRAY_SIZE(s3c64xx_iis0_resource),
         .resource         = s3c64xx_iis0_resource,
+        .dev = {
+                .platform_data = &s3c_i2s0_pdata,
+        },
 };
 EXPORT_SYMBOL(s3c64xx_device_iis0);
 
@@ -46,6 +101,20 @@ static struct resource s3c64xx_iis1_resource[] = {
                 .end   = S3C64XX_PA_IIS1 + 0x100 - 1,
                 .flags = IORESOURCE_MEM,
         },
+        [1] = {
+                .start = DMACH_I2S1_OUT,
+                .end   = DMACH_I2S1_OUT,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_I2S1_IN,
+                .end   = DMACH_I2S1_IN,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct s3c_audio_pdata s3c_i2s1_pdata = {
+        .cfg_gpio = s3c64xx_i2sv3_cfg_gpio,
 };
 
 struct platform_device s3c64xx_device_iis1 = {
@@ -53,6 +122,9 @@ struct platform_device s3c64xx_device_iis1 = {
         .id               = 1,
         .num_resources    = ARRAY_SIZE(s3c64xx_iis1_resource),
         .resource         = s3c64xx_iis1_resource,
+        .dev = {
+                .platform_data = &s3c_i2s1_pdata,
+        },
 };
 EXPORT_SYMBOL(s3c64xx_device_iis1);
 
@@ -62,6 +134,20 @@ static struct resource s3c64xx_iisv4_resource[] = {
                 .end   = S3C64XX_PA_IISV4 + 0x100 - 1,
                 .flags = IORESOURCE_MEM,
         },
+        [1] = {
+                .start = DMACH_HSI_I2SV40_TX,
+                .end   = DMACH_HSI_I2SV40_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_HSI_I2SV40_RX,
+                .end   = DMACH_HSI_I2SV40_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct s3c_audio_pdata s3c_i2sv4_pdata = {
+        .cfg_gpio = s3c64xx_i2sv4_cfg_gpio,
 };
 
 struct platform_device s3c64xx_device_iisv4 = {
@@ -69,6 +155,9 @@ struct platform_device s3c64xx_device_iisv4 = {
         .id               = -1,
         .num_resources    = ARRAY_SIZE(s3c64xx_iisv4_resource),
         .resource         = s3c64xx_iisv4_resource,
+        .dev = {
+                .platform_data = &s3c_i2sv4_pdata,
+        },
 };
 EXPORT_SYMBOL(s3c64xx_device_iisv4);
 
diff --git a/arch/arm/plat-s3c64xx/dev-rtc.c b/arch/arm/plat-s3c64xx/dev-rtc.c
new file mode 100644
index 000000000000..b9e7a05f0129
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/dev-rtc.c
@@ -0,0 +1,43 @@
+/* linux/arch/arm/plat-s3c64xx/dev-rtc.c
+ *
+ * Copyright 2009 by Maurus Cuelenaere <mcuelenaere@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+static struct resource s3c_rtc_resource[] = {
+        [0] = {
+                .start = S3C64XX_PA_RTC,
+                .end   = S3C64XX_PA_RTC + 0xff,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_RTC_ALARM,
+                .end   = IRQ_RTC_ALARM,
+                .flags = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start = IRQ_RTC_TIC,
+                .end   = IRQ_RTC_TIC,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+struct platform_device s3c_device_rtc = {
+        .name             = "s3c64xx-rtc",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s3c_rtc_resource),
+        .resource         = s3c_rtc_resource,
+};
+EXPORT_SYMBOL(s3c_device_rtc);
diff --git a/arch/arm/plat-s3c64xx/dev-spi.c b/arch/arm/plat-s3c64xx/dev-spi.c
new file mode 100644
index 000000000000..6b6d7af06624
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/dev-spi.c
@@ -0,0 +1,180 @@
+/* linux/arch/arm/plat-s3c64xx/dev-spi.c
+ *
+ * Copyright (C) 2009 Samsung Electronics Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/gpio.h>
+
+#include <plat/spi-clocks.h>
+#include <plat/s3c64xx-spi.h>
+#include <plat/gpio-bank-c.h>
+#include <plat/gpio-cfg.h>
+#include <plat/irqs.h>
+
+static char *spi_src_clks[] = {
+        [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
+        [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
+        [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
+};
+
+/* SPI Controller platform_devices */
+
+/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
+ * The emulated CS is toggled by board specific mechanism, as it can
+ * be either some immediate GPIO or some signal out of some other
+ * chip in between ... or some yet another way.
+ * We simply do not assume anything about CS.
+ */
+static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0);
+                s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO);
+                s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO);
+                s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1);
+                s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1);
+                s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1);
+                s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct resource s3c64xx_spi0_resource[] = {
+        [0] = {
+                .start = S3C64XX_PA_SPI0,
+                .end   = S3C64XX_PA_SPI0 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI0_TX,
+                .end   = DMACH_SPI0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI0_RX,
+                .end   = DMACH_SPI0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI0,
+                .end   = IRQ_SPI0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
+        .cfg_gpio = s3c64xx_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x7f,
+        .rx_lvl_offset = 13,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s3c64xx_device_spi0 = {
+        .name             = "s3c64xx-spi",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s3c64xx_spi0_resource),
+        .resource         = s3c64xx_spi0_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s3c64xx_spi0_pdata,
+        },
+};
+EXPORT_SYMBOL(s3c64xx_device_spi0);
+
+static struct resource s3c64xx_spi1_resource[] = {
+        [0] = {
+                .start = S3C64XX_PA_SPI1,
+                .end   = S3C64XX_PA_SPI1 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI1_TX,
+                .end   = DMACH_SPI1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI1_RX,
+                .end   = DMACH_SPI1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI1,
+                .end   = IRQ_SPI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
+        .cfg_gpio = s3c64xx_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x7f,
+        .rx_lvl_offset = 13,
+};
+
+struct platform_device s3c64xx_device_spi1 = {
+        .name             = "s3c64xx-spi",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s3c64xx_spi1_resource),
+        .resource         = s3c64xx_spi1_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s3c64xx_spi1_pdata,
+        },
+};
+EXPORT_SYMBOL(s3c64xx_device_spi1);
+
+void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+{
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0
+                        || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
+                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        switch (cntrlr) {
+        case 0:
+                s3c64xx_spi0_pdata.num_cs = num_cs;
+                s3c64xx_spi0_pdata.src_clk_nr = src_clk_nr;
+                s3c64xx_spi0_pdata.src_clk_name = spi_src_clks[src_clk_nr];
+                break;
+        case 1:
+                s3c64xx_spi1_pdata.num_cs = num_cs;
+                s3c64xx_spi1_pdata.src_clk_nr = src_clk_nr;
+                s3c64xx_spi1_pdata.src_clk_name = spi_src_clks[src_clk_nr];
+                break;
+        default:
+                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
+                                                        __func__, cntrlr);
+                return;
+        }
+}
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-srom.h b/arch/arm/plat-s3c64xx/include/plat/regs-srom.h
new file mode 100644
index 000000000000..756731b36297
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-srom.h
@@ -0,0 +1,59 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
+ *
+ * Copyright 2009 Andy Green <andy@warmcat.com>
+ *
+ * S3C64XX SROM definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_SROM_H
+#define __PLAT_REGS_SROM_H __FILE__
+
+#define S3C64XX_SROMREG(x)      (S3C_VA_MEM + (x))
+
+#define S3C64XX_SROM_BW         S3C64XX_SROMREG(0)
+#define S3C64XX_SROM_BC0        S3C64XX_SROMREG(4)
+#define S3C64XX_SROM_BC1        S3C64XX_SROMREG(8)
+#define S3C64XX_SROM_BC2        S3C64XX_SROMREG(0xc)
+#define S3C64XX_SROM_BC3        S3C64XX_SROMREG(0x10)
+#define S3C64XX_SROM_BC4        S3C64XX_SROMREG(0x14)
+#define S3C64XX_SROM_BC5        S3C64XX_SROMREG(0x18)
+
+/*
+ * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
+ */
+
+#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT       0
+#define S3C64XX_SROM_BW__WAITENABLE__SHIFT      2
+#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT      3
+#define S3C64XX_SROM_BW__CS_MASK 0xf
+
+#define S3C64XX_SROM_BW__NCS0__SHIFT    0
+#define S3C64XX_SROM_BW__NCS1__SHIFT    4
+#define S3C64XX_SROM_BW__NCS2__SHIFT    8
+#define S3C64XX_SROM_BW__NCS3__SHIFT    0xc
+#define S3C64XX_SROM_BW__NCS4__SHIFT    0x10
+
+/*
+ * applies to same to BCS0 - BCS4
+ */
+
+#define S3C64XX_SROM_BCX__PMC__SHIFT    0
+#define S3C64XX_SROM_BCX__PMC__MASK     3
+#define S3C64XX_SROM_BCX__TACP__SHIFT   4
+#define S3C64XX_SROM_BCX__TACP__MASK    0xf
+#define S3C64XX_SROM_BCX__TCAH__SHIFT   8
+#define S3C64XX_SROM_BCX__TCAH__MASK    0xf
+#define S3C64XX_SROM_BCX__TCOH__SHIFT   12
+#define S3C64XX_SROM_BCX__TCOH__MASK    0xf
+#define S3C64XX_SROM_BCX__TACC__SHIFT   16
+#define S3C64XX_SROM_BCX__TACC__MASK    0x1f
+#define S3C64XX_SROM_BCX__TCOS__SHIFT   24
+#define S3C64XX_SROM_BCX__TCOS__MASK    0xf
+#define S3C64XX_SROM_BCX__TACS__SHIFT   28
+#define S3C64XX_SROM_BCX__TACS__MASK    0xf
+
+#endif /* _PLAT_REGS_SROM_H */
diff --git a/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h b/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h
new file mode 100644
index 000000000000..524bdae3f625
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h
@@ -0,0 +1,18 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h
+ *
+ * Copyright (C) 2009 Samsung Electronics Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __S3C64XX_PLAT_SPI_CLKS_H
+#define __S3C64XX_PLAT_SPI_CLKS_H __FILE__
+
+#define S3C64XX_SPI_SRCCLK_PCLK         0
+#define S3C64XX_SPI_SRCCLK_SPIBUS       1
+#define S3C64XX_SPI_SRCCLK_48M          2
+
+#endif /* __S3C64XX_PLAT_SPI_CLKS_H */