aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-s3c64xx/dev-spi.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-s3c64xx/dev-spi.c')
-rw-r--r--arch/arm/plat-s3c64xx/dev-spi.c180
1 files changed, 180 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/dev-spi.c b/arch/arm/plat-s3c64xx/dev-spi.c
new file mode 100644
index 000000000000..6b6d7af06624
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/dev-spi.c
@@ -0,0 +1,180 @@
1/* linux/arch/arm/plat-s3c64xx/dev-spi.c
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15
16#include <mach/dma.h>
17#include <mach/map.h>
18#include <mach/gpio.h>
19
20#include <plat/spi-clocks.h>
21#include <plat/s3c64xx-spi.h>
22#include <plat/gpio-bank-c.h>
23#include <plat/gpio-cfg.h>
24#include <plat/irqs.h>
25
26static char *spi_src_clks[] = {
27 [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
28 [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
29 [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
30};
31
32/* SPI Controller platform_devices */
33
34/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
35 * The emulated CS is toggled by board specific mechanism, as it can
36 * be either some immediate GPIO or some signal out of some other
37 * chip in between ... or some yet another way.
38 * We simply do not assume anything about CS.
39 */
40static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
41{
42 switch (pdev->id) {
43 case 0:
44 s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0);
45 s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO);
46 s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO);
47 s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP);
48 s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP);
49 s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP);
50 break;
51
52 case 1:
53 s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1);
54 s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1);
55 s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1);
56 s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP);
57 s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP);
58 s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP);
59 break;
60
61 default:
62 dev_err(&pdev->dev, "Invalid SPI Controller number!");
63 return -EINVAL;
64 }
65
66 return 0;
67}
68
69static struct resource s3c64xx_spi0_resource[] = {
70 [0] = {
71 .start = S3C64XX_PA_SPI0,
72 .end = S3C64XX_PA_SPI0 + 0x100 - 1,
73 .flags = IORESOURCE_MEM,
74 },
75 [1] = {
76 .start = DMACH_SPI0_TX,
77 .end = DMACH_SPI0_TX,
78 .flags = IORESOURCE_DMA,
79 },
80 [2] = {
81 .start = DMACH_SPI0_RX,
82 .end = DMACH_SPI0_RX,
83 .flags = IORESOURCE_DMA,
84 },
85 [3] = {
86 .start = IRQ_SPI0,
87 .end = IRQ_SPI0,
88 .flags = IORESOURCE_IRQ,
89 },
90};
91
92static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
93 .cfg_gpio = s3c64xx_spi_cfg_gpio,
94 .fifo_lvl_mask = 0x7f,
95 .rx_lvl_offset = 13,
96};
97
98static u64 spi_dmamask = DMA_BIT_MASK(32);
99
100struct platform_device s3c64xx_device_spi0 = {
101 .name = "s3c64xx-spi",
102 .id = 0,
103 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
104 .resource = s3c64xx_spi0_resource,
105 .dev = {
106 .dma_mask = &spi_dmamask,
107 .coherent_dma_mask = DMA_BIT_MASK(32),
108 .platform_data = &s3c64xx_spi0_pdata,
109 },
110};
111EXPORT_SYMBOL(s3c64xx_device_spi0);
112
113static struct resource s3c64xx_spi1_resource[] = {
114 [0] = {
115 .start = S3C64XX_PA_SPI1,
116 .end = S3C64XX_PA_SPI1 + 0x100 - 1,
117 .flags = IORESOURCE_MEM,
118 },
119 [1] = {
120 .start = DMACH_SPI1_TX,
121 .end = DMACH_SPI1_TX,
122 .flags = IORESOURCE_DMA,
123 },
124 [2] = {
125 .start = DMACH_SPI1_RX,
126 .end = DMACH_SPI1_RX,
127 .flags = IORESOURCE_DMA,
128 },
129 [3] = {
130 .start = IRQ_SPI1,
131 .end = IRQ_SPI1,
132 .flags = IORESOURCE_IRQ,
133 },
134};
135
136static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
137 .cfg_gpio = s3c64xx_spi_cfg_gpio,
138 .fifo_lvl_mask = 0x7f,
139 .rx_lvl_offset = 13,
140};
141
142struct platform_device s3c64xx_device_spi1 = {
143 .name = "s3c64xx-spi",
144 .id = 1,
145 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
146 .resource = s3c64xx_spi1_resource,
147 .dev = {
148 .dma_mask = &spi_dmamask,
149 .coherent_dma_mask = DMA_BIT_MASK(32),
150 .platform_data = &s3c64xx_spi1_pdata,
151 },
152};
153EXPORT_SYMBOL(s3c64xx_device_spi1);
154
155void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
156{
157 /* Reject invalid configuration */
158 if (!num_cs || src_clk_nr < 0
159 || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
160 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
161 return;
162 }
163
164 switch (cntrlr) {
165 case 0:
166 s3c64xx_spi0_pdata.num_cs = num_cs;
167 s3c64xx_spi0_pdata.src_clk_nr = src_clk_nr;
168 s3c64xx_spi0_pdata.src_clk_name = spi_src_clks[src_clk_nr];
169 break;
170 case 1:
171 s3c64xx_spi1_pdata.num_cs = num_cs;
172 s3c64xx_spi1_pdata.src_clk_nr = src_clk_nr;
173 s3c64xx_spi1_pdata.src_clk_name = spi_src_clks[src_clk_nr];
174 break;
175 default:
176 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
177 __func__, cntrlr);
178 return;
179 }
180}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 05:10:51 -0500