aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-s3c24xx
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig60
-rw-r--r--arch/arm/plat-s3c24xx/Makefile8
-rw-r--r--arch/arm/plat-s3c24xx/adc.c435
-rw-r--r--arch/arm/plat-s3c24xx/clock-dclk.c22
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c4
-rw-r--r--arch/arm/plat-s3c24xx/devs.c59
-rw-r--r--arch/arm/plat-s3c24xx/dma.c2
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/audio-simtec.h37
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/dma-plat.h84
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/mci.h9
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pm-core.h64
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2440.h17
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2442.h17
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c244x.h (renamed from arch/arm/plat-s3c24xx/s3c244x.h)14
-rw-r--r--arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c97
-rw-r--r--arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c127
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x-clock.c136
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x-irq.c142
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x.c196
20 files changed, 124 insertions, 1408 deletions
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 342647eb91d8..6e93ef8f3d43 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -14,58 +14,40 @@ config PLAT_S3C24XX
14 14
15if PLAT_S3C24XX 15if PLAT_S3C24XX
16 16
17# code that is shared between a number of the s3c24xx implementations 17# low-level serial option nodes
18 18
19config S3C2410_CLOCK 19config CPU_LLSERIAL_S3C2410_ONLY
20 bool 20 bool
21 help 21 default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
22 Clock code for the S3C2410, and similar processors which
23 is currently includes the S3C2410, S3C2440, S3C2442.
24 22
25config S3C24XX_DCLK 23config CPU_LLSERIAL_S3C2440_ONLY
26 bool 24 bool
27 help 25 default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
28 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
29 26
30config CPU_S3C244X 27config CPU_LLSERIAL_S3C2410
31 bool 28 bool
32 depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
33 help
34 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
35
36config S3C2440_CPUFREQ
37 bool "S3C2440/S3C2442 CPU Frequency scaling support"
38 depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
39 select S3C2410_CPUFREQ_UTILS
40 default y
41 help 29 help
42 CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. 30 Selected if there is an S3C2410 (or register compatible) serial
31 low-level implementation needed
43 32
44config S3C2440_XTAL_12000000 33config CPU_LLSERIAL_S3C2440
45 bool 34 bool
46 help 35 help
47 Indicate that the build needs to support 12MHz system 36 Selected if there is an S3C2440 (or register compatible) serial
48 crystal. 37 low-level implementation needed
49 38
50config S3C2440_XTAL_16934400 39# code that is shared between a number of the s3c24xx implementations
51 bool
52 help
53 Indicate that the build needs to support 16.9344MHz system
54 crystal.
55 40
56config S3C2440_PLL_12000000 41config S3C2410_CLOCK
57 bool 42 bool
58 depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
59 default y if CPU_FREQ_S3C24XX_PLL
60 help 43 help
61 PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. 44 Clock code for the S3C2410, and similar processors which
45 is currently includes the S3C2410, S3C2440, S3C2442.
62 46
63config S3C2440_PLL_16934400 47config S3C24XX_DCLK
64 bool 48 bool
65 depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
66 default y if CPU_FREQ_S3C24XX_PLL
67 help 49 help
68 PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. 50 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
69 51
70config S3C24XX_PWM 52config S3C24XX_PWM
71 bool "PWM device support" 53 bool "PWM device support"
@@ -74,7 +56,6 @@ config S3C24XX_PWM
74 Support for exporting the PWM timer blocks via the pwm device 56 Support for exporting the PWM timer blocks via the pwm device
75 system. 57 system.
76 58
77
78# gpio configurations 59# gpio configurations
79 60
80config S3C24XX_GPIO_EXTRA 61config S3C24XX_GPIO_EXTRA
@@ -117,13 +98,6 @@ config S3C2410_DMA_DEBUG
117 Enable debugging output for the DMA code. This option sends info 98 Enable debugging output for the DMA code. This option sends info
118 to the kernel log, at priority KERN_DEBUG. 99 to the kernel log, at priority KERN_DEBUG.
119 100
120config S3C24XX_ADC
121 bool "ADC common driver support"
122 help
123 Core support for the ADC block found in the S3C24XX SoC systems
124 for drivers such as the touchscreen and hwmon to use to share
125 this resource.
126
127# SPI default pin configuration code 101# SPI default pin configuration code
128 102
129config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13 103config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 5dee8c12e8b4..c2237c41141f 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -25,20 +25,12 @@ obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
25 25
26# Architecture dependant builds 26# Architecture dependant builds
27 27
28obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
29obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o
30obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o
31obj-$(CONFIG_S3C2440_CPUFREQ) += s3c2440-cpufreq.o
32obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
33obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
34
35obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o 28obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
36obj-$(CONFIG_PM) += pm.o 29obj-$(CONFIG_PM) += pm.o
37obj-$(CONFIG_PM) += irq-pm.o 30obj-$(CONFIG_PM) += irq-pm.o
38obj-$(CONFIG_PM) += sleep.o 31obj-$(CONFIG_PM) += sleep.o
39obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o 32obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
40obj-$(CONFIG_S3C2410_DMA) += dma.o 33obj-$(CONFIG_S3C2410_DMA) += dma.o
41obj-$(CONFIG_S3C24XX_ADC) += adc.o
42obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o 34obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o
43obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o 35obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o
44obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o 36obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c
deleted file mode 100644
index ce47627f3368..000000000000
--- a/arch/arm/plat-s3c24xx/adc.c
+++ /dev/null
@@ -1,435 +0,0 @@
1/* arch/arm/plat-s3c24xx/adc.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
6 *
7 * S3C24XX ADC device core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12*/
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/sched.h>
18#include <linux/list.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23
24#include <plat/regs-adc.h>
25#include <plat/adc.h>
26
27/* This driver is designed to control the usage of the ADC block between
28 * the touchscreen and any other drivers that may need to use it, such as
29 * the hwmon driver.
30 *
31 * Priority will be given to the touchscreen driver, but as this itself is
32 * rate limited it should not starve other requests which are processed in
33 * order that they are received.
34 *
35 * Each user registers to get a client block which uniquely identifies it
36 * and stores information such as the necessary functions to callback when
37 * action is required.
38 */
39
40struct s3c_adc_client {
41 struct platform_device *pdev;
42 struct list_head pend;
43 wait_queue_head_t *wait;
44
45 unsigned int nr_samples;
46 int result;
47 unsigned char is_ts;
48 unsigned char channel;
49
50 void (*select_cb)(struct s3c_adc_client *c, unsigned selected);
51 void (*convert_cb)(struct s3c_adc_client *c,
52 unsigned val1, unsigned val2,
53 unsigned *samples_left);
54};
55
56struct adc_device {
57 struct platform_device *pdev;
58 struct platform_device *owner;
59 struct clk *clk;
60 struct s3c_adc_client *cur;
61 struct s3c_adc_client *ts_pend;
62 void __iomem *regs;
63
64 unsigned int prescale;
65
66 int irq;
67};
68
69static struct adc_device *adc_dev;
70
71static LIST_HEAD(adc_pending);
72
73#define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
74
75static inline void s3c_adc_convert(struct adc_device *adc)
76{
77 unsigned con = readl(adc->regs + S3C2410_ADCCON);
78
79 con |= S3C2410_ADCCON_ENABLE_START;
80 writel(con, adc->regs + S3C2410_ADCCON);
81}
82
83static inline void s3c_adc_select(struct adc_device *adc,
84 struct s3c_adc_client *client)
85{
86 unsigned con = readl(adc->regs + S3C2410_ADCCON);
87
88 client->select_cb(client, 1);
89
90 con &= ~S3C2410_ADCCON_MUXMASK;
91 con &= ~S3C2410_ADCCON_STDBM;
92 con &= ~S3C2410_ADCCON_STARTMASK;
93
94 if (!client->is_ts)
95 con |= S3C2410_ADCCON_SELMUX(client->channel);
96
97 writel(con, adc->regs + S3C2410_ADCCON);
98}
99
100static void s3c_adc_dbgshow(struct adc_device *adc)
101{
102 adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n",
103 readl(adc->regs + S3C2410_ADCCON),
104 readl(adc->regs + S3C2410_ADCTSC),
105 readl(adc->regs + S3C2410_ADCDLY));
106}
107
108static void s3c_adc_try(struct adc_device *adc)
109{
110 struct s3c_adc_client *next = adc->ts_pend;
111
112 if (!next && !list_empty(&adc_pending)) {
113 next = list_first_entry(&adc_pending,
114 struct s3c_adc_client, pend);
115 list_del(&next->pend);
116 } else
117 adc->ts_pend = NULL;
118
119 if (next) {
120 adc_dbg(adc, "new client is %p\n", next);
121 adc->cur = next;
122 s3c_adc_select(adc, next);
123 s3c_adc_convert(adc);
124 s3c_adc_dbgshow(adc);
125 }
126}
127
128int s3c_adc_start(struct s3c_adc_client *client,
129 unsigned int channel, unsigned int nr_samples)
130{
131 struct adc_device *adc = adc_dev;
132 unsigned long flags;
133
134 if (!adc) {
135 printk(KERN_ERR "%s: failed to find adc\n", __func__);
136 return -EINVAL;
137 }
138
139 if (client->is_ts && adc->ts_pend)
140 return -EAGAIN;
141
142 local_irq_save(flags);
143
144 client->channel = channel;
145 client->nr_samples = nr_samples;
146
147 if (client->is_ts)
148 adc->ts_pend = client;
149 else
150 list_add_tail(&client->pend, &adc_pending);
151
152 if (!adc->cur)
153 s3c_adc_try(adc);
154 local_irq_restore(flags);
155
156 return 0;
157}
158EXPORT_SYMBOL_GPL(s3c_adc_start);
159
160static void s3c_convert_done(struct s3c_adc_client *client,
161 unsigned v, unsigned u, unsigned *left)
162{
163 client->result = v;
164 wake_up(client->wait);
165}
166
167int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
168{
169 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
170 int ret;
171
172 client->convert_cb = s3c_convert_done;
173 client->wait = &wake;
174 client->result = -1;
175
176 ret = s3c_adc_start(client, ch, 1);
177 if (ret < 0)
178 goto err;
179
180 ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
181 if (client->result < 0) {
182 ret = -ETIMEDOUT;
183 goto err;
184 }
185
186 client->convert_cb = NULL;
187 return client->result;
188
189err:
190 return ret;
191}
192EXPORT_SYMBOL_GPL(s3c_adc_read);
193
194static void s3c_adc_default_select(struct s3c_adc_client *client,
195 unsigned select)
196{
197}
198
199struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
200 void (*select)(struct s3c_adc_client *client,
201 unsigned int selected),
202 void (*conv)(struct s3c_adc_client *client,
203 unsigned d0, unsigned d1,
204 unsigned *samples_left),
205 unsigned int is_ts)
206{
207 struct s3c_adc_client *client;
208
209 WARN_ON(!pdev);
210
211 if (!select)
212 select = s3c_adc_default_select;
213
214 if (!pdev)
215 return ERR_PTR(-EINVAL);
216
217 client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
218 if (!client) {
219 dev_err(&pdev->dev, "no memory for adc client\n");
220 return ERR_PTR(-ENOMEM);
221 }
222
223 client->pdev = pdev;
224 client->is_ts = is_ts;
225 client->select_cb = select;
226 client->convert_cb = conv;
227
228 return client;
229}
230EXPORT_SYMBOL_GPL(s3c_adc_register);
231
232void s3c_adc_release(struct s3c_adc_client *client)
233{
234 /* We should really check that nothing is in progress. */
235 if (adc_dev->cur == client)
236 adc_dev->cur = NULL;
237 if (adc_dev->ts_pend == client)
238 adc_dev->ts_pend = NULL;
239 else {
240 struct list_head *p, *n;
241 struct s3c_adc_client *tmp;
242
243 list_for_each_safe(p, n, &adc_pending) {
244 tmp = list_entry(p, struct s3c_adc_client, pend);
245 if (tmp == client)
246 list_del(&tmp->pend);
247 }
248 }
249
250 if (adc_dev->cur == NULL)
251 s3c_adc_try(adc_dev);
252 kfree(client);
253}
254EXPORT_SYMBOL_GPL(s3c_adc_release);
255
256static irqreturn_t s3c_adc_irq(int irq, void *pw)
257{
258 struct adc_device *adc = pw;
259 struct s3c_adc_client *client = adc->cur;
260 unsigned long flags;
261 unsigned data0, data1;
262
263 if (!client) {
264 dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__);
265 return IRQ_HANDLED;
266 }
267
268 data0 = readl(adc->regs + S3C2410_ADCDAT0);
269 data1 = readl(adc->regs + S3C2410_ADCDAT1);
270 adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
271
272 client->nr_samples--;
273
274 if (client->convert_cb)
275 (client->convert_cb)(client, data0 & 0x3ff, data1 & 0x3ff,
276 &client->nr_samples);
277
278 if (client->nr_samples > 0) {
279 /* fire another conversion for this */
280
281 client->select_cb(client, 1);
282 s3c_adc_convert(adc);
283 } else {
284 local_irq_save(flags);
285 (client->select_cb)(client, 0);
286 adc->cur = NULL;
287
288 s3c_adc_try(adc);
289 local_irq_restore(flags);
290 }
291
292 return IRQ_HANDLED;
293}
294
295static int s3c_adc_probe(struct platform_device *pdev)
296{
297 struct device *dev = &pdev->dev;
298 struct adc_device *adc;
299 struct resource *regs;
300 int ret;
301
302 adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL);
303 if (adc == NULL) {
304 dev_err(dev, "failed to allocate adc_device\n");
305 return -ENOMEM;
306 }
307
308 adc->pdev = pdev;
309 adc->prescale = S3C2410_ADCCON_PRSCVL(49);
310
311 adc->irq = platform_get_irq(pdev, 1);
312 if (adc->irq <= 0) {
313 dev_err(dev, "failed to get adc irq\n");
314 ret = -ENOENT;
315 goto err_alloc;
316 }
317
318 ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
319 if (ret < 0) {
320 dev_err(dev, "failed to attach adc irq\n");
321 goto err_alloc;
322 }
323
324 adc->clk = clk_get(dev, "adc");
325 if (IS_ERR(adc->clk)) {
326 dev_err(dev, "failed to get adc clock\n");
327 ret = PTR_ERR(adc->clk);
328 goto err_irq;
329 }
330
331 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
332 if (!regs) {
333 dev_err(dev, "failed to find registers\n");
334 ret = -ENXIO;
335 goto err_clk;
336 }
337
338 adc->regs = ioremap(regs->start, resource_size(regs));
339 if (!adc->regs) {
340 dev_err(dev, "failed to map registers\n");
341 ret = -ENXIO;
342 goto err_clk;
343 }
344
345 clk_enable(adc->clk);
346
347 writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
348 adc->regs + S3C2410_ADCCON);
349
350 dev_info(dev, "attached adc driver\n");
351
352 platform_set_drvdata(pdev, adc);
353 adc_dev = adc;
354
355 return 0;
356
357 err_clk:
358 clk_put(adc->clk);
359
360 err_irq:
361 free_irq(adc->irq, adc);
362
363 err_alloc:
364 kfree(adc);
365 return ret;
366}
367
368static int __devexit s3c_adc_remove(struct platform_device *pdev)
369{
370 struct adc_device *adc = platform_get_drvdata(pdev);
371
372 iounmap(adc->regs);
373 free_irq(adc->irq, adc);
374 clk_disable(adc->clk);
375 clk_put(adc->clk);
376 kfree(adc);
377
378 return 0;
379}
380
381#ifdef CONFIG_PM
382static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
383{
384 struct adc_device *adc = platform_get_drvdata(pdev);
385 u32 con;
386
387 con = readl(adc->regs + S3C2410_ADCCON);
388 con |= S3C2410_ADCCON_STDBM;
389 writel(con, adc->regs + S3C2410_ADCCON);
390
391 clk_disable(adc->clk);
392
393 return 0;
394}
395
396static int s3c_adc_resume(struct platform_device *pdev)
397{
398 struct adc_device *adc = platform_get_drvdata(pdev);
399
400 clk_enable(adc->clk);
401
402 writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
403 adc->regs + S3C2410_ADCCON);
404
405 return 0;
406}
407
408#else
409#define s3c_adc_suspend NULL
410#define s3c_adc_resume NULL
411#endif
412
413static struct platform_driver s3c_adc_driver = {
414 .driver = {
415 .name = "s3c24xx-adc",
416 .owner = THIS_MODULE,
417 },
418 .probe = s3c_adc_probe,
419 .remove = __devexit_p(s3c_adc_remove),
420 .suspend = s3c_adc_suspend,
421 .resume = s3c_adc_resume,
422};
423
424static int __init adc_init(void)
425{
426 int ret;
427
428 ret = platform_driver_register(&s3c_adc_driver);
429 if (ret)
430 printk(KERN_ERR "%s: failed to add adc driver\n", __func__);
431
432 return ret;
433}
434
435arch_initcall(adc_init);
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index ac061a1bcb37..cf97caafe56b 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -161,14 +161,18 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
161 161
162/* external clock definitions */ 162/* external clock definitions */
163 163
164static struct clk_ops dclk_ops = {
165 .set_parent = s3c24xx_dclk_setparent,
166 .set_rate = s3c24xx_set_dclk_rate,
167 .round_rate = s3c24xx_round_dclk_rate,
168};
169
164struct clk s3c24xx_dclk0 = { 170struct clk s3c24xx_dclk0 = {
165 .name = "dclk0", 171 .name = "dclk0",
166 .id = -1, 172 .id = -1,
167 .ctrlbit = S3C2410_DCLKCON_DCLK0EN, 173 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
168 .enable = s3c24xx_dclk_enable, 174 .enable = s3c24xx_dclk_enable,
169 .set_parent = s3c24xx_dclk_setparent, 175 .ops = &dclk_ops,
170 .set_rate = s3c24xx_set_dclk_rate,
171 .round_rate = s3c24xx_round_dclk_rate,
172}; 176};
173 177
174struct clk s3c24xx_dclk1 = { 178struct clk s3c24xx_dclk1 = {
@@ -176,19 +180,21 @@ struct clk s3c24xx_dclk1 = {
176 .id = -1, 180 .id = -1,
177 .ctrlbit = S3C2410_DCLKCON_DCLK1EN, 181 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
178 .enable = s3c24xx_dclk_enable, 182 .enable = s3c24xx_dclk_enable,
179 .set_parent = s3c24xx_dclk_setparent, 183 .ops = &dclk_ops,
180 .set_rate = s3c24xx_set_dclk_rate, 184};
181 .round_rate = s3c24xx_round_dclk_rate, 185
186static struct clk_ops clkout_ops = {
187 .set_parent = s3c24xx_clkout_setparent,
182}; 188};
183 189
184struct clk s3c24xx_clkout0 = { 190struct clk s3c24xx_clkout0 = {
185 .name = "clkout0", 191 .name = "clkout0",
186 .id = -1, 192 .id = -1,
187 .set_parent = s3c24xx_clkout_setparent, 193 .ops = &clkout_ops,
188}; 194};
189 195
190struct clk s3c24xx_clkout1 = { 196struct clk s3c24xx_clkout1 = {
191 .name = "clkout1", 197 .name = "clkout1",
192 .id = -1, 198 .id = -1,
193 .set_parent = s3c24xx_clkout_setparent, 199 .ops = &clkout_ops,
194}; 200};
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 4af9dd948793..9ca64df35bf6 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -49,9 +49,7 @@
49#include <plat/s3c2400.h> 49#include <plat/s3c2400.h>
50#include <plat/s3c2410.h> 50#include <plat/s3c2410.h>
51#include <plat/s3c2412.h> 51#include <plat/s3c2412.h>
52#include "s3c244x.h" 52#include <plat/s3c244x.h>
53#include <plat/s3c2440.h>
54#include <plat/s3c2442.h>
55#include <plat/s3c2443.h> 53#include <plat/s3c2443.h>
56 54
57/* table of supported CPUs */ 55/* table of supported CPUs */
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 7f686a31e672..8c6de1c9968f 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -32,6 +32,7 @@
32 32
33#include <plat/regs-serial.h> 33#include <plat/regs-serial.h>
34#include <plat/udc.h> 34#include <plat/udc.h>
35#include <plat/mci.h>
35 36
36#include <plat/devs.h> 37#include <plat/devs.h>
37#include <plat/cpu.h> 38#include <plat/cpu.h>
@@ -112,34 +113,6 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
112 }, 113 },
113}; 114};
114 115
115/* yart devices */
116
117static struct platform_device s3c24xx_uart_device0 = {
118 .id = 0,
119};
120
121static struct platform_device s3c24xx_uart_device1 = {
122 .id = 1,
123};
124
125static struct platform_device s3c24xx_uart_device2 = {
126 .id = 2,
127};
128
129static struct platform_device s3c24xx_uart_device3 = {
130 .id = 3,
131};
132
133struct platform_device *s3c24xx_uart_src[4] = {
134 &s3c24xx_uart_device0,
135 &s3c24xx_uart_device1,
136 &s3c24xx_uart_device2,
137 &s3c24xx_uart_device3,
138};
139
140struct platform_device *s3c24xx_uart_devs[4] = {
141};
142
143/* LCD Controller */ 116/* LCD Controller */
144 117
145static struct resource s3c_lcd_resource[] = { 118static struct resource s3c_lcd_resource[] = {
@@ -185,9 +158,27 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
185} 158}
186 159
187/* Touchscreen */ 160/* Touchscreen */
161
162static struct resource s3c_ts_resource[] = {
163 [0] = {
164 .start = S3C24XX_PA_ADC,
165 .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
166 .flags = IORESOURCE_MEM,
167 },
168 [1] = {
169 .start = IRQ_TC,
170 .end = IRQ_TC,
171 .flags = IORESOURCE_IRQ,
172 },
173
174};
175
188struct platform_device s3c_device_ts = { 176struct platform_device s3c_device_ts = {
189 .name = "s3c2410-ts", 177 .name = "s3c2410-ts",
190 .id = -1, 178 .id = -1,
179 .dev.parent = &s3c_device_adc.dev,
180 .num_resources = ARRAY_SIZE(s3c_ts_resource),
181 .resource = s3c_ts_resource,
191}; 182};
192EXPORT_SYMBOL(s3c_device_ts); 183EXPORT_SYMBOL(s3c_device_ts);
193 184
@@ -379,6 +370,18 @@ struct platform_device s3c_device_sdi = {
379 370
380EXPORT_SYMBOL(s3c_device_sdi); 371EXPORT_SYMBOL(s3c_device_sdi);
381 372
373void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
374{
375 struct s3c24xx_mci_pdata *npd;
376
377 npd = kmemdup(pdata, sizeof(struct s3c24xx_mci_pdata), GFP_KERNEL);
378 if (!npd)
379 printk(KERN_ERR "%s: no memory to copy pdata", __func__);
380
381 s3c_device_sdi.dev.platform_data = npd;
382}
383
384
382/* SPI (0) */ 385/* SPI (0) */
383 386
384static struct resource s3c_spi0_resource[] = { 387static struct resource s3c_spi0_resource[] = {
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index f0ea7943ac5a..93827b3d4e84 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -33,7 +33,7 @@
33#include <mach/dma.h> 33#include <mach/dma.h>
34#include <mach/map.h> 34#include <mach/map.h>
35 35
36#include <plat/dma-plat.h> 36#include <plat/dma-s3c24xx.h>
37#include <plat/regs-dma.h> 37#include <plat/regs-dma.h>
38 38
39/* io map for dma */ 39/* io map for dma */
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 6d7a961d3269..4f0f11a6a677 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -20,7 +20,7 @@
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/gpio.h> 21#include <linux/gpio.h>
22 22
23#include <mach/gpio-core.h> 23#include <plat/gpio-core.h>
24#include <mach/hardware.h> 24#include <mach/hardware.h>
25#include <asm/irq.h> 25#include <asm/irq.h>
26#include <plat/pm.h> 26#include <plat/pm.h>
diff --git a/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h b/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h
new file mode 100644
index 000000000000..de5e88fdcb31
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h
@@ -0,0 +1,37 @@
1/* arch/arm/plat-s3c24xx/include/plat/audio-simtec.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Simtec Audio support.
12*/
13
14/**
15 * struct s3c24xx_audio_simtec_pdata - platform data for simtec audio
16 * @use_mpllin: Select codec clock from MPLLin
17 * @output_cdclk: Need to output CDCLK to the codec
18 * @have_mic: Set if we have a MIC socket
19 * @have_lout: Set if we have a LineOut socket
20 * @amp_gpio: GPIO pin to enable the AMP
21 * @amp_gain: Option GPIO to control AMP gain
22 */
23struct s3c24xx_audio_simtec_pdata {
24 unsigned int use_mpllin:1;
25 unsigned int output_cdclk:1;
26
27 unsigned int have_mic:1;
28 unsigned int have_lout:1;
29
30 int amp_gpio;
31 int amp_gain[2];
32
33 void (*startup)(void);
34};
35
36extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
37 struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/plat-s3c24xx/include/plat/dma-plat.h b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
deleted file mode 100644
index 9565ead1bc9b..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <plat/dma-core.h>
14
15extern struct sysdev_class dma_sysclass;
16extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
17
18#define DMA_CH_VALID (1<<31)
19#define DMA_CH_NEVER (1<<30)
20
21struct s3c24xx_dma_addr {
22 unsigned long from;
23 unsigned long to;
24};
25
26/* struct s3c24xx_dma_map
27 *
28 * this holds the mapping information for the channel selected
29 * to be connected to the specified device
30*/
31
32struct s3c24xx_dma_map {
33 const char *name;
34 struct s3c24xx_dma_addr hw_addr;
35
36 unsigned long channels[S3C_DMA_CHANNELS];
37 unsigned long channels_rx[S3C_DMA_CHANNELS];
38};
39
40struct s3c24xx_dma_selection {
41 struct s3c24xx_dma_map *map;
42 unsigned long map_size;
43 unsigned long dcon_mask;
44
45 void (*select)(struct s3c2410_dma_chan *chan,
46 struct s3c24xx_dma_map *map);
47
48 void (*direction)(struct s3c2410_dma_chan *chan,
49 struct s3c24xx_dma_map *map,
50 enum s3c2410_dmasrc dir);
51};
52
53extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
54
55/* struct s3c24xx_dma_order_ch
56 *
57 * channel map for one of the `enum dma_ch` dma channels. the list
58 * entry contains a set of low-level channel numbers, orred with
59 * DMA_CH_VALID, which are checked in the order in the array.
60*/
61
62struct s3c24xx_dma_order_ch {
63 unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
64 unsigned int flags; /* flags */
65};
66
67/* struct s3c24xx_dma_order
68 *
69 * information provided by either the core or the board to give the
70 * dma system a hint on how to allocate channels
71*/
72
73struct s3c24xx_dma_order {
74 struct s3c24xx_dma_order_ch channels[DMACH_MAX];
75};
76
77extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
78
79/* DMA init code, called from the cpu support code */
80
81extern int s3c2410_dma_init(void);
82
83extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
84 unsigned int stride);
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h
index 36aaa10fad06..2ac2b21ec490 100644
--- a/arch/arm/plat-s3c24xx/include/plat/mci.h
+++ b/arch/arm/plat-s3c24xx/include/plat/mci.h
@@ -40,4 +40,13 @@ struct s3c24xx_mci_pdata {
40 unsigned short vdd); 40 unsigned short vdd);
41}; 41};
42 42
43/**
44 * s3c24xx_mci_set_platdata - set platform data for mmc/sdi device
45 * @pdata: The platform data
46 *
47 * Copy the platform data supplied by @pdata so that this can be marked
48 * __initdata.
49 */
50extern void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata);
51
43#endif /* _ARCH_NCI_H */ 52#endif /* _ARCH_NCI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
deleted file mode 100644
index fb45dd9adca5..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/pm-core.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14static inline void s3c_pm_debug_init_uart(void)
15{
16 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
17
18 /* re-start uart clocks */
19 tmp |= S3C2410_CLKCON_UART0;
20 tmp |= S3C2410_CLKCON_UART1;
21 tmp |= S3C2410_CLKCON_UART2;
22
23 __raw_writel(tmp, S3C2410_CLKCON);
24 udelay(10);
25}
26
27static inline void s3c_pm_arch_prepare_irqs(void)
28{
29 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
30 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
31
32 /* ack any outstanding external interrupts before we go to sleep */
33
34 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
35 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
36 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
37
38}
39
40static inline void s3c_pm_arch_stop_clocks(void)
41{
42 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
43}
44
45static void s3c_pm_show_resume_irqs(int start, unsigned long which,
46 unsigned long mask);
47
48static inline void s3c_pm_arch_show_resume_irqs(void)
49{
50 S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
51 __raw_readl(S3C2410_SRCPND),
52 __raw_readl(S3C2410_EINTPEND));
53
54 s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
55 s3c_irqwake_intmask);
56
57 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
58 s3c_irqwake_eintmask);
59}
60
61static inline void s3c_pm_arch_update_uart(void __iomem *regs,
62 struct pm_uart_save *save)
63{
64}
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2440.h b/arch/arm/plat-s3c24xx/include/plat/s3c2440.h
deleted file mode 100644
index 107853bf9481..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2440.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2440.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2440 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2440
14extern int s3c2440_init(void);
15#else
16#define s3c2440_init NULL
17#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2442.h b/arch/arm/plat-s3c24xx/include/plat/s3c2442.h
deleted file mode 100644
index 451a23a2092a..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2442.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2442.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2442 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2442
14extern int s3c2442_init(void);
15#else
16#define s3c2442_init NULL
17#endif
diff --git a/arch/arm/plat-s3c24xx/s3c244x.h b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
index 6aab5eaae2b4..307248d1ccbb 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
@@ -1,4 +1,4 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x.h 1/* linux/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
2 * 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics 3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
@@ -23,3 +23,15 @@ extern void s3c244x_init_clocks(int xtal);
23#define s3c244x_init_uarts NULL 23#define s3c244x_init_uarts NULL
24#define s3c244x_map_io NULL 24#define s3c244x_map_io NULL
25#endif 25#endif
26
27#ifdef CONFIG_CPU_S3C2440
28extern int s3c2440_init(void);
29#else
30#define s3c2440_init NULL
31#endif
32
33#ifdef CONFIG_CPU_S3C2442
34extern int s3c2442_init(void);
35#else
36#define s3c2442_init NULL
37#endif
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
deleted file mode 100644
index 49f65032f2c0..000000000000
--- a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
2 *
3 * Copyright (c) 2006-2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 * Vincent Sanders <vince@arm.linux.org.uk>
7 *
8 * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/sysdev.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20
21#include <plat/cpu.h>
22#include <plat/cpu-freq-core.h>
23
24static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
25 { .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
26 { .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */
27 { .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */
28 { .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */
29 { .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */
30 { .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */
31 { .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */
32 { .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */
33 { .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */
34 { .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */
35 { .frequency = 190000000, .index = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */
36 { .frequency = 200000000, .index = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */
37 { .frequency = 210000000, .index = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */
38 { .frequency = 220000000, .index = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */
39 { .frequency = 230000000, .index = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */
40 { .frequency = 240000000, .index = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */
41 { .frequency = 300000000, .index = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */
42 { .frequency = 310000000, .index = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */
43 { .frequency = 320000000, .index = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */
44 { .frequency = 330000000, .index = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */
45 { .frequency = 340000000, .index = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */
46 { .frequency = 350000000, .index = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */
47 { .frequency = 360000000, .index = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */
48 { .frequency = 370000000, .index = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */
49 { .frequency = 380000000, .index = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */
50 { .frequency = 390000000, .index = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */
51 { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
52};
53
54static int s3c2440_plls12_add(struct sys_device *dev)
55{
56 struct clk *xtal_clk;
57 unsigned long xtal;
58
59 xtal_clk = clk_get(NULL, "xtal");
60 if (IS_ERR(xtal_clk))
61 return PTR_ERR(xtal_clk);
62
63 xtal = clk_get_rate(xtal_clk);
64 clk_put(xtal_clk);
65
66 if (xtal == 12000000) {
67 printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
68 return s3c_plltab_register(s3c2440_plls_12,
69 ARRAY_SIZE(s3c2440_plls_12));
70 }
71
72 return 0;
73}
74
75static struct sysdev_driver s3c2440_plls12_drv = {
76 .add = s3c2440_plls12_add,
77};
78
79static int __init s3c2440_pll_12mhz(void)
80{
81 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_plls12_drv);
82
83}
84
85arch_initcall(s3c2440_pll_12mhz);
86
87static struct sysdev_driver s3c2442_plls12_drv = {
88 .add = s3c2440_plls12_add,
89};
90
91static int __init s3c2442_pll_12mhz(void)
92{
93 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv);
94
95}
96
97arch_initcall(s3c2442_pll_12mhz);
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c b/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
deleted file mode 100644
index 7679af13a94d..000000000000
--- a/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
+++ /dev/null
@@ -1,127 +0,0 @@
1/* arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
2 *
3 * Copyright (c) 2006-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 * Vincent Sanders <vince@arm.linux.org.uk>
7 *
8 * S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/sysdev.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20
21#include <plat/cpu.h>
22#include <plat/cpu-freq-core.h>
23
24static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
25 { .frequency = 78019200, .index = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */
26 { .frequency = 84067200, .index = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */
27 { .frequency = 90115200, .index = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */
28 { .frequency = 96163200, .index = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */
29 { .frequency = 102135600, .index = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */
30 { .frequency = 108259200, .index = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */
31 { .frequency = 114307200, .index = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */
32 { .frequency = 120234240, .index = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */
33 { .frequency = 126161280, .index = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */
34 { .frequency = 132088320, .index = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */
35 { .frequency = 138015360, .index = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */
36 { .frequency = 144789120, .index = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */
37 { .frequency = 150100363, .index = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */
38 { .frequency = 156038400, .index = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */
39 { .frequency = 162086400, .index = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */
40 { .frequency = 168134400, .index = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */
41 { .frequency = 174048000, .index = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */
42 { .frequency = 180230400, .index = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */
43 { .frequency = 186278400, .index = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */
44 { .frequency = 192326400, .index = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */
45 { .frequency = 198132480, .index = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */
46 { .frequency = 204271200, .index = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */
47 { .frequency = 210268800, .index = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */
48 { .frequency = 216518400, .index = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */
49 { .frequency = 222264000, .index = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */
50 { .frequency = 228614400, .index = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */
51 { .frequency = 234259200, .index = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */
52 { .frequency = 240468480, .index = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */
53 { .frequency = 246960000, .index = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */
54 { .frequency = 252322560, .index = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */
55 { .frequency = 258249600, .index = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */
56 { .frequency = 264176640, .index = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */
57 { .frequency = 270950400, .index = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */
58 { .frequency = 276030720, .index = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */
59 { .frequency = 282240000, .index = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */
60 { .frequency = 289578240, .index = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */
61 { .frequency = 294235200, .index = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */
62 { .frequency = 300200727, .index = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */
63 { .frequency = 306358690, .index = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */
64 { .frequency = 312076800, .index = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */
65 { .frequency = 318366720, .index = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */
66 { .frequency = 324172800, .index = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */
67 { .frequency = 330220800, .index = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */
68 { .frequency = 336268800, .index = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */
69 { .frequency = 342074880, .index = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */
70 { .frequency = 348096000, .index = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */
71 { .frequency = 355622400, .index = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */
72 { .frequency = 360460800, .index = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */
73 { .frequency = 366206400, .index = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */
74 { .frequency = 372556800, .index = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */
75 { .frequency = 378201600, .index = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */
76 { .frequency = 384652800, .index = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */
77 { .frequency = 391608000, .index = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */
78 { .frequency = 396264960, .index = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */
79 { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */
80};
81
82static int s3c2440_plls169344_add(struct sys_device *dev)
83{
84 struct clk *xtal_clk;
85 unsigned long xtal;
86
87 xtal_clk = clk_get(NULL, "xtal");
88 if (IS_ERR(xtal_clk))
89 return PTR_ERR(xtal_clk);
90
91 xtal = clk_get_rate(xtal_clk);
92 clk_put(xtal_clk);
93
94 if (xtal == 169344000) {
95 printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n");
96 return s3c_plltab_register(s3c2440_plls_169344,
97 ARRAY_SIZE(s3c2440_plls_169344));
98 }
99
100 return 0;
101}
102
103static struct sysdev_driver s3c2440_plls169344_drv = {
104 .add = s3c2440_plls169344_add,
105};
106
107static int __init s3c2440_pll_16934400(void)
108{
109 return sysdev_driver_register(&s3c2440_sysclass,
110 &s3c2440_plls169344_drv);
111
112}
113
114arch_initcall(s3c2440_pll_16934400);
115
116static struct sysdev_driver s3c2442_plls169344_drv = {
117 .add = s3c2440_plls169344_add,
118};
119
120static int __init s3c2442_pll_16934400(void)
121{
122 return sysdev_driver_register(&s3c2442_sysclass,
123 &s3c2442_plls169344_drv);
124
125}
126
127arch_initcall(s3c2442_pll_16934400);
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c
deleted file mode 100644
index 79371091aa38..000000000000
--- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
2 *
3 * Copyright (c) 2004-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440/S3C2442 Common clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/clk.h>
35#include <linux/io.h>
36
37#include <mach/hardware.h>
38#include <asm/atomic.h>
39#include <asm/irq.h>
40
41#include <mach/regs-clock.h>
42
43#include <plat/clock.h>
44#include <plat/cpu.h>
45
46static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
47{
48 unsigned long camdivn;
49 unsigned long dvs;
50
51 if (parent == &clk_f)
52 dvs = 0;
53 else if (parent == &clk_h)
54 dvs = S3C2440_CAMDIVN_DVSEN;
55 else
56 return -EINVAL;
57
58 clk->parent = parent;
59
60 camdivn = __raw_readl(S3C2440_CAMDIVN);
61 camdivn &= ~S3C2440_CAMDIVN_DVSEN;
62 camdivn |= dvs;
63 __raw_writel(camdivn, S3C2440_CAMDIVN);
64
65 return 0;
66}
67
68static struct clk clk_arm = {
69 .name = "armclk",
70 .id = -1,
71 .set_parent = s3c2440_setparent_armclk,
72};
73
74static int s3c244x_clk_add(struct sys_device *sysdev)
75{
76 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
77 unsigned long clkdivn;
78 struct clk *clock_upll;
79 int ret;
80
81 printk("S3C244X: Clock Support, DVS %s\n",
82 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
83
84 clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
85
86 ret = s3c24xx_register_clock(&clk_arm);
87 if (ret < 0) {
88 printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret);
89 return ret;
90 }
91
92 clock_upll = clk_get(NULL, "upll");
93 if (IS_ERR(clock_upll)) {
94 printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
95 return -ENOENT;
96 }
97
98 /* check rate of UPLL, and if it is near 96MHz, then change
99 * to using half the UPLL rate for the system */
100
101 if (clk_get_rate(clock_upll) > (94 * MHZ)) {
102 clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
103
104 spin_lock(&clocks_lock);
105
106 clkdivn = __raw_readl(S3C2410_CLKDIVN);
107 clkdivn |= S3C2440_CLKDIVN_UCLK;
108 __raw_writel(clkdivn, S3C2410_CLKDIVN);
109
110 spin_unlock(&clocks_lock);
111 }
112
113 return 0;
114}
115
116static struct sysdev_driver s3c2440_clk_driver = {
117 .add = s3c244x_clk_add,
118};
119
120static int s3c2440_clk_init(void)
121{
122 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
123}
124
125arch_initcall(s3c2440_clk_init);
126
127static struct sysdev_driver s3c2442_clk_driver = {
128 .add = s3c244x_clk_add,
129};
130
131static int s3c2442_clk_init(void)
132{
133 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
134}
135
136arch_initcall(s3c2442_clk_init);
diff --git a/arch/arm/plat-s3c24xx/s3c244x-irq.c b/arch/arm/plat-s3c24xx/s3c244x-irq.c
deleted file mode 100644
index a75c0c2431ea..000000000000
--- a/arch/arm/plat-s3c24xx/s3c244x-irq.c
+++ /dev/null
@@ -1,142 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/sysdev.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h>
36
37#include <plat/cpu.h>
38#include <plat/pm.h>
39#include <plat/irq.h>
40
41/* camera irq */
42
43static void s3c_irq_demux_cam(unsigned int irq,
44 struct irq_desc *desc)
45{
46 unsigned int subsrc, submsk;
47
48 /* read the current pending interrupts, and the mask
49 * for what it is available */
50
51 subsrc = __raw_readl(S3C2410_SUBSRCPND);
52 submsk = __raw_readl(S3C2410_INTSUBMSK);
53
54 subsrc &= ~submsk;
55 subsrc >>= 11;
56 subsrc &= 3;
57
58 if (subsrc != 0) {
59 if (subsrc & 1) {
60 generic_handle_irq(IRQ_S3C2440_CAM_C);
61 }
62 if (subsrc & 2) {
63 generic_handle_irq(IRQ_S3C2440_CAM_P);
64 }
65 }
66}
67
68#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
69
70static void
71s3c_irq_cam_mask(unsigned int irqno)
72{
73 s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
74}
75
76static void
77s3c_irq_cam_unmask(unsigned int irqno)
78{
79 s3c_irqsub_unmask(irqno, INTMSK_CAM);
80}
81
82static void
83s3c_irq_cam_ack(unsigned int irqno)
84{
85 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
86}
87
88static struct irq_chip s3c_irq_cam = {
89 .mask = s3c_irq_cam_mask,
90 .unmask = s3c_irq_cam_unmask,
91 .ack = s3c_irq_cam_ack,
92};
93
94static int s3c244x_irq_add(struct sys_device *sysdev)
95{
96 unsigned int irqno;
97
98 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
99 set_irq_handler(IRQ_NFCON, handle_level_irq);
100 set_irq_flags(IRQ_NFCON, IRQF_VALID);
101
102 /* add chained handler for camera */
103
104 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
105 set_irq_handler(IRQ_CAM, handle_level_irq);
106 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
107
108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
109 set_irq_chip(irqno, &s3c_irq_cam);
110 set_irq_handler(irqno, handle_level_irq);
111 set_irq_flags(irqno, IRQF_VALID);
112 }
113
114 return 0;
115}
116
117static struct sysdev_driver s3c2440_irq_driver = {
118 .add = s3c244x_irq_add,
119 .suspend = s3c24xx_irq_suspend,
120 .resume = s3c24xx_irq_resume,
121};
122
123static int s3c2440_irq_init(void)
124{
125 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
126}
127
128arch_initcall(s3c2440_irq_init);
129
130static struct sysdev_driver s3c2442_irq_driver = {
131 .add = s3c244x_irq_add,
132 .suspend = s3c24xx_irq_suspend,
133 .resume = s3c24xx_irq_resume,
134};
135
136
137static int s3c2442_irq_init(void)
138{
139 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver);
140}
141
142arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
deleted file mode 100644
index 12623a474b54..000000000000
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ /dev/null
@@ -1,196 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/sysdev.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <plat/cpu-freq.h>
33
34#include <mach/regs-clock.h>
35#include <plat/regs-serial.h>
36#include <mach/regs-gpio.h>
37#include <mach/regs-gpioj.h>
38#include <mach/regs-dsc.h>
39
40#include <plat/s3c2410.h>
41#include <plat/s3c2440.h>
42#include "s3c244x.h"
43#include <plat/clock.h>
44#include <plat/devs.h>
45#include <plat/cpu.h>
46#include <plat/pm.h>
47#include <plat/pll.h>
48
49static struct map_desc s3c244x_iodesc[] __initdata = {
50 IODESC_ENT(CLKPWR),
51 IODESC_ENT(TIMER),
52 IODESC_ENT(WATCHDOG),
53};
54
55/* uart initialisation */
56
57void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
58{
59 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
60}
61
62void __init s3c244x_map_io(void)
63{
64 /* register our io-tables */
65
66 iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
67
68 /* rename any peripherals used differing from the s3c2410 */
69
70 s3c_device_sdi.name = "s3c2440-sdi";
71 s3c_device_i2c0.name = "s3c2440-i2c";
72 s3c_device_nand.name = "s3c2440-nand";
73 s3c_device_ts.name = "s3c2440-ts";
74 s3c_device_usbgadget.name = "s3c2440-usbgadget";
75}
76
77void __init_or_cpufreq s3c244x_setup_clocks(void)
78{
79 struct clk *xtal_clk;
80 unsigned long clkdiv;
81 unsigned long camdiv;
82 unsigned long xtal;
83 unsigned long hclk, fclk, pclk;
84 int hdiv = 1;
85
86 xtal_clk = clk_get(NULL, "xtal");
87 xtal = clk_get_rate(xtal_clk);
88 clk_put(xtal_clk);
89
90 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
91
92 clkdiv = __raw_readl(S3C2410_CLKDIVN);
93 camdiv = __raw_readl(S3C2440_CAMDIVN);
94
95 /* work out clock scalings */
96
97 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
98 case S3C2440_CLKDIVN_HDIVN_1:
99 hdiv = 1;
100 break;
101
102 case S3C2440_CLKDIVN_HDIVN_2:
103 hdiv = 2;
104 break;
105
106 case S3C2440_CLKDIVN_HDIVN_4_8:
107 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
108 break;
109
110 case S3C2440_CLKDIVN_HDIVN_3_6:
111 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
112 break;
113 }
114
115 hclk = fclk / hdiv;
116 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
117
118 /* print brief summary of clocks, etc */
119
120 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
121 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
122
123 s3c24xx_setup_clocks(fclk, hclk, pclk);
124}
125
126void __init s3c244x_init_clocks(int xtal)
127{
128 /* initialise the clocks here, to allow other things like the
129 * console to use them, and to add new ones after the initialisation
130 */
131
132 s3c24xx_register_baseclocks(xtal);
133 s3c244x_setup_clocks();
134 s3c2410_baseclk_add();
135}
136
137#ifdef CONFIG_PM
138
139static struct sleep_save s3c244x_sleep[] = {
140 SAVE_ITEM(S3C2440_DSC0),
141 SAVE_ITEM(S3C2440_DSC1),
142 SAVE_ITEM(S3C2440_GPJDAT),
143 SAVE_ITEM(S3C2440_GPJCON),
144 SAVE_ITEM(S3C2440_GPJUP)
145};
146
147static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
148{
149 s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
150 return 0;
151}
152
153static int s3c244x_resume(struct sys_device *dev)
154{
155 s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
156 return 0;
157}
158
159#else
160#define s3c244x_suspend NULL
161#define s3c244x_resume NULL
162#endif
163
164/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
165
166struct sysdev_class s3c2440_sysclass = {
167 .name = "s3c2440-core",
168 .suspend = s3c244x_suspend,
169 .resume = s3c244x_resume
170};
171
172struct sysdev_class s3c2442_sysclass = {
173 .name = "s3c2442-core",
174 .suspend = s3c244x_suspend,
175 .resume = s3c244x_resume
176};
177
178/* need to register class before we actually register the device, and
179 * we also need to ensure that it has been initialised before any of the
180 * drivers even try to use it (even if not on an s3c2440 based system)
181 * as a driver which may support both 2410 and 2440 may try and use it.
182*/
183
184static int __init s3c2440_core_init(void)
185{
186 return sysdev_class_register(&s3c2440_sysclass);
187}
188
189core_initcall(s3c2440_core_init);
190
191static int __init s3c2442_core_init(void)
192{
193 return sysdev_class_register(&s3c2442_sysclass);
194}
195
196core_initcall(s3c2442_core_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 22:27:10 -0400