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-rw-r--r--arch/arm/plat-s3c24xx/Kconfig99
-rw-r--r--arch/arm/plat-s3c24xx/Makefile30
-rw-r--r--arch/arm/plat-s3c24xx/clock.c449
-rw-r--r--arch/arm/plat-s3c24xx/common-smdk.c200
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c368
-rw-r--r--arch/arm/plat-s3c24xx/devs.c600
-rw-r--r--arch/arm/plat-s3c24xx/dma.c1499
-rw-r--r--arch/arm/plat-s3c24xx/gpio.c188
-rw-r--r--arch/arm/plat-s3c24xx/irq.c801
-rw-r--r--arch/arm/plat-s3c24xx/pm-simtec.c66
-rw-r--r--arch/arm/plat-s3c24xx/pm.c659
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x-irq.c146
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x.c184
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x.h25
-rw-r--r--arch/arm/plat-s3c24xx/sleep.S157
-rw-r--r--arch/arm/plat-s3c24xx/time.c262
16 files changed, 5733 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
new file mode 100644
index 000000000000..e22343160634
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -0,0 +1,99 @@
1# arch/arm/plat-s3c24xx/Kconfig
2#
3# Copyright 2007 Simtec Electronics
4#
5# Licensed under GPLv2
6
7config PLAT_S3C24XX
8 bool
9 depends on ARCH_S3C2410
10 default y if ARCH_S3C2410
11 help
12 Base platform code for any Samsung S3C device
13
14if PLAT_S3C24XX
15
16config CPU_S3C244X
17 bool
18 depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
19 help
20 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
21
22config PM_SIMTEC
23 bool
24 help
25 Common power management code for systems that are
26 compatible with the Simtec style of power management
27
28config S3C2410_BOOT_WATCHDOG
29 bool "S3C2410 Initialisation watchdog"
30 depends on ARCH_S3C2410 && S3C2410_WATCHDOG
31 help
32 Say y to enable the watchdog during the kernel decompression
33 stage. If the kernel fails to uncompress, then the watchdog
34 will trigger a reset and the system should restart.
35
36config S3C2410_BOOT_ERROR_RESET
37 bool "S3C2410 Reboot on decompression error"
38 depends on ARCH_S3C2410
39 help
40 Say y here to use the watchdog to reset the system if the
41 kernel decompressor detects an error during decompression.
42
43config S3C2410_PM_DEBUG
44 bool "S3C2410 PM Suspend debug"
45 depends on ARCH_S3C2410 && PM
46 help
47 Say Y here if you want verbose debugging from the PM Suspend and
48 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
49 for more information.
50
51config S3C2410_PM_CHECK
52 bool "S3C2410 PM Suspend Memory CRC"
53 depends on ARCH_S3C2410 && PM && CRC32
54 help
55 Enable the PM code's memory area checksum over sleep. This option
56 will generate CRCs of all blocks of memory, and store them before
57 going to sleep. The blocks are then checked on resume for any
58 errors.
59
60config S3C2410_PM_CHECK_CHUNKSIZE
61 int "S3C2410 PM Suspend CRC Chunksize (KiB)"
62 depends on ARCH_S3C2410 && PM && S3C2410_PM_CHECK
63 default 64
64 help
65 Set the chunksize in Kilobytes of the CRC for checking memory
66 corruption over suspend and resume. A smaller value will mean that
67 the CRC data block will take more memory, but wil identify any
68 faults with better precision.
69
70config S3C2410_LOWLEVEL_UART_PORT
71 int "S3C2410 UART to use for low-level messages"
72 default 0
73 help
74 Choice of which UART port to use for the low-level messages,
75 such as the `Uncompressing...` at start time. The value of
76 this configuration should be between zero and two. The port
77 must have been initialised by the boot-loader before use.
78
79config S3C2410_DMA
80 bool "S3C2410 DMA support"
81 depends on ARCH_S3C2410
82 help
83 S3C2410 DMA support. This is needed for drivers like sound which
84 use the S3C2410's DMA system to move data to and from the
85 peripheral blocks.
86
87config S3C2410_DMA_DEBUG
88 bool "S3C2410 DMA support debug"
89 depends on ARCH_S3C2410 && S3C2410_DMA
90 help
91 Enable debugging output for the DMA code. This option sends info
92 to the kernel log, at priority KERN_DEBUG.
93
94config MACH_SMDK
95 bool
96 help
97 Common machine code for SMDK2410 and SMDK2440
98
99endif
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
new file mode 100644
index 000000000000..8e5ccaa1f03c
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -0,0 +1,30 @@
1# arch/arm/plat-s3c24xx/Makefile
2#
3# Copyright 2007 Simtec Electronics
4#
5# Licensed under GPLv2
6
7obj-y :=
8obj-m :=
9obj-n :=
10obj- :=
11
12
13# Core files
14
15obj-y += cpu.o
16obj-y += irq.o
17obj-y += devs.o
18obj-y += gpio.o
19obj-y += time.o
20obj-y += clock.o
21
22# Architecture dependant builds
23
24obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
25obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o
26obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
27obj-$(CONFIG_PM) += pm.o
28obj-$(CONFIG_PM) += sleep.o
29obj-$(CONFIG_S3C2410_DMA) += dma.o
30obj-$(CONFIG_MACH_SMDK) += common-smdk.o
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
new file mode 100644
index 000000000000..d3dc03a7383a
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -0,0 +1,449 @@
1/* linux/arch/arm/plat-s3c24xx/clock.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX Core clock control support
7 *
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
9 **
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27*/
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/list.h>
33#include <linux/errno.h>
34#include <linux/err.h>
35#include <linux/platform_device.h>
36#include <linux/sysdev.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/clk.h>
40#include <linux/mutex.h>
41#include <linux/delay.h>
42
43#include <asm/hardware.h>
44#include <asm/irq.h>
45#include <asm/io.h>
46
47#include <asm/arch/regs-clock.h>
48#include <asm/arch/regs-gpio.h>
49
50#include <asm/plat-s3c24xx/clock.h>
51#include <asm/plat-s3c24xx/cpu.h>
52
53/* clock information */
54
55static LIST_HEAD(clocks);
56
57DEFINE_MUTEX(clocks_mutex);
58
59/* enable and disable calls for use with the clk struct */
60
61static int clk_null_enable(struct clk *clk, int enable)
62{
63 return 0;
64}
65
66/* Clock API calls */
67
68struct clk *clk_get(struct device *dev, const char *id)
69{
70 struct clk *p;
71 struct clk *clk = ERR_PTR(-ENOENT);
72 int idno;
73
74 if (dev == NULL || dev->bus != &platform_bus_type)
75 idno = -1;
76 else
77 idno = to_platform_device(dev)->id;
78
79 mutex_lock(&clocks_mutex);
80
81 list_for_each_entry(p, &clocks, list) {
82 if (p->id == idno &&
83 strcmp(id, p->name) == 0 &&
84 try_module_get(p->owner)) {
85 clk = p;
86 break;
87 }
88 }
89
90 /* check for the case where a device was supplied, but the
91 * clock that was being searched for is not device specific */
92
93 if (IS_ERR(clk)) {
94 list_for_each_entry(p, &clocks, list) {
95 if (p->id == -1 && strcmp(id, p->name) == 0 &&
96 try_module_get(p->owner)) {
97 clk = p;
98 break;
99 }
100 }
101 }
102
103 mutex_unlock(&clocks_mutex);
104 return clk;
105}
106
107void clk_put(struct clk *clk)
108{
109 module_put(clk->owner);
110}
111
112int clk_enable(struct clk *clk)
113{
114 if (IS_ERR(clk) || clk == NULL)
115 return -EINVAL;
116
117 clk_enable(clk->parent);
118
119 mutex_lock(&clocks_mutex);
120
121 if ((clk->usage++) == 0)
122 (clk->enable)(clk, 1);
123
124 mutex_unlock(&clocks_mutex);
125 return 0;
126}
127
128void clk_disable(struct clk *clk)
129{
130 if (IS_ERR(clk) || clk == NULL)
131 return;
132
133 mutex_lock(&clocks_mutex);
134
135 if ((--clk->usage) == 0)
136 (clk->enable)(clk, 0);
137
138 mutex_unlock(&clocks_mutex);
139 clk_disable(clk->parent);
140}
141
142
143unsigned long clk_get_rate(struct clk *clk)
144{
145 if (IS_ERR(clk))
146 return 0;
147
148 if (clk->rate != 0)
149 return clk->rate;
150
151 if (clk->get_rate != NULL)
152 return (clk->get_rate)(clk);
153
154 if (clk->parent != NULL)
155 return clk_get_rate(clk->parent);
156
157 return clk->rate;
158}
159
160long clk_round_rate(struct clk *clk, unsigned long rate)
161{
162 if (!IS_ERR(clk) && clk->round_rate)
163 return (clk->round_rate)(clk, rate);
164
165 return rate;
166}
167
168int clk_set_rate(struct clk *clk, unsigned long rate)
169{
170 int ret;
171
172 if (IS_ERR(clk))
173 return -EINVAL;
174
175 mutex_lock(&clocks_mutex);
176 ret = (clk->set_rate)(clk, rate);
177 mutex_unlock(&clocks_mutex);
178
179 return ret;
180}
181
182struct clk *clk_get_parent(struct clk *clk)
183{
184 return clk->parent;
185}
186
187int clk_set_parent(struct clk *clk, struct clk *parent)
188{
189 int ret = 0;
190
191 if (IS_ERR(clk))
192 return -EINVAL;
193
194 mutex_lock(&clocks_mutex);
195
196 if (clk->set_parent)
197 ret = (clk->set_parent)(clk, parent);
198
199 mutex_unlock(&clocks_mutex);
200
201 return ret;
202}
203
204EXPORT_SYMBOL(clk_get);
205EXPORT_SYMBOL(clk_put);
206EXPORT_SYMBOL(clk_enable);
207EXPORT_SYMBOL(clk_disable);
208EXPORT_SYMBOL(clk_get_rate);
209EXPORT_SYMBOL(clk_round_rate);
210EXPORT_SYMBOL(clk_set_rate);
211EXPORT_SYMBOL(clk_get_parent);
212EXPORT_SYMBOL(clk_set_parent);
213
214/* base clocks */
215
216struct clk clk_xtal = {
217 .name = "xtal",
218 .id = -1,
219 .rate = 0,
220 .parent = NULL,
221 .ctrlbit = 0,
222};
223
224struct clk clk_mpll = {
225 .name = "mpll",
226 .id = -1,
227};
228
229struct clk clk_upll = {
230 .name = "upll",
231 .id = -1,
232 .parent = NULL,
233 .ctrlbit = 0,
234};
235
236struct clk clk_f = {
237 .name = "fclk",
238 .id = -1,
239 .rate = 0,
240 .parent = &clk_mpll,
241 .ctrlbit = 0,
242};
243
244struct clk clk_h = {
245 .name = "hclk",
246 .id = -1,
247 .rate = 0,
248 .parent = NULL,
249 .ctrlbit = 0,
250};
251
252struct clk clk_p = {
253 .name = "pclk",
254 .id = -1,
255 .rate = 0,
256 .parent = NULL,
257 .ctrlbit = 0,
258};
259
260struct clk clk_usb_bus = {
261 .name = "usb-bus",
262 .id = -1,
263 .rate = 0,
264 .parent = &clk_upll,
265};
266
267/* clocks that could be registered by external code */
268
269static int s3c24xx_dclk_enable(struct clk *clk, int enable)
270{
271 unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
272
273 if (enable)
274 dclkcon |= clk->ctrlbit;
275 else
276 dclkcon &= ~clk->ctrlbit;
277
278 __raw_writel(dclkcon, S3C24XX_DCLKCON);
279
280 return 0;
281}
282
283static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
284{
285 unsigned long dclkcon;
286 unsigned int uclk;
287
288 if (parent == &clk_upll)
289 uclk = 1;
290 else if (parent == &clk_p)
291 uclk = 0;
292 else
293 return -EINVAL;
294
295 clk->parent = parent;
296
297 dclkcon = __raw_readl(S3C24XX_DCLKCON);
298
299 if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
300 if (uclk)
301 dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
302 else
303 dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
304 } else {
305 if (uclk)
306 dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
307 else
308 dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
309 }
310
311 __raw_writel(dclkcon, S3C24XX_DCLKCON);
312
313 return 0;
314}
315
316
317static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
318{
319 unsigned long mask;
320 unsigned long source;
321
322 /* calculate the MISCCR setting for the clock */
323
324 if (parent == &clk_xtal)
325 source = S3C2410_MISCCR_CLK0_MPLL;
326 else if (parent == &clk_upll)
327 source = S3C2410_MISCCR_CLK0_UPLL;
328 else if (parent == &clk_f)
329 source = S3C2410_MISCCR_CLK0_FCLK;
330 else if (parent == &clk_h)
331 source = S3C2410_MISCCR_CLK0_HCLK;
332 else if (parent == &clk_p)
333 source = S3C2410_MISCCR_CLK0_PCLK;
334 else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
335 source = S3C2410_MISCCR_CLK0_DCLK0;
336 else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
337 source = S3C2410_MISCCR_CLK0_DCLK0;
338 else
339 return -EINVAL;
340
341 clk->parent = parent;
342
343 if (clk == &s3c24xx_dclk0)
344 mask = S3C2410_MISCCR_CLK0_MASK;
345 else {
346 source <<= 4;
347 mask = S3C2410_MISCCR_CLK1_MASK;
348 }
349
350 s3c2410_modify_misccr(mask, source);
351 return 0;
352}
353
354/* external clock definitions */
355
356struct clk s3c24xx_dclk0 = {
357 .name = "dclk0",
358 .id = -1,
359 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
360 .enable = s3c24xx_dclk_enable,
361 .set_parent = s3c24xx_dclk_setparent,
362};
363
364struct clk s3c24xx_dclk1 = {
365 .name = "dclk1",
366 .id = -1,
367 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
368 .enable = s3c24xx_dclk_enable,
369 .set_parent = s3c24xx_dclk_setparent,
370};
371
372struct clk s3c24xx_clkout0 = {
373 .name = "clkout0",
374 .id = -1,
375 .set_parent = s3c24xx_clkout_setparent,
376};
377
378struct clk s3c24xx_clkout1 = {
379 .name = "clkout1",
380 .id = -1,
381 .set_parent = s3c24xx_clkout_setparent,
382};
383
384struct clk s3c24xx_uclk = {
385 .name = "uclk",
386 .id = -1,
387};
388
389/* initialise the clock system */
390
391int s3c24xx_register_clock(struct clk *clk)
392{
393 clk->owner = THIS_MODULE;
394
395 if (clk->enable == NULL)
396 clk->enable = clk_null_enable;
397
398 /* add to the list of available clocks */
399
400 mutex_lock(&clocks_mutex);
401 list_add(&clk->list, &clocks);
402 mutex_unlock(&clocks_mutex);
403
404 return 0;
405}
406
407/* initalise all the clocks */
408
409int __init s3c24xx_setup_clocks(unsigned long xtal,
410 unsigned long fclk,
411 unsigned long hclk,
412 unsigned long pclk)
413{
414 printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
415
416 /* initialise the main system clocks */
417
418 clk_xtal.rate = xtal;
419 clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
420
421 clk_mpll.rate = fclk;
422 clk_h.rate = hclk;
423 clk_p.rate = pclk;
424 clk_f.rate = fclk;
425
426 /* assume uart clocks are correctly setup */
427
428 /* register our clocks */
429
430 if (s3c24xx_register_clock(&clk_xtal) < 0)
431 printk(KERN_ERR "failed to register master xtal\n");
432
433 if (s3c24xx_register_clock(&clk_mpll) < 0)
434 printk(KERN_ERR "failed to register mpll clock\n");
435
436 if (s3c24xx_register_clock(&clk_upll) < 0)
437 printk(KERN_ERR "failed to register upll clock\n");
438
439 if (s3c24xx_register_clock(&clk_f) < 0)
440 printk(KERN_ERR "failed to register cpu fclk\n");
441
442 if (s3c24xx_register_clock(&clk_h) < 0)
443 printk(KERN_ERR "failed to register cpu hclk\n");
444
445 if (s3c24xx_register_clock(&clk_p) < 0)
446 printk(KERN_ERR "failed to register cpu pclk\n");
447
448 return 0;
449}
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
new file mode 100644
index 000000000000..908efa7d745f
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -0,0 +1,200 @@
1/* linux/arch/arm/plat-s3c24xx/common-smdk.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Common code for SMDK2410 and SMDK2440 boards
7 *
8 * http://www.fluff.org/ben/smdk2440/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/nand.h>
25#include <linux/mtd/nand_ecc.h>
26#include <linux/mtd/partitions.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/irq.h>
31
32#include <asm/hardware.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35
36#include <asm/arch/regs-gpio.h>
37#include <asm/arch/leds-gpio.h>
38
39#include <asm/arch/nand.h>
40
41#include <asm/plat-s3c24xx/common-smdk.h>
42#include <asm/plat-s3c24xx/devs.h>
43#include <asm/plat-s3c24xx/pm.h>
44
45/* LED devices */
46
47static struct s3c24xx_led_platdata smdk_pdata_led4 = {
48 .gpio = S3C2410_GPF4,
49 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
50 .name = "led4",
51 .def_trigger = "timer",
52};
53
54static struct s3c24xx_led_platdata smdk_pdata_led5 = {
55 .gpio = S3C2410_GPF5,
56 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
57 .name = "led5",
58 .def_trigger = "nand-disk",
59};
60
61static struct s3c24xx_led_platdata smdk_pdata_led6 = {
62 .gpio = S3C2410_GPF6,
63 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
64 .name = "led6",
65};
66
67static struct s3c24xx_led_platdata smdk_pdata_led7 = {
68 .gpio = S3C2410_GPF7,
69 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
70 .name = "led7",
71};
72
73static struct platform_device smdk_led4 = {
74 .name = "s3c24xx_led",
75 .id = 0,
76 .dev = {
77 .platform_data = &smdk_pdata_led4,
78 },
79};
80
81static struct platform_device smdk_led5 = {
82 .name = "s3c24xx_led",
83 .id = 1,
84 .dev = {
85 .platform_data = &smdk_pdata_led5,
86 },
87};
88
89static struct platform_device smdk_led6 = {
90 .name = "s3c24xx_led",
91 .id = 2,
92 .dev = {
93 .platform_data = &smdk_pdata_led6,
94 },
95};
96
97static struct platform_device smdk_led7 = {
98 .name = "s3c24xx_led",
99 .id = 3,
100 .dev = {
101 .platform_data = &smdk_pdata_led7,
102 },
103};
104
105/* NAND parititon from 2.4.18-swl5 */
106
107static struct mtd_partition smdk_default_nand_part[] = {
108 [0] = {
109 .name = "Boot Agent",
110 .size = SZ_16K,
111 .offset = 0,
112 },
113 [1] = {
114 .name = "S3C2410 flash partition 1",
115 .offset = 0,
116 .size = SZ_2M,
117 },
118 [2] = {
119 .name = "S3C2410 flash partition 2",
120 .offset = SZ_4M,
121 .size = SZ_4M,
122 },
123 [3] = {
124 .name = "S3C2410 flash partition 3",
125 .offset = SZ_8M,
126 .size = SZ_2M,
127 },
128 [4] = {
129 .name = "S3C2410 flash partition 4",
130 .offset = SZ_1M * 10,
131 .size = SZ_4M,
132 },
133 [5] = {
134 .name = "S3C2410 flash partition 5",
135 .offset = SZ_1M * 14,
136 .size = SZ_1M * 10,
137 },
138 [6] = {
139 .name = "S3C2410 flash partition 6",
140 .offset = SZ_1M * 24,
141 .size = SZ_1M * 24,
142 },
143 [7] = {
144 .name = "S3C2410 flash partition 7",
145 .offset = SZ_1M * 48,
146 .size = SZ_16M,
147 }
148};
149
150static struct s3c2410_nand_set smdk_nand_sets[] = {
151 [0] = {
152 .name = "NAND",
153 .nr_chips = 1,
154 .nr_partitions = ARRAY_SIZE(smdk_default_nand_part),
155 .partitions = smdk_default_nand_part,
156 },
157};
158
159/* choose a set of timings which should suit most 512Mbit
160 * chips and beyond.
161*/
162
163static struct s3c2410_platform_nand smdk_nand_info = {
164 .tacls = 20,
165 .twrph0 = 60,
166 .twrph1 = 20,
167 .nr_sets = ARRAY_SIZE(smdk_nand_sets),
168 .sets = smdk_nand_sets,
169};
170
171/* devices we initialise */
172
173static struct platform_device __initdata *smdk_devs[] = {
174 &s3c_device_nand,
175 &smdk_led4,
176 &smdk_led5,
177 &smdk_led6,
178 &smdk_led7,
179};
180
181void __init smdk_machine_init(void)
182{
183 /* Configure the LEDs (even if we have no LED support)*/
184
185 s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP);
186 s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP);
187 s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP);
188 s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP);
189
190 s3c2410_gpio_setpin(S3C2410_GPF4, 1);
191 s3c2410_gpio_setpin(S3C2410_GPF5, 1);
192 s3c2410_gpio_setpin(S3C2410_GPF6, 1);
193 s3c2410_gpio_setpin(S3C2410_GPF7, 1);
194
195 s3c_device_nand.dev.platform_data = &smdk_nand_info;
196
197 platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
198
199 s3c2410_pm_init();
200}
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
new file mode 100644
index 000000000000..6a2d1070e5a0
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -0,0 +1,368 @@
1/* linux/arch/arm/plat-s3c24xx/cpu.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX CPU Support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/serial_core.h>
30#include <linux/platform_device.h>
31
32#include <asm/hardware.h>
33#include <asm/irq.h>
34#include <asm/io.h>
35#include <asm/delay.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39
40#include <asm/arch/regs-gpio.h>
41#include <asm/arch/regs-serial.h>
42
43#include <asm/plat-s3c24xx/cpu.h>
44#include <asm/plat-s3c24xx/devs.h>
45#include <asm/plat-s3c24xx/clock.h>
46#include <asm/plat-s3c24xx/s3c2400.h>
47#include <asm/plat-s3c24xx/s3c2410.h>
48#include <asm/plat-s3c24xx/s3c2412.h>
49#include "s3c244x.h"
50#include <asm/plat-s3c24xx/s3c2440.h>
51#include <asm/plat-s3c24xx/s3c2442.h>
52#include <asm/plat-s3c24xx/s3c2443.h>
53
54struct cpu_table {
55 unsigned long idcode;
56 unsigned long idmask;
57 void (*map_io)(struct map_desc *mach_desc, int size);
58 void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
59 void (*init_clocks)(int xtal);
60 int (*init)(void);
61 const char *name;
62};
63
64/* table of supported CPUs */
65
66static const char name_s3c2400[] = "S3C2400";
67static const char name_s3c2410[] = "S3C2410";
68static const char name_s3c2412[] = "S3C2412";
69static const char name_s3c2440[] = "S3C2440";
70static const char name_s3c2442[] = "S3C2442";
71static const char name_s3c2443[] = "S3C2443";
72static const char name_s3c2410a[] = "S3C2410A";
73static const char name_s3c2440a[] = "S3C2440A";
74
75static struct cpu_table cpu_ids[] __initdata = {
76 {
77 .idcode = 0x32410000,
78 .idmask = 0xffffffff,
79 .map_io = s3c2410_map_io,
80 .init_clocks = s3c2410_init_clocks,
81 .init_uarts = s3c2410_init_uarts,
82 .init = s3c2410_init,
83 .name = name_s3c2410
84 },
85 {
86 .idcode = 0x32410002,
87 .idmask = 0xffffffff,
88 .map_io = s3c2410_map_io,
89 .init_clocks = s3c2410_init_clocks,
90 .init_uarts = s3c2410_init_uarts,
91 .init = s3c2410_init,
92 .name = name_s3c2410a
93 },
94 {
95 .idcode = 0x32440000,
96 .idmask = 0xffffffff,
97 .map_io = s3c244x_map_io,
98 .init_clocks = s3c244x_init_clocks,
99 .init_uarts = s3c244x_init_uarts,
100 .init = s3c2440_init,
101 .name = name_s3c2440
102 },
103 {
104 .idcode = 0x32440001,
105 .idmask = 0xffffffff,
106 .map_io = s3c244x_map_io,
107 .init_clocks = s3c244x_init_clocks,
108 .init_uarts = s3c244x_init_uarts,
109 .init = s3c2440_init,
110 .name = name_s3c2440a
111 },
112 {
113 .idcode = 0x32440aaa,
114 .idmask = 0xffffffff,
115 .map_io = s3c244x_map_io,
116 .init_clocks = s3c244x_init_clocks,
117 .init_uarts = s3c244x_init_uarts,
118 .init = s3c2442_init,
119 .name = name_s3c2442
120 },
121 {
122 .idcode = 0x32412001,
123 .idmask = 0xffffffff,
124 .map_io = s3c2412_map_io,
125 .init_clocks = s3c2412_init_clocks,
126 .init_uarts = s3c2412_init_uarts,
127 .init = s3c2412_init,
128 .name = name_s3c2412,
129 },
130 { /* a newer version of the s3c2412 */
131 .idcode = 0x32412003,
132 .idmask = 0xffffffff,
133 .map_io = s3c2412_map_io,
134 .init_clocks = s3c2412_init_clocks,
135 .init_uarts = s3c2412_init_uarts,
136 .init = s3c2412_init,
137 .name = name_s3c2412,
138 },
139 {
140 .idcode = 0x32443001,
141 .idmask = 0xffffffff,
142 .map_io = s3c2443_map_io,
143 .init_clocks = s3c2443_init_clocks,
144 .init_uarts = s3c2443_init_uarts,
145 .init = s3c2443_init,
146 .name = name_s3c2443,
147 },
148 {
149 .idcode = 0x0, /* S3C2400 doesn't have an idcode */
150 .idmask = 0xffffffff,
151 .map_io = s3c2400_map_io,
152 .init_clocks = s3c2400_init_clocks,
153 .init_uarts = s3c2400_init_uarts,
154 .init = s3c2400_init,
155 .name = name_s3c2400
156 },
157};
158
159/* minimal IO mapping */
160
161static struct map_desc s3c_iodesc[] __initdata = {
162 IODESC_ENT(GPIO),
163 IODESC_ENT(IRQ),
164 IODESC_ENT(MEMCTRL),
165 IODESC_ENT(UART)
166};
167
168
169static struct cpu_table *
170s3c_lookup_cpu(unsigned long idcode)
171{
172 struct cpu_table *tab;
173 int count;
174
175 tab = cpu_ids;
176 for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
177 if ((idcode & tab->idmask) == tab->idcode)
178 return tab;
179 }
180
181 return NULL;
182}
183
184/* board information */
185
186static struct s3c24xx_board *board;
187
188void s3c24xx_set_board(struct s3c24xx_board *b)
189{
190 int i;
191
192 board = b;
193
194 if (b->clocks_count != 0) {
195 struct clk **ptr = b->clocks;
196
197 for (i = b->clocks_count; i > 0; i--, ptr++)
198 s3c24xx_register_clock(*ptr);
199 }
200}
201
202/* cpu information */
203
204static struct cpu_table *cpu;
205
206static unsigned long s3c24xx_read_idcode_v5(void)
207{
208#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
209 return __raw_readl(S3C2412_GSTATUS1);
210#else
211 return 1UL; /* don't look like an 2400 */
212#endif
213}
214
215static unsigned long s3c24xx_read_idcode_v4(void)
216{
217#ifndef CONFIG_CPU_S3C2400
218 return __raw_readl(S3C2410_GSTATUS1);
219#else
220 return 0UL;
221#endif
222}
223
224void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
225{
226 unsigned long idcode = 0x0;
227
228 /* initialise the io descriptors we need for initialisation */
229 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
230
231 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
232 idcode = s3c24xx_read_idcode_v5();
233 } else {
234 idcode = s3c24xx_read_idcode_v4();
235 }
236
237 cpu = s3c_lookup_cpu(idcode);
238
239 if (cpu == NULL) {
240 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
241 panic("Unknown S3C24XX CPU");
242 }
243
244 printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
245
246 if (cpu->map_io == NULL || cpu->init == NULL) {
247 printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
248 panic("Unsupported S3C24XX CPU");
249 }
250
251 (cpu->map_io)(mach_desc, size);
252}
253
254/* s3c24xx_init_clocks
255 *
256 * Initialise the clock subsystem and associated information from the
257 * given master crystal value.
258 *
259 * xtal = 0 -> use default PLL crystal value (normally 12MHz)
260 * != 0 -> PLL crystal value in Hz
261*/
262
263void __init s3c24xx_init_clocks(int xtal)
264{
265 if (xtal == 0)
266 xtal = 12*1000*1000;
267
268 if (cpu == NULL)
269 panic("s3c24xx_init_clocks: no cpu setup?\n");
270
271 if (cpu->init_clocks == NULL)
272 panic("s3c24xx_init_clocks: cpu has no clock init\n");
273 else
274 (cpu->init_clocks)(xtal);
275}
276
277/* uart management */
278
279static int nr_uarts __initdata = 0;
280
281static struct s3c2410_uartcfg uart_cfgs[3];
282
283/* s3c24xx_init_uartdevs
284 *
285 * copy the specified platform data and configuration into our central
286 * set of devices, before the data is thrown away after the init process.
287 *
288 * This also fills in the array passed to the serial driver for the
289 * early initialisation of the console.
290*/
291
292void __init s3c24xx_init_uartdevs(char *name,
293 struct s3c24xx_uart_resources *res,
294 struct s3c2410_uartcfg *cfg, int no)
295{
296 struct platform_device *platdev;
297 struct s3c2410_uartcfg *cfgptr = uart_cfgs;
298 struct s3c24xx_uart_resources *resp;
299 int uart;
300
301 memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
302
303 for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
304 platdev = s3c24xx_uart_src[cfgptr->hwport];
305
306 resp = res + cfgptr->hwport;
307
308 s3c24xx_uart_devs[uart] = platdev;
309
310 platdev->name = name;
311 platdev->resource = resp->resources;
312 platdev->num_resources = resp->nr_resources;
313
314 platdev->dev.platform_data = cfgptr;
315 }
316
317 nr_uarts = no;
318}
319
320void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
321{
322 if (cpu == NULL)
323 return;
324
325 if (cpu->init_uarts == NULL) {
326 printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
327 } else
328 (cpu->init_uarts)(cfg, no);
329}
330
331static int __init s3c_arch_init(void)
332{
333 int ret;
334
335 // do the correct init for cpu
336
337 if (cpu == NULL)
338 panic("s3c_arch_init: NULL cpu\n");
339
340 ret = (cpu->init)();
341 if (ret != 0)
342 return ret;
343
344 ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
345 if (ret != 0)
346 return ret;
347
348 if (board != NULL) {
349 struct platform_device **ptr = board->devices;
350 int i;
351
352 for (i = 0; i < board->devices_count; i++, ptr++) {
353 ret = platform_device_register(*ptr);
354
355 if (ret) {
356 printk(KERN_ERR "s3c24xx: failed to add board device %s (%d) @%p\n", (*ptr)->name, ret, *ptr);
357 }
358 }
359
360 /* mask any error, we may not need all these board
361 * devices */
362 ret = 0;
363 }
364
365 return ret;
366}
367
368arch_initcall(s3c_arch_init);
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
new file mode 100644
index 000000000000..0fe53b39cb2f
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -0,0 +1,600 @@
1/* linux/arch/arm/plat-s3c24xx/devs.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Base S3C24XX platform device definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26#include <asm/arch/fb.h>
27#include <asm/hardware.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30
31#include <asm/arch/regs-serial.h>
32#include <asm/arch/udc.h>
33
34#include <asm/plat-s3c24xx/devs.h>
35#include <asm/plat-s3c24xx/cpu.h>
36
37/* Serial port registrations */
38
39static struct resource s3c2410_uart0_resource[] = {
40 [0] = {
41 .start = S3C2410_PA_UART0,
42 .end = S3C2410_PA_UART0 + 0x3fff,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = IRQ_S3CUART_RX0,
47 .end = IRQ_S3CUART_ERR0,
48 .flags = IORESOURCE_IRQ,
49 }
50};
51
52static struct resource s3c2410_uart1_resource[] = {
53 [0] = {
54 .start = S3C2410_PA_UART1,
55 .end = S3C2410_PA_UART1 + 0x3fff,
56 .flags = IORESOURCE_MEM,
57 },
58 [1] = {
59 .start = IRQ_S3CUART_RX1,
60 .end = IRQ_S3CUART_ERR1,
61 .flags = IORESOURCE_IRQ,
62 }
63};
64
65static struct resource s3c2410_uart2_resource[] = {
66 [0] = {
67 .start = S3C2410_PA_UART2,
68 .end = S3C2410_PA_UART2 + 0x3fff,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = IRQ_S3CUART_RX2,
73 .end = IRQ_S3CUART_ERR2,
74 .flags = IORESOURCE_IRQ,
75 }
76};
77
78struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
79 [0] = {
80 .resources = s3c2410_uart0_resource,
81 .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
82 },
83 [1] = {
84 .resources = s3c2410_uart1_resource,
85 .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
86 },
87 [2] = {
88 .resources = s3c2410_uart2_resource,
89 .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
90 },
91};
92
93/* yart devices */
94
95static struct platform_device s3c24xx_uart_device0 = {
96 .id = 0,
97};
98
99static struct platform_device s3c24xx_uart_device1 = {
100 .id = 1,
101};
102
103static struct platform_device s3c24xx_uart_device2 = {
104 .id = 2,
105};
106
107struct platform_device *s3c24xx_uart_src[3] = {
108 &s3c24xx_uart_device0,
109 &s3c24xx_uart_device1,
110 &s3c24xx_uart_device2,
111};
112
113struct platform_device *s3c24xx_uart_devs[3] = {
114};
115
116/* USB Host Controller */
117
118static struct resource s3c_usb_resource[] = {
119 [0] = {
120 .start = S3C24XX_PA_USBHOST,
121 .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
122 .flags = IORESOURCE_MEM,
123 },
124 [1] = {
125 .start = IRQ_USBH,
126 .end = IRQ_USBH,
127 .flags = IORESOURCE_IRQ,
128 }
129};
130
131static u64 s3c_device_usb_dmamask = 0xffffffffUL;
132
133struct platform_device s3c_device_usb = {
134 .name = "s3c2410-ohci",
135 .id = -1,
136 .num_resources = ARRAY_SIZE(s3c_usb_resource),
137 .resource = s3c_usb_resource,
138 .dev = {
139 .dma_mask = &s3c_device_usb_dmamask,
140 .coherent_dma_mask = 0xffffffffUL
141 }
142};
143
144EXPORT_SYMBOL(s3c_device_usb);
145
146/* LCD Controller */
147
148static struct resource s3c_lcd_resource[] = {
149 [0] = {
150 .start = S3C24XX_PA_LCD,
151 .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = IRQ_LCD,
156 .end = IRQ_LCD,
157 .flags = IORESOURCE_IRQ,
158 }
159
160};
161
162static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
163
164struct platform_device s3c_device_lcd = {
165 .name = "s3c2410-lcd",
166 .id = -1,
167 .num_resources = ARRAY_SIZE(s3c_lcd_resource),
168 .resource = s3c_lcd_resource,
169 .dev = {
170 .dma_mask = &s3c_device_lcd_dmamask,
171 .coherent_dma_mask = 0xffffffffUL
172 }
173};
174
175EXPORT_SYMBOL(s3c_device_lcd);
176
177void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
178{
179 struct s3c2410fb_mach_info *npd;
180
181 npd = kmalloc(sizeof(*npd), GFP_KERNEL);
182 if (npd) {
183 memcpy(npd, pd, sizeof(*npd));
184 s3c_device_lcd.dev.platform_data = npd;
185 } else {
186 printk(KERN_ERR "no memory for LCD platform data\n");
187 }
188}
189
190/* NAND Controller */
191
192static struct resource s3c_nand_resource[] = {
193 [0] = {
194 .start = S3C2410_PA_NAND,
195 .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
196 .flags = IORESOURCE_MEM,
197 }
198};
199
200struct platform_device s3c_device_nand = {
201 .name = "s3c2410-nand",
202 .id = -1,
203 .num_resources = ARRAY_SIZE(s3c_nand_resource),
204 .resource = s3c_nand_resource,
205};
206
207EXPORT_SYMBOL(s3c_device_nand);
208
209/* USB Device (Gadget)*/
210
211static struct resource s3c_usbgadget_resource[] = {
212 [0] = {
213 .start = S3C24XX_PA_USBDEV,
214 .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
215 .flags = IORESOURCE_MEM,
216 },
217 [1] = {
218 .start = IRQ_USBD,
219 .end = IRQ_USBD,
220 .flags = IORESOURCE_IRQ,
221 }
222
223};
224
225struct platform_device s3c_device_usbgadget = {
226 .name = "s3c2410-usbgadget",
227 .id = -1,
228 .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
229 .resource = s3c_usbgadget_resource,
230};
231
232EXPORT_SYMBOL(s3c_device_usbgadget);
233
234void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
235{
236 struct s3c2410_udc_mach_info *npd;
237
238 npd = kmalloc(sizeof(*npd), GFP_KERNEL);
239 if (npd) {
240 memcpy(npd, pd, sizeof(*npd));
241 s3c_device_usbgadget.dev.platform_data = npd;
242 } else {
243 printk(KERN_ERR "no memory for udc platform data\n");
244 }
245}
246
247
248/* Watchdog */
249
250static struct resource s3c_wdt_resource[] = {
251 [0] = {
252 .start = S3C24XX_PA_WATCHDOG,
253 .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
254 .flags = IORESOURCE_MEM,
255 },
256 [1] = {
257 .start = IRQ_WDT,
258 .end = IRQ_WDT,
259 .flags = IORESOURCE_IRQ,
260 }
261
262};
263
264struct platform_device s3c_device_wdt = {
265 .name = "s3c2410-wdt",
266 .id = -1,
267 .num_resources = ARRAY_SIZE(s3c_wdt_resource),
268 .resource = s3c_wdt_resource,
269};
270
271EXPORT_SYMBOL(s3c_device_wdt);
272
273/* I2C */
274
275static struct resource s3c_i2c_resource[] = {
276 [0] = {
277 .start = S3C24XX_PA_IIC,
278 .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
279 .flags = IORESOURCE_MEM,
280 },
281 [1] = {
282 .start = IRQ_IIC,
283 .end = IRQ_IIC,
284 .flags = IORESOURCE_IRQ,
285 }
286
287};
288
289struct platform_device s3c_device_i2c = {
290 .name = "s3c2410-i2c",
291 .id = -1,
292 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
293 .resource = s3c_i2c_resource,
294};
295
296EXPORT_SYMBOL(s3c_device_i2c);
297
298/* IIS */
299
300static struct resource s3c_iis_resource[] = {
301 [0] = {
302 .start = S3C24XX_PA_IIS,
303 .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
304 .flags = IORESOURCE_MEM,
305 }
306};
307
308static u64 s3c_device_iis_dmamask = 0xffffffffUL;
309
310struct platform_device s3c_device_iis = {
311 .name = "s3c2410-iis",
312 .id = -1,
313 .num_resources = ARRAY_SIZE(s3c_iis_resource),
314 .resource = s3c_iis_resource,
315 .dev = {
316 .dma_mask = &s3c_device_iis_dmamask,
317 .coherent_dma_mask = 0xffffffffUL
318 }
319};
320
321EXPORT_SYMBOL(s3c_device_iis);
322
323/* RTC */
324
325static struct resource s3c_rtc_resource[] = {
326 [0] = {
327 .start = S3C24XX_PA_RTC,
328 .end = S3C24XX_PA_RTC + 0xff,
329 .flags = IORESOURCE_MEM,
330 },
331 [1] = {
332 .start = IRQ_RTC,
333 .end = IRQ_RTC,
334 .flags = IORESOURCE_IRQ,
335 },
336 [2] = {
337 .start = IRQ_TICK,
338 .end = IRQ_TICK,
339 .flags = IORESOURCE_IRQ
340 }
341};
342
343struct platform_device s3c_device_rtc = {
344 .name = "s3c2410-rtc",
345 .id = -1,
346 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
347 .resource = s3c_rtc_resource,
348};
349
350EXPORT_SYMBOL(s3c_device_rtc);
351
352/* ADC */
353
354static struct resource s3c_adc_resource[] = {
355 [0] = {
356 .start = S3C24XX_PA_ADC,
357 .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
358 .flags = IORESOURCE_MEM,
359 },
360 [1] = {
361 .start = IRQ_TC,
362 .end = IRQ_TC,
363 .flags = IORESOURCE_IRQ,
364 },
365 [2] = {
366 .start = IRQ_ADC,
367 .end = IRQ_ADC,
368 .flags = IORESOURCE_IRQ,
369 }
370
371};
372
373struct platform_device s3c_device_adc = {
374 .name = "s3c2410-adc",
375 .id = -1,
376 .num_resources = ARRAY_SIZE(s3c_adc_resource),
377 .resource = s3c_adc_resource,
378};
379
380/* SDI */
381
382static struct resource s3c_sdi_resource[] = {
383 [0] = {
384 .start = S3C2410_PA_SDI,
385 .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = IRQ_SDI,
390 .end = IRQ_SDI,
391 .flags = IORESOURCE_IRQ,
392 }
393
394};
395
396struct platform_device s3c_device_sdi = {
397 .name = "s3c2410-sdi",
398 .id = -1,
399 .num_resources = ARRAY_SIZE(s3c_sdi_resource),
400 .resource = s3c_sdi_resource,
401};
402
403EXPORT_SYMBOL(s3c_device_sdi);
404
405/* SPI (0) */
406
407static struct resource s3c_spi0_resource[] = {
408 [0] = {
409 .start = S3C24XX_PA_SPI,
410 .end = S3C24XX_PA_SPI + 0x1f,
411 .flags = IORESOURCE_MEM,
412 },
413 [1] = {
414 .start = IRQ_SPI0,
415 .end = IRQ_SPI0,
416 .flags = IORESOURCE_IRQ,
417 }
418
419};
420
421static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
422
423struct platform_device s3c_device_spi0 = {
424 .name = "s3c2410-spi",
425 .id = 0,
426 .num_resources = ARRAY_SIZE(s3c_spi0_resource),
427 .resource = s3c_spi0_resource,
428 .dev = {
429 .dma_mask = &s3c_device_spi0_dmamask,
430 .coherent_dma_mask = 0xffffffffUL
431 }
432};
433
434EXPORT_SYMBOL(s3c_device_spi0);
435
436/* SPI (1) */
437
438static struct resource s3c_spi1_resource[] = {
439 [0] = {
440 .start = S3C24XX_PA_SPI + 0x20,
441 .end = S3C24XX_PA_SPI + 0x20 + 0x1f,
442 .flags = IORESOURCE_MEM,
443 },
444 [1] = {
445 .start = IRQ_SPI1,
446 .end = IRQ_SPI1,
447 .flags = IORESOURCE_IRQ,
448 }
449
450};
451
452static u64 s3c_device_spi1_dmamask = 0xffffffffUL;
453
454struct platform_device s3c_device_spi1 = {
455 .name = "s3c2410-spi",
456 .id = 1,
457 .num_resources = ARRAY_SIZE(s3c_spi1_resource),
458 .resource = s3c_spi1_resource,
459 .dev = {
460 .dma_mask = &s3c_device_spi1_dmamask,
461 .coherent_dma_mask = 0xffffffffUL
462 }
463};
464
465EXPORT_SYMBOL(s3c_device_spi1);
466
467/* pwm timer blocks */
468
469static struct resource s3c_timer0_resource[] = {
470 [0] = {
471 .start = S3C24XX_PA_TIMER + 0x0C,
472 .end = S3C24XX_PA_TIMER + 0x0C + 0xB,
473 .flags = IORESOURCE_MEM,
474 },
475 [1] = {
476 .start = IRQ_TIMER0,
477 .end = IRQ_TIMER0,
478 .flags = IORESOURCE_IRQ,
479 }
480
481};
482
483struct platform_device s3c_device_timer0 = {
484 .name = "s3c2410-timer",
485 .id = 0,
486 .num_resources = ARRAY_SIZE(s3c_timer0_resource),
487 .resource = s3c_timer0_resource,
488};
489
490EXPORT_SYMBOL(s3c_device_timer0);
491
492/* timer 1 */
493
494static struct resource s3c_timer1_resource[] = {
495 [0] = {
496 .start = S3C24XX_PA_TIMER + 0x18,
497 .end = S3C24XX_PA_TIMER + 0x23,
498 .flags = IORESOURCE_MEM,
499 },
500 [1] = {
501 .start = IRQ_TIMER1,
502 .end = IRQ_TIMER1,
503 .flags = IORESOURCE_IRQ,
504 }
505
506};
507
508struct platform_device s3c_device_timer1 = {
509 .name = "s3c2410-timer",
510 .id = 1,
511 .num_resources = ARRAY_SIZE(s3c_timer1_resource),
512 .resource = s3c_timer1_resource,
513};
514
515EXPORT_SYMBOL(s3c_device_timer1);
516
517/* timer 2 */
518
519static struct resource s3c_timer2_resource[] = {
520 [0] = {
521 .start = S3C24XX_PA_TIMER + 0x24,
522 .end = S3C24XX_PA_TIMER + 0x2F,
523 .flags = IORESOURCE_MEM,
524 },
525 [1] = {
526 .start = IRQ_TIMER2,
527 .end = IRQ_TIMER2,
528 .flags = IORESOURCE_IRQ,
529 }
530
531};
532
533struct platform_device s3c_device_timer2 = {
534 .name = "s3c2410-timer",
535 .id = 2,
536 .num_resources = ARRAY_SIZE(s3c_timer2_resource),
537 .resource = s3c_timer2_resource,
538};
539
540EXPORT_SYMBOL(s3c_device_timer2);
541
542/* timer 3 */
543
544static struct resource s3c_timer3_resource[] = {
545 [0] = {
546 .start = S3C24XX_PA_TIMER + 0x30,
547 .end = S3C24XX_PA_TIMER + 0x3B,
548 .flags = IORESOURCE_MEM,
549 },
550 [1] = {
551 .start = IRQ_TIMER3,
552 .end = IRQ_TIMER3,
553 .flags = IORESOURCE_IRQ,
554 }
555
556};
557
558struct platform_device s3c_device_timer3 = {
559 .name = "s3c2410-timer",
560 .id = 3,
561 .num_resources = ARRAY_SIZE(s3c_timer3_resource),
562 .resource = s3c_timer3_resource,
563};
564
565EXPORT_SYMBOL(s3c_device_timer3);
566
567#ifdef CONFIG_CPU_S3C2440
568
569/* Camif Controller */
570
571static struct resource s3c_camif_resource[] = {
572 [0] = {
573 .start = S3C2440_PA_CAMIF,
574 .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
575 .flags = IORESOURCE_MEM,
576 },
577 [1] = {
578 .start = IRQ_CAM,
579 .end = IRQ_CAM,
580 .flags = IORESOURCE_IRQ,
581 }
582
583};
584
585static u64 s3c_device_camif_dmamask = 0xffffffffUL;
586
587struct platform_device s3c_device_camif = {
588 .name = "s3c2440-camif",
589 .id = -1,
590 .num_resources = ARRAY_SIZE(s3c_camif_resource),
591 .resource = s3c_camif_resource,
592 .dev = {
593 .dma_mask = &s3c_device_camif_dmamask,
594 .coherent_dma_mask = 0xffffffffUL
595 }
596};
597
598EXPORT_SYMBOL(s3c_device_camif);
599
600#endif // CONFIG_CPU_S32440
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
new file mode 100644
index 000000000000..4540a806f522
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -0,0 +1,1499 @@
1/* linux/arch/arm/plat-s3c24xx/dma.c
2 *
3 * Copyright (c) 2003-2005,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 DMA core
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15
16#ifdef CONFIG_S3C2410_DMA_DEBUG
17#define DEBUG
18#endif
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/sched.h>
23#include <linux/spinlock.h>
24#include <linux/interrupt.h>
25#include <linux/sysdev.h>
26#include <linux/slab.h>
27#include <linux/errno.h>
28#include <linux/delay.h>
29
30#include <asm/system.h>
31#include <asm/irq.h>
32#include <asm/hardware.h>
33#include <asm/io.h>
34#include <asm/dma.h>
35
36#include <asm/mach/dma.h>
37#include <asm/arch/map.h>
38
39#include <asm/plat-s3c24xx/dma.h>
40
41/* io map for dma */
42static void __iomem *dma_base;
43static struct kmem_cache *dma_kmem;
44
45static int dma_channels;
46
47struct s3c24xx_dma_selection dma_sel;
48
49/* dma channel state information */
50struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
51
52/* debugging functions */
53
54#define BUF_MAGIC (0xcafebabe)
55
56#define dmawarn(fmt...) printk(KERN_DEBUG fmt)
57
58#define dma_regaddr(chan, reg) ((chan)->regs + (reg))
59
60#if 1
61#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
62#else
63static inline void
64dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
65{
66 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
67 writel(val, dma_regaddr(chan, reg));
68}
69#endif
70
71#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
72
73/* captured register state for debug */
74
75struct s3c2410_dma_regstate {
76 unsigned long dcsrc;
77 unsigned long disrc;
78 unsigned long dstat;
79 unsigned long dcon;
80 unsigned long dmsktrig;
81};
82
83#ifdef CONFIG_S3C2410_DMA_DEBUG
84
85/* dmadbg_showregs
86 *
87 * simple debug routine to print the current state of the dma registers
88*/
89
90static void
91dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
92{
93 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
94 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
95 regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
96 regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
97 regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
98}
99
100static void
101dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
102 struct s3c2410_dma_regstate *regs)
103{
104 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
105 chan->number, fname, line,
106 regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
107 regs->dcon);
108}
109
110static void
111dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
112{
113 struct s3c2410_dma_regstate state;
114
115 dmadbg_capture(chan, &state);
116
117 printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
118 chan->number, fname, line, chan->load_state,
119 chan->curr, chan->next, chan->end);
120
121 dmadbg_dumpregs(fname, line, chan, &state);
122}
123
124static void
125dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
126{
127 struct s3c2410_dma_regstate state;
128
129 dmadbg_capture(chan, &state);
130 dmadbg_dumpregs(fname, line, chan, &state);
131}
132
133#define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan))
134#define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan))
135#else
136#define dbg_showregs(chan) do { } while(0)
137#define dbg_showchan(chan) do { } while(0)
138#endif /* CONFIG_S3C2410_DMA_DEBUG */
139
140static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
141
142/* lookup_dma_channel
143 *
144 * change the dma channel number given into a real dma channel id
145*/
146
147static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
148{
149 if (channel & DMACH_LOW_LEVEL)
150 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
151 else
152 return dma_chan_map[channel];
153}
154
155/* s3c2410_dma_stats_timeout
156 *
157 * Update DMA stats from timeout info
158*/
159
160static void
161s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
162{
163 if (stats == NULL)
164 return;
165
166 if (val > stats->timeout_longest)
167 stats->timeout_longest = val;
168 if (val < stats->timeout_shortest)
169 stats->timeout_shortest = val;
170
171 stats->timeout_avg += val;
172}
173
174/* s3c2410_dma_waitforload
175 *
176 * wait for the DMA engine to load a buffer, and update the state accordingly
177*/
178
179static int
180s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
181{
182 int timeout = chan->load_timeout;
183 int took;
184
185 if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
186 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
187 return 0;
188 }
189
190 if (chan->stats != NULL)
191 chan->stats->loads++;
192
193 while (--timeout > 0) {
194 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
195 took = chan->load_timeout - timeout;
196
197 s3c2410_dma_stats_timeout(chan->stats, took);
198
199 switch (chan->load_state) {
200 case S3C2410_DMALOAD_1LOADED:
201 chan->load_state = S3C2410_DMALOAD_1RUNNING;
202 break;
203
204 default:
205 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
206 }
207
208 return 1;
209 }
210 }
211
212 if (chan->stats != NULL) {
213 chan->stats->timeout_failed++;
214 }
215
216 return 0;
217}
218
219
220
221/* s3c2410_dma_loadbuffer
222 *
223 * load a buffer, and update the channel state
224*/
225
226static inline int
227s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
228 struct s3c2410_dma_buf *buf)
229{
230 unsigned long reload;
231
232 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
233 buf, (unsigned long)buf->data, buf->size);
234
235 if (buf == NULL) {
236 dmawarn("buffer is NULL\n");
237 return -EINVAL;
238 }
239
240 /* check the state of the channel before we do anything */
241
242 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
243 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
244 }
245
246 if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
247 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
248 }
249
250 /* it would seem sensible if we are the last buffer to not bother
251 * with the auto-reload bit, so that the DMA engine will not try
252 * and load another transfer after this one has finished...
253 */
254 if (chan->load_state == S3C2410_DMALOAD_NONE) {
255 pr_debug("load_state is none, checking for noreload (next=%p)\n",
256 buf->next);
257 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
258 } else {
259 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
260 reload = S3C2410_DCON_AUTORELOAD;
261 }
262
263 if ((buf->data & 0xf0000000) != 0x30000000) {
264 dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
265 }
266
267 writel(buf->data, chan->addr_reg);
268
269 dma_wrreg(chan, S3C2410_DMA_DCON,
270 chan->dcon | reload | (buf->size/chan->xfer_unit));
271
272 chan->next = buf->next;
273
274 /* update the state of the channel */
275
276 switch (chan->load_state) {
277 case S3C2410_DMALOAD_NONE:
278 chan->load_state = S3C2410_DMALOAD_1LOADED;
279 break;
280
281 case S3C2410_DMALOAD_1RUNNING:
282 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
283 break;
284
285 default:
286 dmawarn("dmaload: unknown state %d in loadbuffer\n",
287 chan->load_state);
288 break;
289 }
290
291 return 0;
292}
293
294/* s3c2410_dma_call_op
295 *
296 * small routine to call the op routine with the given op if it has been
297 * registered
298*/
299
300static void
301s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
302{
303 if (chan->op_fn != NULL) {
304 (chan->op_fn)(chan, op);
305 }
306}
307
308/* s3c2410_dma_buffdone
309 *
310 * small wrapper to check if callback routine needs to be called, and
311 * if so, call it
312*/
313
314static inline void
315s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
316 enum s3c2410_dma_buffresult result)
317{
318#if 0
319 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
320 chan->callback_fn, buf, buf->id, buf->size, result);
321#endif
322
323 if (chan->callback_fn != NULL) {
324 (chan->callback_fn)(chan, buf->id, buf->size, result);
325 }
326}
327
328/* s3c2410_dma_start
329 *
330 * start a dma channel going
331*/
332
333static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
334{
335 unsigned long tmp;
336 unsigned long flags;
337
338 pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
339
340 local_irq_save(flags);
341
342 if (chan->state == S3C2410_DMA_RUNNING) {
343 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
344 local_irq_restore(flags);
345 return 0;
346 }
347
348 chan->state = S3C2410_DMA_RUNNING;
349
350 /* check wether there is anything to load, and if not, see
351 * if we can find anything to load
352 */
353
354 if (chan->load_state == S3C2410_DMALOAD_NONE) {
355 if (chan->next == NULL) {
356 printk(KERN_ERR "dma%d: channel has nothing loaded\n",
357 chan->number);
358 chan->state = S3C2410_DMA_IDLE;
359 local_irq_restore(flags);
360 return -EINVAL;
361 }
362
363 s3c2410_dma_loadbuffer(chan, chan->next);
364 }
365
366 dbg_showchan(chan);
367
368 /* enable the channel */
369
370 if (!chan->irq_enabled) {
371 enable_irq(chan->irq);
372 chan->irq_enabled = 1;
373 }
374
375 /* start the channel going */
376
377 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
378 tmp &= ~S3C2410_DMASKTRIG_STOP;
379 tmp |= S3C2410_DMASKTRIG_ON;
380 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
381
382 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
383
384#if 0
385 /* the dma buffer loads should take care of clearing the AUTO
386 * reloading feature */
387 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
388 tmp &= ~S3C2410_DCON_NORELOAD;
389 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
390#endif
391
392 s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
393
394 dbg_showchan(chan);
395
396 /* if we've only loaded one buffer onto the channel, then chec
397 * to see if we have another, and if so, try and load it so when
398 * the first buffer is finished, the new one will be loaded onto
399 * the channel */
400
401 if (chan->next != NULL) {
402 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
403
404 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
405 pr_debug("%s: buff not yet loaded, no more todo\n",
406 __FUNCTION__);
407 } else {
408 chan->load_state = S3C2410_DMALOAD_1RUNNING;
409 s3c2410_dma_loadbuffer(chan, chan->next);
410 }
411
412 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
413 s3c2410_dma_loadbuffer(chan, chan->next);
414 }
415 }
416
417
418 local_irq_restore(flags);
419
420 return 0;
421}
422
423/* s3c2410_dma_canload
424 *
425 * work out if we can queue another buffer into the DMA engine
426*/
427
428static int
429s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
430{
431 if (chan->load_state == S3C2410_DMALOAD_NONE ||
432 chan->load_state == S3C2410_DMALOAD_1RUNNING)
433 return 1;
434
435 return 0;
436}
437
438/* s3c2410_dma_enqueue
439 *
440 * queue an given buffer for dma transfer.
441 *
442 * id the device driver's id information for this buffer
443 * data the physical address of the buffer data
444 * size the size of the buffer in bytes
445 *
446 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
447 * is checked, and if set, the channel is started. If this flag isn't set,
448 * then an error will be returned.
449 *
450 * It is possible to queue more than one DMA buffer onto a channel at
451 * once, and the code will deal with the re-loading of the next buffer
452 * when necessary.
453*/
454
455int s3c2410_dma_enqueue(unsigned int channel, void *id,
456 dma_addr_t data, int size)
457{
458 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
459 struct s3c2410_dma_buf *buf;
460 unsigned long flags;
461
462 if (chan == NULL)
463 return -EINVAL;
464
465 pr_debug("%s: id=%p, data=%08x, size=%d\n",
466 __FUNCTION__, id, (unsigned int)data, size);
467
468 buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
469 if (buf == NULL) {
470 pr_debug("%s: out of memory (%ld alloc)\n",
471 __FUNCTION__, (long)sizeof(*buf));
472 return -ENOMEM;
473 }
474
475 //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
476 //dbg_showchan(chan);
477
478 buf->next = NULL;
479 buf->data = buf->ptr = data;
480 buf->size = size;
481 buf->id = id;
482 buf->magic = BUF_MAGIC;
483
484 local_irq_save(flags);
485
486 if (chan->curr == NULL) {
487 /* we've got nothing loaded... */
488 pr_debug("%s: buffer %p queued onto empty channel\n",
489 __FUNCTION__, buf);
490
491 chan->curr = buf;
492 chan->end = buf;
493 chan->next = NULL;
494 } else {
495 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
496 chan->number, __FUNCTION__, buf);
497
498 if (chan->end == NULL)
499 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
500 chan->number, __FUNCTION__, chan);
501
502 chan->end->next = buf;
503 chan->end = buf;
504 }
505
506 /* if necessary, update the next buffer field */
507 if (chan->next == NULL)
508 chan->next = buf;
509
510 /* check to see if we can load a buffer */
511 if (chan->state == S3C2410_DMA_RUNNING) {
512 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
513 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
514 printk(KERN_ERR "dma%d: loadbuffer:"
515 "timeout loading buffer\n",
516 chan->number);
517 dbg_showchan(chan);
518 local_irq_restore(flags);
519 return -EINVAL;
520 }
521 }
522
523 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
524 s3c2410_dma_loadbuffer(chan, chan->next);
525 }
526 } else if (chan->state == S3C2410_DMA_IDLE) {
527 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
528 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START);
529 }
530 }
531
532 local_irq_restore(flags);
533 return 0;
534}
535
536EXPORT_SYMBOL(s3c2410_dma_enqueue);
537
538static inline void
539s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
540{
541 int magicok = (buf->magic == BUF_MAGIC);
542
543 buf->magic = -1;
544
545 if (magicok) {
546 kmem_cache_free(dma_kmem, buf);
547 } else {
548 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
549 }
550}
551
552/* s3c2410_dma_lastxfer
553 *
554 * called when the system is out of buffers, to ensure that the channel
555 * is prepared for shutdown.
556*/
557
558static inline void
559s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
560{
561#if 0
562 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
563 chan->number, chan->load_state);
564#endif
565
566 switch (chan->load_state) {
567 case S3C2410_DMALOAD_NONE:
568 break;
569
570 case S3C2410_DMALOAD_1LOADED:
571 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
572 /* flag error? */
573 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
574 chan->number, __FUNCTION__);
575 return;
576 }
577 break;
578
579 case S3C2410_DMALOAD_1LOADED_1RUNNING:
580 /* I belive in this case we do not have anything to do
581 * until the next buffer comes along, and we turn off the
582 * reload */
583 return;
584
585 default:
586 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
587 chan->number, chan->load_state);
588 return;
589
590 }
591
592 /* hopefully this'll shut the damned thing up after the transfer... */
593 dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
594}
595
596
597#define dmadbg2(x...)
598
599static irqreturn_t
600s3c2410_dma_irq(int irq, void *devpw)
601{
602 struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
603 struct s3c2410_dma_buf *buf;
604
605 buf = chan->curr;
606
607 dbg_showchan(chan);
608
609 /* modify the channel state */
610
611 switch (chan->load_state) {
612 case S3C2410_DMALOAD_1RUNNING:
613 /* TODO - if we are running only one buffer, we probably
614 * want to reload here, and then worry about the buffer
615 * callback */
616
617 chan->load_state = S3C2410_DMALOAD_NONE;
618 break;
619
620 case S3C2410_DMALOAD_1LOADED:
621 /* iirc, we should go back to NONE loaded here, we
622 * had a buffer, and it was never verified as being
623 * loaded.
624 */
625
626 chan->load_state = S3C2410_DMALOAD_NONE;
627 break;
628
629 case S3C2410_DMALOAD_1LOADED_1RUNNING:
630 /* we'll worry about checking to see if another buffer is
631 * ready after we've called back the owner. This should
632 * ensure we do not wait around too long for the DMA
633 * engine to start the next transfer
634 */
635
636 chan->load_state = S3C2410_DMALOAD_1LOADED;
637 break;
638
639 case S3C2410_DMALOAD_NONE:
640 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
641 chan->number);
642 break;
643
644 default:
645 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
646 chan->number, chan->load_state);
647 break;
648 }
649
650 if (buf != NULL) {
651 /* update the chain to make sure that if we load any more
652 * buffers when we call the callback function, things should
653 * work properly */
654
655 chan->curr = buf->next;
656 buf->next = NULL;
657
658 if (buf->magic != BUF_MAGIC) {
659 printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
660 chan->number, __FUNCTION__, buf);
661 return IRQ_HANDLED;
662 }
663
664 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
665
666 /* free resouces */
667 s3c2410_dma_freebuf(buf);
668 } else {
669 }
670
671 /* only reload if the channel is still running... our buffer done
672 * routine may have altered the state by requesting the dma channel
673 * to stop or shutdown... */
674
675 /* todo: check that when the channel is shut-down from inside this
676 * function, we cope with unsetting reload, etc */
677
678 if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
679 unsigned long flags;
680
681 switch (chan->load_state) {
682 case S3C2410_DMALOAD_1RUNNING:
683 /* don't need to do anything for this state */
684 break;
685
686 case S3C2410_DMALOAD_NONE:
687 /* can load buffer immediately */
688 break;
689
690 case S3C2410_DMALOAD_1LOADED:
691 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
692 /* flag error? */
693 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
694 chan->number, __FUNCTION__);
695 return IRQ_HANDLED;
696 }
697
698 break;
699
700 case S3C2410_DMALOAD_1LOADED_1RUNNING:
701 goto no_load;
702
703 default:
704 printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
705 chan->number, chan->load_state);
706 return IRQ_HANDLED;
707 }
708
709 local_irq_save(flags);
710 s3c2410_dma_loadbuffer(chan, chan->next);
711 local_irq_restore(flags);
712 } else {
713 s3c2410_dma_lastxfer(chan);
714
715 /* see if we can stop this channel.. */
716 if (chan->load_state == S3C2410_DMALOAD_NONE) {
717 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
718 chan->number, jiffies);
719 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
720 S3C2410_DMAOP_STOP);
721 }
722 }
723
724 no_load:
725 return IRQ_HANDLED;
726}
727
728static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
729
730/* s3c2410_request_dma
731 *
732 * get control of an dma channel
733*/
734
735int s3c2410_dma_request(unsigned int channel,
736 struct s3c2410_dma_client *client,
737 void *dev)
738{
739 struct s3c2410_dma_chan *chan;
740 unsigned long flags;
741 int err;
742
743 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
744 channel, client->name, dev);
745
746 local_irq_save(flags);
747
748 chan = s3c2410_dma_map_channel(channel);
749 if (chan == NULL) {
750 local_irq_restore(flags);
751 return -EBUSY;
752 }
753
754 dbg_showchan(chan);
755
756 chan->client = client;
757 chan->in_use = 1;
758
759 if (!chan->irq_claimed) {
760 pr_debug("dma%d: %s : requesting irq %d\n",
761 channel, __FUNCTION__, chan->irq);
762
763 chan->irq_claimed = 1;
764 local_irq_restore(flags);
765
766 err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
767 client->name, (void *)chan);
768
769 local_irq_save(flags);
770
771 if (err) {
772 chan->in_use = 0;
773 chan->irq_claimed = 0;
774 local_irq_restore(flags);
775
776 printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
777 client->name, chan->irq, chan->number);
778 return err;
779 }
780
781 chan->irq_enabled = 1;
782 }
783
784 local_irq_restore(flags);
785
786 /* need to setup */
787
788 pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan);
789
790 return 0;
791}
792
793EXPORT_SYMBOL(s3c2410_dma_request);
794
795/* s3c2410_dma_free
796 *
797 * release the given channel back to the system, will stop and flush
798 * any outstanding transfers, and ensure the channel is ready for the
799 * next claimant.
800 *
801 * Note, although a warning is currently printed if the freeing client
802 * info is not the same as the registrant's client info, the free is still
803 * allowed to go through.
804*/
805
806int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
807{
808 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
809 unsigned long flags;
810
811 if (chan == NULL)
812 return -EINVAL;
813
814 local_irq_save(flags);
815
816 if (chan->client != client) {
817 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
818 channel, chan->client, client);
819 }
820
821 /* sort out stopping and freeing the channel */
822
823 if (chan->state != S3C2410_DMA_IDLE) {
824 pr_debug("%s: need to stop dma channel %p\n",
825 __FUNCTION__, chan);
826
827 /* possibly flush the channel */
828 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
829 }
830
831 chan->client = NULL;
832 chan->in_use = 0;
833
834 if (chan->irq_claimed)
835 free_irq(chan->irq, (void *)chan);
836
837 chan->irq_claimed = 0;
838
839 if (!(channel & DMACH_LOW_LEVEL))
840 dma_chan_map[channel] = NULL;
841
842 local_irq_restore(flags);
843
844 return 0;
845}
846
847EXPORT_SYMBOL(s3c2410_dma_free);
848
849static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
850{
851 unsigned long flags;
852 unsigned long tmp;
853
854 pr_debug("%s:\n", __FUNCTION__);
855
856 dbg_showchan(chan);
857
858 local_irq_save(flags);
859
860 s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
861
862 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
863 tmp |= S3C2410_DMASKTRIG_STOP;
864 //tmp &= ~S3C2410_DMASKTRIG_ON;
865 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
866
867#if 0
868 /* should also clear interrupts, according to WinCE BSP */
869 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
870 tmp |= S3C2410_DCON_NORELOAD;
871 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
872#endif
873
874 /* should stop do this, or should we wait for flush? */
875 chan->state = S3C2410_DMA_IDLE;
876 chan->load_state = S3C2410_DMALOAD_NONE;
877
878 local_irq_restore(flags);
879
880 return 0;
881}
882
883void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
884{
885 unsigned long tmp;
886 unsigned int timeout = 0x10000;
887
888 while (timeout-- > 0) {
889 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
890
891 if (!(tmp & S3C2410_DMASKTRIG_ON))
892 return;
893 }
894
895 pr_debug("dma%d: failed to stop?\n", chan->number);
896}
897
898
899/* s3c2410_dma_flush
900 *
901 * stop the channel, and remove all current and pending transfers
902*/
903
904static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
905{
906 struct s3c2410_dma_buf *buf, *next;
907 unsigned long flags;
908
909 pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number);
910
911 dbg_showchan(chan);
912
913 local_irq_save(flags);
914
915 if (chan->state != S3C2410_DMA_IDLE) {
916 pr_debug("%s: stopping channel...\n", __FUNCTION__ );
917 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
918 }
919
920 buf = chan->curr;
921 if (buf == NULL)
922 buf = chan->next;
923
924 chan->curr = chan->next = chan->end = NULL;
925
926 if (buf != NULL) {
927 for ( ; buf != NULL; buf = next) {
928 next = buf->next;
929
930 pr_debug("%s: free buffer %p, next %p\n",
931 __FUNCTION__, buf, buf->next);
932
933 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
934 s3c2410_dma_freebuf(buf);
935 }
936 }
937
938 dbg_showregs(chan);
939
940 s3c2410_dma_waitforstop(chan);
941
942#if 0
943 /* should also clear interrupts, according to WinCE BSP */
944 {
945 unsigned long tmp;
946
947 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
948 tmp |= S3C2410_DCON_NORELOAD;
949 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
950 }
951#endif
952
953 dbg_showregs(chan);
954
955 local_irq_restore(flags);
956
957 return 0;
958}
959
960int
961s3c2410_dma_started(struct s3c2410_dma_chan *chan)
962{
963 unsigned long flags;
964
965 local_irq_save(flags);
966
967 dbg_showchan(chan);
968
969 /* if we've only loaded one buffer onto the channel, then chec
970 * to see if we have another, and if so, try and load it so when
971 * the first buffer is finished, the new one will be loaded onto
972 * the channel */
973
974 if (chan->next != NULL) {
975 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
976
977 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
978 pr_debug("%s: buff not yet loaded, no more todo\n",
979 __FUNCTION__);
980 } else {
981 chan->load_state = S3C2410_DMALOAD_1RUNNING;
982 s3c2410_dma_loadbuffer(chan, chan->next);
983 }
984
985 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
986 s3c2410_dma_loadbuffer(chan, chan->next);
987 }
988 }
989
990
991 local_irq_restore(flags);
992
993 return 0;
994
995}
996
997int
998s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
999{
1000 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1001
1002 if (chan == NULL)
1003 return -EINVAL;
1004
1005 switch (op) {
1006 case S3C2410_DMAOP_START:
1007 return s3c2410_dma_start(chan);
1008
1009 case S3C2410_DMAOP_STOP:
1010 return s3c2410_dma_dostop(chan);
1011
1012 case S3C2410_DMAOP_PAUSE:
1013 case S3C2410_DMAOP_RESUME:
1014 return -ENOENT;
1015
1016 case S3C2410_DMAOP_FLUSH:
1017 return s3c2410_dma_flush(chan);
1018
1019 case S3C2410_DMAOP_STARTED:
1020 return s3c2410_dma_started(chan);
1021
1022 case S3C2410_DMAOP_TIMEOUT:
1023 return 0;
1024
1025 }
1026
1027 return -ENOENT; /* unknown, don't bother */
1028}
1029
1030EXPORT_SYMBOL(s3c2410_dma_ctrl);
1031
1032/* DMA configuration for each channel
1033 *
1034 * DISRCC -> source of the DMA (AHB,APB)
1035 * DISRC -> source address of the DMA
1036 * DIDSTC -> destination of the DMA (AHB,APD)
1037 * DIDST -> destination address of the DMA
1038*/
1039
1040/* s3c2410_dma_config
1041 *
1042 * xfersize: size of unit in bytes (1,2,4)
1043 * dcon: base value of the DCONx register
1044*/
1045
1046int s3c2410_dma_config(dmach_t channel,
1047 int xferunit,
1048 int dcon)
1049{
1050 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1051
1052 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1053 __FUNCTION__, channel, xferunit, dcon);
1054
1055 if (chan == NULL)
1056 return -EINVAL;
1057
1058 pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon);
1059
1060 dcon |= chan->dcon & dma_sel.dcon_mask;
1061
1062 pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon);
1063
1064 switch (xferunit) {
1065 case 1:
1066 dcon |= S3C2410_DCON_BYTE;
1067 break;
1068
1069 case 2:
1070 dcon |= S3C2410_DCON_HALFWORD;
1071 break;
1072
1073 case 4:
1074 dcon |= S3C2410_DCON_WORD;
1075 break;
1076
1077 default:
1078 pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit);
1079 return -EINVAL;
1080 }
1081
1082 dcon |= S3C2410_DCON_HWTRIG;
1083 dcon |= S3C2410_DCON_INTREQ;
1084
1085 pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
1086
1087 chan->dcon = dcon;
1088 chan->xfer_unit = xferunit;
1089
1090 return 0;
1091}
1092
1093EXPORT_SYMBOL(s3c2410_dma_config);
1094
1095int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
1096{
1097 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1098
1099 if (chan == NULL)
1100 return -EINVAL;
1101
1102 pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
1103
1104 chan->flags = flags;
1105
1106 return 0;
1107}
1108
1109EXPORT_SYMBOL(s3c2410_dma_setflags);
1110
1111
1112/* do we need to protect the settings of the fields from
1113 * irq?
1114*/
1115
1116int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
1117{
1118 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1119
1120 if (chan == NULL)
1121 return -EINVAL;
1122
1123 pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
1124
1125 chan->op_fn = rtn;
1126
1127 return 0;
1128}
1129
1130EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1131
1132int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
1133{
1134 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1135
1136 if (chan == NULL)
1137 return -EINVAL;
1138
1139 pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
1140
1141 chan->callback_fn = rtn;
1142
1143 return 0;
1144}
1145
1146EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1147
1148/* s3c2410_dma_devconfig
1149 *
1150 * configure the dma source/destination hardware type and address
1151 *
1152 * source: S3C2410_DMASRC_HW: source is hardware
1153 * S3C2410_DMASRC_MEM: source is memory
1154 *
1155 * hwcfg: the value for xxxSTCn register,
1156 * bit 0: 0=increment pointer, 1=leave pointer
1157 * bit 1: 0=soucre is AHB, 1=soucre is APB
1158 *
1159 * devaddr: physical address of the source
1160*/
1161
1162int s3c2410_dma_devconfig(int channel,
1163 enum s3c2410_dmasrc source,
1164 int hwcfg,
1165 unsigned long devaddr)
1166{
1167 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1168
1169 if (chan == NULL)
1170 return -EINVAL;
1171
1172 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
1173 __FUNCTION__, (int)source, hwcfg, devaddr);
1174
1175 chan->source = source;
1176 chan->dev_addr = devaddr;
1177
1178 switch (source) {
1179 case S3C2410_DMASRC_HW:
1180 /* source is hardware */
1181 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1182 __FUNCTION__, devaddr, hwcfg);
1183 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1184 dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
1185 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1186
1187 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1188 return 0;
1189
1190 case S3C2410_DMASRC_MEM:
1191 /* source is memory */
1192 pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1193 __FUNCTION__, devaddr, hwcfg);
1194 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1195 dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
1196 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1197
1198 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1199 return 0;
1200 }
1201
1202 printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source);
1203 return -EINVAL;
1204}
1205
1206EXPORT_SYMBOL(s3c2410_dma_devconfig);
1207
1208/* s3c2410_dma_getposition
1209 *
1210 * returns the current transfer points for the dma source and destination
1211*/
1212
1213int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
1214{
1215 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1216
1217 if (chan == NULL)
1218 return -EINVAL;
1219
1220 if (src != NULL)
1221 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1222
1223 if (dst != NULL)
1224 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1225
1226 return 0;
1227}
1228
1229EXPORT_SYMBOL(s3c2410_dma_getposition);
1230
1231
1232/* system device class */
1233
1234#ifdef CONFIG_PM
1235
1236static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state)
1237{
1238 struct s3c2410_dma_chan *cp = container_of(dev, struct s3c2410_dma_chan, dev);
1239
1240 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1241
1242 if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1243 /* the dma channel is still working, which is probably
1244 * a bad thing to do over suspend/resume. We stop the
1245 * channel and assume that the client is either going to
1246 * retry after resume, or that it is broken.
1247 */
1248
1249 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1250 cp->number);
1251
1252 s3c2410_dma_dostop(cp);
1253 }
1254
1255 return 0;
1256}
1257
1258static int s3c2410_dma_resume(struct sys_device *dev)
1259{
1260 return 0;
1261}
1262
1263#else
1264#define s3c2410_dma_suspend NULL
1265#define s3c2410_dma_resume NULL
1266#endif /* CONFIG_PM */
1267
1268struct sysdev_class dma_sysclass = {
1269 set_kset_name("s3c24xx-dma"),
1270 .suspend = s3c2410_dma_suspend,
1271 .resume = s3c2410_dma_resume,
1272};
1273
1274/* kmem cache implementation */
1275
1276static void s3c2410_dma_cache_ctor(void *p, struct kmem_cache *c, unsigned long f)
1277{
1278 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1279}
1280
1281/* initialisation code */
1282
1283int __init s3c24xx_dma_sysclass_init(void)
1284{
1285 int ret = sysdev_class_register(&dma_sysclass);
1286
1287 if (ret != 0)
1288 printk(KERN_ERR "dma sysclass registration failed\n");
1289
1290 return ret;
1291}
1292
1293core_initcall(s3c24xx_dma_sysclass_init);
1294
1295int __init s3c24xx_dma_sysdev_register(void)
1296{
1297 struct s3c2410_dma_chan *cp = s3c2410_chans;
1298 int channel, ret;
1299
1300 for (channel = 0; channel < dma_channels; cp++, channel++) {
1301 cp->dev.cls = &dma_sysclass;
1302 cp->dev.id = channel;
1303 ret = sysdev_register(&cp->dev);
1304
1305 if (ret) {
1306 printk(KERN_ERR "error registering dev for dma %d\n",
1307 channel);
1308 return ret;
1309 }
1310 }
1311
1312 return 0;
1313}
1314
1315late_initcall(s3c24xx_dma_sysdev_register);
1316
1317int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1318 unsigned int stride)
1319{
1320 struct s3c2410_dma_chan *cp;
1321 int channel;
1322 int ret;
1323
1324 printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
1325
1326 dma_channels = channels;
1327
1328 dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
1329 if (dma_base == NULL) {
1330 printk(KERN_ERR "dma failed to remap register block\n");
1331 return -ENOMEM;
1332 }
1333
1334 dma_kmem = kmem_cache_create("dma_desc",
1335 sizeof(struct s3c2410_dma_buf), 0,
1336 SLAB_HWCACHE_ALIGN,
1337 s3c2410_dma_cache_ctor, NULL);
1338
1339 if (dma_kmem == NULL) {
1340 printk(KERN_ERR "dma failed to make kmem cache\n");
1341 ret = -ENOMEM;
1342 goto err;
1343 }
1344
1345 for (channel = 0; channel < channels; channel++) {
1346 cp = &s3c2410_chans[channel];
1347
1348 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1349
1350 /* dma channel irqs are in order.. */
1351 cp->number = channel;
1352 cp->irq = channel + irq;
1353 cp->regs = dma_base + (channel * stride);
1354
1355 /* point current stats somewhere */
1356 cp->stats = &cp->stats_store;
1357 cp->stats_store.timeout_shortest = LONG_MAX;
1358
1359 /* basic channel configuration */
1360
1361 cp->load_timeout = 1<<18;
1362
1363 printk("DMA channel %d at %p, irq %d\n",
1364 cp->number, cp->regs, cp->irq);
1365 }
1366
1367 return 0;
1368
1369 err:
1370 kmem_cache_destroy(dma_kmem);
1371 iounmap(dma_base);
1372 dma_base = NULL;
1373 return ret;
1374}
1375
1376int s3c2410_dma_init(void)
1377{
1378 return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
1379}
1380
1381static inline int is_channel_valid(unsigned int channel)
1382{
1383 return (channel & DMA_CH_VALID);
1384}
1385
1386static struct s3c24xx_dma_order *dma_order;
1387
1388
1389/* s3c2410_dma_map_channel()
1390 *
1391 * turn the virtual channel number into a real, and un-used hardware
1392 * channel.
1393 *
1394 * first, try the dma ordering given to us by either the relevant
1395 * dma code, or the board. Then just find the first usable free
1396 * channel
1397*/
1398
1399struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1400{
1401 struct s3c24xx_dma_order_ch *ord = NULL;
1402 struct s3c24xx_dma_map *ch_map;
1403 struct s3c2410_dma_chan *dmach;
1404 int ch;
1405
1406 if (dma_sel.map == NULL || channel > dma_sel.map_size)
1407 return NULL;
1408
1409 ch_map = dma_sel.map + channel;
1410
1411 /* first, try the board mapping */
1412
1413 if (dma_order) {
1414 ord = &dma_order->channels[channel];
1415
1416 for (ch = 0; ch < dma_channels; ch++) {
1417 if (!is_channel_valid(ord->list[ch]))
1418 continue;
1419
1420 if (s3c2410_chans[ord->list[ch]].in_use == 0) {
1421 ch = ord->list[ch] & ~DMA_CH_VALID;
1422 goto found;
1423 }
1424 }
1425
1426 if (ord->flags & DMA_CH_NEVER)
1427 return NULL;
1428 }
1429
1430 /* second, search the channel map for first free */
1431
1432 for (ch = 0; ch < dma_channels; ch++) {
1433 if (!is_channel_valid(ch_map->channels[ch]))
1434 continue;
1435
1436 if (s3c2410_chans[ch].in_use == 0) {
1437 printk("mapped channel %d to %d\n", channel, ch);
1438 break;
1439 }
1440 }
1441
1442 if (ch >= dma_channels)
1443 return NULL;
1444
1445 /* update our channel mapping */
1446
1447 found:
1448 dmach = &s3c2410_chans[ch];
1449 dma_chan_map[channel] = dmach;
1450
1451 /* select the channel */
1452
1453 (dma_sel.select)(dmach, ch_map);
1454
1455 return dmach;
1456}
1457
1458static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1459{
1460 return 0;
1461}
1462
1463int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1464{
1465 struct s3c24xx_dma_map *nmap;
1466 size_t map_sz = sizeof(*nmap) * sel->map_size;
1467 int ptr;
1468
1469 nmap = kmalloc(map_sz, GFP_KERNEL);
1470 if (nmap == NULL)
1471 return -ENOMEM;
1472
1473 memcpy(nmap, sel->map, map_sz);
1474 memcpy(&dma_sel, sel, sizeof(*sel));
1475
1476 dma_sel.map = nmap;
1477
1478 for (ptr = 0; ptr < sel->map_size; ptr++)
1479 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1480
1481 return 0;
1482}
1483
1484int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
1485{
1486 struct s3c24xx_dma_order *nord = dma_order;
1487
1488 if (nord == NULL)
1489 nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
1490
1491 if (nord == NULL) {
1492 printk(KERN_ERR "no memory to store dma channel order\n");
1493 return -ENOMEM;
1494 }
1495
1496 dma_order = nord;
1497 memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
1498 return 0;
1499}
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
new file mode 100644
index 000000000000..ec3a09c4d181
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -0,0 +1,188 @@
1/* linux/arch/arm/plat-s3c24xx/gpio.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX GPIO support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29
30#include <asm/hardware.h>
31#include <asm/irq.h>
32#include <asm/io.h>
33
34#include <asm/arch/regs-gpio.h>
35
36void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
37{
38 void __iomem *base = S3C24XX_GPIO_BASE(pin);
39 unsigned long mask;
40 unsigned long con;
41 unsigned long flags;
42
43 if (pin < S3C2410_GPIO_BANKB) {
44 mask = 1 << S3C2410_GPIO_OFFSET(pin);
45 } else {
46 mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
47 }
48
49 switch (function) {
50 case S3C2410_GPIO_LEAVE:
51 mask = 0;
52 function = 0;
53 break;
54
55 case S3C2410_GPIO_INPUT:
56 case S3C2410_GPIO_OUTPUT:
57 case S3C2410_GPIO_SFN2:
58 case S3C2410_GPIO_SFN3:
59 if (pin < S3C2410_GPIO_BANKB) {
60 function -= 1;
61 function &= 1;
62 function <<= S3C2410_GPIO_OFFSET(pin);
63 } else {
64 function &= 3;
65 function <<= S3C2410_GPIO_OFFSET(pin)*2;
66 }
67 }
68
69 /* modify the specified register wwith IRQs off */
70
71 local_irq_save(flags);
72
73 con = __raw_readl(base + 0x00);
74 con &= ~mask;
75 con |= function;
76
77 __raw_writel(con, base + 0x00);
78
79 local_irq_restore(flags);
80}
81
82EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
83
84unsigned int s3c2410_gpio_getcfg(unsigned int pin)
85{
86 void __iomem *base = S3C24XX_GPIO_BASE(pin);
87 unsigned long val = __raw_readl(base);
88
89 if (pin < S3C2410_GPIO_BANKB) {
90 val >>= S3C2410_GPIO_OFFSET(pin);
91 val &= 1;
92 val += 1;
93 } else {
94 val >>= S3C2410_GPIO_OFFSET(pin)*2;
95 val &= 3;
96 }
97
98 return val | S3C2410_GPIO_INPUT;
99}
100
101EXPORT_SYMBOL(s3c2410_gpio_getcfg);
102
103void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
104{
105 void __iomem *base = S3C24XX_GPIO_BASE(pin);
106 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
107 unsigned long flags;
108 unsigned long up;
109
110 if (pin < S3C2410_GPIO_BANKB)
111 return;
112
113 local_irq_save(flags);
114
115 up = __raw_readl(base + 0x08);
116 up &= ~(1L << offs);
117 up |= to << offs;
118 __raw_writel(up, base + 0x08);
119
120 local_irq_restore(flags);
121}
122
123EXPORT_SYMBOL(s3c2410_gpio_pullup);
124
125void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
126{
127 void __iomem *base = S3C24XX_GPIO_BASE(pin);
128 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
129 unsigned long flags;
130 unsigned long dat;
131
132 local_irq_save(flags);
133
134 dat = __raw_readl(base + 0x04);
135 dat &= ~(1 << offs);
136 dat |= to << offs;
137 __raw_writel(dat, base + 0x04);
138
139 local_irq_restore(flags);
140}
141
142EXPORT_SYMBOL(s3c2410_gpio_setpin);
143
144unsigned int s3c2410_gpio_getpin(unsigned int pin)
145{
146 void __iomem *base = S3C24XX_GPIO_BASE(pin);
147 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
148
149 return __raw_readl(base + 0x04) & (1<< offs);
150}
151
152EXPORT_SYMBOL(s3c2410_gpio_getpin);
153
154unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
155{
156 unsigned long flags;
157 unsigned long misccr;
158
159 local_irq_save(flags);
160 misccr = __raw_readl(S3C24XX_MISCCR);
161 misccr &= ~clear;
162 misccr ^= change;
163 __raw_writel(misccr, S3C24XX_MISCCR);
164 local_irq_restore(flags);
165
166 return misccr;
167}
168
169EXPORT_SYMBOL(s3c2410_modify_misccr);
170
171int s3c2410_gpio_getirq(unsigned int pin)
172{
173 if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15)
174 return -1; /* not valid interrupts */
175
176 if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
177 return -1; /* not valid pin */
178
179 if (pin < S3C2410_GPF4)
180 return (pin - S3C2410_GPF0) + IRQ_EINT0;
181
182 if (pin < S3C2410_GPG0)
183 return (pin - S3C2410_GPF4) + IRQ_EINT4;
184
185 return (pin - S3C2410_GPG0) + IRQ_EINT8;
186}
187
188EXPORT_SYMBOL(s3c2410_gpio_getirq);
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
new file mode 100644
index 000000000000..ce186398e3fd
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -0,0 +1,801 @@
1/* linux/arch/arm/plat-s3c24xx/irq.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * Changelog:
21 *
22 * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
23 * Fixed compile warnings
24 *
25 * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
26 * Fixed s3c_extirq_type
27 *
28 * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
29 * Addition of ADC/TC demux
30 *
31 * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
32 * Fix for set_irq_type() on low EINT numbers
33 *
34 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
35 * Tidy up KF's patch and sort out new release
36 *
37 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
38 * Add support for power management controls
39 *
40 * 04-Nov-2004 Ben Dooks
41 * Fix standard IRQ wake for EINT0..4 and RTC
42 *
43 * 22-Feb-2005 Ben Dooks
44 * Fixed edge-triggering on ADC IRQ
45 *
46 * 28-Jun-2005 Ben Dooks
47 * Mark IRQ_LCD valid
48 *
49 * 25-Jul-2005 Ben Dooks
50 * Split the S3C2440 IRQ code to seperate file
51*/
52
53#include <linux/init.h>
54#include <linux/module.h>
55#include <linux/interrupt.h>
56#include <linux/ioport.h>
57#include <linux/ptrace.h>
58#include <linux/sysdev.h>
59
60#include <asm/hardware.h>
61#include <asm/irq.h>
62#include <asm/io.h>
63
64#include <asm/mach/irq.h>
65
66#include <asm/arch/regs-irq.h>
67#include <asm/arch/regs-gpio.h>
68
69#include <asm/plat-s3c24xx/cpu.h>
70#include <asm/plat-s3c24xx/pm.h>
71#include <asm/plat-s3c24xx/irq.h>
72
73/* wakeup irq control */
74
75#ifdef CONFIG_PM
76
77/* state for IRQs over sleep */
78
79/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
80 *
81 * set bit to 1 in allow bitfield to enable the wakeup settings on it
82*/
83
84unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
85unsigned long s3c_irqwake_intmask = 0xffffffffL;
86unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
87unsigned long s3c_irqwake_eintmask = 0xffffffffL;
88
89int
90s3c_irq_wake(unsigned int irqno, unsigned int state)
91{
92 unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
93
94 if (!(s3c_irqwake_intallow & irqbit))
95 return -ENOENT;
96
97 printk(KERN_INFO "wake %s for irq %d\n",
98 state ? "enabled" : "disabled", irqno);
99
100 if (!state)
101 s3c_irqwake_intmask |= irqbit;
102 else
103 s3c_irqwake_intmask &= ~irqbit;
104
105 return 0;
106}
107
108static int
109s3c_irqext_wake(unsigned int irqno, unsigned int state)
110{
111 unsigned long bit = 1L << (irqno - EXTINT_OFF);
112
113 if (!(s3c_irqwake_eintallow & bit))
114 return -ENOENT;
115
116 printk(KERN_INFO "wake %s for irq %d\n",
117 state ? "enabled" : "disabled", irqno);
118
119 if (!state)
120 s3c_irqwake_eintmask |= bit;
121 else
122 s3c_irqwake_eintmask &= ~bit;
123
124 return 0;
125}
126
127#else
128#define s3c_irqext_wake NULL
129#define s3c_irq_wake NULL
130#endif
131
132
133static void
134s3c_irq_mask(unsigned int irqno)
135{
136 unsigned long mask;
137
138 irqno -= IRQ_EINT0;
139
140 mask = __raw_readl(S3C2410_INTMSK);
141 mask |= 1UL << irqno;
142 __raw_writel(mask, S3C2410_INTMSK);
143}
144
145static inline void
146s3c_irq_ack(unsigned int irqno)
147{
148 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
149
150 __raw_writel(bitval, S3C2410_SRCPND);
151 __raw_writel(bitval, S3C2410_INTPND);
152}
153
154static inline void
155s3c_irq_maskack(unsigned int irqno)
156{
157 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
158 unsigned long mask;
159
160 mask = __raw_readl(S3C2410_INTMSK);
161 __raw_writel(mask|bitval, S3C2410_INTMSK);
162
163 __raw_writel(bitval, S3C2410_SRCPND);
164 __raw_writel(bitval, S3C2410_INTPND);
165}
166
167
168static void
169s3c_irq_unmask(unsigned int irqno)
170{
171 unsigned long mask;
172
173 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
174 irqdbf2("s3c_irq_unmask %d\n", irqno);
175
176 irqno -= IRQ_EINT0;
177
178 mask = __raw_readl(S3C2410_INTMSK);
179 mask &= ~(1UL << irqno);
180 __raw_writel(mask, S3C2410_INTMSK);
181}
182
183struct irq_chip s3c_irq_level_chip = {
184 .name = "s3c-level",
185 .ack = s3c_irq_maskack,
186 .mask = s3c_irq_mask,
187 .unmask = s3c_irq_unmask,
188 .set_wake = s3c_irq_wake
189};
190
191static struct irq_chip s3c_irq_chip = {
192 .name = "s3c",
193 .ack = s3c_irq_ack,
194 .mask = s3c_irq_mask,
195 .unmask = s3c_irq_unmask,
196 .set_wake = s3c_irq_wake
197};
198
199static void
200s3c_irqext_mask(unsigned int irqno)
201{
202 unsigned long mask;
203
204 irqno -= EXTINT_OFF;
205
206 mask = __raw_readl(S3C24XX_EINTMASK);
207 mask |= ( 1UL << irqno);
208 __raw_writel(mask, S3C24XX_EINTMASK);
209}
210
211static void
212s3c_irqext_ack(unsigned int irqno)
213{
214 unsigned long req;
215 unsigned long bit;
216 unsigned long mask;
217
218 bit = 1UL << (irqno - EXTINT_OFF);
219
220 mask = __raw_readl(S3C24XX_EINTMASK);
221
222 __raw_writel(bit, S3C24XX_EINTPEND);
223
224 req = __raw_readl(S3C24XX_EINTPEND);
225 req &= ~mask;
226
227 /* not sure if we should be acking the parent irq... */
228
229 if (irqno <= IRQ_EINT7 ) {
230 if ((req & 0xf0) == 0)
231 s3c_irq_ack(IRQ_EINT4t7);
232 } else {
233 if ((req >> 8) == 0)
234 s3c_irq_ack(IRQ_EINT8t23);
235 }
236}
237
238static void
239s3c_irqext_unmask(unsigned int irqno)
240{
241 unsigned long mask;
242
243 irqno -= EXTINT_OFF;
244
245 mask = __raw_readl(S3C24XX_EINTMASK);
246 mask &= ~( 1UL << irqno);
247 __raw_writel(mask, S3C24XX_EINTMASK);
248}
249
250int
251s3c_irqext_type(unsigned int irq, unsigned int type)
252{
253 void __iomem *extint_reg;
254 void __iomem *gpcon_reg;
255 unsigned long gpcon_offset, extint_offset;
256 unsigned long newvalue = 0, value;
257
258 if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
259 {
260 gpcon_reg = S3C2410_GPFCON;
261 extint_reg = S3C24XX_EXTINT0;
262 gpcon_offset = (irq - IRQ_EINT0) * 2;
263 extint_offset = (irq - IRQ_EINT0) * 4;
264 }
265 else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
266 {
267 gpcon_reg = S3C2410_GPFCON;
268 extint_reg = S3C24XX_EXTINT0;
269 gpcon_offset = (irq - (EXTINT_OFF)) * 2;
270 extint_offset = (irq - (EXTINT_OFF)) * 4;
271 }
272 else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
273 {
274 gpcon_reg = S3C2410_GPGCON;
275 extint_reg = S3C24XX_EXTINT1;
276 gpcon_offset = (irq - IRQ_EINT8) * 2;
277 extint_offset = (irq - IRQ_EINT8) * 4;
278 }
279 else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
280 {
281 gpcon_reg = S3C2410_GPGCON;
282 extint_reg = S3C24XX_EXTINT2;
283 gpcon_offset = (irq - IRQ_EINT8) * 2;
284 extint_offset = (irq - IRQ_EINT16) * 4;
285 } else
286 return -1;
287
288 /* Set the GPIO to external interrupt mode */
289 value = __raw_readl(gpcon_reg);
290 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
291 __raw_writel(value, gpcon_reg);
292
293 /* Set the external interrupt to pointed trigger type */
294 switch (type)
295 {
296 case IRQT_NOEDGE:
297 printk(KERN_WARNING "No edge setting!\n");
298 break;
299
300 case IRQT_RISING:
301 newvalue = S3C2410_EXTINT_RISEEDGE;
302 break;
303
304 case IRQT_FALLING:
305 newvalue = S3C2410_EXTINT_FALLEDGE;
306 break;
307
308 case IRQT_BOTHEDGE:
309 newvalue = S3C2410_EXTINT_BOTHEDGE;
310 break;
311
312 case IRQT_LOW:
313 newvalue = S3C2410_EXTINT_LOWLEV;
314 break;
315
316 case IRQT_HIGH:
317 newvalue = S3C2410_EXTINT_HILEV;
318 break;
319
320 default:
321 printk(KERN_ERR "No such irq type %d", type);
322 return -1;
323 }
324
325 value = __raw_readl(extint_reg);
326 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
327 __raw_writel(value, extint_reg);
328
329 return 0;
330}
331
332static struct irq_chip s3c_irqext_chip = {
333 .name = "s3c-ext",
334 .mask = s3c_irqext_mask,
335 .unmask = s3c_irqext_unmask,
336 .ack = s3c_irqext_ack,
337 .set_type = s3c_irqext_type,
338 .set_wake = s3c_irqext_wake
339};
340
341static struct irq_chip s3c_irq_eint0t4 = {
342 .name = "s3c-ext0",
343 .ack = s3c_irq_ack,
344 .mask = s3c_irq_mask,
345 .unmask = s3c_irq_unmask,
346 .set_wake = s3c_irq_wake,
347 .set_type = s3c_irqext_type,
348};
349
350/* mask values for the parent registers for each of the interrupt types */
351
352#define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
353#define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
354#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
355#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
356
357
358/* UART0 */
359
360static void
361s3c_irq_uart0_mask(unsigned int irqno)
362{
363 s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
364}
365
366static void
367s3c_irq_uart0_unmask(unsigned int irqno)
368{
369 s3c_irqsub_unmask(irqno, INTMSK_UART0);
370}
371
372static void
373s3c_irq_uart0_ack(unsigned int irqno)
374{
375 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
376}
377
378static struct irq_chip s3c_irq_uart0 = {
379 .name = "s3c-uart0",
380 .mask = s3c_irq_uart0_mask,
381 .unmask = s3c_irq_uart0_unmask,
382 .ack = s3c_irq_uart0_ack,
383};
384
385/* UART1 */
386
387static void
388s3c_irq_uart1_mask(unsigned int irqno)
389{
390 s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
391}
392
393static void
394s3c_irq_uart1_unmask(unsigned int irqno)
395{
396 s3c_irqsub_unmask(irqno, INTMSK_UART1);
397}
398
399static void
400s3c_irq_uart1_ack(unsigned int irqno)
401{
402 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
403}
404
405static struct irq_chip s3c_irq_uart1 = {
406 .name = "s3c-uart1",
407 .mask = s3c_irq_uart1_mask,
408 .unmask = s3c_irq_uart1_unmask,
409 .ack = s3c_irq_uart1_ack,
410};
411
412/* UART2 */
413
414static void
415s3c_irq_uart2_mask(unsigned int irqno)
416{
417 s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
418}
419
420static void
421s3c_irq_uart2_unmask(unsigned int irqno)
422{
423 s3c_irqsub_unmask(irqno, INTMSK_UART2);
424}
425
426static void
427s3c_irq_uart2_ack(unsigned int irqno)
428{
429 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
430}
431
432static struct irq_chip s3c_irq_uart2 = {
433 .name = "s3c-uart2",
434 .mask = s3c_irq_uart2_mask,
435 .unmask = s3c_irq_uart2_unmask,
436 .ack = s3c_irq_uart2_ack,
437};
438
439/* ADC and Touchscreen */
440
441static void
442s3c_irq_adc_mask(unsigned int irqno)
443{
444 s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
445}
446
447static void
448s3c_irq_adc_unmask(unsigned int irqno)
449{
450 s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
451}
452
453static void
454s3c_irq_adc_ack(unsigned int irqno)
455{
456 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
457}
458
459static struct irq_chip s3c_irq_adc = {
460 .name = "s3c-adc",
461 .mask = s3c_irq_adc_mask,
462 .unmask = s3c_irq_adc_unmask,
463 .ack = s3c_irq_adc_ack,
464};
465
466/* irq demux for adc */
467static void s3c_irq_demux_adc(unsigned int irq,
468 struct irq_desc *desc)
469{
470 unsigned int subsrc, submsk;
471 unsigned int offset = 9;
472 struct irq_desc *mydesc;
473
474 /* read the current pending interrupts, and the mask
475 * for what it is available */
476
477 subsrc = __raw_readl(S3C2410_SUBSRCPND);
478 submsk = __raw_readl(S3C2410_INTSUBMSK);
479
480 subsrc &= ~submsk;
481 subsrc >>= offset;
482 subsrc &= 3;
483
484 if (subsrc != 0) {
485 if (subsrc & 1) {
486 mydesc = irq_desc + IRQ_TC;
487 desc_handle_irq(IRQ_TC, mydesc);
488 }
489 if (subsrc & 2) {
490 mydesc = irq_desc + IRQ_ADC;
491 desc_handle_irq(IRQ_ADC, mydesc);
492 }
493 }
494}
495
496static void s3c_irq_demux_uart(unsigned int start)
497{
498 unsigned int subsrc, submsk;
499 unsigned int offset = start - IRQ_S3CUART_RX0;
500 struct irq_desc *desc;
501
502 /* read the current pending interrupts, and the mask
503 * for what it is available */
504
505 subsrc = __raw_readl(S3C2410_SUBSRCPND);
506 submsk = __raw_readl(S3C2410_INTSUBMSK);
507
508 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
509 start, offset, subsrc, submsk);
510
511 subsrc &= ~submsk;
512 subsrc >>= offset;
513 subsrc &= 7;
514
515 if (subsrc != 0) {
516 desc = irq_desc + start;
517
518 if (subsrc & 1)
519 desc_handle_irq(start, desc);
520
521 desc++;
522
523 if (subsrc & 2)
524 desc_handle_irq(start+1, desc);
525
526 desc++;
527
528 if (subsrc & 4)
529 desc_handle_irq(start+2, desc);
530 }
531}
532
533/* uart demux entry points */
534
535static void
536s3c_irq_demux_uart0(unsigned int irq,
537 struct irq_desc *desc)
538{
539 irq = irq;
540 s3c_irq_demux_uart(IRQ_S3CUART_RX0);
541}
542
543static void
544s3c_irq_demux_uart1(unsigned int irq,
545 struct irq_desc *desc)
546{
547 irq = irq;
548 s3c_irq_demux_uart(IRQ_S3CUART_RX1);
549}
550
551static void
552s3c_irq_demux_uart2(unsigned int irq,
553 struct irq_desc *desc)
554{
555 irq = irq;
556 s3c_irq_demux_uart(IRQ_S3CUART_RX2);
557}
558
559static void
560s3c_irq_demux_extint8(unsigned int irq,
561 struct irq_desc *desc)
562{
563 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
564 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
565
566 eintpnd &= ~eintmsk;
567 eintpnd &= ~0xff; /* ignore lower irqs */
568
569 /* we may as well handle all the pending IRQs here */
570
571 while (eintpnd) {
572 irq = __ffs(eintpnd);
573 eintpnd &= ~(1<<irq);
574
575 irq += (IRQ_EINT4 - 4);
576 desc_handle_irq(irq, irq_desc + irq);
577 }
578
579}
580
581static void
582s3c_irq_demux_extint4t7(unsigned int irq,
583 struct irq_desc *desc)
584{
585 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
586 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
587
588 eintpnd &= ~eintmsk;
589 eintpnd &= 0xff; /* only lower irqs */
590
591 /* we may as well handle all the pending IRQs here */
592
593 while (eintpnd) {
594 irq = __ffs(eintpnd);
595 eintpnd &= ~(1<<irq);
596
597 irq += (IRQ_EINT4 - 4);
598
599 desc_handle_irq(irq, irq_desc + irq);
600 }
601}
602
603#ifdef CONFIG_PM
604
605static struct sleep_save irq_save[] = {
606 SAVE_ITEM(S3C2410_INTMSK),
607 SAVE_ITEM(S3C2410_INTSUBMSK),
608};
609
610/* the extint values move between the s3c2410/s3c2440 and the s3c2412
611 * so we use an array to hold them, and to calculate the address of
612 * the register at run-time
613*/
614
615static unsigned long save_extint[3];
616static unsigned long save_eintflt[4];
617static unsigned long save_eintmask;
618
619int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
620{
621 unsigned int i;
622
623 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
624 save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
625
626 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
627 save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
628
629 s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
630 save_eintmask = __raw_readl(S3C24XX_EINTMASK);
631
632 return 0;
633}
634
635int s3c24xx_irq_resume(struct sys_device *dev)
636{
637 unsigned int i;
638
639 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
640 __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
641
642 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
643 __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
644
645 s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
646 __raw_writel(save_eintmask, S3C24XX_EINTMASK);
647
648 return 0;
649}
650
651#else
652#define s3c24xx_irq_suspend NULL
653#define s3c24xx_irq_resume NULL
654#endif
655
656/* s3c24xx_init_irq
657 *
658 * Initialise S3C2410 IRQ system
659*/
660
661void __init s3c24xx_init_irq(void)
662{
663 unsigned long pend;
664 unsigned long last;
665 int irqno;
666 int i;
667
668 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
669
670 /* first, clear all interrupts pending... */
671
672 last = 0;
673 for (i = 0; i < 4; i++) {
674 pend = __raw_readl(S3C24XX_EINTPEND);
675
676 if (pend == 0 || pend == last)
677 break;
678
679 __raw_writel(pend, S3C24XX_EINTPEND);
680 printk("irq: clearing pending ext status %08x\n", (int)pend);
681 last = pend;
682 }
683
684 last = 0;
685 for (i = 0; i < 4; i++) {
686 pend = __raw_readl(S3C2410_INTPND);
687
688 if (pend == 0 || pend == last)
689 break;
690
691 __raw_writel(pend, S3C2410_SRCPND);
692 __raw_writel(pend, S3C2410_INTPND);
693 printk("irq: clearing pending status %08x\n", (int)pend);
694 last = pend;
695 }
696
697 last = 0;
698 for (i = 0; i < 4; i++) {
699 pend = __raw_readl(S3C2410_SUBSRCPND);
700
701 if (pend == 0 || pend == last)
702 break;
703
704 printk("irq: clearing subpending status %08x\n", (int)pend);
705 __raw_writel(pend, S3C2410_SUBSRCPND);
706 last = pend;
707 }
708
709 /* register the main interrupts */
710
711 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
712
713 for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
714 /* set all the s3c2410 internal irqs */
715
716 switch (irqno) {
717 /* deal with the special IRQs (cascaded) */
718
719 case IRQ_EINT4t7:
720 case IRQ_EINT8t23:
721 case IRQ_UART0:
722 case IRQ_UART1:
723 case IRQ_UART2:
724 case IRQ_ADCPARENT:
725 set_irq_chip(irqno, &s3c_irq_level_chip);
726 set_irq_handler(irqno, handle_level_irq);
727 break;
728
729 case IRQ_RESERVED6:
730 case IRQ_RESERVED24:
731 /* no IRQ here */
732 break;
733
734 default:
735 //irqdbf("registering irq %d (s3c irq)\n", irqno);
736 set_irq_chip(irqno, &s3c_irq_chip);
737 set_irq_handler(irqno, handle_edge_irq);
738 set_irq_flags(irqno, IRQF_VALID);
739 }
740 }
741
742 /* setup the cascade irq handlers */
743
744 set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
745 set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
746
747 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
748 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
749 set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
750 set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
751
752 /* external interrupts */
753
754 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
755 irqdbf("registering irq %d (ext int)\n", irqno);
756 set_irq_chip(irqno, &s3c_irq_eint0t4);
757 set_irq_handler(irqno, handle_edge_irq);
758 set_irq_flags(irqno, IRQF_VALID);
759 }
760
761 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
762 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
763 set_irq_chip(irqno, &s3c_irqext_chip);
764 set_irq_handler(irqno, handle_edge_irq);
765 set_irq_flags(irqno, IRQF_VALID);
766 }
767
768 /* register the uart interrupts */
769
770 irqdbf("s3c2410: registering external interrupts\n");
771
772 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
773 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
774 set_irq_chip(irqno, &s3c_irq_uart0);
775 set_irq_handler(irqno, handle_level_irq);
776 set_irq_flags(irqno, IRQF_VALID);
777 }
778
779 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
780 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
781 set_irq_chip(irqno, &s3c_irq_uart1);
782 set_irq_handler(irqno, handle_level_irq);
783 set_irq_flags(irqno, IRQF_VALID);
784 }
785
786 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
787 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
788 set_irq_chip(irqno, &s3c_irq_uart2);
789 set_irq_handler(irqno, handle_level_irq);
790 set_irq_flags(irqno, IRQF_VALID);
791 }
792
793 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
794 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
795 set_irq_chip(irqno, &s3c_irq_adc);
796 set_irq_handler(irqno, handle_edge_irq);
797 set_irq_flags(irqno, IRQF_VALID);
798 }
799
800 irqdbf("s3c2410: registered interrupt handlers\n");
801}
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c
new file mode 100644
index 000000000000..bd965f2feeca
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -0,0 +1,66 @@
1/* linux/arch/arm/plat-s3c24xx/pm-simtec.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/
7 *
8 * Power Management helpers for Simtec S3C24XX implementations
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25
26#include <asm/hardware.h>
27#include <asm/io.h>
28
29#include <asm/arch/map.h>
30#include <asm/arch/regs-gpio.h>
31#include <asm/arch/regs-mem.h>
32
33#include <asm/mach-types.h>
34
35#include <asm/plat-s3c24xx/pm.h>
36
37#define COPYRIGHT ", (c) 2005 Simtec Electronics"
38
39/* pm_simtec_init
40 *
41 * enable the power management functions
42*/
43
44static __init int pm_simtec_init(void)
45{
46 unsigned long gstatus4;
47
48 /* check which machine we are running on */
49
50 if (!machine_is_bast() && !machine_is_vr1000() &&
51 !machine_is_anubis() && !machine_is_osiris() &&
52 !machine_is_aml_m5900())
53 return 0;
54
55 printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n");
56
57 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30;
58 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28;
59 gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK);
60
61 __raw_writel(gstatus4, S3C2410_GSTATUS4);
62
63 return s3c2410_pm_init();
64}
65
66arch_initcall(pm_simtec_init);
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
new file mode 100644
index 000000000000..ecf68d611904
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -0,0 +1,659 @@
1/* linux/arch/arm/plat-s3c24xx/pm.c
2 *
3 * Copyright (c) 2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX Power Manager (Suspend-To-RAM) support
7 *
8 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * Parts based on arch/arm/mach-pxa/pm.c
25 *
26 * Thanks to Dimitry Andric for debugging
27*/
28
29#include <linux/init.h>
30#include <linux/suspend.h>
31#include <linux/errno.h>
32#include <linux/time.h>
33#include <linux/interrupt.h>
34#include <linux/crc32.h>
35#include <linux/ioport.h>
36#include <linux/delay.h>
37#include <linux/serial_core.h>
38
39#include <asm/cacheflush.h>
40#include <asm/hardware.h>
41#include <asm/io.h>
42
43#include <asm/arch/regs-serial.h>
44#include <asm/arch/regs-clock.h>
45#include <asm/arch/regs-gpio.h>
46#include <asm/arch/regs-mem.h>
47#include <asm/arch/regs-irq.h>
48
49#include <asm/mach/time.h>
50
51#include <asm/plat-s3c24xx/pm.h>
52
53/* for external use */
54
55unsigned long s3c_pm_flags;
56
57#define PFX "s3c24xx-pm: "
58
59static struct sleep_save core_save[] = {
60 SAVE_ITEM(S3C2410_LOCKTIME),
61 SAVE_ITEM(S3C2410_CLKCON),
62
63 /* we restore the timings here, with the proviso that the board
64 * brings the system up in an slower, or equal frequency setting
65 * to the original system.
66 *
67 * if we cannot guarantee this, then things are going to go very
68 * wrong here, as we modify the refresh and both pll settings.
69 */
70
71 SAVE_ITEM(S3C2410_BWSCON),
72 SAVE_ITEM(S3C2410_BANKCON0),
73 SAVE_ITEM(S3C2410_BANKCON1),
74 SAVE_ITEM(S3C2410_BANKCON2),
75 SAVE_ITEM(S3C2410_BANKCON3),
76 SAVE_ITEM(S3C2410_BANKCON4),
77 SAVE_ITEM(S3C2410_BANKCON5),
78
79 SAVE_ITEM(S3C2410_CLKDIVN),
80 SAVE_ITEM(S3C2410_MPLLCON),
81 SAVE_ITEM(S3C2410_UPLLCON),
82 SAVE_ITEM(S3C2410_CLKSLOW),
83 SAVE_ITEM(S3C2410_REFRESH),
84};
85
86static struct sleep_save gpio_save[] = {
87 SAVE_ITEM(S3C2410_GPACON),
88 SAVE_ITEM(S3C2410_GPADAT),
89
90 SAVE_ITEM(S3C2410_GPBCON),
91 SAVE_ITEM(S3C2410_GPBDAT),
92 SAVE_ITEM(S3C2410_GPBUP),
93
94 SAVE_ITEM(S3C2410_GPCCON),
95 SAVE_ITEM(S3C2410_GPCDAT),
96 SAVE_ITEM(S3C2410_GPCUP),
97
98 SAVE_ITEM(S3C2410_GPDCON),
99 SAVE_ITEM(S3C2410_GPDDAT),
100 SAVE_ITEM(S3C2410_GPDUP),
101
102 SAVE_ITEM(S3C2410_GPECON),
103 SAVE_ITEM(S3C2410_GPEDAT),
104 SAVE_ITEM(S3C2410_GPEUP),
105
106 SAVE_ITEM(S3C2410_GPFCON),
107 SAVE_ITEM(S3C2410_GPFDAT),
108 SAVE_ITEM(S3C2410_GPFUP),
109
110 SAVE_ITEM(S3C2410_GPGCON),
111 SAVE_ITEM(S3C2410_GPGDAT),
112 SAVE_ITEM(S3C2410_GPGUP),
113
114 SAVE_ITEM(S3C2410_GPHCON),
115 SAVE_ITEM(S3C2410_GPHDAT),
116 SAVE_ITEM(S3C2410_GPHUP),
117
118 SAVE_ITEM(S3C2410_DCLKCON),
119};
120
121#ifdef CONFIG_S3C2410_PM_DEBUG
122
123#define SAVE_UART(va) \
124 SAVE_ITEM((va) + S3C2410_ULCON), \
125 SAVE_ITEM((va) + S3C2410_UCON), \
126 SAVE_ITEM((va) + S3C2410_UFCON), \
127 SAVE_ITEM((va) + S3C2410_UMCON), \
128 SAVE_ITEM((va) + S3C2410_UBRDIV)
129
130static struct sleep_save uart_save[] = {
131 SAVE_UART(S3C24XX_VA_UART0),
132 SAVE_UART(S3C24XX_VA_UART1),
133#ifndef CONFIG_CPU_S3C2400
134 SAVE_UART(S3C24XX_VA_UART2),
135#endif
136};
137
138/* debug
139 *
140 * we send the debug to printascii() to allow it to be seen if the
141 * system never wakes up from the sleep
142*/
143
144extern void printascii(const char *);
145
146void pm_dbg(const char *fmt, ...)
147{
148 va_list va;
149 char buff[256];
150
151 va_start(va, fmt);
152 vsprintf(buff, fmt, va);
153 va_end(va);
154
155 printascii(buff);
156}
157
158static void s3c2410_pm_debug_init(void)
159{
160 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
161
162 /* re-start uart clocks */
163 tmp |= S3C2410_CLKCON_UART0;
164 tmp |= S3C2410_CLKCON_UART1;
165 tmp |= S3C2410_CLKCON_UART2;
166
167 __raw_writel(tmp, S3C2410_CLKCON);
168 udelay(10);
169}
170
171#define DBG(fmt...) pm_dbg(fmt)
172#else
173#define DBG(fmt...) printk(KERN_DEBUG fmt)
174
175#define s3c2410_pm_debug_init() do { } while(0)
176
177static struct sleep_save uart_save[] = {};
178#endif
179
180#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
181
182/* suspend checking code...
183 *
184 * this next area does a set of crc checks over all the installed
185 * memory, so the system can verify if the resume was ok.
186 *
187 * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
188 * increasing it will mean that the area corrupted will be less easy to spot,
189 * and reducing the size will cause the CRC save area to grow
190*/
191
192#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
193
194static u32 crc_size; /* size needed for the crc block */
195static u32 *crcs; /* allocated over suspend/resume */
196
197typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
198
199/* s3c2410_pm_run_res
200 *
201 * go thorugh the given resource list, and look for system ram
202*/
203
204static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
205{
206 while (ptr != NULL) {
207 if (ptr->child != NULL)
208 s3c2410_pm_run_res(ptr->child, fn, arg);
209
210 if ((ptr->flags & IORESOURCE_MEM) &&
211 strcmp(ptr->name, "System RAM") == 0) {
212 DBG("Found system RAM at %08lx..%08lx\n",
213 ptr->start, ptr->end);
214 arg = (fn)(ptr, arg);
215 }
216
217 ptr = ptr->sibling;
218 }
219}
220
221static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
222{
223 s3c2410_pm_run_res(&iomem_resource, fn, arg);
224}
225
226static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
227{
228 u32 size = (u32)(res->end - res->start)+1;
229
230 size += CHECK_CHUNKSIZE-1;
231 size /= CHECK_CHUNKSIZE;
232
233 DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
234
235 *val += size * sizeof(u32);
236 return val;
237}
238
239/* s3c2410_pm_prepare_check
240 *
241 * prepare the necessary information for creating the CRCs. This
242 * must be done before the final save, as it will require memory
243 * allocating, and thus touching bits of the kernel we do not
244 * know about.
245*/
246
247static void s3c2410_pm_check_prepare(void)
248{
249 crc_size = 0;
250
251 s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
252
253 DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
254
255 crcs = kmalloc(crc_size+4, GFP_KERNEL);
256 if (crcs == NULL)
257 printk(KERN_ERR "Cannot allocated CRC save area\n");
258}
259
260static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
261{
262 unsigned long addr, left;
263
264 for (addr = res->start; addr < res->end;
265 addr += CHECK_CHUNKSIZE) {
266 left = res->end - addr;
267
268 if (left > CHECK_CHUNKSIZE)
269 left = CHECK_CHUNKSIZE;
270
271 *val = crc32_le(~0, phys_to_virt(addr), left);
272 val++;
273 }
274
275 return val;
276}
277
278/* s3c2410_pm_check_store
279 *
280 * compute the CRC values for the memory blocks before the final
281 * sleep.
282*/
283
284static void s3c2410_pm_check_store(void)
285{
286 if (crcs != NULL)
287 s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
288}
289
290/* in_region
291 *
292 * return TRUE if the area defined by ptr..ptr+size contatins the
293 * what..what+whatsz
294*/
295
296static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
297{
298 if ((what+whatsz) < ptr)
299 return 0;
300
301 if (what > (ptr+size))
302 return 0;
303
304 return 1;
305}
306
307static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
308{
309 void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
310 unsigned long addr;
311 unsigned long left;
312 void *ptr;
313 u32 calc;
314
315 for (addr = res->start; addr < res->end;
316 addr += CHECK_CHUNKSIZE) {
317 left = res->end - addr;
318
319 if (left > CHECK_CHUNKSIZE)
320 left = CHECK_CHUNKSIZE;
321
322 ptr = phys_to_virt(addr);
323
324 if (in_region(ptr, left, crcs, crc_size)) {
325 DBG("skipping %08lx, has crc block in\n", addr);
326 goto skip_check;
327 }
328
329 if (in_region(ptr, left, save_at, 32*4 )) {
330 DBG("skipping %08lx, has save block in\n", addr);
331 goto skip_check;
332 }
333
334 /* calculate and check the checksum */
335
336 calc = crc32_le(~0, ptr, left);
337 if (calc != *val) {
338 printk(KERN_ERR PFX "Restore CRC error at "
339 "%08lx (%08x vs %08x)\n", addr, calc, *val);
340
341 DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
342 addr, calc, *val);
343 }
344
345 skip_check:
346 val++;
347 }
348
349 return val;
350}
351
352/* s3c2410_pm_check_restore
353 *
354 * check the CRCs after the restore event and free the memory used
355 * to hold them
356*/
357
358static void s3c2410_pm_check_restore(void)
359{
360 if (crcs != NULL) {
361 s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
362 kfree(crcs);
363 crcs = NULL;
364 }
365}
366
367#else
368
369#define s3c2410_pm_check_prepare() do { } while(0)
370#define s3c2410_pm_check_restore() do { } while(0)
371#define s3c2410_pm_check_store() do { } while(0)
372#endif
373
374/* helper functions to save and restore register state */
375
376void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
377{
378 for (; count > 0; count--, ptr++) {
379 ptr->val = __raw_readl(ptr->reg);
380 DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
381 }
382}
383
384/* s3c2410_pm_do_restore
385 *
386 * restore the system from the given list of saved registers
387 *
388 * Note, we do not use DBG() in here, as the system may not have
389 * restore the UARTs state yet
390*/
391
392void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
393{
394 for (; count > 0; count--, ptr++) {
395 printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
396 ptr->reg, ptr->val, __raw_readl(ptr->reg));
397
398 __raw_writel(ptr->val, ptr->reg);
399 }
400}
401
402/* s3c2410_pm_do_restore_core
403 *
404 * similar to s3c2410_pm_do_restore_core
405 *
406 * WARNING: Do not put any debug in here that may effect memory or use
407 * peripherals, as things may be changing!
408*/
409
410static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
411{
412 for (; count > 0; count--, ptr++) {
413 __raw_writel(ptr->val, ptr->reg);
414 }
415}
416
417/* s3c2410_pm_show_resume_irqs
418 *
419 * print any IRQs asserted at resume time (ie, we woke from)
420*/
421
422static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
423 unsigned long mask)
424{
425 int i;
426
427 which &= ~mask;
428
429 for (i = 0; i <= 31; i++) {
430 if ((which) & (1L<<i)) {
431 DBG("IRQ %d asserted at resume\n", start+i);
432 }
433 }
434}
435
436/* s3c2410_pm_check_resume_pin
437 *
438 * check to see if the pin is configured correctly for sleep mode, and
439 * make any necessary adjustments if it is not
440*/
441
442static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
443{
444 unsigned long irqstate;
445 unsigned long pinstate;
446 int irq = s3c2410_gpio_getirq(pin);
447
448 if (irqoffs < 4)
449 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
450 else
451 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
452
453 pinstate = s3c2410_gpio_getcfg(pin);
454
455 if (!irqstate) {
456 if (pinstate == S3C2410_GPIO_IRQ)
457 DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
458 } else {
459 if (pinstate == S3C2410_GPIO_IRQ) {
460 DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
461 s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
462 }
463 }
464}
465
466/* s3c2410_pm_configure_extint
467 *
468 * configure all external interrupt pins
469*/
470
471static void s3c2410_pm_configure_extint(void)
472{
473 int pin;
474
475 /* for each of the external interrupts (EINT0..EINT15) we
476 * need to check wether it is an external interrupt source,
477 * and then configure it as an input if it is not
478 */
479
480 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
481 s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
482 }
483
484 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
485 s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
486 }
487}
488
489void (*pm_cpu_prep)(void);
490void (*pm_cpu_sleep)(void);
491
492#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
493
494/* s3c2410_pm_enter
495 *
496 * central control for sleep/resume process
497*/
498
499static int s3c2410_pm_enter(suspend_state_t state)
500{
501 unsigned long regs_save[16];
502
503 /* ensure the debug is initialised (if enabled) */
504
505 s3c2410_pm_debug_init();
506
507 DBG("s3c2410_pm_enter(%d)\n", state);
508
509 if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
510 printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
511 return -EINVAL;
512 }
513
514 if (state != PM_SUSPEND_MEM) {
515 printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
516 return -EINVAL;
517 }
518
519 /* check if we have anything to wake-up with... bad things seem
520 * to happen if you suspend with no wakeup (system will often
521 * require a full power-cycle)
522 */
523
524 if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
525 !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
526 printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
527 printk(KERN_ERR PFX "Aborting sleep\n");
528 return -EINVAL;
529 }
530
531 /* prepare check area if configured */
532
533 s3c2410_pm_check_prepare();
534
535 /* store the physical address of the register recovery block */
536
537 s3c2410_sleep_save_phys = virt_to_phys(regs_save);
538
539 DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
540
541 /* save all necessary core registers not covered by the drivers */
542
543 s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
544 s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
545 s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
546
547 /* set the irq configuration for wake */
548
549 s3c2410_pm_configure_extint();
550
551 DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
552 s3c_irqwake_intmask, s3c_irqwake_eintmask);
553
554 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
555 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
556
557 /* ack any outstanding external interrupts before we go to sleep */
558
559 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
560 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
561 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
562
563 /* call cpu specific preperation */
564
565 pm_cpu_prep();
566
567 /* flush cache back to ram */
568
569 flush_cache_all();
570
571 s3c2410_pm_check_store();
572
573 /* send the cpu to sleep... */
574
575 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
576
577 /* s3c2410_cpu_save will also act as our return point from when
578 * we resume as it saves its own register state, so use the return
579 * code to differentiate return from save and return from sleep */
580
581 if (s3c2410_cpu_save(regs_save) == 0) {
582 flush_cache_all();
583 pm_cpu_sleep();
584 }
585
586 /* restore the cpu state */
587
588 cpu_init();
589
590 /* restore the system state */
591
592 s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
593 s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
594 s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
595
596 s3c2410_pm_debug_init();
597
598 /* check what irq (if any) restored the system */
599
600 DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
601 __raw_readl(S3C2410_SRCPND),
602 __raw_readl(S3C2410_EINTPEND));
603
604 s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
605 s3c_irqwake_intmask);
606
607 s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
608 s3c_irqwake_eintmask);
609
610 DBG("post sleep, preparing to return\n");
611
612 s3c2410_pm_check_restore();
613
614 /* ok, let's return from sleep */
615
616 DBG("S3C2410 PM Resume (post-restore)\n");
617 return 0;
618}
619
620/*
621 * Called after processes are frozen, but before we shut down devices.
622 */
623static int s3c2410_pm_prepare(suspend_state_t state)
624{
625 return 0;
626}
627
628/*
629 * Called after devices are re-setup, but before processes are thawed.
630 */
631static int s3c2410_pm_finish(suspend_state_t state)
632{
633 return 0;
634}
635
636/*
637 * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
638 */
639static struct pm_ops s3c2410_pm_ops = {
640 .pm_disk_mode = PM_DISK_FIRMWARE,
641 .prepare = s3c2410_pm_prepare,
642 .enter = s3c2410_pm_enter,
643 .finish = s3c2410_pm_finish,
644};
645
646/* s3c2410_pm_init
647 *
648 * Attach the power management functions. This should be called
649 * from the board specific initialisation if the board supports
650 * it.
651*/
652
653int __init s3c2410_pm_init(void)
654{
655 printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
656
657 pm_set_ops(&s3c2410_pm_ops);
658 return 0;
659}
diff --git a/arch/arm/plat-s3c24xx/s3c244x-irq.c b/arch/arm/plat-s3c24xx/s3c244x-irq.c
new file mode 100644
index 000000000000..a0e39d894014
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c244x-irq.c
@@ -0,0 +1,146 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/ptrace.h>
27#include <linux/sysdev.h>
28
29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/io.h>
32
33#include <asm/mach/irq.h>
34
35#include <asm/arch/regs-irq.h>
36#include <asm/arch/regs-gpio.h>
37
38#include <asm/plat-s3c24xx/cpu.h>
39#include <asm/plat-s3c24xx/pm.h>
40#include <asm/plat-s3c24xx/irq.h>
41
42/* camera irq */
43
44static void s3c_irq_demux_cam(unsigned int irq,
45 struct irq_desc *desc)
46{
47 unsigned int subsrc, submsk;
48 struct irq_desc *mydesc;
49
50 /* read the current pending interrupts, and the mask
51 * for what it is available */
52
53 subsrc = __raw_readl(S3C2410_SUBSRCPND);
54 submsk = __raw_readl(S3C2410_INTSUBMSK);
55
56 subsrc &= ~submsk;
57 subsrc >>= 11;
58 subsrc &= 3;
59
60 if (subsrc != 0) {
61 if (subsrc & 1) {
62 mydesc = irq_desc + IRQ_S3C2440_CAM_C;
63 desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc);
64 }
65 if (subsrc & 2) {
66 mydesc = irq_desc + IRQ_S3C2440_CAM_P;
67 desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc);
68 }
69 }
70}
71
72#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
73
74static void
75s3c_irq_cam_mask(unsigned int irqno)
76{
77 s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
78}
79
80static void
81s3c_irq_cam_unmask(unsigned int irqno)
82{
83 s3c_irqsub_unmask(irqno, INTMSK_CAM);
84}
85
86static void
87s3c_irq_cam_ack(unsigned int irqno)
88{
89 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
90}
91
92static struct irq_chip s3c_irq_cam = {
93 .mask = s3c_irq_cam_mask,
94 .unmask = s3c_irq_cam_unmask,
95 .ack = s3c_irq_cam_ack,
96};
97
98static int s3c244x_irq_add(struct sys_device *sysdev)
99{
100 unsigned int irqno;
101
102 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
103 set_irq_handler(IRQ_NFCON, handle_level_irq);
104 set_irq_flags(IRQ_NFCON, IRQF_VALID);
105
106 /* add chained handler for camera */
107
108 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
109 set_irq_handler(IRQ_CAM, handle_level_irq);
110 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
111
112 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
113 set_irq_chip(irqno, &s3c_irq_cam);
114 set_irq_handler(irqno, handle_level_irq);
115 set_irq_flags(irqno, IRQF_VALID);
116 }
117
118 return 0;
119}
120
121static struct sysdev_driver s3c2440_irq_driver = {
122 .add = s3c244x_irq_add,
123 .suspend = s3c24xx_irq_suspend,
124 .resume = s3c24xx_irq_resume,
125};
126
127static int s3c2440_irq_init(void)
128{
129 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
130}
131
132arch_initcall(s3c2440_irq_init);
133
134static struct sysdev_driver s3c2442_irq_driver = {
135 .add = s3c244x_irq_add,
136 .suspend = s3c24xx_irq_suspend,
137 .resume = s3c24xx_irq_resume,
138};
139
140
141static int s3c2442_irq_init(void)
142{
143 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver);
144}
145
146arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
new file mode 100644
index 000000000000..767f2e9a3a55
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -0,0 +1,184 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/sysdev.h>
22#include <linux/clk.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <asm/hardware.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31
32#include <asm/arch/regs-clock.h>
33#include <asm/arch/regs-serial.h>
34#include <asm/arch/regs-gpio.h>
35#include <asm/arch/regs-gpioj.h>
36#include <asm/arch/regs-dsc.h>
37
38#include <asm/plat-s3c24xx/s3c2410.h>
39#include <asm/plat-s3c24xx/s3c2440.h>
40#include "s3c244x.h"
41#include <asm/plat-s3c24xx/clock.h>
42#include <asm/plat-s3c24xx/devs.h>
43#include <asm/plat-s3c24xx/cpu.h>
44#include <asm/plat-s3c24xx/pm.h>
45
46static struct map_desc s3c244x_iodesc[] __initdata = {
47 IODESC_ENT(CLKPWR),
48 IODESC_ENT(TIMER),
49 IODESC_ENT(WATCHDOG),
50 IODESC_ENT(LCD),
51};
52
53/* uart initialisation */
54
55void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
56{
57 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
58}
59
60void __init s3c244x_map_io(struct map_desc *mach_desc, int size)
61{
62 /* register our io-tables */
63
64 iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
65 iotable_init(mach_desc, size);
66
67 /* rename any peripherals used differing from the s3c2410 */
68
69 s3c_device_i2c.name = "s3c2440-i2c";
70 s3c_device_nand.name = "s3c2440-nand";
71 s3c_device_usbgadget.name = "s3c2440-usbgadget";
72}
73
74void __init s3c244x_init_clocks(int xtal)
75{
76 unsigned long clkdiv;
77 unsigned long camdiv;
78 unsigned long hclk, fclk, pclk;
79 int hdiv = 1;
80
81 /* now we've got our machine bits initialised, work out what
82 * clocks we've got */
83
84 fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
85
86 clkdiv = __raw_readl(S3C2410_CLKDIVN);
87 camdiv = __raw_readl(S3C2440_CAMDIVN);
88
89 /* work out clock scalings */
90
91 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
92 case S3C2440_CLKDIVN_HDIVN_1:
93 hdiv = 1;
94 break;
95
96 case S3C2440_CLKDIVN_HDIVN_2:
97 hdiv = 2;
98 break;
99
100 case S3C2440_CLKDIVN_HDIVN_4_8:
101 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
102 break;
103
104 case S3C2440_CLKDIVN_HDIVN_3_6:
105 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
106 break;
107 }
108
109 hclk = fclk / hdiv;
110 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
111
112 /* print brief summary of clocks, etc */
113
114 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
115 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
116
117 /* initialise the clocks here, to allow other things like the
118 * console to use them, and to add new ones after the initialisation
119 */
120
121 s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
122 s3c2410_baseclk_add();
123}
124
125#ifdef CONFIG_PM
126
127static struct sleep_save s3c244x_sleep[] = {
128 SAVE_ITEM(S3C2440_DSC0),
129 SAVE_ITEM(S3C2440_DSC1),
130 SAVE_ITEM(S3C2440_GPJDAT),
131 SAVE_ITEM(S3C2440_GPJCON),
132 SAVE_ITEM(S3C2440_GPJUP)
133};
134
135static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
136{
137 s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
138 return 0;
139}
140
141static int s3c244x_resume(struct sys_device *dev)
142{
143 s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
144 return 0;
145}
146
147#else
148#define s3c244x_suspend NULL
149#define s3c244x_resume NULL
150#endif
151
152/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
153
154struct sysdev_class s3c2440_sysclass = {
155 set_kset_name("s3c2440-core"),
156 .suspend = s3c244x_suspend,
157 .resume = s3c244x_resume
158};
159
160struct sysdev_class s3c2442_sysclass = {
161 set_kset_name("s3c2442-core"),
162 .suspend = s3c244x_suspend,
163 .resume = s3c244x_resume
164};
165
166/* need to register class before we actually register the device, and
167 * we also need to ensure that it has been initialised before any of the
168 * drivers even try to use it (even if not on an s3c2440 based system)
169 * as a driver which may support both 2410 and 2440 may try and use it.
170*/
171
172static int __init s3c2440_core_init(void)
173{
174 return sysdev_class_register(&s3c2440_sysclass);
175}
176
177core_initcall(s3c2440_core_init);
178
179static int __init s3c2442_core_init(void)
180{
181 return sysdev_class_register(&s3c2442_sysclass);
182}
183
184core_initcall(s3c2442_core_init);
diff --git a/arch/arm/plat-s3c24xx/s3c244x.h b/arch/arm/plat-s3c24xx/s3c244x.h
new file mode 100644
index 000000000000..f8ed17676a35
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c244x.h
@@ -0,0 +1,25 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C2440 and S3C2442 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
14
15extern void s3c244x_map_io(struct map_desc *mach_desc, int size);
16
17extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18
19extern void s3c244x_init_clocks(int xtal);
20
21#else
22#define s3c244x_init_clocks NULL
23#define s3c244x_init_uarts NULL
24#define s3c244x_map_io NULL
25#endif
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
new file mode 100644
index 000000000000..435349dc3243
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -0,0 +1,157 @@
1/* linux/arch/arm/mach-s3c2410/sleep.S
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Power Manager (Suspend-To-RAM) support
7 *
8 * Based on PXA/SA1100 sleep code by:
9 * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
10 * Cliff Brake, (c) 2001
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25*/
26
27#include <linux/linkage.h>
28#include <asm/assembler.h>
29#include <asm/hardware.h>
30#include <asm/arch/map.h>
31
32#include <asm/arch/regs-gpio.h>
33#include <asm/arch/regs-clock.h>
34#include <asm/arch/regs-mem.h>
35#include <asm/arch/regs-serial.h>
36
37/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
38 * reset the UART configuration, only enable if you really need this!
39*/
40//#define CONFIG_DEBUG_RESUME
41
42 .text
43
44 /* s3c2410_cpu_save
45 *
46 * save enough of the CPU state to allow us to re-start
47 * pm.c code. as we store items like the sp/lr, we will
48 * end up returning from this function when the cpu resumes
49 * so the return value is set to mark this.
50 *
51 * This arangement means we avoid having to flush the cache
52 * from this code.
53 *
54 * entry:
55 * r0 = pointer to save block
56 *
57 * exit:
58 * r0 = 0 => we stored everything
59 * 1 => resumed from sleep
60 */
61
62ENTRY(s3c2410_cpu_save)
63 stmfd sp!, { r4 - r12, lr }
64
65 @@ store co-processor registers
66
67 mrc p15, 0, r4, c13, c0, 0 @ PID
68 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
69 mrc p15, 0, r6, c2, c0, 0 @ translation table base address
70 mrc p15, 0, r7, c1, c0, 0 @ control register
71
72 stmia r0, { r4 - r13 }
73
74 mov r0, #0
75 ldmfd sp, { r4 - r12, pc }
76
77 @@ return to the caller, after having the MMU
78 @@ turned on, this restores the last bits from the
79 @@ stack
80resume_with_mmu:
81 mov r0, #1
82 ldmfd sp!, { r4 - r12, pc }
83
84 .ltorg
85
86 @@ the next bits sit in the .data segment, even though they
87 @@ happen to be code... the s3c2410_sleep_save_phys needs to be
88 @@ accessed by the resume code before it can restore the MMU.
89 @@ This means that the variable has to be close enough for the
90 @@ code to read it... since the .text segment needs to be RO,
91 @@ the data segment can be the only place to put this code.
92
93 .data
94
95 .global s3c2410_sleep_save_phys
96s3c2410_sleep_save_phys:
97 .word 0
98
99 /* s3c2410_cpu_resume
100 *
101 * resume code entry for bootloader to call
102 *
103 * we must put this code here in the data segment as we have no
104 * other way of restoring the stack pointer after sleep, and we
105 * must not write to the code segment (code is read-only)
106 */
107
108ENTRY(s3c2410_cpu_resume)
109 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
110 msr cpsr_c, r0
111
112 @@ load UART to allow us to print the two characters for
113 @@ resume debug
114
115 mov r2, #S3C24XX_PA_UART & 0xff000000
116 orr r2, r2, #S3C24XX_PA_UART & 0xff000
117
118#if 0
119 /* SMDK2440 LED set */
120 mov r14, #S3C24XX_PA_GPIO
121 ldr r12, [ r14, #0x54 ]
122 bic r12, r12, #3<<4
123 orr r12, r12, #1<<7
124 str r12, [ r14, #0x54 ]
125#endif
126
127#ifdef CONFIG_DEBUG_RESUME
128 mov r3, #'L'
129 strb r3, [ r2, #S3C2410_UTXH ]
1301001:
131 ldrb r14, [ r3, #S3C2410_UTRSTAT ]
132 tst r14, #S3C2410_UTRSTAT_TXE
133 beq 1001b
134#endif /* CONFIG_DEBUG_RESUME */
135
136 mov r1, #0
137 mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
138 mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
139
140 ldr r0, s3c2410_sleep_save_phys @ address of restore block
141 ldmia r0, { r4 - r13 }
142
143 mcr p15, 0, r4, c13, c0, 0 @ PID
144 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
145 mcr p15, 0, r6, c2, c0, 0 @ translation table base
146
147#ifdef CONFIG_DEBUG_RESUME
148 mov r3, #'R'
149 strb r3, [ r2, #S3C2410_UTXH ]
150#endif
151
152 ldr r2, =resume_with_mmu
153 mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, etc
154 nop @ second-to-last before mmu
155 mov pc, r2 @ go back to virtual address
156
157 .ltorg
diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c
new file mode 100644
index 000000000000..c523d1c9cce5
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/time.c
@@ -0,0 +1,262 @@
1/* linux/arch/arm/plat-s3c24xx/time.c
2 *
3 * Copyright (C) 2003-2005 Simtec Electronics
4 * Ben Dooks, <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/sched.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/err.h>
27#include <linux/clk.h>
28
29#include <asm/system.h>
30#include <asm/leds.h>
31#include <asm/mach-types.h>
32
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/arch/map.h>
36#include <asm/arch/regs-timer.h>
37#include <asm/arch/regs-irq.h>
38#include <asm/mach/time.h>
39
40#include <asm/plat-s3c24xx/clock.h>
41#include <asm/plat-s3c24xx/cpu.h>
42
43static unsigned long timer_startval;
44static unsigned long timer_usec_ticks;
45
46#define TIMER_USEC_SHIFT 16
47
48/* we use the shifted arithmetic to work out the ratio of timer ticks
49 * to usecs, as often the peripheral clock is not a nice even multiple
50 * of 1MHz.
51 *
52 * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
53 * for the current HZ value of 200 without producing overflows.
54 *
55 * Original patch by Dimitry Andric, updated by Ben Dooks
56*/
57
58
59/* timer_mask_usec_ticks
60 *
61 * given a clock and divisor, make the value to pass into timer_ticks_to_usec
62 * to scale the ticks into usecs
63*/
64
65static inline unsigned long
66timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
67{
68 unsigned long den = pclk / 1000;
69
70 return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
71}
72
73/* timer_ticks_to_usec
74 *
75 * convert timer ticks to usec.
76*/
77
78static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
79{
80 unsigned long res;
81
82 res = ticks * timer_usec_ticks;
83 res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */
84
85 return res >> TIMER_USEC_SHIFT;
86}
87
88/***
89 * Returns microsecond since last clock interrupt. Note that interrupts
90 * will have been disabled by do_gettimeoffset()
91 * IRQs are disabled before entering here from do_gettimeofday()
92 */
93
94#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
95
96static unsigned long s3c2410_gettimeoffset (void)
97{
98 unsigned long tdone;
99 unsigned long irqpend;
100 unsigned long tval;
101
102 /* work out how many ticks have gone since last timer interrupt */
103
104 tval = __raw_readl(S3C2410_TCNTO(4));
105 tdone = timer_startval - tval;
106
107 /* check to see if there is an interrupt pending */
108
109 irqpend = __raw_readl(S3C2410_SRCPND);
110 if (irqpend & SRCPND_TIMER4) {
111 /* re-read the timer, and try and fix up for the missed
112 * interrupt. Note, the interrupt may go off before the
113 * timer has re-loaded from wrapping.
114 */
115
116 tval = __raw_readl(S3C2410_TCNTO(4));
117 tdone = timer_startval - tval;
118
119 if (tval != 0)
120 tdone += timer_startval;
121 }
122
123 return timer_ticks_to_usec(tdone);
124}
125
126
127/*
128 * IRQ handler for the timer
129 */
130static irqreturn_t
131s3c2410_timer_interrupt(int irq, void *dev_id)
132{
133 write_seqlock(&xtime_lock);
134 timer_tick();
135 write_sequnlock(&xtime_lock);
136 return IRQ_HANDLED;
137}
138
139static struct irqaction s3c2410_timer_irq = {
140 .name = "S3C2410 Timer Tick",
141 .flags = IRQF_DISABLED | IRQF_TIMER,
142 .handler = s3c2410_timer_interrupt,
143};
144
145#define use_tclk1_12() ( \
146 machine_is_bast() || \
147 machine_is_vr1000() || \
148 machine_is_anubis() || \
149 machine_is_osiris() )
150
151/*
152 * Set up timer interrupt, and return the current time in seconds.
153 *
154 * Currently we only use timer4, as it is the only timer which has no
155 * other function that can be exploited externally
156 */
157static void s3c2410_timer_setup (void)
158{
159 unsigned long tcon;
160 unsigned long tcnt;
161 unsigned long tcfg1;
162 unsigned long tcfg0;
163
164 tcnt = 0xffff; /* default value for tcnt */
165
166 /* read the current timer configuration bits */
167
168 tcon = __raw_readl(S3C2410_TCON);
169 tcfg1 = __raw_readl(S3C2410_TCFG1);
170 tcfg0 = __raw_readl(S3C2410_TCFG0);
171
172 /* configure the system for whichever machine is in use */
173
174 if (use_tclk1_12()) {
175 /* timer is at 12MHz, scaler is 1 */
176 timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
177 tcnt = 12000000 / HZ;
178
179 tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
180 tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
181 } else {
182 unsigned long pclk;
183 struct clk *clk;
184
185 /* for the h1940 (and others), we use the pclk from the core
186 * to generate the timer values. since values around 50 to
187 * 70MHz are not values we can directly generate the timer
188 * value from, we need to pre-scale and divide before using it.
189 *
190 * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
191 * (8.45 ticks per usec)
192 */
193
194 /* this is used as default if no other timer can be found */
195
196 clk = clk_get(NULL, "timers");
197 if (IS_ERR(clk))
198 panic("failed to get clock for system timer");
199
200 clk_enable(clk);
201
202 pclk = clk_get_rate(clk);
203
204 /* configure clock tick */
205
206 timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
207
208 tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
209 tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
210
211 tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
212 tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
213
214 tcnt = (pclk / 6) / HZ;
215 }
216
217 /* timers reload after counting zero, so reduce the count by 1 */
218
219 tcnt--;
220
221 printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
222 tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
223
224 /* check to see if timer is within 16bit range... */
225 if (tcnt > 0xffff) {
226 panic("setup_timer: HZ is too small, cannot configure timer!");
227 return;
228 }
229
230 __raw_writel(tcfg1, S3C2410_TCFG1);
231 __raw_writel(tcfg0, S3C2410_TCFG0);
232
233 timer_startval = tcnt;
234 __raw_writel(tcnt, S3C2410_TCNTB(4));
235
236 /* ensure timer is stopped... */
237
238 tcon &= ~(7<<20);
239 tcon |= S3C2410_TCON_T4RELOAD;
240 tcon |= S3C2410_TCON_T4MANUALUPD;
241
242 __raw_writel(tcon, S3C2410_TCON);
243 __raw_writel(tcnt, S3C2410_TCNTB(4));
244 __raw_writel(tcnt, S3C2410_TCMPB(4));
245
246 /* start the timer running */
247 tcon |= S3C2410_TCON_T4START;
248 tcon &= ~S3C2410_TCON_T4MANUALUPD;
249 __raw_writel(tcon, S3C2410_TCON);
250}
251
252static void __init s3c2410_timer_init (void)
253{
254 s3c2410_timer_setup();
255 setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
256}
257
258struct sys_timer s3c24xx_timer = {
259 .init = s3c2410_timer_init,
260 .offset = s3c2410_gettimeoffset,
261 .resume = s3c2410_timer_setup
262};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 05:34:40 -0500