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-rw-r--r--arch/arm/plat-s3c24xx/clock.c56
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c27
2 files changed, 83 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index 99a44746f8f2..d84167fb33b1 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -332,6 +332,58 @@ static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
332 return 0; 332 return 0;
333} 333}
334 334
335static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
336{
337 unsigned long div;
338
339 if ((rate == 0) || !clk->parent)
340 return 0;
341
342 div = clk_get_rate(clk->parent) / rate;
343 if (div < 2)
344 div = 2;
345 else if (div > 16)
346 div = 16;
347
348 return div;
349}
350
351static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
352 unsigned long rate)
353{
354 unsigned long div = s3c24xx_calc_div(clk, rate);
355
356 if (div == 0)
357 return 0;
358
359 return clk_get_rate(clk->parent) / div;
360}
361
362static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
363{
364 unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
365
366 if (div == 0)
367 return -EINVAL;
368
369 if (clk == &s3c24xx_dclk0) {
370 mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
371 S3C2410_DCLKCON_DCLK0_CMP_MASK;
372 data = S3C2410_DCLKCON_DCLK0_DIV(div) |
373 S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
374 } else if (clk == &s3c24xx_dclk1) {
375 mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
376 S3C2410_DCLKCON_DCLK1_CMP_MASK;
377 data = S3C2410_DCLKCON_DCLK1_DIV(div) |
378 S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
379 } else
380 return -EINVAL;
381
382 clk->rate = clk_get_rate(clk->parent) / div;
383 __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
384 S3C24XX_DCLKCON);
385 return clk->rate;
386}
335 387
336static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) 388static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
337{ 389{
@@ -378,6 +430,8 @@ struct clk s3c24xx_dclk0 = {
378 .ctrlbit = S3C2410_DCLKCON_DCLK0EN, 430 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
379 .enable = s3c24xx_dclk_enable, 431 .enable = s3c24xx_dclk_enable,
380 .set_parent = s3c24xx_dclk_setparent, 432 .set_parent = s3c24xx_dclk_setparent,
433 .set_rate = s3c24xx_set_dclk_rate,
434 .round_rate = s3c24xx_round_dclk_rate,
381}; 435};
382 436
383struct clk s3c24xx_dclk1 = { 437struct clk s3c24xx_dclk1 = {
@@ -386,6 +440,8 @@ struct clk s3c24xx_dclk1 = {
386 .ctrlbit = S3C2410_DCLKCON_DCLK0EN, 440 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
387 .enable = s3c24xx_dclk_enable, 441 .enable = s3c24xx_dclk_enable,
388 .set_parent = s3c24xx_dclk_setparent, 442 .set_parent = s3c24xx_dclk_setparent,
443 .set_rate = s3c24xx_set_dclk_rate,
444 .round_rate = s3c24xx_round_dclk_rate,
389}; 445};
390 446
391struct clk s3c24xx_clkout0 = { 447struct clk s3c24xx_clkout0 = {
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index f513ab083b8f..f5699cadb0c3 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -28,15 +28,19 @@
28#include <linux/ioport.h> 28#include <linux/ioport.h>
29#include <linux/serial_core.h> 29#include <linux/serial_core.h>
30#include <linux/platform_device.h> 30#include <linux/platform_device.h>
31#include <linux/delay.h>
31 32
32#include <asm/hardware.h> 33#include <asm/hardware.h>
33#include <asm/irq.h> 34#include <asm/irq.h>
34#include <asm/io.h> 35#include <asm/io.h>
35#include <asm/delay.h> 36#include <asm/delay.h>
37#include <asm/cacheflush.h>
36 38
37#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
38#include <asm/mach/map.h> 40#include <asm/mach/map.h>
39 41
42#include <asm/arch/system-reset.h>
43
40#include <asm/arch/regs-gpio.h> 44#include <asm/arch/regs-gpio.h>
41#include <asm/plat-s3c/regs-serial.h> 45#include <asm/plat-s3c/regs-serial.h>
42 46
@@ -203,6 +207,27 @@ static unsigned long s3c24xx_read_idcode_v4(void)
203#endif 207#endif
204} 208}
205 209
210/* Hook for arm_pm_restart to ensure we execute the reset code
211 * with the caches enabled. It seems at least the S3C2440 has a problem
212 * resetting if there is bus activity interrupted by the reset.
213 */
214static void s3c24xx_pm_restart(char mode)
215{
216 if (mode != 's') {
217 unsigned long flags;
218
219 local_irq_save(flags);
220 __cpuc_flush_kern_all();
221 __cpuc_flush_user_all();
222
223 arch_reset(mode);
224 local_irq_restore(flags);
225 }
226
227 /* fallback, or unhandled */
228 arm_machine_restart(mode);
229}
230
206void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) 231void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
207{ 232{
208 unsigned long idcode = 0x0; 233 unsigned long idcode = 0x0;
@@ -230,6 +255,8 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
230 panic("Unsupported S3C24XX CPU"); 255 panic("Unsupported S3C24XX CPU");
231 } 256 }
232 257
258 arm_pm_restart = s3c24xx_pm_restart;
259
233 (cpu->map_io)(mach_desc, size); 260 (cpu->map_io)(mach_desc, size);
234} 261}
235 262