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-rw-r--r--arch/arm/plat-s3c24xx/Kconfig8
-rw-r--r--arch/arm/plat-s3c24xx/Makefile3
-rw-r--r--arch/arm/plat-s3c24xx/devs.c100
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c259
-rw-r--r--arch/arm/plat-s3c24xx/pwm-clock.c437
-rw-r--r--arch/arm/plat-s3c24xx/pwm.c402
6 files changed, 1109 insertions, 100 deletions
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index b66fb3c4e228..5e28c217b8c2 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -9,6 +9,7 @@ config PLAT_S3C24XX
9 depends on ARCH_S3C2410 9 depends on ARCH_S3C2410
10 default y if ARCH_S3C2410 10 default y if ARCH_S3C2410
11 select NO_IOPORT 11 select NO_IOPORT
12 select HAVE_GPIO_LIB
12 help 13 help
13 Base platform code for any Samsung S3C24XX device 14 Base platform code for any Samsung S3C24XX device
14 15
@@ -20,6 +21,13 @@ config CPU_S3C244X
20 help 21 help
21 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems. 22 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
22 23
24config S3C24XX_PWM
25 bool "PWM device support"
26 select HAVE_PWM
27 help
28 Support for exporting the PWM timer blocks via the pwm device
29 system.
30
23config PM_SIMTEC 31config PM_SIMTEC
24 bool 32 bool
25 help 33 help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 131d20237dd7..d82767b2b833 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -16,8 +16,10 @@ obj-y += cpu.o
16obj-y += irq.o 16obj-y += irq.o
17obj-y += devs.o 17obj-y += devs.o
18obj-y += gpio.o 18obj-y += gpio.o
19obj-y += gpiolib.o
19obj-y += time.o 20obj-y += time.o
20obj-y += clock.o 21obj-y += clock.o
22obj-y += pwm-clock.o
21 23
22# Architecture dependant builds 24# Architecture dependant builds
23 25
@@ -27,5 +29,6 @@ obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o
27obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o 29obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
28obj-$(CONFIG_PM) += pm.o 30obj-$(CONFIG_PM) += pm.o
29obj-$(CONFIG_PM) += sleep.o 31obj-$(CONFIG_PM) += sleep.o
32obj-$(CONFIG_HAVE_PWM) += pwm.o
30obj-$(CONFIG_S3C2410_DMA) += dma.o 33obj-$(CONFIG_S3C2410_DMA) += dma.o
31obj-$(CONFIG_MACH_SMDK) += common-smdk.o 34obj-$(CONFIG_MACH_SMDK) += common-smdk.o
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index e546e933b3f7..eea3b32ff798 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -495,106 +495,6 @@ struct platform_device s3c_device_spi1 = {
495 495
496EXPORT_SYMBOL(s3c_device_spi1); 496EXPORT_SYMBOL(s3c_device_spi1);
497 497
498/* pwm timer blocks */
499
500static struct resource s3c_timer0_resource[] = {
501 [0] = {
502 .start = S3C24XX_PA_TIMER + 0x0C,
503 .end = S3C24XX_PA_TIMER + 0x0C + 0xB,
504 .flags = IORESOURCE_MEM,
505 },
506 [1] = {
507 .start = IRQ_TIMER0,
508 .end = IRQ_TIMER0,
509 .flags = IORESOURCE_IRQ,
510 }
511
512};
513
514struct platform_device s3c_device_timer0 = {
515 .name = "s3c2410-timer",
516 .id = 0,
517 .num_resources = ARRAY_SIZE(s3c_timer0_resource),
518 .resource = s3c_timer0_resource,
519};
520
521EXPORT_SYMBOL(s3c_device_timer0);
522
523/* timer 1 */
524
525static struct resource s3c_timer1_resource[] = {
526 [0] = {
527 .start = S3C24XX_PA_TIMER + 0x18,
528 .end = S3C24XX_PA_TIMER + 0x23,
529 .flags = IORESOURCE_MEM,
530 },
531 [1] = {
532 .start = IRQ_TIMER1,
533 .end = IRQ_TIMER1,
534 .flags = IORESOURCE_IRQ,
535 }
536
537};
538
539struct platform_device s3c_device_timer1 = {
540 .name = "s3c2410-timer",
541 .id = 1,
542 .num_resources = ARRAY_SIZE(s3c_timer1_resource),
543 .resource = s3c_timer1_resource,
544};
545
546EXPORT_SYMBOL(s3c_device_timer1);
547
548/* timer 2 */
549
550static struct resource s3c_timer2_resource[] = {
551 [0] = {
552 .start = S3C24XX_PA_TIMER + 0x24,
553 .end = S3C24XX_PA_TIMER + 0x2F,
554 .flags = IORESOURCE_MEM,
555 },
556 [1] = {
557 .start = IRQ_TIMER2,
558 .end = IRQ_TIMER2,
559 .flags = IORESOURCE_IRQ,
560 }
561
562};
563
564struct platform_device s3c_device_timer2 = {
565 .name = "s3c2410-timer",
566 .id = 2,
567 .num_resources = ARRAY_SIZE(s3c_timer2_resource),
568 .resource = s3c_timer2_resource,
569};
570
571EXPORT_SYMBOL(s3c_device_timer2);
572
573/* timer 3 */
574
575static struct resource s3c_timer3_resource[] = {
576 [0] = {
577 .start = S3C24XX_PA_TIMER + 0x30,
578 .end = S3C24XX_PA_TIMER + 0x3B,
579 .flags = IORESOURCE_MEM,
580 },
581 [1] = {
582 .start = IRQ_TIMER3,
583 .end = IRQ_TIMER3,
584 .flags = IORESOURCE_IRQ,
585 }
586
587};
588
589struct platform_device s3c_device_timer3 = {
590 .name = "s3c2410-timer",
591 .id = 3,
592 .num_resources = ARRAY_SIZE(s3c_timer3_resource),
593 .resource = s3c_timer3_resource,
594};
595
596EXPORT_SYMBOL(s3c_device_timer3);
597
598#ifdef CONFIG_CPU_S3C2440 498#ifdef CONFIG_CPU_S3C2440
599 499
600/* Camif Controller */ 500/* Camif Controller */
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
new file mode 100644
index 000000000000..825d8d0c5ca2
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -0,0 +1,259 @@
1/* linux/arch/arm/plat-s3c24xx/gpiolib.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX GPIOlib support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12*/
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21
22#include <asm/hardware.h>
23#include <asm/irq.h>
24
25#include <asm/arch/regs-gpio.h>
26
27struct s3c24xx_gpio_chip {
28 struct gpio_chip chip;
29 void __iomem *base;
30};
31
32static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
33{
34 return container_of(gpc, struct s3c24xx_gpio_chip, chip);
35}
36
37/* these routines are exported for use by other parts of the platform
38 * and system support, but are not intended to be used directly by the
39 * drivers themsevles.
40 */
41
42int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
43{
44 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
45 void __iomem *base = ourchip->base;
46 unsigned long flags;
47 unsigned long con;
48
49 local_irq_save(flags);
50
51 con = __raw_readl(base + 0x00);
52 con &= ~(3 << (offset * 2));
53 con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
54
55 __raw_writel(con, base + 0x00);
56
57 local_irq_restore(flags);
58 return 0;
59}
60
61int s3c24xx_gpiolib_output(struct gpio_chip *chip,
62 unsigned offset, int value)
63{
64 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
65 void __iomem *base = ourchip->base;
66 unsigned long flags;
67 unsigned long dat;
68 unsigned long con;
69
70 local_irq_save(flags);
71
72 dat = __raw_readl(base + 0x04);
73 dat &= ~(1 << offset);
74 if (value)
75 dat |= 1 << offset;
76 __raw_writel(dat, base + 0x04);
77
78 con = __raw_readl(base + 0x00);
79 con &= ~(3 << (offset * 2));
80 con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
81
82 __raw_writel(con, base + 0x00);
83 __raw_writel(dat, base + 0x04);
84
85 local_irq_restore(flags);
86 return 0;
87}
88
89void s3c24xx_gpiolib_set(struct gpio_chip *chip, unsigned offset, int value)
90{
91 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
92 void __iomem *base = ourchip->base;
93 unsigned long flags;
94 unsigned long dat;
95
96 local_irq_save(flags);
97
98 dat = __raw_readl(base + 0x04);
99 dat &= ~(1 << offset);
100 if (value)
101 dat |= 1 << offset;
102 __raw_writel(dat, base + 0x04);
103
104 local_irq_restore(flags);
105}
106
107int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
108{
109 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
110 unsigned long val;
111
112 val = __raw_readl(ourchip->base + 0x04);
113 val >>= offset;
114 val &= 1;
115
116 return val;
117}
118
119static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
120{
121 return -EINVAL;
122}
123
124static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
125 unsigned offset, int value)
126{
127 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
128 void __iomem *base = ourchip->base;
129 unsigned long flags;
130 unsigned long dat;
131 unsigned long con;
132
133 local_irq_save(flags);
134
135 con = __raw_readl(base + 0x00);
136 dat = __raw_readl(base + 0x04);
137
138 dat &= ~(1 << offset);
139 if (value)
140 dat |= 1 << offset;
141
142 __raw_writel(dat, base + 0x04);
143
144 con &= ~(1 << offset);
145
146 __raw_writel(con, base + 0x00);
147 __raw_writel(dat, base + 0x04);
148
149 local_irq_restore(flags);
150 return 0;
151}
152
153
154struct s3c24xx_gpio_chip gpios[] = {
155 [0] = {
156 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
157 .chip = {
158 .base = S3C2410_GPA0,
159 .owner = THIS_MODULE,
160 .label = "GPIOA",
161 .ngpio = 24,
162 .direction_input = s3c24xx_gpiolib_banka_input,
163 .direction_output = s3c24xx_gpiolib_banka_output,
164 .set = s3c24xx_gpiolib_set,
165 .get = s3c24xx_gpiolib_get,
166 },
167 },
168 [1] = {
169 .base = S3C24XX_GPIO_BASE(S3C2410_GPB0),
170 .chip = {
171 .base = S3C2410_GPB0,
172 .owner = THIS_MODULE,
173 .label = "GPIOB",
174 .ngpio = 16,
175 .direction_input = s3c24xx_gpiolib_input,
176 .direction_output = s3c24xx_gpiolib_output,
177 .set = s3c24xx_gpiolib_set,
178 .get = s3c24xx_gpiolib_get,
179 },
180 },
181 [2] = {
182 .base = S3C24XX_GPIO_BASE(S3C2410_GPC0),
183 .chip = {
184 .base = S3C2410_GPC0,
185 .owner = THIS_MODULE,
186 .label = "GPIOC",
187 .ngpio = 16,
188 .direction_input = s3c24xx_gpiolib_input,
189 .direction_output = s3c24xx_gpiolib_output,
190 .set = s3c24xx_gpiolib_set,
191 .get = s3c24xx_gpiolib_get,
192 },
193 },
194 [3] = {
195 .base = S3C24XX_GPIO_BASE(S3C2410_GPD0),
196 .chip = {
197 .base = S3C2410_GPD0,
198 .owner = THIS_MODULE,
199 .label = "GPIOD",
200 .ngpio = 16,
201 .direction_input = s3c24xx_gpiolib_input,
202 .direction_output = s3c24xx_gpiolib_output,
203 .set = s3c24xx_gpiolib_set,
204 .get = s3c24xx_gpiolib_get,
205 },
206 },
207 [4] = {
208 .base = S3C24XX_GPIO_BASE(S3C2410_GPE0),
209 .chip = {
210 .base = S3C2410_GPE0,
211 .label = "GPIOE",
212 .owner = THIS_MODULE,
213 .ngpio = 16,
214 .direction_input = s3c24xx_gpiolib_input,
215 .direction_output = s3c24xx_gpiolib_output,
216 .set = s3c24xx_gpiolib_set,
217 .get = s3c24xx_gpiolib_get,
218 },
219 },
220 [5] = {
221 .base = S3C24XX_GPIO_BASE(S3C2410_GPF0),
222 .chip = {
223 .base = S3C2410_GPF0,
224 .owner = THIS_MODULE,
225 .label = "GPIOF",
226 .ngpio = 8,
227 .direction_input = s3c24xx_gpiolib_input,
228 .direction_output = s3c24xx_gpiolib_output,
229 .set = s3c24xx_gpiolib_set,
230 .get = s3c24xx_gpiolib_get,
231 },
232 },
233 [6] = {
234 .base = S3C24XX_GPIO_BASE(S3C2410_GPG0),
235 .chip = {
236 .base = S3C2410_GPG0,
237 .owner = THIS_MODULE,
238 .label = "GPIOG",
239 .ngpio = 10,
240 .direction_input = s3c24xx_gpiolib_input,
241 .direction_output = s3c24xx_gpiolib_output,
242 .set = s3c24xx_gpiolib_set,
243 .get = s3c24xx_gpiolib_get,
244 },
245 },
246};
247
248static __init int s3c24xx_gpiolib_init(void)
249{
250 struct s3c24xx_gpio_chip *chip = gpios;
251 int gpn;
252
253 for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++)
254 gpiochip_add(&chip->chip);
255
256 return 0;
257}
258
259arch_initcall(s3c24xx_gpiolib_init);
diff --git a/arch/arm/plat-s3c24xx/pwm-clock.c b/arch/arm/plat-s3c24xx/pwm-clock.c
new file mode 100644
index 000000000000..2cda3e3c6786
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/pwm-clock.c
@@ -0,0 +1,437 @@
1/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Copyright (c) 2007, 2008 Ben Dooks
5 * Ben Dooks <ben-linux@fluff.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10*/
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/io.h>
20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23
24#include <asm/arch/regs-clock.h>
25#include <asm/arch/regs-gpio.h>
26
27#include <asm/plat-s3c24xx/clock.h>
28#include <asm/plat-s3c24xx/cpu.h>
29
30#include <asm/plat-s3c/regs-timer.h>
31
32/* Each of the timers 0 through 5 go through the following
33 * clock tree, with the inputs depending on the timers.
34 *
35 * pclk ---- [ prescaler 0 ] -+---> timer 0
36 * +---> timer 1
37 *
38 * pclk ---- [ prescaler 1 ] -+---> timer 2
39 * +---> timer 3
40 * \---> timer 4
41 *
42 * Which are fed into the timers as so:
43 *
44 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
45 * [mux] -> timer 0
46 * tclk 0 ------------------------------/
47 *
48 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
49 * [mux] -> timer 1
50 * tclk 0 ------------------------------/
51 *
52 *
53 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
54 * [mux] -> timer 2
55 * tclk 1 ------------------------------/
56 *
57 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
58 * [mux] -> timer 3
59 * tclk 1 ------------------------------/
60 *
61 * prescaled 1 ---- [ div 2,4,8, 16 ] --\
62 * [mux] -> timer 4
63 * tclk 1 ------------------------------/
64 *
65 * Since the mux and the divider are tied together in the
66 * same register space, it is impossible to set the parent
67 * and the rate at the same time. To avoid this, we add an
68 * intermediate 'prescaled-and-divided' clock to select
69 * as the parent for the timer input clock called tdiv.
70 *
71 * prescaled clk --> pwm-tdiv ---\
72 * [ mux ] --> timer X
73 * tclk -------------------------/
74*/
75
76static unsigned long clk_pwm_scaler_getrate(struct clk *clk)
77{
78 unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
79
80 if (clk->id == 1) {
81 tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
82 tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
83 } else {
84 tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
85 }
86
87 return clk_get_rate(clk->parent) / (tcfg0 + 1);
88}
89
90/* TODO - add set rate calls. */
91
92struct clk clk_timer_scaler[] = {
93 [0] = {
94 .name = "pwm-scaler0",
95 .id = -1,
96 .get_rate = clk_pwm_scaler_getrate,
97 },
98 [1] = {
99 .name = "pwm-scaler1",
100 .id = -1,
101 .get_rate = clk_pwm_scaler_getrate,
102 },
103};
104
105struct clk clk_timer_tclk[] = {
106 [0] = {
107 .name = "pwm-tclk0",
108 .id = -1,
109 },
110 [1] = {
111 .name = "pwm-tclk1",
112 .id = -1,
113 },
114};
115
116struct pwm_tdiv_clk {
117 struct clk clk;
118 unsigned int divisor;
119};
120
121static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
122{
123 return container_of(clk, struct pwm_tdiv_clk, clk);
124}
125
126static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
127{
128 return 1 << (1 + tcfg1);
129}
130
131static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
132{
133 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
134 unsigned int divisor;
135
136 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
137 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
138
139 if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
140 divisor = to_tdiv(clk)->divisor;
141 else
142 divisor = tcfg_to_divisor(tcfg1);
143
144 return clk_get_rate(clk->parent) / divisor;
145}
146
147static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
148 unsigned long rate)
149{
150 unsigned long parent_rate;
151 unsigned long divisor;
152
153 parent_rate = clk_get_rate(clk->parent);
154 divisor = parent_rate / rate;
155
156 if (divisor <= 2)
157 divisor = 2;
158 else if (divisor <= 4)
159 divisor = 4;
160 else if (divisor <= 8)
161 divisor = 8;
162 else
163 divisor = 16;
164
165 return parent_rate / divisor;
166}
167
168static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
169{
170 unsigned long bits;
171
172 switch (divclk->divisor) {
173 case 2:
174 bits = S3C2410_TCFG1_MUX_DIV2;
175 break;
176 case 4:
177 bits = S3C2410_TCFG1_MUX_DIV4;
178 break;
179 case 8:
180 bits = S3C2410_TCFG1_MUX_DIV8;
181 break;
182 case 16:
183 default:
184 bits = S3C2410_TCFG1_MUX_DIV16;
185 break;
186 }
187
188 return bits;
189}
190
191static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
192{
193 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
194 unsigned long bits = clk_pwm_tdiv_bits(divclk);
195 unsigned long flags;
196 unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id);
197
198 local_irq_save(flags);
199
200 tcfg1 = __raw_readl(S3C2410_TCFG1);
201 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
202 tcfg1 |= bits << shift;
203 __raw_writel(tcfg1, S3C2410_TCFG1);
204
205 local_irq_restore(flags);
206}
207
208static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
209{
210 struct pwm_tdiv_clk *divclk = to_tdiv(clk);
211 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
212 unsigned long parent_rate = clk_get_rate(clk->parent);
213 unsigned long divisor;
214
215 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
216 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
217
218 rate = clk_round_rate(clk, rate);
219 divisor = parent_rate / rate;
220
221 if (divisor > 16)
222 return -EINVAL;
223
224 divclk->divisor = divisor;
225
226 /* Update the current MUX settings if we are currently
227 * selected as the clock source for this clock. */
228
229 if (tcfg1 != S3C2410_TCFG1_MUX_TCLK)
230 clk_pwm_tdiv_update(divclk);
231
232 return 0;
233}
234
235struct pwm_tdiv_clk clk_timer_tdiv[] = {
236 [0] = {
237 .clk = {
238 .name = "pwm-tdiv",
239 .parent = &clk_timer_scaler[0],
240 .get_rate = clk_pwm_tdiv_get_rate,
241 .set_rate = clk_pwm_tdiv_set_rate,
242 .round_rate = clk_pwm_tdiv_round_rate,
243 },
244 },
245 [1] = {
246 .clk = {
247 .name = "pwm-tdiv",
248 .parent = &clk_timer_scaler[0],
249 .get_rate = clk_pwm_tdiv_get_rate,
250 .set_rate = clk_pwm_tdiv_set_rate,
251 .round_rate = clk_pwm_tdiv_round_rate,
252 }
253 },
254 [2] = {
255 .clk = {
256 .name = "pwm-tdiv",
257 .parent = &clk_timer_scaler[1],
258 .get_rate = clk_pwm_tdiv_get_rate,
259 .set_rate = clk_pwm_tdiv_set_rate,
260 .round_rate = clk_pwm_tdiv_round_rate,
261 },
262 },
263 [3] = {
264 .clk = {
265 .name = "pwm-tdiv",
266 .parent = &clk_timer_scaler[1],
267 .get_rate = clk_pwm_tdiv_get_rate,
268 .set_rate = clk_pwm_tdiv_set_rate,
269 .round_rate = clk_pwm_tdiv_round_rate,
270 },
271 },
272 [4] = {
273 .clk = {
274 .name = "pwm-tdiv",
275 .parent = &clk_timer_scaler[1],
276 .get_rate = clk_pwm_tdiv_get_rate,
277 .set_rate = clk_pwm_tdiv_set_rate,
278 .round_rate = clk_pwm_tdiv_round_rate,
279 },
280 },
281};
282
283static int __init clk_pwm_tdiv_register(unsigned int id)
284{
285 struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
286 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
287
288 tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
289 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
290
291 divclk->clk.id = id;
292 divclk->divisor = tcfg_to_divisor(tcfg1);
293
294 return s3c24xx_register_clock(&divclk->clk);
295}
296
297static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
298{
299 return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
300}
301
302static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
303{
304 return &clk_timer_tdiv[id].clk;
305}
306
307static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
308{
309 unsigned int id = clk->id;
310 unsigned long tcfg1;
311 unsigned long flags;
312 unsigned long bits;
313 unsigned long shift = S3C2410_TCFG1_SHIFT(id);
314
315 if (parent == s3c24xx_pwmclk_tclk(id))
316 bits = S3C2410_TCFG1_MUX_TCLK << shift;
317 else if (parent == s3c24xx_pwmclk_tdiv(id))
318 bits = clk_pwm_tdiv_bits(to_tdiv(clk)) << shift;
319 else
320 return -EINVAL;
321
322 clk->parent = parent;
323
324 local_irq_save(flags);
325
326 tcfg1 = __raw_readl(S3C2410_TCFG1);
327 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
328 __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
329
330 local_irq_restore(flags);
331
332 return 0;
333}
334
335static struct clk clk_tin[] = {
336 [0] = {
337 .name = "pwm-tin",
338 .id = 0,
339 .set_parent = clk_pwm_tin_set_parent,
340 },
341 [1] = {
342 .name = "pwm-tin",
343 .id = 1,
344 .set_parent = clk_pwm_tin_set_parent,
345 },
346 [2] = {
347 .name = "pwm-tin",
348 .id = 2,
349 .set_parent = clk_pwm_tin_set_parent,
350 },
351 [3] = {
352 .name = "pwm-tin",
353 .id = 3,
354 .set_parent = clk_pwm_tin_set_parent,
355 },
356 [4] = {
357 .name = "pwm-tin",
358 .id = 4,
359 .set_parent = clk_pwm_tin_set_parent,
360 },
361};
362
363static __init int clk_pwm_tin_register(struct clk *pwm)
364{
365 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
366 unsigned int id = pwm->id;
367
368 struct clk *parent;
369 int ret;
370
371 ret = s3c24xx_register_clock(pwm);
372 if (ret < 0)
373 return ret;
374
375 tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
376 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
377
378 if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
379 parent = s3c24xx_pwmclk_tclk(id);
380 else
381 parent = s3c24xx_pwmclk_tdiv(id);
382
383 return clk_set_parent(pwm, parent);
384}
385
386static __init int s3c24xx_pwmclk_init(void)
387{
388 struct clk *clk_timers;
389 unsigned int clk;
390 int ret;
391
392 clk_timers = clk_get(NULL, "timers");
393 if (IS_ERR(clk_timers)) {
394 printk(KERN_ERR "%s: no parent clock\n", __func__);
395 return -EINVAL;
396 }
397
398 for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
399 clk_timer_scaler[clk].parent = clk_timers;
400 ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
401 if (ret < 0) {
402 printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
403 goto err;
404 }
405 }
406
407 for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
408 ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
409 if (ret < 0) {
410 printk(KERN_ERR "error adding pww tclk%d\n", clk);
411 goto err;
412 }
413 }
414
415 for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
416 ret = clk_pwm_tdiv_register(clk);
417 if (ret < 0) {
418 printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
419 goto err;
420 }
421 }
422
423 for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
424 ret = clk_pwm_tin_register(&clk_tin[clk]);
425 if (ret < 0) {
426 printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
427 goto err;
428 }
429 }
430
431 return 0;
432
433 err:
434 return ret;
435}
436
437arch_initcall(s3c24xx_pwmclk_init);
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c24xx/pwm.c
new file mode 100644
index 000000000000..18c4bdc49a05
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/pwm.c
@@ -0,0 +1,402 @@
1/* arch/arm/plat-s3c24xx/pwm.c
2 *
3 * Copyright (c) 2007 Ben Dooks
4 * Copyright (c) 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
6 *
7 * S3C24XX PWM device core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12*/
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/pwm.h>
21
22#include <asm/plat-s3c/regs-timer.h>
23
24struct pwm_device {
25 struct list_head list;
26 struct platform_device *pdev;
27
28 struct clk *clk_div;
29 struct clk *clk;
30 const char *label;
31
32 unsigned int period_ns;
33 unsigned int duty_ns;
34
35 unsigned char tcon_base;
36 unsigned char running;
37 unsigned char use_count;
38 unsigned char pwm_id;
39};
40
41#define pwm_dbg(_pwm, msg...) dev_info(&(_pwm)->pdev->dev, msg)
42
43static struct clk *clk_scaler[2];
44
45/* Standard setup for a timer block. */
46
47#define TIMER_RESOURCE_SIZE (1)
48
49#define TIMER_RESOURCE(_tmr, _irq) \
50 (struct resource [TIMER_RESOURCE_SIZE]) { \
51 [0] = { \
52 .start = _irq, \
53 .end = _irq, \
54 .flags = IORESOURCE_IRQ \
55 } \
56 }
57
58#define DEFINE_TIMER(_tmr_no, _irq) \
59 .name = "s3c24xx-pwm", \
60 .id = _tmr_no, \
61 .num_resources = TIMER_RESOURCE_SIZE, \
62 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
63
64/* since we already have an static mapping for the timer, we do not
65 * bother setting any IO resource for the base.
66 */
67
68struct platform_device s3c_device_timer[] = {
69 [0] = { DEFINE_TIMER(0, IRQ_TIMER0) },
70 [1] = { DEFINE_TIMER(1, IRQ_TIMER1) },
71 [2] = { DEFINE_TIMER(2, IRQ_TIMER2) },
72 [3] = { DEFINE_TIMER(3, IRQ_TIMER3) },
73 [4] = { DEFINE_TIMER(4, IRQ_TIMER4) },
74};
75
76static inline int pwm_is_tdiv(struct pwm_device *pwm)
77{
78 return clk_get_parent(pwm->clk) == pwm->clk_div;
79}
80
81static DEFINE_MUTEX(pwm_lock);
82static LIST_HEAD(pwm_list);
83
84struct pwm_device *pwm_request(int pwm_id, const char *label)
85{
86 struct pwm_device *pwm;
87 int found = 0;
88
89 mutex_lock(&pwm_lock);
90
91 list_for_each_entry(pwm, &pwm_list, list) {
92 if (pwm->pwm_id == pwm_id) {
93 found = 1;
94 break;
95 }
96 }
97
98 if (found) {
99 if (pwm->use_count == 0) {
100 pwm->use_count = 1;
101 pwm->label = label;
102 } else
103 pwm = ERR_PTR(-EBUSY);
104 } else
105 pwm = ERR_PTR(-ENOENT);
106
107 mutex_unlock(&pwm_lock);
108 return pwm;
109}
110
111EXPORT_SYMBOL(pwm_request);
112
113
114void pwm_free(struct pwm_device *pwm)
115{
116 mutex_lock(&pwm_lock);
117
118 if (pwm->use_count) {
119 pwm->use_count--;
120 pwm->label = NULL;
121 } else
122 printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id);
123
124 mutex_unlock(&pwm_lock);
125}
126
127EXPORT_SYMBOL(pwm_free);
128
129#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0))
130#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2))
131#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3))
132#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1))
133
134int pwm_enable(struct pwm_device *pwm)
135{
136 unsigned long flags;
137 unsigned long tcon;
138
139 local_irq_save(flags);
140
141 tcon = __raw_readl(S3C2410_TCON);
142 tcon |= pwm_tcon_start(pwm);
143 __raw_writel(tcon, S3C2410_TCON);
144
145 local_irq_restore(flags);
146
147 pwm->running = 1;
148 return 0;
149}
150
151EXPORT_SYMBOL(pwm_enable);
152
153void pwm_disable(struct pwm_device *pwm)
154{
155 unsigned long flags;
156 unsigned long tcon;
157
158 local_irq_save(flags);
159
160 tcon = __raw_readl(S3C2410_TCON);
161 tcon &= ~pwm_tcon_start(pwm);
162 __raw_writel(tcon, S3C2410_TCON);
163
164 local_irq_restore(flags);
165
166 pwm->running = 0;
167}
168
169EXPORT_SYMBOL(pwm_disable);
170
171unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
172{
173 unsigned long tin_parent_rate;
174 unsigned int div;
175
176 tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div));
177 pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate);
178
179 for (div = 2; div <= 16; div *= 2) {
180 if ((tin_parent_rate / (div << 16)) < freq)
181 return tin_parent_rate / div;
182 }
183
184 return tin_parent_rate / 16;
185}
186
187#define NS_IN_HZ (1000000000UL)
188
189int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
190{
191 unsigned long tin_rate;
192 unsigned long tin_ns;
193 unsigned long period;
194 unsigned long flags;
195 unsigned long tcon;
196 unsigned long tcnt;
197 long tcmp;
198
199 /* We currently avoid using 64bit arithmetic by using the
200 * fact that anything faster than 1Hz is easily representable
201 * by 32bits. */
202
203 if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
204 return -ERANGE;
205
206 if (duty_ns > period_ns)
207 return -EINVAL;
208
209 if (period_ns == pwm->period_ns &&
210 duty_ns == pwm->duty_ns)
211 return 0;
212
213 /* The TCMP and TCNT can be read without a lock, they're not
214 * shared between the timers. */
215
216 tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id));
217 tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id));
218
219 period = NS_IN_HZ / period_ns;
220
221 pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n",
222 duty_ns, period_ns, period);
223
224 /* Check to see if we are changing the clock rate of the PWM */
225
226 if (pwm->period_ns != period_ns) {
227 if (pwm_is_tdiv(pwm)) {
228 tin_rate = pwm_calc_tin(pwm, period);
229 clk_set_rate(pwm->clk_div, tin_rate);
230 } else
231 tin_rate = clk_get_rate(pwm->clk);
232
233 pwm->period_ns = period_ns;
234
235 pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate);
236
237 tin_ns = NS_IN_HZ / tin_rate;
238 tcnt = period_ns / tin_ns;
239 } else
240 tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk);
241
242 /* Note, counters count down */
243
244 tcmp = duty_ns / tin_ns;
245 tcmp = tcnt - tcmp;
246
247 pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
248
249 if (tcmp < 0)
250 tcmp = 0;
251
252 /* Update the PWM register block. */
253
254 local_irq_save(flags);
255
256 __raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id));
257 __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id));
258
259 tcon = __raw_readl(S3C2410_TCON);
260 tcon |= pwm_tcon_manulupdate(pwm);
261 tcon |= pwm_tcon_autoreload(pwm);
262 __raw_writel(tcon, S3C2410_TCON);
263
264 tcon &= ~pwm_tcon_manulupdate(pwm);
265 __raw_writel(tcon, S3C2410_TCON);
266
267 local_irq_restore(flags);
268
269 return 0;
270}
271
272EXPORT_SYMBOL(pwm_config);
273
274static int pwm_register(struct pwm_device *pwm)
275{
276 pwm->duty_ns = -1;
277 pwm->period_ns = -1;
278
279 mutex_lock(&pwm_lock);
280 list_add_tail(&pwm->list, &pwm_list);
281 mutex_unlock(&pwm_lock);
282
283 return 0;
284}
285
286static int s3c_pwm_probe(struct platform_device *pdev)
287{
288 struct device *dev = &pdev->dev;
289 struct pwm_device *pwm;
290 unsigned long flags;
291 unsigned long tcon;
292 unsigned int id = pdev->id;
293 int ret;
294
295 if (id == 4) {
296 dev_err(dev, "TIMER4 is currently not supported\n");
297 return -ENXIO;
298 }
299
300 pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
301 if (pwm == NULL) {
302 dev_err(dev, "failed to allocate pwm_device\n");
303 return -ENOMEM;
304 }
305
306 pwm->pdev = pdev;
307 pwm->pwm_id = id;
308
309 /* calculate base of control bits in TCON */
310 pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4;
311
312 pwm->clk = clk_get(dev, "pwm-tin");
313 if (IS_ERR(pwm->clk)) {
314 dev_err(dev, "failed to get pwm tin clk\n");
315 ret = PTR_ERR(pwm->clk);
316 goto err_alloc;
317 }
318
319 pwm->clk_div = clk_get(dev, "pwm-tdiv");
320 if (IS_ERR(pwm->clk_div)) {
321 dev_err(dev, "failed to get pwm tdiv clk\n");
322 ret = PTR_ERR(pwm->clk_div);
323 goto err_clk_tin;
324 }
325
326 local_irq_save(flags);
327
328 tcon = __raw_readl(S3C2410_TCON);
329 tcon |= pwm_tcon_invert(pwm);
330 __raw_writel(tcon, S3C2410_TCON);
331
332 local_irq_restore(flags);
333
334
335 ret = pwm_register(pwm);
336 if (ret) {
337 dev_err(dev, "failed to register pwm\n");
338 goto err_clk_tdiv;
339 }
340
341 pwm_dbg(pwm, "config bits %02x\n",
342 (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f);
343
344 dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
345 clk_get_rate(pwm->clk),
346 clk_get_rate(pwm->clk_div),
347 pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base);
348
349 platform_set_drvdata(pdev, pwm);
350 return 0;
351
352 err_clk_tdiv:
353 clk_put(pwm->clk_div);
354
355 err_clk_tin:
356 clk_put(pwm->clk);
357
358 err_alloc:
359 kfree(pwm);
360 return ret;
361}
362
363static int s3c_pwm_remove(struct platform_device *pdev)
364{
365 struct pwm_device *pwm = platform_get_drvdata(pdev);
366
367 clk_put(pwm->clk_div);
368 clk_put(pwm->clk);
369 kfree(pwm);
370
371 return 0;
372}
373
374static struct platform_driver s3c_pwm_driver = {
375 .driver = {
376 .name = "s3c24xx-pwm",
377 .owner = THIS_MODULE,
378 },
379 .probe = s3c_pwm_probe,
380 .remove = __devexit_p(s3c_pwm_remove),
381};
382
383static int __init pwm_init(void)
384{
385 int ret;
386
387 clk_scaler[0] = clk_get(NULL, "pwm-scaler0");
388 clk_scaler[1] = clk_get(NULL, "pwm-scaler1");
389
390 if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) {
391 printk(KERN_ERR "%s: failed to get scaler clocks\n", __func__);
392 return -EINVAL;
393 }
394
395 ret = platform_driver_register(&s3c_pwm_driver);
396 if (ret)
397 printk(KERN_ERR "%s: failed to add pwm driver\n", __func__);
398
399 return ret;
400}
401
402arch_initcall(pwm_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 17:57:11 -0500