diff options
Diffstat (limited to 'arch/arm/plat-s3c24xx/s3c2443-clock.c')
-rw-r--r-- | arch/arm/plat-s3c24xx/s3c2443-clock.c | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 59552c0ea5fb..07a4c81587ac 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c | |||
@@ -205,9 +205,64 @@ static struct clksrc_clk clksrc_clks[] = { | |||
205 | }, | 205 | }, |
206 | }; | 206 | }; |
207 | 207 | ||
208 | static struct clk clk_i2s_ext = { | ||
209 | .name = "i2s-ext", | ||
210 | }; | ||
211 | |||
212 | /* i2s_eplldiv | ||
213 | * | ||
214 | * This clock is the output from the I2S divisor of ESYSCLK, and is separate | ||
215 | * from the mux that comes after it (cannot merge into one single clock) | ||
216 | */ | ||
217 | |||
218 | static struct clksrc_clk clk_i2s_eplldiv = { | ||
219 | .clk = { | ||
220 | .name = "i2s-eplldiv", | ||
221 | .parent = &clk_esysclk.clk, | ||
222 | }, | ||
223 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, | ||
224 | }; | ||
225 | |||
226 | /* i2s-ref | ||
227 | * | ||
228 | * i2s bus reference clock, selectable from external, esysclk or epllref | ||
229 | * | ||
230 | * Note, this used to be two clocks, but was compressed into one. | ||
231 | */ | ||
232 | |||
233 | static struct clk *clk_i2s_srclist[] = { | ||
234 | [0] = &clk_i2s_eplldiv.clk, | ||
235 | [1] = &clk_i2s_ext, | ||
236 | [2] = &clk_epllref.clk, | ||
237 | [3] = &clk_epllref.clk, | ||
238 | }; | ||
239 | |||
240 | static struct clksrc_clk clk_i2s = { | ||
241 | .clk = { | ||
242 | .name = "i2s-if", | ||
243 | .ctrlbit = S3C2443_SCLKCON_I2SCLK, | ||
244 | .enable = s3c2443_clkcon_enable_s, | ||
245 | |||
246 | }, | ||
247 | .sources = &(struct clksrc_sources) { | ||
248 | .sources = clk_i2s_srclist, | ||
249 | .nr_sources = ARRAY_SIZE(clk_i2s_srclist), | ||
250 | }, | ||
251 | .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 }, | ||
252 | }; | ||
208 | 253 | ||
209 | static struct clk init_clocks_off[] = { | 254 | static struct clk init_clocks_off[] = { |
210 | { | 255 | { |
256 | .name = "iis", | ||
257 | .parent = &clk_p, | ||
258 | .enable = s3c2443_clkcon_enable_p, | ||
259 | .ctrlbit = S3C2443_PCLKCON_IIS, | ||
260 | }, { | ||
261 | .name = "hsspi", | ||
262 | .parent = &clk_p, | ||
263 | .enable = s3c2443_clkcon_enable_p, | ||
264 | .ctrlbit = S3C2443_PCLKCON_HSSPI, | ||
265 | }, { | ||
211 | .name = "adc", | 266 | .name = "adc", |
212 | .parent = &clk_p, | 267 | .parent = &clk_p, |
213 | .enable = s3c2443_clkcon_enable_p, | 268 | .enable = s3c2443_clkcon_enable_p, |
@@ -406,6 +461,8 @@ static struct clk *clks[] __initdata = { | |||
406 | }; | 461 | }; |
407 | 462 | ||
408 | static struct clksrc_clk *clksrcs[] __initdata = { | 463 | static struct clksrc_clk *clksrcs[] __initdata = { |
464 | &clk_i2s_eplldiv, | ||
465 | &clk_i2s, | ||
409 | &clk_usb_bus_host, | 466 | &clk_usb_bus_host, |
410 | &clk_epllref, | 467 | &clk_epllref, |
411 | &clk_esysclk, | 468 | &clk_esysclk, |