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-rw-r--r--arch/arm/plat-s3c24xx/include/mach/pwm-clock.h55
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/clock.h64
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/cpu.h54
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/devs.h49
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/map.h99
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/mci.h15
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pll.h37
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-spi.h82
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-udc.h153
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2400.h2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2410.h2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2412.h2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2443.h2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/udc.h36
14 files changed, 481 insertions, 171 deletions
diff --git a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
new file mode 100644
index 000000000000..a087de21bc20
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
@@ -0,0 +1,55 @@
1/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C24xx - pwm clock and timer support
8 */
9
10/**
11 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
12 * @cfg: The timer TCFG1 register bits shifted down to 0.
13 *
14 * Return true if the given configuration from TCFG1 is a TCLK instead
15 * any of the TDIV clocks.
16 */
17static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
18{
19 return tcfg == S3C2410_TCFG1_MUX_TCLK;
20}
21
22/**
23 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
24 * @tcfg1: The tcfg1 setting, shifted down.
25 *
26 * Get the divisor value for the given tcfg1 setting. We assume the
27 * caller has already checked to see if this is not a TCLK source.
28 */
29static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
30{
31 return 1 << (1 + tcfg1);
32}
33
34/**
35 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
36 *
37 * Return true if we have a /1 in the tdiv setting.
38 */
39static inline unsigned int pwm_tdiv_has_div1(void)
40{
41 return 0;
42}
43
44/**
45 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
46 * @div: The divisor to calculate the bit information for.
47 *
48 * Turn a divisor into the necessary bit field for TCFG1.
49 */
50static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
51{
52 return ilog2(div) - 1;
53}
54
55#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
diff --git a/arch/arm/plat-s3c24xx/include/plat/clock.h b/arch/arm/plat-s3c24xx/include/plat/clock.h
deleted file mode 100644
index 235b753cd877..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/clock.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/clock.h
2 * linux/arch/arm/mach-s3c2410/clock.h
3 *
4 * Copyright (c) 2004-2005 Simtec Electronics
5 * http://www.simtec.co.uk/products/SWLINUX/
6 * Written by Ben Dooks, <ben@simtec.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct clk {
14 struct list_head list;
15 struct module *owner;
16 struct clk *parent;
17 const char *name;
18 int id;
19 int usage;
20 unsigned long rate;
21 unsigned long ctrlbit;
22
23 int (*enable)(struct clk *, int enable);
24 int (*set_rate)(struct clk *c, unsigned long rate);
25 unsigned long (*get_rate)(struct clk *c);
26 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
27 int (*set_parent)(struct clk *c, struct clk *parent);
28};
29
30/* other clocks which may be registered by board support */
31
32extern struct clk s3c24xx_dclk0;
33extern struct clk s3c24xx_dclk1;
34extern struct clk s3c24xx_clkout0;
35extern struct clk s3c24xx_clkout1;
36extern struct clk s3c24xx_uclk;
37
38extern struct clk clk_usb_bus;
39
40/* core clock support */
41
42extern struct clk clk_f;
43extern struct clk clk_h;
44extern struct clk clk_p;
45extern struct clk clk_mpll;
46extern struct clk clk_upll;
47extern struct clk clk_xtal;
48
49/* exports for arch/arm/mach-s3c2410
50 *
51 * Please DO NOT use these outside of arch/arm/mach-s3c2410
52*/
53
54extern struct mutex clocks_mutex;
55
56extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
57
58extern int s3c24xx_register_clock(struct clk *clk);
59extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
60
61extern int s3c24xx_setup_clocks(unsigned long xtal,
62 unsigned long fclk,
63 unsigned long hclk,
64 unsigned long pclk);
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu.h b/arch/arm/plat-s3c24xx/include/plat/cpu.h
deleted file mode 100644
index 23e420e8bd5b..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/cpu.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/cpu.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* todo - fix when rmk changes iodescs to use `void __iomem *` */
14
15#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
16
17#ifndef MHZ
18#define MHZ (1000*1000)
19#endif
20
21#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
22
23/* forward declaration */
24struct s3c24xx_uart_resources;
25struct platform_device;
26struct s3c2410_uartcfg;
27struct map_desc;
28
29/* core initialisation functions */
30
31extern void s3c24xx_init_irq(void);
32
33extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
34
35extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
36
37extern void s3c24xx_init_clocks(int xtal);
38
39extern void s3c24xx_init_uartdevs(char *name,
40 struct s3c24xx_uart_resources *res,
41 struct s3c2410_uartcfg *cfg, int no);
42
43/* timer for 2410/2440 */
44
45struct sys_timer;
46extern struct sys_timer s3c24xx_timer;
47
48/* system device classes */
49
50extern struct sysdev_class s3c2410_sysclass;
51extern struct sysdev_class s3c2412_sysclass;
52extern struct sysdev_class s3c2440_sysclass;
53extern struct sysdev_class s3c2442_sysclass;
54extern struct sysdev_class s3c2443_sysclass;
diff --git a/arch/arm/plat-s3c24xx/include/plat/devs.h b/arch/arm/plat-s3c24xx/include/plat/devs.h
deleted file mode 100644
index badaac9d64a8..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/devs.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/devs.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2410 standard platform devices
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12#include <linux/platform_device.h>
13
14struct s3c24xx_uart_resources {
15 struct resource *resources;
16 unsigned long nr_resources;
17};
18
19extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
20
21extern struct platform_device *s3c24xx_uart_devs[];
22extern struct platform_device *s3c24xx_uart_src[];
23
24extern struct platform_device s3c_device_timer[];
25
26extern struct platform_device s3c_device_usb;
27extern struct platform_device s3c_device_lcd;
28extern struct platform_device s3c_device_wdt;
29extern struct platform_device s3c_device_i2c;
30extern struct platform_device s3c_device_iis;
31extern struct platform_device s3c_device_rtc;
32extern struct platform_device s3c_device_adc;
33extern struct platform_device s3c_device_sdi;
34extern struct platform_device s3c_device_hsmmc;
35
36extern struct platform_device s3c_device_spi0;
37extern struct platform_device s3c_device_spi1;
38
39extern struct platform_device s3c_device_nand;
40
41extern struct platform_device s3c_device_usbgadget;
42
43/* s3c2440 specific devices */
44
45#ifdef CONFIG_CPU_S3C2440
46
47extern struct platform_device s3c_device_camif;
48
49#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
new file mode 100644
index 000000000000..fef8ea8b8e1e
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/map.h
@@ -0,0 +1,99 @@
1/* linux/include/asm-arm/plat-s3c24xx/map.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S3C24XX_MAP_H
14#define __ASM_PLAT_S3C24XX_MAP_H
15
16/* interrupt controller is the first thing we put in, to make
17 * the assembly code for the irq detection easier
18 */
19#define S3C24XX_VA_IRQ S3C_VA_IRQ
20#define S3C2410_PA_IRQ (0x4A000000)
21#define S3C24XX_SZ_IRQ SZ_1M
22
23/* memory controller registers */
24#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
25#define S3C2410_PA_MEMCTRL (0x48000000)
26#define S3C24XX_SZ_MEMCTRL SZ_1M
27
28/* UARTs */
29#define S3C24XX_VA_UART S3C_VA_UART
30#define S3C2410_PA_UART (0x50000000)
31#define S3C24XX_SZ_UART SZ_1M
32#define S3C_UART_OFFSET (0x4000)
33
34/* Timers */
35#define S3C24XX_VA_TIMER S3C_VA_TIMER
36#define S3C2410_PA_TIMER (0x51000000)
37#define S3C24XX_SZ_TIMER SZ_1M
38
39/* Clock and Power management */
40#define S3C24XX_VA_CLKPWR S3C_VA_SYS
41#define S3C24XX_SZ_CLKPWR SZ_1M
42
43/* USB Device port */
44#define S3C2410_PA_USBDEV (0x52000000)
45#define S3C24XX_SZ_USBDEV SZ_1M
46
47/* Watchdog */
48#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
49#define S3C2410_PA_WATCHDOG (0x53000000)
50#define S3C24XX_SZ_WATCHDOG SZ_1M
51
52/* Standard size definitions for peripheral blocks. */
53
54#define S3C24XX_SZ_IIS SZ_1M
55#define S3C24XX_SZ_ADC SZ_1M
56#define S3C24XX_SZ_SPI SZ_1M
57#define S3C24XX_SZ_SDI SZ_1M
58#define S3C24XX_SZ_NAND SZ_1M
59#define S3C24XX_SZ_USBHOST SZ_1M
60
61/* GPIO ports */
62
63/* the calculation for the VA of this must ensure that
64 * it is the same distance apart from the UART in the
65 * phsyical address space, as the initial mapping for the IO
66 * is done as a 1:1 maping. This puts it (currently) at
67 * 0xFA800000, which is not in the way of any current mapping
68 * by the base system.
69*/
70
71#define S3C2410_PA_GPIO (0x56000000)
72#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
73#define S3C24XX_SZ_GPIO SZ_1M
74
75
76/* ISA style IO, for each machine to sort out mappings for, if it
77 * implements it. We reserve two 16M regions for ISA.
78 */
79
80#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
81#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
82
83/* deal with the registers that move under the 2412/2413 */
84
85#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
86#ifndef __ASSEMBLY__
87extern void __iomem *s3c24xx_va_gpio2;
88#endif
89#ifdef CONFIG_CPU_S3C2412_ONLY
90#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
91#else
92#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
93#endif
94#else
95#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
96#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
97#endif
98
99#endif /* __ASM_PLAT_S3C24XX_MAP_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h
new file mode 100644
index 000000000000..2d0852ac3b27
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/mci.h
@@ -0,0 +1,15 @@
1#ifndef _ARCH_MCI_H
2#define _ARCH_MCI_H
3
4struct s3c24xx_mci_pdata {
5 unsigned int wprotect_invert : 1;
6 unsigned int detect_invert : 1; /* set => detect active high. */
7
8 unsigned int gpio_detect;
9 unsigned int gpio_wprotect;
10 unsigned long ocr_avail;
11 void (*set_power)(unsigned char power_mode,
12 unsigned short vdd);
13};
14
15#endif /* _ARCH_NCI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h
new file mode 100644
index 000000000000..7ea8bffa7a9c
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/pll.h
@@ -0,0 +1,37 @@
1/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C24xx - common pll registers and code
8 */
9
10#define S3C24XX_PLLCON_MDIVSHIFT 12
11#define S3C24XX_PLLCON_PDIVSHIFT 4
12#define S3C24XX_PLLCON_SDIVSHIFT 0
13#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
14#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1)
15#define S3C24XX_PLLCON_SDIVMASK 3
16
17#include <asm/div64.h>
18
19static inline unsigned int
20s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
21{
22 unsigned int mdiv, pdiv, sdiv;
23 uint64_t fvco;
24
25 mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
26 pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
27 sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
28
29 mdiv &= S3C24XX_PLLCON_MDIVMASK;
30 pdiv &= S3C24XX_PLLCON_PDIVMASK;
31 sdiv &= S3C24XX_PLLCON_SDIVMASK;
32
33 fvco = (uint64_t)baseclk * (mdiv + 8);
34 do_div(fvco, (pdiv + 2) << sdiv);
35
36 return (unsigned int)fvco;
37}
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
new file mode 100644
index 000000000000..2b35479ee35c
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
@@ -0,0 +1,82 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
2 *
3 * Copyright (c) 2004 Fetron GmbH
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 SPI register definition
10*/
11
12#ifndef __ASM_ARCH_REGS_SPI_H
13#define __ASM_ARCH_REGS_SPI_H
14
15#define S3C2410_SPI1 (0x20)
16#define S3C2412_SPI1 (0x100)
17
18#define S3C2410_SPCON (0x00)
19
20#define S3C2412_SPCON_RXFIFO_RB2 (0<<14)
21#define S3C2412_SPCON_RXFIFO_RB4 (1<<14)
22#define S3C2412_SPCON_RXFIFO_RB12 (2<<14)
23#define S3C2412_SPCON_RXFIFO_RB14 (3<<14)
24#define S3C2412_SPCON_TXFIFO_RB2 (0<<12)
25#define S3C2412_SPCON_TXFIFO_RB4 (1<<12)
26#define S3C2412_SPCON_TXFIFO_RB12 (2<<12)
27#define S3C2412_SPCON_TXFIFO_RB14 (3<<12)
28#define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */
29#define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */
30#define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */
31#define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */
32
33#define S3C2412_SPCON_DIRC_RX (1<<7)
34
35#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
36#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
37#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
38#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
39#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
40 0: slave, 1: master */
41#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
42#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
43
44#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */
45#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */
46
47#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */
48
49
50#define S3C2410_SPSTA (0x04)
51
52#define S3C2412_SPSTA_RXFIFO_AE (1<<11)
53#define S3C2412_SPSTA_TXFIFO_AE (1<<10)
54#define S3C2412_SPSTA_RXFIFO_ERROR (1<<9)
55#define S3C2412_SPSTA_TXFIFO_ERROR (1<<8)
56#define S3C2412_SPSTA_RXFIFO_FIFO (1<<7)
57#define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6)
58#define S3C2412_SPSTA_TXFIFO_NFULL (1<<5)
59#define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4)
60
61#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
62#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
63#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
64#define S3C2412_SPSTA_READY_ORG (1<<3)
65
66#define S3C2410_SPPIN (0x08)
67
68#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
69#define S3C2410_SPPIN_RESERVED (1<<1)
70#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
71#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
72
73#define S3C2410_SPPRE (0x0C)
74#define S3C2410_SPTDAT (0x10)
75#define S3C2410_SPRDAT (0x14)
76
77#define S3C2412_TXFIFO (0x18)
78#define S3C2412_RXFIFO (0x18)
79#define S3C2412_SPFIC (0x24)
80
81
82#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
new file mode 100644
index 000000000000..f0dd4a41b37b
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
@@ -0,0 +1,153 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
2 *
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 *
5 * This include file is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9*/
10
11#ifndef __ASM_ARCH_REGS_UDC_H
12#define __ASM_ARCH_REGS_UDC_H
13
14#define S3C2410_USBDREG(x) (x)
15
16#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
17#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
18#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
19
20#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
21#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
22
23#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
24
25#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
26#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
27
28#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
29#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
30#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
31#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
32#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
33
34#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
35#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
36#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
37#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
38#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
39#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
40
41#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
42#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
43#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
44#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
45#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
46#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
47
48#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
49#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
50#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
51#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
52#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
53#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
54
55#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
56#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
57#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
58#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
59#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
60#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
61
62#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
63
64/* indexed registers */
65
66#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
67
68#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
69
70#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
71#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
72
73#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
74#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
75#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
76#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
77
78#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7)
79
80#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
81#define S3C2410_UDC_PWR_RESET (1<<3) // R
82#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
83#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
84#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
85
86#define S3C2410_UDC_PWR_DEFAULT 0x00
87
88#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
89#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
90#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
91#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
92#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
93
94#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
95#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
96#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
97
98#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
99#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
100#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
101#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
102#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
103
104#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
105#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
106
107
108#define S3C2410_UDC_INDEX_EP0 (0x00)
109#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
110#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
111#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
112#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
113
114#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
115#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
116#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
117#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
118#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
119#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
120
121#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
122#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
123#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
124#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
125
126#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
127#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
128#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
129#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
130#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
131#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
132#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
133
134#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
135#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
136#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
137
138#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
139#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
140#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
141#define S3C2410_UDC_EP0_CSR_DE (1<<3)
142#define S3C2410_UDC_EP0_CSR_SE (1<<4)
143#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
144#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
145#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
146
147#define S3C2410_UDC_MAXP_8 (1<<0)
148#define S3C2410_UDC_MAXP_16 (1<<1)
149#define S3C2410_UDC_MAXP_32 (1<<2)
150#define S3C2410_UDC_MAXP_64 (1<<3)
151
152
153#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
index 3a5a16821af8..b3feaea5c70b 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
@@ -17,7 +17,7 @@
17 17
18extern int s3c2400_init(void); 18extern int s3c2400_init(void);
19 19
20extern void s3c2400_map_io(struct map_desc *mach_desc, int size); 20extern void s3c2400_map_io(void);
21 21
22extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no); 22extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
23 23
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
index 3cd1ec677b3f..a9ac9e29759e 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
@@ -15,7 +15,7 @@
15 15
16extern int s3c2410_init(void); 16extern int s3c2410_init(void);
17 17
18extern void s3c2410_map_io(struct map_desc *mach_desc, int size); 18extern void s3c2410_map_io(void);
19 19
20extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); 20extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
21 21
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
index 3ec97685e781..bb15d3b68be5 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
@@ -14,7 +14,7 @@
14 14
15extern int s3c2412_init(void); 15extern int s3c2412_init(void);
16 16
17extern void s3c2412_map_io(struct map_desc *mach_desc, int size); 17extern void s3c2412_map_io(void);
18 18
19extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); 19extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
20 20
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
index 11d83b5c84e6..815b107ed890 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
@@ -16,7 +16,7 @@ struct s3c2410_uartcfg;
16 16
17extern int s3c2443_init(void); 17extern int s3c2443_init(void);
18 18
19extern void s3c2443_map_io(struct map_desc *mach_desc, int size); 19extern void s3c2443_map_io(void);
20 20
21extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); 21extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
22 22
diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-s3c24xx/include/plat/udc.h
new file mode 100644
index 000000000000..546bb4008f49
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/udc.h
@@ -0,0 +1,36 @@
1/* arch/arm/mach-s3c2410/include/mach/udc.h
2 *
3 * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *
11 * Changelog:
12 * 14-Mar-2005 RTP Created file
13 * 02-Aug-2005 RTP File rename
14 * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
15 * 18-Jan-2007 HMW Add per-platform vbus_draw function
16*/
17
18#ifndef __ASM_ARM_ARCH_UDC_H
19#define __ASM_ARM_ARCH_UDC_H
20
21enum s3c2410_udc_cmd_e {
22 S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
23 S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
24 S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
25};
26
27struct s3c2410_udc_mach_info {
28 void (*udc_command)(enum s3c2410_udc_cmd_e);
29 void (*vbus_draw)(unsigned int ma);
30 unsigned int vbus_pin;
31 unsigned char vbus_pin_inverted;
32};
33
34extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
35
36#endif /* __ASM_ARM_ARCH_UDC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 14:26:23 -0500