diff options
Diffstat (limited to 'arch/arm/plat-s3c24xx/cpu.c')
-rw-r--r-- | arch/arm/plat-s3c24xx/cpu.c | 142 |
1 files changed, 3 insertions, 139 deletions
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 22a329513c0f..542062f8cbc1 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c | |||
@@ -30,7 +30,6 @@ | |||
30 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
31 | #include <linux/delay.h> | 31 | #include <linux/delay.h> |
32 | #include <linux/io.h> | 32 | #include <linux/io.h> |
33 | #include <linux/delay.h> | ||
34 | 33 | ||
35 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
36 | #include <asm/irq.h> | 35 | #include <asm/irq.h> |
@@ -55,16 +54,6 @@ | |||
55 | #include <plat/s3c2442.h> | 54 | #include <plat/s3c2442.h> |
56 | #include <plat/s3c2443.h> | 55 | #include <plat/s3c2443.h> |
57 | 56 | ||
58 | struct cpu_table { | ||
59 | unsigned long idcode; | ||
60 | unsigned long idmask; | ||
61 | void (*map_io)(struct map_desc *mach_desc, int size); | ||
62 | void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); | ||
63 | void (*init_clocks)(int xtal); | ||
64 | int (*init)(void); | ||
65 | const char *name; | ||
66 | }; | ||
67 | |||
68 | /* table of supported CPUs */ | 57 | /* table of supported CPUs */ |
69 | 58 | ||
70 | static const char name_s3c2400[] = "S3C2400"; | 59 | static const char name_s3c2400[] = "S3C2400"; |
@@ -169,23 +158,7 @@ static struct map_desc s3c_iodesc[] __initdata = { | |||
169 | IODESC_ENT(UART) | 158 | IODESC_ENT(UART) |
170 | }; | 159 | }; |
171 | 160 | ||
172 | static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode) | 161 | /* read cpu identificaiton code */ |
173 | { | ||
174 | struct cpu_table *tab; | ||
175 | int count; | ||
176 | |||
177 | tab = cpu_ids; | ||
178 | for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) { | ||
179 | if ((idcode & tab->idmask) == tab->idcode) | ||
180 | return tab; | ||
181 | } | ||
182 | |||
183 | return NULL; | ||
184 | } | ||
185 | |||
186 | /* cpu information */ | ||
187 | |||
188 | static struct cpu_table *cpu; | ||
189 | 162 | ||
190 | static unsigned long s3c24xx_read_idcode_v5(void) | 163 | static unsigned long s3c24xx_read_idcode_v5(void) |
191 | { | 164 | { |
@@ -231,6 +204,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | |||
231 | unsigned long idcode = 0x0; | 204 | unsigned long idcode = 0x0; |
232 | 205 | ||
233 | /* initialise the io descriptors we need for initialisation */ | 206 | /* initialise the io descriptors we need for initialisation */ |
207 | iotable_init(mach_desc, size); | ||
234 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); | 208 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); |
235 | 209 | ||
236 | if (cpu_architecture() >= CPU_ARCH_ARMv5) { | 210 | if (cpu_architecture() >= CPU_ARCH_ARMv5) { |
@@ -239,117 +213,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | |||
239 | idcode = s3c24xx_read_idcode_v4(); | 213 | idcode = s3c24xx_read_idcode_v4(); |
240 | } | 214 | } |
241 | 215 | ||
242 | cpu = s3c_lookup_cpu(idcode); | ||
243 | |||
244 | if (cpu == NULL) { | ||
245 | printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); | ||
246 | panic("Unknown S3C24XX CPU"); | ||
247 | } | ||
248 | |||
249 | printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); | ||
250 | |||
251 | if (cpu->map_io == NULL || cpu->init == NULL) { | ||
252 | printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); | ||
253 | panic("Unsupported S3C24XX CPU"); | ||
254 | } | ||
255 | |||
256 | arm_pm_restart = s3c24xx_pm_restart; | 216 | arm_pm_restart = s3c24xx_pm_restart; |
257 | 217 | ||
258 | (cpu->map_io)(mach_desc, size); | 218 | s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); |
259 | } | ||
260 | |||
261 | /* s3c24xx_init_clocks | ||
262 | * | ||
263 | * Initialise the clock subsystem and associated information from the | ||
264 | * given master crystal value. | ||
265 | * | ||
266 | * xtal = 0 -> use default PLL crystal value (normally 12MHz) | ||
267 | * != 0 -> PLL crystal value in Hz | ||
268 | */ | ||
269 | |||
270 | void __init s3c24xx_init_clocks(int xtal) | ||
271 | { | ||
272 | if (xtal == 0) | ||
273 | xtal = 12*1000*1000; | ||
274 | |||
275 | if (cpu == NULL) | ||
276 | panic("s3c24xx_init_clocks: no cpu setup?\n"); | ||
277 | |||
278 | if (cpu->init_clocks == NULL) | ||
279 | panic("s3c24xx_init_clocks: cpu has no clock init\n"); | ||
280 | else | ||
281 | (cpu->init_clocks)(xtal); | ||
282 | } | 219 | } |
283 | |||
284 | /* uart management */ | ||
285 | |||
286 | static int nr_uarts __initdata = 0; | ||
287 | |||
288 | static struct s3c2410_uartcfg uart_cfgs[3]; | ||
289 | |||
290 | /* s3c24xx_init_uartdevs | ||
291 | * | ||
292 | * copy the specified platform data and configuration into our central | ||
293 | * set of devices, before the data is thrown away after the init process. | ||
294 | * | ||
295 | * This also fills in the array passed to the serial driver for the | ||
296 | * early initialisation of the console. | ||
297 | */ | ||
298 | |||
299 | void __init s3c24xx_init_uartdevs(char *name, | ||
300 | struct s3c24xx_uart_resources *res, | ||
301 | struct s3c2410_uartcfg *cfg, int no) | ||
302 | { | ||
303 | struct platform_device *platdev; | ||
304 | struct s3c2410_uartcfg *cfgptr = uart_cfgs; | ||
305 | struct s3c24xx_uart_resources *resp; | ||
306 | int uart; | ||
307 | |||
308 | memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); | ||
309 | |||
310 | for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { | ||
311 | platdev = s3c24xx_uart_src[cfgptr->hwport]; | ||
312 | |||
313 | resp = res + cfgptr->hwport; | ||
314 | |||
315 | s3c24xx_uart_devs[uart] = platdev; | ||
316 | |||
317 | platdev->name = name; | ||
318 | platdev->resource = resp->resources; | ||
319 | platdev->num_resources = resp->nr_resources; | ||
320 | |||
321 | platdev->dev.platform_data = cfgptr; | ||
322 | } | ||
323 | |||
324 | nr_uarts = no; | ||
325 | } | ||
326 | |||
327 | void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) | ||
328 | { | ||
329 | if (cpu == NULL) | ||
330 | return; | ||
331 | |||
332 | if (cpu->init_uarts == NULL) { | ||
333 | printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); | ||
334 | } else | ||
335 | (cpu->init_uarts)(cfg, no); | ||
336 | } | ||
337 | |||
338 | static int __init s3c_arch_init(void) | ||
339 | { | ||
340 | int ret; | ||
341 | |||
342 | // do the correct init for cpu | ||
343 | |||
344 | if (cpu == NULL) | ||
345 | panic("s3c_arch_init: NULL cpu\n"); | ||
346 | |||
347 | ret = (cpu->init)(); | ||
348 | if (ret != 0) | ||
349 | return ret; | ||
350 | |||
351 | ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); | ||
352 | return ret; | ||
353 | } | ||
354 | |||
355 | arch_initcall(s3c_arch_init); | ||