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-rw-r--r--arch/arm/plat-s3c24xx/cpu.c141
1 files changed, 3 insertions, 138 deletions
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 22a329513c0f..7a0f494c93b6 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -55,16 +55,6 @@
55#include <plat/s3c2442.h> 55#include <plat/s3c2442.h>
56#include <plat/s3c2443.h> 56#include <plat/s3c2443.h>
57 57
58struct cpu_table {
59 unsigned long idcode;
60 unsigned long idmask;
61 void (*map_io)(struct map_desc *mach_desc, int size);
62 void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
63 void (*init_clocks)(int xtal);
64 int (*init)(void);
65 const char *name;
66};
67
68/* table of supported CPUs */ 58/* table of supported CPUs */
69 59
70static const char name_s3c2400[] = "S3C2400"; 60static const char name_s3c2400[] = "S3C2400";
@@ -169,23 +159,7 @@ static struct map_desc s3c_iodesc[] __initdata = {
169 IODESC_ENT(UART) 159 IODESC_ENT(UART)
170}; 160};
171 161
172static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode) 162/* read cpu identificaiton code */
173{
174 struct cpu_table *tab;
175 int count;
176
177 tab = cpu_ids;
178 for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
179 if ((idcode & tab->idmask) == tab->idcode)
180 return tab;
181 }
182
183 return NULL;
184}
185
186/* cpu information */
187
188static struct cpu_table *cpu;
189 163
190static unsigned long s3c24xx_read_idcode_v5(void) 164static unsigned long s3c24xx_read_idcode_v5(void)
191{ 165{
@@ -231,6 +205,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
231 unsigned long idcode = 0x0; 205 unsigned long idcode = 0x0;
232 206
233 /* initialise the io descriptors we need for initialisation */ 207 /* initialise the io descriptors we need for initialisation */
208 iotable_init(mach_desc, size);
234 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); 209 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
235 210
236 if (cpu_architecture() >= CPU_ARCH_ARMv5) { 211 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
@@ -239,117 +214,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
239 idcode = s3c24xx_read_idcode_v4(); 214 idcode = s3c24xx_read_idcode_v4();
240 } 215 }
241 216
242 cpu = s3c_lookup_cpu(idcode);
243
244 if (cpu == NULL) {
245 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
246 panic("Unknown S3C24XX CPU");
247 }
248
249 printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
250
251 if (cpu->map_io == NULL || cpu->init == NULL) {
252 printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
253 panic("Unsupported S3C24XX CPU");
254 }
255
256 arm_pm_restart = s3c24xx_pm_restart; 217 arm_pm_restart = s3c24xx_pm_restart;
257 218
258 (cpu->map_io)(mach_desc, size); 219 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
259}
260
261/* s3c24xx_init_clocks
262 *
263 * Initialise the clock subsystem and associated information from the
264 * given master crystal value.
265 *
266 * xtal = 0 -> use default PLL crystal value (normally 12MHz)
267 * != 0 -> PLL crystal value in Hz
268*/
269
270void __init s3c24xx_init_clocks(int xtal)
271{
272 if (xtal == 0)
273 xtal = 12*1000*1000;
274
275 if (cpu == NULL)
276 panic("s3c24xx_init_clocks: no cpu setup?\n");
277
278 if (cpu->init_clocks == NULL)
279 panic("s3c24xx_init_clocks: cpu has no clock init\n");
280 else
281 (cpu->init_clocks)(xtal);
282}
283
284/* uart management */
285
286static int nr_uarts __initdata = 0;
287
288static struct s3c2410_uartcfg uart_cfgs[3];
289
290/* s3c24xx_init_uartdevs
291 *
292 * copy the specified platform data and configuration into our central
293 * set of devices, before the data is thrown away after the init process.
294 *
295 * This also fills in the array passed to the serial driver for the
296 * early initialisation of the console.
297*/
298
299void __init s3c24xx_init_uartdevs(char *name,
300 struct s3c24xx_uart_resources *res,
301 struct s3c2410_uartcfg *cfg, int no)
302{
303 struct platform_device *platdev;
304 struct s3c2410_uartcfg *cfgptr = uart_cfgs;
305 struct s3c24xx_uart_resources *resp;
306 int uart;
307
308 memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
309
310 for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
311 platdev = s3c24xx_uart_src[cfgptr->hwport];
312
313 resp = res + cfgptr->hwport;
314
315 s3c24xx_uart_devs[uart] = platdev;
316
317 platdev->name = name;
318 platdev->resource = resp->resources;
319 platdev->num_resources = resp->nr_resources;
320
321 platdev->dev.platform_data = cfgptr;
322 }
323
324 nr_uarts = no;
325} 220}
326
327void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
328{
329 if (cpu == NULL)
330 return;
331
332 if (cpu->init_uarts == NULL) {
333 printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
334 } else
335 (cpu->init_uarts)(cfg, no);
336}
337
338static int __init s3c_arch_init(void)
339{
340 int ret;
341
342 // do the correct init for cpu
343
344 if (cpu == NULL)
345 panic("s3c_arch_init: NULL cpu\n");
346
347 ret = (cpu->init)();
348 if (ret != 0)
349 return ret;
350
351 ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
352 return ret;
353}
354
355arch_initcall(s3c_arch_init);