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-rw-r--r--arch/arm/plat-s3c24xx/clock.c493
1 files changed, 8 insertions, 485 deletions
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index a005ddbd9ef3..8474d05274bd 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -27,18 +27,8 @@
27*/ 27*/
28 28
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/kernel.h> 30#include <linux/kernel.h>
32#include <linux/list.h>
33#include <linux/errno.h>
34#include <linux/err.h>
35#include <linux/platform_device.h>
36#include <linux/sysdev.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/clk.h> 31#include <linux/clk.h>
40#include <linux/mutex.h>
41#include <linux/delay.h>
42#include <linux/io.h> 32#include <linux/io.h>
43 33
44#include <mach/hardware.h> 34#include <mach/hardware.h>
@@ -47,490 +37,23 @@
47#include <mach/regs-clock.h> 37#include <mach/regs-clock.h>
48#include <mach/regs-gpio.h> 38#include <mach/regs-gpio.h>
49 39
40#include <plat/cpu-freq.h>
41
50#include <plat/clock.h> 42#include <plat/clock.h>
51#include <plat/cpu.h> 43#include <plat/cpu.h>
52 44#include <plat/pll.h>
53/* clock information */
54
55static LIST_HEAD(clocks);
56
57DEFINE_MUTEX(clocks_mutex);
58
59/* enable and disable calls for use with the clk struct */
60
61static int clk_null_enable(struct clk *clk, int enable)
62{
63 return 0;
64}
65
66/* Clock API calls */
67
68struct clk *clk_get(struct device *dev, const char *id)
69{
70 struct clk *p;
71 struct clk *clk = ERR_PTR(-ENOENT);
72 int idno;
73
74 if (dev == NULL || dev->bus != &platform_bus_type)
75 idno = -1;
76 else
77 idno = to_platform_device(dev)->id;
78
79 mutex_lock(&clocks_mutex);
80
81 list_for_each_entry(p, &clocks, list) {
82 if (p->id == idno &&
83 strcmp(id, p->name) == 0 &&
84 try_module_get(p->owner)) {
85 clk = p;
86 break;
87 }
88 }
89
90 /* check for the case where a device was supplied, but the
91 * clock that was being searched for is not device specific */
92
93 if (IS_ERR(clk)) {
94 list_for_each_entry(p, &clocks, list) {
95 if (p->id == -1 && strcmp(id, p->name) == 0 &&
96 try_module_get(p->owner)) {
97 clk = p;
98 break;
99 }
100 }
101 }
102
103 mutex_unlock(&clocks_mutex);
104 return clk;
105}
106
107void clk_put(struct clk *clk)
108{
109 module_put(clk->owner);
110}
111
112int clk_enable(struct clk *clk)
113{
114 if (IS_ERR(clk) || clk == NULL)
115 return -EINVAL;
116
117 clk_enable(clk->parent);
118
119 mutex_lock(&clocks_mutex);
120
121 if ((clk->usage++) == 0)
122 (clk->enable)(clk, 1);
123
124 mutex_unlock(&clocks_mutex);
125 return 0;
126}
127
128void clk_disable(struct clk *clk)
129{
130 if (IS_ERR(clk) || clk == NULL)
131 return;
132
133 mutex_lock(&clocks_mutex);
134
135 if ((--clk->usage) == 0)
136 (clk->enable)(clk, 0);
137
138 mutex_unlock(&clocks_mutex);
139 clk_disable(clk->parent);
140}
141
142
143unsigned long clk_get_rate(struct clk *clk)
144{
145 if (IS_ERR(clk))
146 return 0;
147
148 if (clk->rate != 0)
149 return clk->rate;
150
151 if (clk->get_rate != NULL)
152 return (clk->get_rate)(clk);
153
154 if (clk->parent != NULL)
155 return clk_get_rate(clk->parent);
156
157 return clk->rate;
158}
159
160long clk_round_rate(struct clk *clk, unsigned long rate)
161{
162 if (!IS_ERR(clk) && clk->round_rate)
163 return (clk->round_rate)(clk, rate);
164
165 return rate;
166}
167
168int clk_set_rate(struct clk *clk, unsigned long rate)
169{
170 int ret;
171
172 if (IS_ERR(clk))
173 return -EINVAL;
174
175 /* We do not default just do a clk->rate = rate as
176 * the clock may have been made this way by choice.
177 */
178
179 WARN_ON(clk->set_rate == NULL);
180
181 if (clk->set_rate == NULL)
182 return -EINVAL;
183
184 mutex_lock(&clocks_mutex);
185 ret = (clk->set_rate)(clk, rate);
186 mutex_unlock(&clocks_mutex);
187
188 return ret;
189}
190
191struct clk *clk_get_parent(struct clk *clk)
192{
193 return clk->parent;
194}
195
196int clk_set_parent(struct clk *clk, struct clk *parent)
197{
198 int ret = 0;
199
200 if (IS_ERR(clk))
201 return -EINVAL;
202
203 mutex_lock(&clocks_mutex);
204
205 if (clk->set_parent)
206 ret = (clk->set_parent)(clk, parent);
207
208 mutex_unlock(&clocks_mutex);
209
210 return ret;
211}
212
213EXPORT_SYMBOL(clk_get);
214EXPORT_SYMBOL(clk_put);
215EXPORT_SYMBOL(clk_enable);
216EXPORT_SYMBOL(clk_disable);
217EXPORT_SYMBOL(clk_get_rate);
218EXPORT_SYMBOL(clk_round_rate);
219EXPORT_SYMBOL(clk_set_rate);
220EXPORT_SYMBOL(clk_get_parent);
221EXPORT_SYMBOL(clk_set_parent);
222
223/* base clocks */
224
225static int clk_default_setrate(struct clk *clk, unsigned long rate)
226{
227 clk->rate = rate;
228 return 0;
229}
230
231struct clk clk_xtal = {
232 .name = "xtal",
233 .id = -1,
234 .rate = 0,
235 .parent = NULL,
236 .ctrlbit = 0,
237};
238
239struct clk clk_mpll = {
240 .name = "mpll",
241 .id = -1,
242 .set_rate = clk_default_setrate,
243};
244
245struct clk clk_upll = {
246 .name = "upll",
247 .id = -1,
248 .parent = NULL,
249 .ctrlbit = 0,
250};
251
252struct clk clk_f = {
253 .name = "fclk",
254 .id = -1,
255 .rate = 0,
256 .parent = &clk_mpll,
257 .ctrlbit = 0,
258 .set_rate = clk_default_setrate,
259};
260
261struct clk clk_h = {
262 .name = "hclk",
263 .id = -1,
264 .rate = 0,
265 .parent = NULL,
266 .ctrlbit = 0,
267 .set_rate = clk_default_setrate,
268};
269
270struct clk clk_p = {
271 .name = "pclk",
272 .id = -1,
273 .rate = 0,
274 .parent = NULL,
275 .ctrlbit = 0,
276 .set_rate = clk_default_setrate,
277};
278
279struct clk clk_usb_bus = {
280 .name = "usb-bus",
281 .id = -1,
282 .rate = 0,
283 .parent = &clk_upll,
284};
285
286/* clocks that could be registered by external code */
287
288static int s3c24xx_dclk_enable(struct clk *clk, int enable)
289{
290 unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
291
292 if (enable)
293 dclkcon |= clk->ctrlbit;
294 else
295 dclkcon &= ~clk->ctrlbit;
296
297 __raw_writel(dclkcon, S3C24XX_DCLKCON);
298
299 return 0;
300}
301
302static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
303{
304 unsigned long dclkcon;
305 unsigned int uclk;
306
307 if (parent == &clk_upll)
308 uclk = 1;
309 else if (parent == &clk_p)
310 uclk = 0;
311 else
312 return -EINVAL;
313
314 clk->parent = parent;
315
316 dclkcon = __raw_readl(S3C24XX_DCLKCON);
317
318 if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
319 if (uclk)
320 dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
321 else
322 dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
323 } else {
324 if (uclk)
325 dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
326 else
327 dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
328 }
329
330 __raw_writel(dclkcon, S3C24XX_DCLKCON);
331
332 return 0;
333}
334
335static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
336{
337 unsigned long div;
338
339 if ((rate == 0) || !clk->parent)
340 return 0;
341
342 div = clk_get_rate(clk->parent) / rate;
343 if (div < 2)
344 div = 2;
345 else if (div > 16)
346 div = 16;
347
348 return div;
349}
350
351static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
352 unsigned long rate)
353{
354 unsigned long div = s3c24xx_calc_div(clk, rate);
355
356 if (div == 0)
357 return 0;
358
359 return clk_get_rate(clk->parent) / div;
360}
361
362static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
363{
364 unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
365
366 if (div == 0)
367 return -EINVAL;
368
369 if (clk == &s3c24xx_dclk0) {
370 mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
371 S3C2410_DCLKCON_DCLK0_CMP_MASK;
372 data = S3C2410_DCLKCON_DCLK0_DIV(div) |
373 S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
374 } else if (clk == &s3c24xx_dclk1) {
375 mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
376 S3C2410_DCLKCON_DCLK1_CMP_MASK;
377 data = S3C2410_DCLKCON_DCLK1_DIV(div) |
378 S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
379 } else
380 return -EINVAL;
381
382 clk->rate = clk_get_rate(clk->parent) / div;
383 __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
384 S3C24XX_DCLKCON);
385 return clk->rate;
386}
387
388static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
389{
390 unsigned long mask;
391 unsigned long source;
392
393 /* calculate the MISCCR setting for the clock */
394
395 if (parent == &clk_xtal)
396 source = S3C2410_MISCCR_CLK0_MPLL;
397 else if (parent == &clk_upll)
398 source = S3C2410_MISCCR_CLK0_UPLL;
399 else if (parent == &clk_f)
400 source = S3C2410_MISCCR_CLK0_FCLK;
401 else if (parent == &clk_h)
402 source = S3C2410_MISCCR_CLK0_HCLK;
403 else if (parent == &clk_p)
404 source = S3C2410_MISCCR_CLK0_PCLK;
405 else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
406 source = S3C2410_MISCCR_CLK0_DCLK0;
407 else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
408 source = S3C2410_MISCCR_CLK0_DCLK0;
409 else
410 return -EINVAL;
411
412 clk->parent = parent;
413
414 if (clk == &s3c24xx_clkout0)
415 mask = S3C2410_MISCCR_CLK0_MASK;
416 else {
417 source <<= 4;
418 mask = S3C2410_MISCCR_CLK1_MASK;
419 }
420
421 s3c2410_modify_misccr(mask, source);
422 return 0;
423}
424
425/* external clock definitions */
426
427struct clk s3c24xx_dclk0 = {
428 .name = "dclk0",
429 .id = -1,
430 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
431 .enable = s3c24xx_dclk_enable,
432 .set_parent = s3c24xx_dclk_setparent,
433 .set_rate = s3c24xx_set_dclk_rate,
434 .round_rate = s3c24xx_round_dclk_rate,
435};
436
437struct clk s3c24xx_dclk1 = {
438 .name = "dclk1",
439 .id = -1,
440 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
441 .enable = s3c24xx_dclk_enable,
442 .set_parent = s3c24xx_dclk_setparent,
443 .set_rate = s3c24xx_set_dclk_rate,
444 .round_rate = s3c24xx_round_dclk_rate,
445};
446
447struct clk s3c24xx_clkout0 = {
448 .name = "clkout0",
449 .id = -1,
450 .set_parent = s3c24xx_clkout_setparent,
451};
452
453struct clk s3c24xx_clkout1 = {
454 .name = "clkout1",
455 .id = -1,
456 .set_parent = s3c24xx_clkout_setparent,
457};
458
459struct clk s3c24xx_uclk = {
460 .name = "uclk",
461 .id = -1,
462};
463
464/* initialise the clock system */
465
466int s3c24xx_register_clock(struct clk *clk)
467{
468 clk->owner = THIS_MODULE;
469
470 if (clk->enable == NULL)
471 clk->enable = clk_null_enable;
472
473 /* add to the list of available clocks */
474
475 mutex_lock(&clocks_mutex);
476 list_add(&clk->list, &clocks);
477 mutex_unlock(&clocks_mutex);
478
479 return 0;
480}
481
482int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
483{
484 int fails = 0;
485
486 for (; nr_clks > 0; nr_clks--, clks++) {
487 if (s3c24xx_register_clock(*clks) < 0)
488 fails++;
489 }
490
491 return fails;
492}
493 45
494/* initalise all the clocks */ 46/* initalise all the clocks */
495 47
496int __init s3c24xx_setup_clocks(unsigned long xtal, 48void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
497 unsigned long fclk, 49 unsigned long hclk,
498 unsigned long hclk, 50 unsigned long pclk)
499 unsigned long pclk)
500{ 51{
501 printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); 52 clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
502 53 clk_xtal.rate);
503 /* initialise the main system clocks */
504
505 clk_xtal.rate = xtal;
506 clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
507 54
508 clk_mpll.rate = fclk; 55 clk_mpll.rate = fclk;
509 clk_h.rate = hclk; 56 clk_h.rate = hclk;
510 clk_p.rate = pclk; 57 clk_p.rate = pclk;
511 clk_f.rate = fclk; 58 clk_f.rate = fclk;
512
513 /* assume uart clocks are correctly setup */
514
515 /* register our clocks */
516
517 if (s3c24xx_register_clock(&clk_xtal) < 0)
518 printk(KERN_ERR "failed to register master xtal\n");
519
520 if (s3c24xx_register_clock(&clk_mpll) < 0)
521 printk(KERN_ERR "failed to register mpll clock\n");
522
523 if (s3c24xx_register_clock(&clk_upll) < 0)
524 printk(KERN_ERR "failed to register upll clock\n");
525
526 if (s3c24xx_register_clock(&clk_f) < 0)
527 printk(KERN_ERR "failed to register cpu fclk\n");
528
529 if (s3c24xx_register_clock(&clk_h) < 0)
530 printk(KERN_ERR "failed to register cpu hclk\n");
531
532 if (s3c24xx_register_clock(&clk_p) < 0)
533 printk(KERN_ERR "failed to register cpu pclk\n");
534
535 return 0;
536} 59}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 22:22:11 -0500