4 files changed, 520 insertions, 0 deletions

diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
new file mode 100644
index 000000000000..198f3dde2be3
--- /dev/null
+++ b/arch/arm/plat-orion/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y   := irq.o pcie.o time.o
+obj-m   :=
+obj-n   :=
+obj-    :=
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
new file mode 100644
index 000000000000..c5b669d234bc
--- /dev/null
+++ b/arch/arm/plat-orion/irq.c
@@ -0,0 +1,64 @@
+/*
+ * arch/arm/plat-orion/irq.c
+ *
+ * Marvell Orion SoC IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/plat-orion/irq.h>
+
+static void orion_irq_mask(u32 irq)
+{
+        void __iomem *maskaddr = get_irq_chip_data(irq);
+        u32 mask;
+
+        mask = readl(maskaddr);
+        mask &= ~(1 << (irq & 31));
+        writel(mask, maskaddr);
+}
+
+static void orion_irq_unmask(u32 irq)
+{
+        void __iomem *maskaddr = get_irq_chip_data(irq);
+        u32 mask;
+
+        mask = readl(maskaddr);
+        mask |= 1 << (irq & 31);
+        writel(mask, maskaddr);
+}
+
+static struct irq_chip orion_irq_chip = {
+        .name           = "orion_irq",
+        .ack            = orion_irq_mask,
+        .mask           = orion_irq_mask,
+        .unmask         = orion_irq_unmask,
+};
+
+void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
+{
+        unsigned int i;
+
+        /*
+         * Mask all interrupts initially.
+         */
+        writel(0, maskaddr);
+
+        /*
+         * Register IRQ sources.
+         */
+        for (i = 0; i < 32; i++) {
+                unsigned int irq = irq_start + i;
+
+                set_irq_chip(irq, &orion_irq_chip);
+                set_irq_chip_data(irq, maskaddr);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
new file mode 100644
index 000000000000..abfda53f1800
--- /dev/null
+++ b/arch/arm/plat-orion/pcie.c
@@ -0,0 +1,245 @@
+/*
+ * arch/arm/plat-orion/pcie.c
+ *
+ * Marvell Orion SoC PCIe handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+
+/*
+ * PCIe unit register offsets.
+ */
+#define PCIE_DEV_ID_OFF         0x0000
+#define PCIE_CMD_OFF            0x0004
+#define PCIE_DEV_REV_OFF        0x0008
+#define PCIE_BAR_LO_OFF(n)      (0x0010 + ((n) << 3))
+#define PCIE_BAR_HI_OFF(n)      (0x0014 + ((n) << 3))
+#define PCIE_HEADER_LOG_4_OFF   0x0128
+#define PCIE_BAR_CTRL_OFF(n)    (0x1804 + ((n - 1) * 4))
+#define PCIE_WIN04_CTRL_OFF(n)  (0x1820 + ((n) << 4))
+#define PCIE_WIN04_BASE_OFF(n)  (0x1824 + ((n) << 4))
+#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
+#define PCIE_WIN5_CTRL_OFF      0x1880
+#define PCIE_WIN5_BASE_OFF      0x1884
+#define PCIE_WIN5_REMAP_OFF     0x188c
+#define PCIE_CONF_ADDR_OFF      0x18f8
+#define  PCIE_CONF_ADDR_EN              0x80000000
+#define  PCIE_CONF_REG(r)               ((((r) & 0xf00) << 16) | ((r) & 0xfc))
+#define  PCIE_CONF_BUS(b)               (((b) & 0xff) << 16)
+#define  PCIE_CONF_DEV(d)               (((d) & 0x1f) << 11)
+#define  PCIE_CONF_FUNC(f)              (((f) & 0x3) << 8)
+#define PCIE_CONF_DATA_OFF      0x18fc
+#define PCIE_MASK_OFF           0x1910
+#define PCIE_CTRL_OFF           0x1a00
+#define PCIE_STAT_OFF           0x1a04
+#define  PCIE_STAT_DEV_OFFS             20
+#define  PCIE_STAT_DEV_MASK             0x1f
+#define  PCIE_STAT_BUS_OFFS             8
+#define  PCIE_STAT_BUS_MASK             0xff
+#define  PCIE_STAT_LINK_DOWN            1
+
+
+u32 __init orion_pcie_dev_id(void __iomem *base)
+{
+        return readl(base + PCIE_DEV_ID_OFF) >> 16;
+}
+
+u32 __init orion_pcie_rev(void __iomem *base)
+{
+        return readl(base + PCIE_DEV_REV_OFF) & 0xff;
+}
+
+int orion_pcie_link_up(void __iomem *base)
+{
+        return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
+}
+
+int orion_pcie_get_local_bus_nr(void __iomem *base)
+{
+        u32 stat = readl(base + PCIE_STAT_OFF);
+
+        return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK;
+}
+
+void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
+{
+        u32 stat;
+
+        stat = readl(base + PCIE_STAT_OFF);
+        stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS);
+        stat |= nr << PCIE_STAT_BUS_OFFS;
+        writel(stat, base + PCIE_STAT_OFF);
+}
+
+/*
+ * Setup PCIE BARs and Address Decode Wins:
+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * WIN[0-3] -> DRAM bank[0-3]
+ */
+static void __init orion_pcie_setup_wins(void __iomem *base,
+                                         struct mbus_dram_target_info *dram)
+{
+        u32 size;
+        int i;
+
+        /*
+         * First, disable and clear BARs and windows.
+         */
+        for (i = 1; i <= 2; i++) {
+                writel(0, base + PCIE_BAR_CTRL_OFF(i));
+                writel(0, base + PCIE_BAR_LO_OFF(i));
+                writel(0, base + PCIE_BAR_HI_OFF(i));
+        }
+
+        for (i = 0; i < 5; i++) {
+                writel(0, base + PCIE_WIN04_CTRL_OFF(i));
+                writel(0, base + PCIE_WIN04_BASE_OFF(i));
+                writel(0, base + PCIE_WIN04_REMAP_OFF(i));
+        }
+
+        writel(0, base + PCIE_WIN5_CTRL_OFF);
+        writel(0, base + PCIE_WIN5_BASE_OFF);
+        writel(0, base + PCIE_WIN5_REMAP_OFF);
+
+        /*
+         * Setup windows for DDR banks.  Count total DDR size on the fly.
+         */
+        size = 0;
+        for (i = 0; i < dram->num_cs; i++) {
+                struct mbus_dram_window *cs = dram->cs + i;
+
+                writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
+                writel(0, base + PCIE_WIN04_REMAP_OFF(i));
+                writel(((cs->size - 1) & 0xffff0000) |
+                        (cs->mbus_attr << 8) |
+                        (dram->mbus_dram_target_id << 4) | 1,
+                                base + PCIE_WIN04_CTRL_OFF(i));
+
+                size += cs->size;
+        }
+
+        /*
+         * Setup BAR[1] to all DRAM banks.
+         */
+        writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
+        writel(0, base + PCIE_BAR_HI_OFF(1));
+        writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
+}
+
+void __init orion_pcie_setup(void __iomem *base,
+                             struct mbus_dram_target_info *dram)
+{
+        u16 cmd;
+        u32 mask;
+
+        /*
+         * Point PCIe unit MBUS decode windows to DRAM space.
+         */
+        orion_pcie_setup_wins(base, dram);
+
+        /*
+         * Master + slave enable.
+         */
+        cmd = readw(base + PCIE_CMD_OFF);
+        cmd |= PCI_COMMAND_IO;
+        cmd |= PCI_COMMAND_MEMORY;
+        cmd |= PCI_COMMAND_MASTER;
+        writew(cmd, base + PCIE_CMD_OFF);
+
+        /*
+         * Enable interrupt lines A-D.
+         */
+        mask = readl(base + PCIE_MASK_OFF);
+        mask |= 0x0f000000;
+        writel(mask, base + PCIE_MASK_OFF);
+}
+
+int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
+                       u32 devfn, int where, int size, u32 *val)
+{
+        writel(PCIE_CONF_BUS(bus->number) |
+                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+                        base + PCIE_CONF_ADDR_OFF);
+
+        *val = readl(base + PCIE_CONF_DATA_OFF);
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
+                           u32 devfn, int where, int size, u32 *val)
+{
+        writel(PCIE_CONF_BUS(bus->number) |
+                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+                        base + PCIE_CONF_ADDR_OFF);
+
+        *val = readl(base + PCIE_CONF_DATA_OFF);
+
+        if (bus->number != orion_pcie_get_local_bus_nr(base) ||
+            PCI_FUNC(devfn) != 0)
+                *val = readl(base + PCIE_HEADER_LOG_4_OFF);
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
+                          u32 devfn, int where, int size, u32 *val)
+{
+        *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
+                                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                                PCIE_CONF_REG(where)));
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
+                       u32 devfn, int where, int size, u32 val)
+{
+        int ret = PCIBIOS_SUCCESSFUL;
+
+        writel(PCIE_CONF_BUS(bus->number) |
+                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+                        base + PCIE_CONF_ADDR_OFF);
+
+        if (size == 4) {
+                writel(val, base + PCIE_CONF_DATA_OFF);
+        } else if (size == 2) {
+                writew(val, base + PCIE_CONF_DATA_OFF + (where & 3));
+        } else if (size == 1) {
+                writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3));
+        } else {
+                ret = PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        return ret;
+}
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
new file mode 100644
index 000000000000..28b5285446e8
--- /dev/null
+++ b/arch/arm/plat-orion/time.c
@@ -0,0 +1,203 @@
+/*
+ * arch/arm/plat-orion/time.c
+ *
+ * Marvell Orion SoC timer handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Timer 0 is used as free-running clocksource, while timer 1 is
+ * used as clock_event_device.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/mach/time.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
+
+
+/*
+ * Timer block registers.
+ */
+#define TIMER_CTRL              (TIMER_VIRT_BASE + 0x0000)
+#define  TIMER0_EN              0x0001
+#define  TIMER0_RELOAD_EN       0x0002
+#define  TIMER1_EN              0x0004
+#define  TIMER1_RELOAD_EN       0x0008
+#define TIMER0_RELOAD           (TIMER_VIRT_BASE + 0x0010)
+#define TIMER0_VAL              (TIMER_VIRT_BASE + 0x0014)
+#define TIMER1_RELOAD           (TIMER_VIRT_BASE + 0x0018)
+#define TIMER1_VAL              (TIMER_VIRT_BASE + 0x001c)
+
+
+/*
+ * Clocksource handling.
+ */
+static cycle_t orion_clksrc_read(void)
+{
+        return 0xffffffff - readl(TIMER0_VAL);
+}
+
+static struct clocksource orion_clksrc = {
+        .name           = "orion_clocksource",
+        .shift          = 20,
+        .rating         = 300,
+        .read           = orion_clksrc_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+
+
+/*
+ * Clockevent handling.
+ */
+static int
+orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
+{
+        unsigned long flags;
+        u32 u;
+
+        if (delta == 0)
+                return -ETIME;
+
+        local_irq_save(flags);
+
+        /*
+         * Clear and enable clockevent timer interrupt.
+         */
+        writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+
+        u = readl(BRIDGE_MASK);
+        u |= BRIDGE_INT_TIMER1;
+        writel(u, BRIDGE_MASK);
+
+        /*
+         * Setup new clockevent timer value.
+         */
+        writel(delta, TIMER1_VAL);
+
+        /*
+         * Enable the timer.
+         */
+        u = readl(TIMER_CTRL);
+        u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
+        writel(u, TIMER_CTRL);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static void
+orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
+{
+        unsigned long flags;
+        u32 u;
+
+        local_irq_save(flags);
+        if (mode == CLOCK_EVT_MODE_PERIODIC) {
+                /*
+                 * Setup timer to fire at 1/HZ intervals.
+                 */
+                writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
+                writel(ticks_per_jiffy - 1, TIMER1_VAL);
+
+                /*
+                 * Enable timer interrupt.
+                 */
+                u = readl(BRIDGE_MASK);
+                writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
+
+                /*
+                 * Enable timer.
+                 */
+                u = readl(TIMER_CTRL);
+                writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
+        } else {
+                /*
+                 * Disable timer.
+                 */
+                u = readl(TIMER_CTRL);
+                writel(u & ~TIMER1_EN, TIMER_CTRL);
+
+                /*
+                 * Disable timer interrupt.
+                 */
+                u = readl(BRIDGE_MASK);
+                writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
+
+                /*
+                 * ACK pending timer interrupt.
+                 */
+                writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+
+        }
+        local_irq_restore(flags);
+}
+
+static struct clock_event_device orion_clkevt = {
+        .name           = "orion_tick",
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+        .shift          = 32,
+        .rating         = 300,
+        .cpumask        = CPU_MASK_CPU0,
+        .set_next_event = orion_clkevt_next_event,
+        .set_mode       = orion_clkevt_mode,
+};
+
+static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
+{
+        /*
+         * ACK timer interrupt and call event handler.
+         */
+        writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+        orion_clkevt.event_handler(&orion_clkevt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction orion_timer_irq = {
+        .name           = "orion_tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = orion_timer_interrupt
+};
+
+void __init orion_time_init(unsigned int irq, unsigned int tclk)
+{
+        u32 u;
+
+        ticks_per_jiffy = (tclk + HZ/2) / HZ;
+
+
+        /*
+         * Setup free-running clocksource timer (interrupts
+         * disabled.)
+         */
+        writel(0xffffffff, TIMER0_VAL);
+        writel(0xffffffff, TIMER0_RELOAD);
+        u = readl(BRIDGE_MASK);
+        writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
+        u = readl(TIMER_CTRL);
+        writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
+        orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
+        clocksource_register(&orion_clksrc);
+
+
+        /*
+         * Setup clockevent timer (interrupt-driven.)
+         */
+        setup_irq(irq, &orion_timer_irq);
+        orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
+        orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
+        orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
+        clockevents_register_device(&orion_clkevt);
+}