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-rw-r--r--arch/arm/plat-orion/gpio.c456
-rw-r--r--arch/arm/plat-orion/include/plat/gpio.h5
-rw-r--r--arch/arm/plat-orion/include/plat/time.h5
-rw-r--r--arch/arm/plat-orion/time.c119
4 files changed, 392 insertions, 193 deletions
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 5f3522314815..078894bc3b9a 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -17,55 +17,123 @@
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19 19
20static DEFINE_SPINLOCK(gpio_lock); 20/*
21static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)]; 21 * GPIO unit register offsets.
22static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)]; 22 */
23#define GPIO_OUT_OFF 0x0000
24#define GPIO_IO_CONF_OFF 0x0004
25#define GPIO_BLINK_EN_OFF 0x0008
26#define GPIO_IN_POL_OFF 0x000c
27#define GPIO_DATA_IN_OFF 0x0010
28#define GPIO_EDGE_CAUSE_OFF 0x0014
29#define GPIO_EDGE_MASK_OFF 0x0018
30#define GPIO_LEVEL_MASK_OFF 0x001c
31
32struct orion_gpio_chip {
33 struct gpio_chip chip;
34 spinlock_t lock;
35 void __iomem *base;
36 unsigned long valid_input;
37 unsigned long valid_output;
38 int mask_offset;
39 int secondary_irq_base;
40};
41
42static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
43{
44 return ochip->base + GPIO_OUT_OFF;
45}
46
47static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
48{
49 return ochip->base + GPIO_IO_CONF_OFF;
50}
51
52static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
53{
54 return ochip->base + GPIO_BLINK_EN_OFF;
55}
56
57static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
58{
59 return ochip->base + GPIO_IN_POL_OFF;
60}
61
62static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
63{
64 return ochip->base + GPIO_DATA_IN_OFF;
65}
66
67static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
68{
69 return ochip->base + GPIO_EDGE_CAUSE_OFF;
70}
71
72static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
73{
74 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
75}
76
77static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
78{
79 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
80}
81
23 82
24static inline void __set_direction(unsigned pin, int input) 83static struct orion_gpio_chip orion_gpio_chips[2];
84static int orion_gpio_chip_count;
85
86static inline void
87__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
25{ 88{
26 u32 u; 89 u32 u;
27 90
28 u = readl(GPIO_IO_CONF(pin)); 91 u = readl(GPIO_IO_CONF(ochip));
29 if (input) 92 if (input)
30 u |= 1 << (pin & 31); 93 u |= 1 << pin;
31 else 94 else
32 u &= ~(1 << (pin & 31)); 95 u &= ~(1 << pin);
33 writel(u, GPIO_IO_CONF(pin)); 96 writel(u, GPIO_IO_CONF(ochip));
34} 97}
35 98
36static void __set_level(unsigned pin, int high) 99static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
37{ 100{
38 u32 u; 101 u32 u;
39 102
40 u = readl(GPIO_OUT(pin)); 103 u = readl(GPIO_OUT(ochip));
41 if (high) 104 if (high)
42 u |= 1 << (pin & 31); 105 u |= 1 << pin;
43 else 106 else
44 u &= ~(1 << (pin & 31)); 107 u &= ~(1 << pin);
45 writel(u, GPIO_OUT(pin)); 108 writel(u, GPIO_OUT(ochip));
46} 109}
47 110
48static inline void __set_blinking(unsigned pin, int blink) 111static inline void
112__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
49{ 113{
50 u32 u; 114 u32 u;
51 115
52 u = readl(GPIO_BLINK_EN(pin)); 116 u = readl(GPIO_BLINK_EN(ochip));
53 if (blink) 117 if (blink)
54 u |= 1 << (pin & 31); 118 u |= 1 << pin;
55 else 119 else
56 u &= ~(1 << (pin & 31)); 120 u &= ~(1 << pin);
57 writel(u, GPIO_BLINK_EN(pin)); 121 writel(u, GPIO_BLINK_EN(ochip));
58} 122}
59 123
60static inline int orion_gpio_is_valid(unsigned pin, int mode) 124static inline int
125orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
61{ 126{
62 if (pin < GPIO_MAX) { 127 if (pin >= ochip->chip.ngpio)
63 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input)) 128 goto err_out;
64 goto err_out; 129
65 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output)) 130 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
66 goto err_out; 131 goto err_out;
67 return true; 132
68 } 133 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
134 goto err_out;
135
136 return 1;
69 137
70err_out: 138err_out:
71 pr_debug("%s: invalid GPIO %d\n", __func__, pin); 139 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
@@ -75,134 +143,155 @@ err_out:
75/* 143/*
76 * GENERIC_GPIO primitives. 144 * GENERIC_GPIO primitives.
77 */ 145 */
146static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
147{
148 struct orion_gpio_chip *ochip =
149 container_of(chip, struct orion_gpio_chip, chip);
150
151 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
152 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
153 return 0;
154
155 return -EINVAL;
156}
157
78static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 158static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
79{ 159{
160 struct orion_gpio_chip *ochip =
161 container_of(chip, struct orion_gpio_chip, chip);
80 unsigned long flags; 162 unsigned long flags;
81 163
82 if (!orion_gpio_is_valid(pin, GPIO_INPUT_OK)) 164 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
83 return -EINVAL; 165 return -EINVAL;
84 166
85 spin_lock_irqsave(&gpio_lock, flags); 167 spin_lock_irqsave(&ochip->lock, flags);
86 168 __set_direction(ochip, pin, 1);
87 /* Configure GPIO direction. */ 169 spin_unlock_irqrestore(&ochip->lock, flags);
88 __set_direction(pin, 1);
89
90 spin_unlock_irqrestore(&gpio_lock, flags);
91 170
92 return 0; 171 return 0;
93} 172}
94 173
95static int orion_gpio_get_value(struct gpio_chip *chip, unsigned pin) 174static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
96{ 175{
176 struct orion_gpio_chip *ochip =
177 container_of(chip, struct orion_gpio_chip, chip);
97 int val; 178 int val;
98 179
99 if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31))) 180 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
100 val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin)); 181 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
101 else 182 } else {
102 val = readl(GPIO_OUT(pin)); 183 val = readl(GPIO_OUT(ochip));
184 }
103 185
104 return (val >> (pin & 31)) & 1; 186 return (val >> pin) & 1;
105} 187}
106 188
107static int orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, 189static int
108 int value) 190orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
109{ 191{
192 struct orion_gpio_chip *ochip =
193 container_of(chip, struct orion_gpio_chip, chip);
110 unsigned long flags; 194 unsigned long flags;
111 195
112 if (!orion_gpio_is_valid(pin, GPIO_OUTPUT_OK)) 196 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
113 return -EINVAL; 197 return -EINVAL;
114 198
115 spin_lock_irqsave(&gpio_lock, flags); 199 spin_lock_irqsave(&ochip->lock, flags);
116 200 __set_blinking(ochip, pin, 0);
117 /* Disable blinking. */ 201 __set_level(ochip, pin, value);
118 __set_blinking(pin, 0); 202 __set_direction(ochip, pin, 0);
119 203 spin_unlock_irqrestore(&ochip->lock, flags);
120 /* Configure GPIO output value. */
121 __set_level(pin, value);
122
123 /* Configure GPIO direction. */
124 __set_direction(pin, 0);
125
126 spin_unlock_irqrestore(&gpio_lock, flags);
127 204
128 return 0; 205 return 0;
129} 206}
130 207
131static void orion_gpio_set_value(struct gpio_chip *chip, unsigned pin, 208static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
132 int value)
133{ 209{
210 struct orion_gpio_chip *ochip =
211 container_of(chip, struct orion_gpio_chip, chip);
134 unsigned long flags; 212 unsigned long flags;
135 213
136 spin_lock_irqsave(&gpio_lock, flags); 214 spin_lock_irqsave(&ochip->lock, flags);
137 215 __set_level(ochip, pin, value);
138 /* Configure GPIO output value. */ 216 spin_unlock_irqrestore(&ochip->lock, flags);
139 __set_level(pin, value);
140
141 spin_unlock_irqrestore(&gpio_lock, flags);
142} 217}
143 218
144static int orion_gpio_request(struct gpio_chip *chip, unsigned pin) 219static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
145{ 220{
146 if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) || 221 struct orion_gpio_chip *ochip =
147 orion_gpio_is_valid(pin, GPIO_OUTPUT_OK)) 222 container_of(chip, struct orion_gpio_chip, chip);
148 return 0;
149 return -EINVAL;
150}
151 223
152static struct gpio_chip orion_gpiochip = { 224 return ochip->secondary_irq_base + pin;
153 .label = "orion_gpio",
154 .direction_input = orion_gpio_direction_input,
155 .get = orion_gpio_get_value,
156 .direction_output = orion_gpio_direction_output,
157 .set = orion_gpio_set_value,
158 .request = orion_gpio_request,
159 .base = 0,
160 .ngpio = GPIO_MAX,
161 .can_sleep = 0,
162};
163
164void __init orion_gpio_init(void)
165{
166 gpiochip_add(&orion_gpiochip);
167} 225}
168 226
227
169/* 228/*
170 * Orion-specific GPIO API extensions. 229 * Orion-specific GPIO API extensions.
171 */ 230 */
231static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
232{
233 int i;
234
235 for (i = 0; i < orion_gpio_chip_count; i++) {
236 struct orion_gpio_chip *ochip = orion_gpio_chips + i;
237 struct gpio_chip *chip = &ochip->chip;
238
239 if (pin >= chip->base && pin < chip->base + chip->ngpio)
240 return ochip;
241 }
242
243 return NULL;
244}
245
172void __init orion_gpio_set_unused(unsigned pin) 246void __init orion_gpio_set_unused(unsigned pin)
173{ 247{
248 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
249
250 if (ochip == NULL)
251 return;
252
253 pin -= ochip->chip.base;
254
174 /* Configure as output, drive low. */ 255 /* Configure as output, drive low. */
175 __set_level(pin, 0); 256 __set_level(ochip, pin, 0);
176 __set_direction(pin, 0); 257 __set_direction(ochip, pin, 0);
177} 258}
178 259
179void __init orion_gpio_set_valid(unsigned pin, int mode) 260void __init orion_gpio_set_valid(unsigned pin, int mode)
180{ 261{
262 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
263
264 if (ochip == NULL)
265 return;
266
267 pin -= ochip->chip.base;
268
181 if (mode == 1) 269 if (mode == 1)
182 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; 270 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
271
183 if (mode & GPIO_INPUT_OK) 272 if (mode & GPIO_INPUT_OK)
184 __set_bit(pin, gpio_valid_input); 273 __set_bit(pin, &ochip->valid_input);
185 else 274 else
186 __clear_bit(pin, gpio_valid_input); 275 __clear_bit(pin, &ochip->valid_input);
276
187 if (mode & GPIO_OUTPUT_OK) 277 if (mode & GPIO_OUTPUT_OK)
188 __set_bit(pin, gpio_valid_output); 278 __set_bit(pin, &ochip->valid_output);
189 else 279 else
190 __clear_bit(pin, gpio_valid_output); 280 __clear_bit(pin, &ochip->valid_output);
191} 281}
192 282
193void orion_gpio_set_blink(unsigned pin, int blink) 283void orion_gpio_set_blink(unsigned pin, int blink)
194{ 284{
285 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
195 unsigned long flags; 286 unsigned long flags;
196 287
197 spin_lock_irqsave(&gpio_lock, flags); 288 if (ochip == NULL)
289 return;
198 290
199 /* Set output value to zero. */ 291 spin_lock_irqsave(&ochip->lock, flags);
200 __set_level(pin, 0); 292 __set_level(ochip, pin, 0);
201 293 __set_blinking(ochip, pin, blink);
202 /* Set blinking. */ 294 spin_unlock_irqrestore(&ochip->lock, flags);
203 __set_blinking(pin, blink);
204
205 spin_unlock_irqrestore(&gpio_lock, flags);
206} 295}
207EXPORT_SYMBOL(orion_gpio_set_blink); 296EXPORT_SYMBOL(orion_gpio_set_blink);
208 297
@@ -234,59 +323,78 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
234 ****************************************************************************/ 323 ****************************************************************************/
235static void gpio_irq_ack(struct irq_data *d) 324static void gpio_irq_ack(struct irq_data *d)
236{ 325{
237 int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; 326 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
327 int type;
328
329 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
238 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 330 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
239 int pin = irq_to_gpio(d->irq); 331 int pin = d->irq - ochip->secondary_irq_base;
240 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin)); 332
333 writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
241 } 334 }
242} 335}
243 336
244static void gpio_irq_mask(struct irq_data *d) 337static void gpio_irq_mask(struct irq_data *d)
245{ 338{
246 int pin = irq_to_gpio(d->irq); 339 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
247 int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; 340 int type;
248 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? 341 void __iomem *reg;
249 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); 342 int pin;
250 u32 u = readl(reg); 343
251 u &= ~(1 << (pin & 31)); 344 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
252 writel(u, reg); 345 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
346 reg = GPIO_EDGE_MASK(ochip);
347 else
348 reg = GPIO_LEVEL_MASK(ochip);
349
350 pin = d->irq - ochip->secondary_irq_base;
351
352 writel(readl(reg) & ~(1 << pin), reg);
253} 353}
254 354
255static void gpio_irq_unmask(struct irq_data *d) 355static void gpio_irq_unmask(struct irq_data *d)
256{ 356{
257 int pin = irq_to_gpio(d->irq); 357 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
258 int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; 358 int type;
259 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? 359 void __iomem *reg;
260 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); 360 int pin;
261 u32 u = readl(reg); 361
262 u |= 1 << (pin & 31); 362 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
263 writel(u, reg); 363 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
364 reg = GPIO_EDGE_MASK(ochip);
365 else
366 reg = GPIO_LEVEL_MASK(ochip);
367
368 pin = d->irq - ochip->secondary_irq_base;
369
370 writel(readl(reg) | (1 << pin), reg);
264} 371}
265 372
266static int gpio_irq_set_type(struct irq_data *d, u32 type) 373static int gpio_irq_set_type(struct irq_data *d, u32 type)
267{ 374{
268 int pin = irq_to_gpio(d->irq); 375 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
269 struct irq_desc *desc; 376 int pin;
270 u32 u; 377 u32 u;
271 378
272 u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)); 379 pin = d->irq - ochip->secondary_irq_base;
380
381 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
273 if (!u) { 382 if (!u) {
274 printk(KERN_ERR "orion gpio_irq_set_type failed " 383 printk(KERN_ERR "orion gpio_irq_set_type failed "
275 "(irq %d, pin %d).\n", d->irq, pin); 384 "(irq %d, pin %d).\n", d->irq, pin);
276 return -EINVAL; 385 return -EINVAL;
277 } 386 }
278 387
279 desc = irq_desc + d->irq;
280
281 /* 388 /*
282 * Set edge/level type. 389 * Set edge/level type.
283 */ 390 */
284 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 391 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
285 desc->handle_irq = handle_edge_irq; 392 set_irq_handler(d->irq, handle_edge_irq);
286 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 393 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
287 desc->handle_irq = handle_level_irq; 394 set_irq_handler(d->irq, handle_level_irq);
288 } else { 395 } else {
289 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type); 396 printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
397 d->irq, type);
290 return -EINVAL; 398 return -EINVAL;
291 } 399 }
292 400
@@ -294,31 +402,29 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
294 * Configure interrupt polarity. 402 * Configure interrupt polarity.
295 */ 403 */
296 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) { 404 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
297 u = readl(GPIO_IN_POL(pin)); 405 u = readl(GPIO_IN_POL(ochip));
298 u &= ~(1 << (pin & 31)); 406 u &= ~(1 << pin);
299 writel(u, GPIO_IN_POL(pin)); 407 writel(u, GPIO_IN_POL(ochip));
300 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) { 408 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
301 u = readl(GPIO_IN_POL(pin)); 409 u = readl(GPIO_IN_POL(ochip));
302 u |= 1 << (pin & 31); 410 u |= 1 << pin;
303 writel(u, GPIO_IN_POL(pin)); 411 writel(u, GPIO_IN_POL(ochip));
304 } else if (type == IRQ_TYPE_EDGE_BOTH) { 412 } else if (type == IRQ_TYPE_EDGE_BOTH) {
305 u32 v; 413 u32 v;
306 414
307 v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin)); 415 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
308 416
309 /* 417 /*
310 * set initial polarity based on current input level 418 * set initial polarity based on current input level
311 */ 419 */
312 u = readl(GPIO_IN_POL(pin)); 420 u = readl(GPIO_IN_POL(ochip));
313 if (v & (1 << (pin & 31))) 421 if (v & (1 << pin))
314 u |= 1 << (pin & 31); /* falling */ 422 u |= 1 << pin; /* falling */
315 else 423 else
316 u &= ~(1 << (pin & 31)); /* rising */ 424 u &= ~(1 << pin); /* rising */
317 writel(u, GPIO_IN_POL(pin)); 425 writel(u, GPIO_IN_POL(ochip));
318 } 426 }
319 427
320 desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
321
322 return 0; 428 return 0;
323} 429}
324 430
@@ -330,29 +436,87 @@ struct irq_chip orion_gpio_irq_chip = {
330 .irq_set_type = gpio_irq_set_type, 436 .irq_set_type = gpio_irq_set_type,
331}; 437};
332 438
439void __init orion_gpio_init(int gpio_base, int ngpio,
440 u32 base, int mask_offset, int secondary_irq_base)
441{
442 struct orion_gpio_chip *ochip;
443 int i;
444
445 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
446 return;
447
448 ochip = orion_gpio_chips + orion_gpio_chip_count;
449 ochip->chip.label = "orion_gpio";
450 ochip->chip.request = orion_gpio_request;
451 ochip->chip.direction_input = orion_gpio_direction_input;
452 ochip->chip.get = orion_gpio_get;
453 ochip->chip.direction_output = orion_gpio_direction_output;
454 ochip->chip.set = orion_gpio_set;
455 ochip->chip.to_irq = orion_gpio_to_irq;
456 ochip->chip.base = gpio_base;
457 ochip->chip.ngpio = ngpio;
458 ochip->chip.can_sleep = 0;
459 spin_lock_init(&ochip->lock);
460 ochip->base = (void __iomem *)base;
461 ochip->valid_input = 0;
462 ochip->valid_output = 0;
463 ochip->mask_offset = mask_offset;
464 ochip->secondary_irq_base = secondary_irq_base;
465
466 gpiochip_add(&ochip->chip);
467
468 orion_gpio_chip_count++;
469
470 /*
471 * Mask and clear GPIO interrupts.
472 */
473 writel(0, GPIO_EDGE_CAUSE(ochip));
474 writel(0, GPIO_EDGE_MASK(ochip));
475 writel(0, GPIO_LEVEL_MASK(ochip));
476
477 for (i = 0; i < ngpio; i++) {
478 unsigned int irq = secondary_irq_base + i;
479
480 set_irq_chip(irq, &orion_gpio_irq_chip);
481 set_irq_handler(irq, handle_level_irq);
482 set_irq_chip_data(irq, ochip);
483 irq_desc[irq].status |= IRQ_LEVEL;
484 set_irq_flags(irq, IRQF_VALID);
485 }
486}
487
333void orion_gpio_irq_handler(int pinoff) 488void orion_gpio_irq_handler(int pinoff)
334{ 489{
490 struct orion_gpio_chip *ochip;
335 u32 cause; 491 u32 cause;
336 int pin; 492 int i;
337 493
338 cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff)); 494 ochip = orion_gpio_chip_find(pinoff);
339 cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff)); 495 if (ochip == NULL)
496 return;
340 497
341 for (pin = pinoff; pin < pinoff + 8; pin++) { 498 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
342 int irq = gpio_to_irq(pin); 499 cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
343 struct irq_desc *desc = irq_desc + irq;
344 500
345 if (!(cause & (1 << (pin & 31)))) 501 for (i = 0; i < ochip->chip.ngpio; i++) {
502 int irq;
503 struct irq_desc *desc;
504
505 irq = ochip->secondary_irq_base + i;
506
507 if (!(cause & (1 << i)))
346 continue; 508 continue;
347 509
510 desc = irq_desc + irq;
348 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 511 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
349 /* Swap polarity (race with GPIO line) */ 512 /* Swap polarity (race with GPIO line) */
350 u32 polarity; 513 u32 polarity;
351 514
352 polarity = readl(GPIO_IN_POL(pin)); 515 polarity = readl(GPIO_IN_POL(ochip));
353 polarity ^= 1 << (pin & 31); 516 polarity ^= 1 << i;
354 writel(polarity, GPIO_IN_POL(pin)); 517 writel(polarity, GPIO_IN_POL(ochip));
355 } 518 }
519
356 desc_handle_irq(irq, desc); 520 desc_handle_irq(irq, desc);
357 } 521 }
358} 522}
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 07c430fdc9ef..5578b9803fc6 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -12,6 +12,7 @@
12#define __PLAT_GPIO_H 12#define __PLAT_GPIO_H
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm-generic/gpio.h>
15 16
16/* 17/*
17 * GENERIC_GPIO primitives. 18 * GENERIC_GPIO primitives.
@@ -19,6 +20,7 @@
19#define gpio_get_value __gpio_get_value 20#define gpio_get_value __gpio_get_value
20#define gpio_set_value __gpio_set_value 21#define gpio_set_value __gpio_set_value
21#define gpio_cansleep __gpio_cansleep 22#define gpio_cansleep __gpio_cansleep
23#define gpio_to_irq __gpio_to_irq
22 24
23/* 25/*
24 * Orion-specific GPIO API extensions. 26 * Orion-specific GPIO API extensions.
@@ -31,7 +33,8 @@ void orion_gpio_set_blink(unsigned pin, int blink);
31void orion_gpio_set_valid(unsigned pin, int mode); 33void orion_gpio_set_valid(unsigned pin, int mode);
32 34
33/* Initialize gpiolib. */ 35/* Initialize gpiolib. */
34void __init orion_gpio_init(void); 36void __init orion_gpio_init(int gpio_base, int ngpio,
37 u32 base, int mask_offset, int secondary_irq_base);
35 38
36/* 39/*
37 * GPIO interrupt handling. 40 * GPIO interrupt handling.
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index c06ca35f3613..4d5f1f6e18df 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,7 +11,10 @@
11#ifndef __PLAT_TIME_H 11#ifndef __PLAT_TIME_H
12#define __PLAT_TIME_H 12#define __PLAT_TIME_H
13 13
14void orion_time_init(unsigned int irq, unsigned int tclk); 14void orion_time_set_base(u32 timer_base);
15
16void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
17 unsigned int irq, unsigned int tclk);
15 18
16 19
17#endif 20#endif
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index c3da2478b2aa..742b0323c57b 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -18,28 +18,42 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/irq.h> 19#include <linux/irq.h>
20#include <asm/sched_clock.h> 20#include <asm/sched_clock.h>
21#include <asm/mach/time.h>
22#include <mach/bridge-regs.h>
23#include <mach/hardware.h>
24 21
25/* 22/*
26 * Number of timer ticks per jiffy. 23 * MBus bridge block registers.
27 */ 24 */
28static u32 ticks_per_jiffy; 25#define BRIDGE_CAUSE_OFF 0x0110
26#define BRIDGE_MASK_OFF 0x0114
27#define BRIDGE_INT_TIMER0 0x0002
28#define BRIDGE_INT_TIMER1 0x0004
29 29
30 30
31/* 31/*
32 * Timer block registers. 32 * Timer block registers.
33 */ 33 */
34#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) 34#define TIMER_CTRL_OFF 0x0000
35#define TIMER0_EN 0x0001 35#define TIMER0_EN 0x0001
36#define TIMER0_RELOAD_EN 0x0002 36#define TIMER0_RELOAD_EN 0x0002
37#define TIMER1_EN 0x0004 37#define TIMER1_EN 0x0004
38#define TIMER1_RELOAD_EN 0x0008 38#define TIMER1_RELOAD_EN 0x0008
39#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010) 39#define TIMER0_RELOAD_OFF 0x0010
40#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014) 40#define TIMER0_VAL_OFF 0x0014
41#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018) 41#define TIMER1_RELOAD_OFF 0x0018
42#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c) 42#define TIMER1_VAL_OFF 0x001c
43
44
45/*
46 * SoC-specific data.
47 */
48static void __iomem *bridge_base;
49static u32 bridge_timer1_clr_mask;
50static void __iomem *timer_base;
51
52
53/*
54 * Number of timer ticks per jiffy.
55 */
56static u32 ticks_per_jiffy;
43 57
44 58
45/* 59/*
@@ -50,14 +64,14 @@ static DEFINE_CLOCK_DATA(cd);
50 64
51unsigned long long notrace sched_clock(void) 65unsigned long long notrace sched_clock(void)
52{ 66{
53 u32 cyc = 0xffffffff - readl(TIMER0_VAL); 67 u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
54 return cyc_to_sched_clock(&cd, cyc, (u32)~0); 68 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
55} 69}
56 70
57 71
58static void notrace orion_update_sched_clock(void) 72static void notrace orion_update_sched_clock(void)
59{ 73{
60 u32 cyc = 0xffffffff - readl(TIMER0_VAL); 74 u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
61 update_sched_clock(&cd, cyc, (u32)~0); 75 update_sched_clock(&cd, cyc, (u32)~0);
62} 76}
63 77
@@ -71,7 +85,7 @@ static void __init setup_sched_clock(unsigned long tclk)
71 */ 85 */
72static cycle_t orion_clksrc_read(struct clocksource *cs) 86static cycle_t orion_clksrc_read(struct clocksource *cs)
73{ 87{
74 return 0xffffffff - readl(TIMER0_VAL); 88 return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
75} 89}
76 90
77static struct clocksource orion_clksrc = { 91static struct clocksource orion_clksrc = {
@@ -101,23 +115,23 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
101 /* 115 /*
102 * Clear and enable clockevent timer interrupt. 116 * Clear and enable clockevent timer interrupt.
103 */ 117 */
104 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 118 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
105 119
106 u = readl(BRIDGE_MASK); 120 u = readl(bridge_base + BRIDGE_MASK_OFF);
107 u |= BRIDGE_INT_TIMER1; 121 u |= BRIDGE_INT_TIMER1;
108 writel(u, BRIDGE_MASK); 122 writel(u, bridge_base + BRIDGE_MASK_OFF);
109 123
110 /* 124 /*
111 * Setup new clockevent timer value. 125 * Setup new clockevent timer value.
112 */ 126 */
113 writel(delta, TIMER1_VAL); 127 writel(delta, timer_base + TIMER1_VAL_OFF);
114 128
115 /* 129 /*
116 * Enable the timer. 130 * Enable the timer.
117 */ 131 */
118 u = readl(TIMER_CTRL); 132 u = readl(timer_base + TIMER_CTRL_OFF);
119 u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; 133 u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
120 writel(u, TIMER_CTRL); 134 writel(u, timer_base + TIMER_CTRL_OFF);
121 135
122 local_irq_restore(flags); 136 local_irq_restore(flags);
123 137
@@ -135,37 +149,38 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
135 /* 149 /*
136 * Setup timer to fire at 1/HZ intervals. 150 * Setup timer to fire at 1/HZ intervals.
137 */ 151 */
138 writel(ticks_per_jiffy - 1, TIMER1_RELOAD); 152 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
139 writel(ticks_per_jiffy - 1, TIMER1_VAL); 153 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
140 154
141 /* 155 /*
142 * Enable timer interrupt. 156 * Enable timer interrupt.
143 */ 157 */
144 u = readl(BRIDGE_MASK); 158 u = readl(bridge_base + BRIDGE_MASK_OFF);
145 writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK); 159 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
146 160
147 /* 161 /*
148 * Enable timer. 162 * Enable timer.
149 */ 163 */
150 u = readl(TIMER_CTRL); 164 u = readl(timer_base + TIMER_CTRL_OFF);
151 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL); 165 writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
166 timer_base + TIMER_CTRL_OFF);
152 } else { 167 } else {
153 /* 168 /*
154 * Disable timer. 169 * Disable timer.
155 */ 170 */
156 u = readl(TIMER_CTRL); 171 u = readl(timer_base + TIMER_CTRL_OFF);
157 writel(u & ~TIMER1_EN, TIMER_CTRL); 172 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
158 173
159 /* 174 /*
160 * Disable timer interrupt. 175 * Disable timer interrupt.
161 */ 176 */
162 u = readl(BRIDGE_MASK); 177 u = readl(bridge_base + BRIDGE_MASK_OFF);
163 writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK); 178 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
164 179
165 /* 180 /*
166 * ACK pending timer interrupt. 181 * ACK pending timer interrupt.
167 */ 182 */
168 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 183 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
169 184
170 } 185 }
171 local_irq_restore(flags); 186 local_irq_restore(flags);
@@ -185,7 +200,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
185 /* 200 /*
186 * ACK timer interrupt and call event handler. 201 * ACK timer interrupt and call event handler.
187 */ 202 */
188 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 203 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
189 orion_clkevt.event_handler(&orion_clkevt); 204 orion_clkevt.event_handler(&orion_clkevt);
190 205
191 return IRQ_HANDLED; 206 return IRQ_HANDLED;
@@ -197,31 +212,45 @@ static struct irqaction orion_timer_irq = {
197 .handler = orion_timer_interrupt 212 .handler = orion_timer_interrupt
198}; 213};
199 214
200void __init orion_time_init(unsigned int irq, unsigned int tclk) 215void __init
216orion_time_set_base(u32 _timer_base)
217{
218 timer_base = (void __iomem *)_timer_base;
219}
220
221void __init
222orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
223 unsigned int irq, unsigned int tclk)
201{ 224{
202 u32 u; 225 u32 u;
203 226
227 /*
228 * Set SoC-specific data.
229 */
230 bridge_base = (void __iomem *)_bridge_base;
231 bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
232
204 ticks_per_jiffy = (tclk + HZ/2) / HZ; 233 ticks_per_jiffy = (tclk + HZ/2) / HZ;
205 234
206 /* 235 /*
207 * Set scale and timer for sched_clock 236 * Set scale and timer for sched_clock.
208 */ 237 */
209 setup_sched_clock(tclk); 238 setup_sched_clock(tclk);
210 239
211 /* 240 /*
212 * Setup free-running clocksource timer (interrupts 241 * Setup free-running clocksource timer (interrupts
213 * disabled.) 242 * disabled).
214 */ 243 */
215 writel(0xffffffff, TIMER0_VAL); 244 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
216 writel(0xffffffff, TIMER0_RELOAD); 245 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
217 u = readl(BRIDGE_MASK); 246 u = readl(bridge_base + BRIDGE_MASK_OFF);
218 writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); 247 writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
219 u = readl(TIMER_CTRL); 248 u = readl(timer_base + TIMER_CTRL_OFF);
220 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); 249 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
221 clocksource_register_hz(&orion_clksrc, tclk); 250 clocksource_register_hz(&orion_clksrc, tclk);
222 251
223 /* 252 /*
224 * Setup clockevent timer (interrupt-driven.) 253 * Setup clockevent timer (interrupt-driven).
225 */ 254 */
226 setup_irq(irq, &orion_timer_irq); 255 setup_irq(irq, &orion_timer_irq);
227 orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); 256 orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 02:54:56 -0500