diff options
Diffstat (limited to 'arch/arm/plat-orion')
-rw-r--r-- | arch/arm/plat-orion/gpio.c | 37 | ||||
-rw-r--r-- | arch/arm/plat-orion/irq.c | 18 |
2 files changed, 27 insertions, 28 deletions
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index e814803d4741..5f3522314815 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c | |||
@@ -232,20 +232,19 @@ EXPORT_SYMBOL(orion_gpio_set_blink); | |||
232 | * polarity LEVEL mask | 232 | * polarity LEVEL mask |
233 | * | 233 | * |
234 | ****************************************************************************/ | 234 | ****************************************************************************/ |
235 | 235 | static void gpio_irq_ack(struct irq_data *d) | |
236 | static void gpio_irq_ack(u32 irq) | ||
237 | { | 236 | { |
238 | int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; | 237 | int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; |
239 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | 238 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
240 | int pin = irq_to_gpio(irq); | 239 | int pin = irq_to_gpio(d->irq); |
241 | writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin)); | 240 | writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin)); |
242 | } | 241 | } |
243 | } | 242 | } |
244 | 243 | ||
245 | static void gpio_irq_mask(u32 irq) | 244 | static void gpio_irq_mask(struct irq_data *d) |
246 | { | 245 | { |
247 | int pin = irq_to_gpio(irq); | 246 | int pin = irq_to_gpio(d->irq); |
248 | int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; | 247 | int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; |
249 | u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? | 248 | u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? |
250 | GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); | 249 | GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); |
251 | u32 u = readl(reg); | 250 | u32 u = readl(reg); |
@@ -253,10 +252,10 @@ static void gpio_irq_mask(u32 irq) | |||
253 | writel(u, reg); | 252 | writel(u, reg); |
254 | } | 253 | } |
255 | 254 | ||
256 | static void gpio_irq_unmask(u32 irq) | 255 | static void gpio_irq_unmask(struct irq_data *d) |
257 | { | 256 | { |
258 | int pin = irq_to_gpio(irq); | 257 | int pin = irq_to_gpio(d->irq); |
259 | int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; | 258 | int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; |
260 | u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? | 259 | u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? |
261 | GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); | 260 | GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); |
262 | u32 u = readl(reg); | 261 | u32 u = readl(reg); |
@@ -264,20 +263,20 @@ static void gpio_irq_unmask(u32 irq) | |||
264 | writel(u, reg); | 263 | writel(u, reg); |
265 | } | 264 | } |
266 | 265 | ||
267 | static int gpio_irq_set_type(u32 irq, u32 type) | 266 | static int gpio_irq_set_type(struct irq_data *d, u32 type) |
268 | { | 267 | { |
269 | int pin = irq_to_gpio(irq); | 268 | int pin = irq_to_gpio(d->irq); |
270 | struct irq_desc *desc; | 269 | struct irq_desc *desc; |
271 | u32 u; | 270 | u32 u; |
272 | 271 | ||
273 | u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)); | 272 | u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)); |
274 | if (!u) { | 273 | if (!u) { |
275 | printk(KERN_ERR "orion gpio_irq_set_type failed " | 274 | printk(KERN_ERR "orion gpio_irq_set_type failed " |
276 | "(irq %d, pin %d).\n", irq, pin); | 275 | "(irq %d, pin %d).\n", d->irq, pin); |
277 | return -EINVAL; | 276 | return -EINVAL; |
278 | } | 277 | } |
279 | 278 | ||
280 | desc = irq_desc + irq; | 279 | desc = irq_desc + d->irq; |
281 | 280 | ||
282 | /* | 281 | /* |
283 | * Set edge/level type. | 282 | * Set edge/level type. |
@@ -287,7 +286,7 @@ static int gpio_irq_set_type(u32 irq, u32 type) | |||
287 | } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | 286 | } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
288 | desc->handle_irq = handle_level_irq; | 287 | desc->handle_irq = handle_level_irq; |
289 | } else { | 288 | } else { |
290 | printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); | 289 | printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type); |
291 | return -EINVAL; | 290 | return -EINVAL; |
292 | } | 291 | } |
293 | 292 | ||
@@ -325,10 +324,10 @@ static int gpio_irq_set_type(u32 irq, u32 type) | |||
325 | 324 | ||
326 | struct irq_chip orion_gpio_irq_chip = { | 325 | struct irq_chip orion_gpio_irq_chip = { |
327 | .name = "orion_gpio_irq", | 326 | .name = "orion_gpio_irq", |
328 | .ack = gpio_irq_ack, | 327 | .irq_ack = gpio_irq_ack, |
329 | .mask = gpio_irq_mask, | 328 | .irq_mask = gpio_irq_mask, |
330 | .unmask = gpio_irq_unmask, | 329 | .irq_unmask = gpio_irq_unmask, |
331 | .set_type = gpio_irq_set_type, | 330 | .irq_set_type = gpio_irq_set_type, |
332 | }; | 331 | }; |
333 | 332 | ||
334 | void orion_gpio_irq_handler(int pinoff) | 333 | void orion_gpio_irq_handler(int pinoff) |
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 3f9d34fc738c..7d0c7eb59f09 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c | |||
@@ -14,31 +14,31 @@ | |||
14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
15 | #include <plat/irq.h> | 15 | #include <plat/irq.h> |
16 | 16 | ||
17 | static void orion_irq_mask(u32 irq) | 17 | static void orion_irq_mask(struct irq_data *d) |
18 | { | 18 | { |
19 | void __iomem *maskaddr = get_irq_chip_data(irq); | 19 | void __iomem *maskaddr = irq_data_get_irq_chip_data(d); |
20 | u32 mask; | 20 | u32 mask; |
21 | 21 | ||
22 | mask = readl(maskaddr); | 22 | mask = readl(maskaddr); |
23 | mask &= ~(1 << (irq & 31)); | 23 | mask &= ~(1 << (d->irq & 31)); |
24 | writel(mask, maskaddr); | 24 | writel(mask, maskaddr); |
25 | } | 25 | } |
26 | 26 | ||
27 | static void orion_irq_unmask(u32 irq) | 27 | static void orion_irq_unmask(struct irq_data *d) |
28 | { | 28 | { |
29 | void __iomem *maskaddr = get_irq_chip_data(irq); | 29 | void __iomem *maskaddr = irq_data_get_irq_chip_data(d); |
30 | u32 mask; | 30 | u32 mask; |
31 | 31 | ||
32 | mask = readl(maskaddr); | 32 | mask = readl(maskaddr); |
33 | mask |= 1 << (irq & 31); | 33 | mask |= 1 << (d->irq & 31); |
34 | writel(mask, maskaddr); | 34 | writel(mask, maskaddr); |
35 | } | 35 | } |
36 | 36 | ||
37 | static struct irq_chip orion_irq_chip = { | 37 | static struct irq_chip orion_irq_chip = { |
38 | .name = "orion_irq", | 38 | .name = "orion_irq", |
39 | .mask = orion_irq_mask, | 39 | .irq_mask = orion_irq_mask, |
40 | .mask_ack = orion_irq_mask, | 40 | .irq_mask_ack = orion_irq_mask, |
41 | .unmask = orion_irq_unmask, | 41 | .irq_unmask = orion_irq_unmask, |
42 | }; | 42 | }; |
43 | 43 | ||
44 | void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) | 44 | void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) |