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-rw-r--r--arch/arm/plat-omap/devices.c46
-rw-r--r--arch/arm/plat-omap/i2c.c8
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
-rw-r--r--arch/arm/plat-omap/include/plat/common.h13
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h108
-rw-r--r--arch/arm/plat-omap/include/plat/io.h2
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h208
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h30
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h2
-rw-r--r--arch/arm/plat-omap/mcbsp.c385
-rw-r--r--arch/arm/plat-omap/omap_device.c185
11 files changed, 373 insertions, 616 deletions
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index ea28f98d5d6a..bd9a06b3ee89 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -26,54 +26,8 @@
26#include <plat/mmc.h> 26#include <plat/mmc.h>
27#include <mach/gpio.h> 27#include <mach/gpio.h>
28#include <plat/menelaus.h> 28#include <plat/menelaus.h>
29#include <plat/mcbsp.h>
30#include <plat/omap44xx.h> 29#include <plat/omap44xx.h>
31 30
32/*-------------------------------------------------------------------------*/
33
34#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
35
36static struct platform_device **omap_mcbsp_devices;
37
38void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
39 struct omap_mcbsp_platform_data *config, int size)
40{
41 int i;
42
43 omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
44 GFP_KERNEL);
45 if (!omap_mcbsp_devices) {
46 printk(KERN_ERR "Could not register McBSP devices\n");
47 return;
48 }
49
50 for (i = 0; i < size; i++) {
51 struct platform_device *new_mcbsp;
52 int ret;
53
54 new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
55 if (!new_mcbsp)
56 continue;
57 platform_device_add_resources(new_mcbsp, &res[i * res_count],
58 res_count);
59 new_mcbsp->dev.platform_data = &config[i];
60 ret = platform_device_add(new_mcbsp);
61 if (ret) {
62 platform_device_put(new_mcbsp);
63 continue;
64 }
65 omap_mcbsp_devices[i] = new_mcbsp;
66 }
67}
68
69#else
70void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
71 struct omap_mcbsp_platform_data *config, int size)
72{ }
73#endif
74
75/*-------------------------------------------------------------------------*/
76
77#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \ 31#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
78 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE) 32 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
79 33
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 3341ca4703e9..0c7caf2458b4 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -135,7 +135,7 @@ static inline int omap2_i2c_add_bus(int bus_id)
135{ 135{
136 int l; 136 int l;
137 struct omap_hwmod *oh; 137 struct omap_hwmod *oh;
138 struct omap_device *od; 138 struct platform_device *pdev;
139 char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN]; 139 char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
140 struct omap_i2c_bus_platform_data *pdata; 140 struct omap_i2c_bus_platform_data *pdata;
141 141
@@ -160,12 +160,12 @@ static inline int omap2_i2c_add_bus(int bus_id)
160 */ 160 */
161 if (cpu_is_omap34xx()) 161 if (cpu_is_omap34xx())
162 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; 162 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
163 od = omap_device_build(name, bus_id, oh, pdata, 163 pdev = omap_device_build(name, bus_id, oh, pdata,
164 sizeof(struct omap_i2c_bus_platform_data), 164 sizeof(struct omap_i2c_bus_platform_data),
165 omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0); 165 omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0);
166 WARN(IS_ERR(od), "Could not build omap_device for %s\n", name); 166 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
167 167
168 return PTR_ERR(od); 168 return PTR_ERR(pdev);
169} 169}
170#else 170#else
171static inline int omap2_i2c_add_bus(int bus_id) 171static inline int omap2_i2c_add_bus(int bus_id)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index df4b9683f17f..197ca03c3f7d 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -80,8 +80,6 @@ struct clkops {
80 * 80 *
81 * @div is the divisor that should be applied to the parent clock's rate 81 * @div is the divisor that should be applied to the parent clock's rate
82 * to produce the current clock's rate. 82 * to produce the current clock's rate.
83 *
84 * XXX @flags probably should be replaced with an struct omap_chip.
85 */ 83 */
86struct clksel_rate { 84struct clksel_rate {
87 u32 val; 85 u32 val;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 4564cc697d7f..abda2c7e499b 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -45,6 +45,15 @@ extern unsigned long long notrace omap_32k_sched_clock(void);
45 45
46extern void omap_reserve(void); 46extern void omap_reserve(void);
47 47
48void omap2420_init_early(void);
49void omap2430_init_early(void);
50void omap3430_init_early(void);
51void omap35xx_init_early(void);
52void omap3630_init_early(void);
53void am35xx_init_early(void);
54void ti816x_init_early(void);
55void omap4430_init_early(void);
56
48/* 57/*
49 * IO bases for various OMAP processors 58 * IO bases for various OMAP processors
50 * Except the tap base, rest all the io bases 59 * Except the tap base, rest all the io bases
@@ -74,7 +83,11 @@ void omap2_set_globals_sdrc(struct omap_globals *);
74void omap2_set_globals_control(struct omap_globals *); 83void omap2_set_globals_control(struct omap_globals *);
75void omap2_set_globals_prcm(struct omap_globals *); 84void omap2_set_globals_prcm(struct omap_globals *);
76 85
86void omap242x_map_io(void);
87void omap243x_map_io(void);
77void omap3_map_io(void); 88void omap3_map_io(void);
89void omap4_map_io(void);
90
78 91
79/** 92/**
80 * omap_test_timeout - busy-loop, testing a condition 93 * omap_test_timeout - busy-loop, testing a condition
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 67b3d75884cd..2f9026942229 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -44,13 +44,6 @@
44 44
45int omap_type(void); 45int omap_type(void);
46 46
47struct omap_chip_id {
48 u16 oc;
49 u8 type;
50};
51
52#define OMAP_CHIP_INIT(x) { .oc = x }
53
54/* 47/*
55 * omap_rev bits: 48 * omap_rev bits:
56 * CPU id bits (0730, 1510, 1710, 2422...) [31:16] 49 * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
@@ -60,19 +53,6 @@ struct omap_chip_id {
60unsigned int omap_rev(void); 53unsigned int omap_rev(void);
61 54
62/* 55/*
63 * Define CPU revision bits
64 *
65 * Verbose meaning of the revision bits may be different for a silicon
66 * family. This difference can be handled separately.
67 */
68#define OMAP_REVBITS_00 0x00
69#define OMAP_REVBITS_01 0x01
70#define OMAP_REVBITS_02 0x02
71#define OMAP_REVBITS_03 0x03
72#define OMAP_REVBITS_04 0x04
73#define OMAP_REVBITS_05 0x05
74
75/*
76 * Get the CPU revision for OMAP devices 56 * Get the CPU revision for OMAP devices
77 */ 57 */
78#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) 58#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
@@ -262,7 +242,7 @@ IS_OMAP_TYPE(2422, 0x2422)
262IS_OMAP_TYPE(2423, 0x2423) 242IS_OMAP_TYPE(2423, 0x2423)
263IS_OMAP_TYPE(2430, 0x2430) 243IS_OMAP_TYPE(2430, 0x2430)
264IS_OMAP_TYPE(3430, 0x3430) 244IS_OMAP_TYPE(3430, 0x3430)
265IS_OMAP_TYPE(3505, 0x3505) 245IS_OMAP_TYPE(3505, 0x3517)
266IS_OMAP_TYPE(3517, 0x3517) 246IS_OMAP_TYPE(3517, 0x3517)
267 247
268#define cpu_is_omap310() 0 248#define cpu_is_omap310() 0
@@ -354,8 +334,9 @@ IS_OMAP_TYPE(3517, 0x3517)
354 (!omap3_has_sgx()) && \ 334 (!omap3_has_sgx()) && \
355 (omap3_has_iva())) 335 (omap3_has_iva()))
356# define cpu_is_omap3530() (cpu_is_omap3430()) 336# define cpu_is_omap3530() (cpu_is_omap3430())
357# define cpu_is_omap3505() is_omap3505()
358# define cpu_is_omap3517() is_omap3517() 337# define cpu_is_omap3517() is_omap3517()
338# define cpu_is_omap3505() (cpu_is_omap3517() && \
339 !omap3_has_sgx())
359# undef cpu_is_omap3630 340# undef cpu_is_omap3630
360# define cpu_is_omap3630() is_omap363x() 341# define cpu_is_omap3630() is_omap363x()
361# define cpu_is_ti816x() is_ti816x() 342# define cpu_is_ti816x() is_ti816x()
@@ -379,35 +360,31 @@ IS_OMAP_TYPE(3517, 0x3517)
379/* Various silicon revisions for omap2 */ 360/* Various silicon revisions for omap2 */
380#define OMAP242X_CLASS 0x24200024 361#define OMAP242X_CLASS 0x24200024
381#define OMAP2420_REV_ES1_0 OMAP242X_CLASS 362#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
382#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8)) 363#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
383 364
384#define OMAP243X_CLASS 0x24300024 365#define OMAP243X_CLASS 0x24300024
385#define OMAP2430_REV_ES1_0 OMAP243X_CLASS 366#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
386 367
387#define OMAP343X_CLASS 0x34300034 368#define OMAP343X_CLASS 0x34300034
388#define OMAP3430_REV_ES1_0 OMAP343X_CLASS 369#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
389#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8)) 370#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
390#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8)) 371#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8))
391#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8)) 372#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8))
392#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8)) 373#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8))
393#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8)) 374#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8))
394 375
395#define OMAP363X_CLASS 0x36300034 376#define OMAP363X_CLASS 0x36300034
396#define OMAP3630_REV_ES1_0 OMAP363X_CLASS 377#define OMAP3630_REV_ES1_0 OMAP363X_CLASS
397#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8)) 378#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8))
398#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8)) 379#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8))
399 380
400#define OMAP35XX_CLASS 0x35000034 381#define OMAP3517_CLASS 0x35170034
401#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) 382#define OMAP3517_REV_ES1_0 OMAP3517_CLASS
402#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8)) 383#define OMAP3517_REV_ES1_1 (OMAP3517_CLASS | (0x1 << 8))
403#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
404#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
405#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
406#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
407 384
408#define TI816X_CLASS 0x81600034 385#define TI816X_CLASS 0x81600034
409#define TI8168_REV_ES1_0 TI816X_CLASS 386#define TI8168_REV_ES1_0 TI816X_CLASS
410#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) 387#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
411 388
412#define OMAP443X_CLASS 0x44300044 389#define OMAP443X_CLASS 0x44300044
413#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) 390#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
@@ -418,61 +395,6 @@ IS_OMAP_TYPE(3517, 0x3517)
418#define OMAP446X_CLASS 0x44600044 395#define OMAP446X_CLASS 0x44600044
419#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8)) 396#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
420 397
421/*
422 * omap_chip bits
423 *
424 * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
425 * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
426 * something that is only valid on that particular ES revision.
427 *
428 * These bits may be ORed together to indicate structures that are
429 * available on multiple chip types.
430 *
431 * To test whether a particular structure matches the current OMAP chip type,
432 * use omap_chip_is().
433 *
434 */
435#define CHIP_IS_OMAP2420 (1 << 0)
436#define CHIP_IS_OMAP2430 (1 << 1)
437#define CHIP_IS_OMAP3430 (1 << 2)
438#define CHIP_IS_OMAP3430ES1 (1 << 3)
439#define CHIP_IS_OMAP3430ES2 (1 << 4)
440#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
441#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
442#define CHIP_IS_OMAP3630ES1 (1 << 7)
443#define CHIP_IS_OMAP4430ES1 (1 << 8)
444#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
445#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
446#define CHIP_IS_OMAP4430ES2 (1 << 11)
447#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
448#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
449#define CHIP_IS_TI816X (1 << 14)
450#define CHIP_IS_OMAP4460ES1_0 (1 << 15)
451
452#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
453
454#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
455 CHIP_IS_OMAP4430ES2 | \
456 CHIP_IS_OMAP4430ES2_1 | \
457 CHIP_IS_OMAP4430ES2_2 | \
458 CHIP_IS_OMAP4460ES1_0)
459
460/*
461 * "GE" here represents "greater than or equal to" in terms of ES
462 * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
463 * chips at ES2 and beyond, but not, for example, any OMAP lines after
464 * OMAP3.
465 */
466#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
467 CHIP_IS_OMAP3430ES3_0 | \
468 CHIP_GE_OMAP3430ES3_1)
469#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
470 CHIP_IS_OMAP3630ES1 | \
471 CHIP_GE_OMAP3630ES1_1)
472#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \
473 CHIP_IS_OMAP3630ES1_2)
474
475int omap_chip_is(struct omap_chip_id oci);
476void omap2_check_revision(void); 398void omap2_check_revision(void);
477 399
478/* 400/*
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index d72ec85c97e6..75311fc9c018 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -300,7 +300,7 @@ static inline void omap44xx_map_common_io(void)
300#endif 300#endif
301 301
302extern void omap2_init_common_infrastructure(void); 302extern void omap2_init_common_infrastructure(void);
303extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, 303extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
304 struct omap_sdrc_params *sdrc_cs1); 304 struct omap_sdrc_params *sdrc_cs1);
305 305
306#define __arch_ioremap omap_ioremap 306#define __arch_ioremap omap_ioremap
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 9882c657b2d4..8fa74e2c9d6e 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -25,9 +25,7 @@
25#define __ASM_ARCH_OMAP_MCBSP_H 25#define __ASM_ARCH_OMAP_MCBSP_H
26 26
27#include <linux/spinlock.h> 27#include <linux/spinlock.h>
28 28#include <linux/clk.h>
29#include <mach/hardware.h>
30#include <plat/clock.h>
31 29
32/* macro for building platform_device for McBSP ports */ 30/* macro for building platform_device for McBSP ports */
33#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \ 31#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
@@ -40,104 +38,60 @@ static struct platform_device omap_mcbsp##port_nr = { \
40#define MCBSP_CONFIG_TYPE3 0x3 38#define MCBSP_CONFIG_TYPE3 0x3
41#define MCBSP_CONFIG_TYPE4 0x4 39#define MCBSP_CONFIG_TYPE4 0x4
42 40
43#define OMAP7XX_MCBSP1_BASE 0xfffb1000 41/* McBSP register numbers. Register address offset = num * reg_step */
44#define OMAP7XX_MCBSP2_BASE 0xfffb1800 42enum {
45 43 /* Common registers */
46#define OMAP1510_MCBSP1_BASE 0xe1011800 44 OMAP_MCBSP_REG_SPCR2 = 4,
47#define OMAP1510_MCBSP2_BASE 0xfffb1000 45 OMAP_MCBSP_REG_SPCR1,
48#define OMAP1510_MCBSP3_BASE 0xe1017000 46 OMAP_MCBSP_REG_RCR2,
49 47 OMAP_MCBSP_REG_RCR1,
50#define OMAP1610_MCBSP1_BASE 0xe1011800 48 OMAP_MCBSP_REG_XCR2,
51#define OMAP1610_MCBSP2_BASE 0xfffb1000 49 OMAP_MCBSP_REG_XCR1,
52#define OMAP1610_MCBSP3_BASE 0xe1017000 50 OMAP_MCBSP_REG_SRGR2,
53 51 OMAP_MCBSP_REG_SRGR1,
54#ifdef CONFIG_ARCH_OMAP1 52 OMAP_MCBSP_REG_MCR2,
55 53 OMAP_MCBSP_REG_MCR1,
56#define OMAP_MCBSP_REG_DRR2 0x00 54 OMAP_MCBSP_REG_RCERA,
57#define OMAP_MCBSP_REG_DRR1 0x02 55 OMAP_MCBSP_REG_RCERB,
58#define OMAP_MCBSP_REG_DXR2 0x04 56 OMAP_MCBSP_REG_XCERA,
59#define OMAP_MCBSP_REG_DXR1 0x06 57 OMAP_MCBSP_REG_XCERB,
60#define OMAP_MCBSP_REG_DRR 0x02 58 OMAP_MCBSP_REG_PCR0,
61#define OMAP_MCBSP_REG_DXR 0x06 59 OMAP_MCBSP_REG_RCERC,
62#define OMAP_MCBSP_REG_SPCR2 0x08 60 OMAP_MCBSP_REG_RCERD,
63#define OMAP_MCBSP_REG_SPCR1 0x0a 61 OMAP_MCBSP_REG_XCERC,
64#define OMAP_MCBSP_REG_RCR2 0x0c 62 OMAP_MCBSP_REG_XCERD,
65#define OMAP_MCBSP_REG_RCR1 0x0e 63 OMAP_MCBSP_REG_RCERE,
66#define OMAP_MCBSP_REG_XCR2 0x10 64 OMAP_MCBSP_REG_RCERF,
67#define OMAP_MCBSP_REG_XCR1 0x12 65 OMAP_MCBSP_REG_XCERE,
68#define OMAP_MCBSP_REG_SRGR2 0x14 66 OMAP_MCBSP_REG_XCERF,
69#define OMAP_MCBSP_REG_SRGR1 0x16 67 OMAP_MCBSP_REG_RCERG,
70#define OMAP_MCBSP_REG_MCR2 0x18 68 OMAP_MCBSP_REG_RCERH,
71#define OMAP_MCBSP_REG_MCR1 0x1a 69 OMAP_MCBSP_REG_XCERG,
72#define OMAP_MCBSP_REG_RCERA 0x1c 70 OMAP_MCBSP_REG_XCERH,
73#define OMAP_MCBSP_REG_RCERB 0x1e 71
74#define OMAP_MCBSP_REG_XCERA 0x20 72 /* OMAP1-OMAP2420 registers */
75#define OMAP_MCBSP_REG_XCERB 0x22 73 OMAP_MCBSP_REG_DRR2 = 0,
76#define OMAP_MCBSP_REG_PCR0 0x24 74 OMAP_MCBSP_REG_DRR1,
77#define OMAP_MCBSP_REG_RCERC 0x26 75 OMAP_MCBSP_REG_DXR2,
78#define OMAP_MCBSP_REG_RCERD 0x28 76 OMAP_MCBSP_REG_DXR1,
79#define OMAP_MCBSP_REG_XCERC 0x2A 77
80#define OMAP_MCBSP_REG_XCERD 0x2C 78 /* OMAP2430 and onwards */
81#define OMAP_MCBSP_REG_RCERE 0x2E 79 OMAP_MCBSP_REG_DRR = 0,
82#define OMAP_MCBSP_REG_RCERF 0x30 80 OMAP_MCBSP_REG_DXR = 2,
83#define OMAP_MCBSP_REG_XCERE 0x32 81 OMAP_MCBSP_REG_SYSCON = 35,
84#define OMAP_MCBSP_REG_XCERF 0x34 82 OMAP_MCBSP_REG_THRSH2,
85#define OMAP_MCBSP_REG_RCERG 0x36 83 OMAP_MCBSP_REG_THRSH1,
86#define OMAP_MCBSP_REG_RCERH 0x38 84 OMAP_MCBSP_REG_IRQST = 40,
87#define OMAP_MCBSP_REG_XCERG 0x3A 85 OMAP_MCBSP_REG_IRQEN,
88#define OMAP_MCBSP_REG_XCERH 0x3C 86 OMAP_MCBSP_REG_WAKEUPEN,
89 87 OMAP_MCBSP_REG_XCCR,
90/* Dummy defines, these are not available on omap1 */ 88 OMAP_MCBSP_REG_RCCR,
91#define OMAP_MCBSP_REG_XCCR 0x00 89 OMAP_MCBSP_REG_XBUFFSTAT,
92#define OMAP_MCBSP_REG_RCCR 0x00 90 OMAP_MCBSP_REG_RBUFFSTAT,
93 91 OMAP_MCBSP_REG_SSELCR,
94#else 92};
95
96#define OMAP_MCBSP_REG_DRR2 0x00
97#define OMAP_MCBSP_REG_DRR1 0x04
98#define OMAP_MCBSP_REG_DXR2 0x08
99#define OMAP_MCBSP_REG_DXR1 0x0C
100#define OMAP_MCBSP_REG_DRR 0x00
101#define OMAP_MCBSP_REG_DXR 0x08
102#define OMAP_MCBSP_REG_SPCR2 0x10
103#define OMAP_MCBSP_REG_SPCR1 0x14
104#define OMAP_MCBSP_REG_RCR2 0x18
105#define OMAP_MCBSP_REG_RCR1 0x1C
106#define OMAP_MCBSP_REG_XCR2 0x20
107#define OMAP_MCBSP_REG_XCR1 0x24
108#define OMAP_MCBSP_REG_SRGR2 0x28
109#define OMAP_MCBSP_REG_SRGR1 0x2C
110#define OMAP_MCBSP_REG_MCR2 0x30
111#define OMAP_MCBSP_REG_MCR1 0x34
112#define OMAP_MCBSP_REG_RCERA 0x38
113#define OMAP_MCBSP_REG_RCERB 0x3C
114#define OMAP_MCBSP_REG_XCERA 0x40
115#define OMAP_MCBSP_REG_XCERB 0x44
116#define OMAP_MCBSP_REG_PCR0 0x48
117#define OMAP_MCBSP_REG_RCERC 0x4C
118#define OMAP_MCBSP_REG_RCERD 0x50
119#define OMAP_MCBSP_REG_XCERC 0x54
120#define OMAP_MCBSP_REG_XCERD 0x58
121#define OMAP_MCBSP_REG_RCERE 0x5C
122#define OMAP_MCBSP_REG_RCERF 0x60
123#define OMAP_MCBSP_REG_XCERE 0x64
124#define OMAP_MCBSP_REG_XCERF 0x68
125#define OMAP_MCBSP_REG_RCERG 0x6C
126#define OMAP_MCBSP_REG_RCERH 0x70
127#define OMAP_MCBSP_REG_XCERG 0x74
128#define OMAP_MCBSP_REG_XCERH 0x78
129#define OMAP_MCBSP_REG_SYSCON 0x8C
130#define OMAP_MCBSP_REG_THRSH2 0x90
131#define OMAP_MCBSP_REG_THRSH1 0x94
132#define OMAP_MCBSP_REG_IRQST 0xA0
133#define OMAP_MCBSP_REG_IRQEN 0xA4
134#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
135#define OMAP_MCBSP_REG_XCCR 0xAC
136#define OMAP_MCBSP_REG_RCCR 0xB0
137#define OMAP_MCBSP_REG_XBUFFSTAT 0xB4
138#define OMAP_MCBSP_REG_RBUFFSTAT 0xB8
139#define OMAP_MCBSP_REG_SSELCR 0xBC
140 93
94/* OMAP3 sidetone control registers */
141#define OMAP_ST_REG_REV 0x00 95#define OMAP_ST_REG_REV 0x00
142#define OMAP_ST_REG_SYSCONFIG 0x10 96#define OMAP_ST_REG_SYSCONFIG 0x10
143#define OMAP_ST_REG_IRQSTATUS 0x18 97#define OMAP_ST_REG_IRQSTATUS 0x18
@@ -146,8 +100,6 @@ static struct platform_device omap_mcbsp##port_nr = { \
146#define OMAP_ST_REG_SFIRCR 0x28 100#define OMAP_ST_REG_SFIRCR 0x28
147#define OMAP_ST_REG_SSELCR 0x2C 101#define OMAP_ST_REG_SSELCR 0x2C
148 102
149#endif
150
151/************************** McBSP SPCR1 bit definitions ***********************/ 103/************************** McBSP SPCR1 bit definitions ***********************/
152#define RRST 0x0001 104#define RRST 0x0001
153#define RRDY 0x0002 105#define RRDY 0x0002
@@ -344,20 +296,20 @@ typedef enum {
344struct omap_mcbsp_ops { 296struct omap_mcbsp_ops {
345 void (*request)(unsigned int); 297 void (*request)(unsigned int);
346 void (*free)(unsigned int); 298 void (*free)(unsigned int);
347 int (*set_clks_src)(u8, u8);
348}; 299};
349 300
350struct omap_mcbsp_platform_data { 301struct omap_mcbsp_platform_data {
351 unsigned long phys_base;
352 u8 dma_rx_sync, dma_tx_sync;
353 u16 rx_irq, tx_irq;
354 struct omap_mcbsp_ops *ops; 302 struct omap_mcbsp_ops *ops;
355#ifdef CONFIG_ARCH_OMAP3
356 /* Sidetone block for McBSP 2 and 3 */
357 unsigned long phys_base_st;
358#endif
359 u16 buffer_size; 303 u16 buffer_size;
360 unsigned int mcbsp_config_type; 304 u8 reg_size;
305 u8 reg_step;
306
307 /* McBSP platform and instance specific features */
308 bool has_wakeup; /* Wakeup capability */
309 bool has_ccr; /* Transceiver has configuration control registers */
310 int (*enable_st_clock)(unsigned int, bool);
311 int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
312 int (*mux_signal)(struct device *dev, const char *signal, const char *src);
361}; 313};
362 314
363struct omap_mcbsp_st_data { 315struct omap_mcbsp_st_data {
@@ -389,14 +341,12 @@ struct omap_mcbsp {
389 spinlock_t lock; 341 spinlock_t lock;
390 struct omap_mcbsp_platform_data *pdata; 342 struct omap_mcbsp_platform_data *pdata;
391 struct clk *fclk; 343 struct clk *fclk;
392#ifdef CONFIG_ARCH_OMAP3
393 struct omap_mcbsp_st_data *st_data; 344 struct omap_mcbsp_st_data *st_data;
394 int dma_op_mode; 345 int dma_op_mode;
395 u16 max_tx_thres; 346 u16 max_tx_thres;
396 u16 max_rx_thres; 347 u16 max_rx_thres;
397#endif
398 void *reg_cache; 348 void *reg_cache;
399 unsigned int mcbsp_config_type; 349 int reg_cache_size;
400}; 350};
401 351
402/** 352/**
@@ -408,16 +358,10 @@ struct omap_mcbsp_dev_attr {
408}; 358};
409 359
410extern struct omap_mcbsp **mcbsp_ptr; 360extern struct omap_mcbsp **mcbsp_ptr;
411extern int omap_mcbsp_count, omap_mcbsp_cache_size; 361extern int omap_mcbsp_count;
412
413#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
414#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
415 362
416int omap_mcbsp_init(void); 363int omap_mcbsp_init(void);
417void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
418 struct omap_mcbsp_platform_data *config, int size);
419void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 364void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
420#ifdef CONFIG_ARCH_OMAP3
421void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); 365void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
422void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); 366void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
423u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); 367u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
@@ -426,18 +370,6 @@ u16 omap_mcbsp_get_fifo_size(unsigned int id);
426u16 omap_mcbsp_get_tx_delay(unsigned int id); 370u16 omap_mcbsp_get_tx_delay(unsigned int id);
427u16 omap_mcbsp_get_rx_delay(unsigned int id); 371u16 omap_mcbsp_get_rx_delay(unsigned int id);
428int omap_mcbsp_get_dma_op_mode(unsigned int id); 372int omap_mcbsp_get_dma_op_mode(unsigned int id);
429#else
430static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
431{ }
432static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
433{ }
434static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
435static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
436static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
437static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
438static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
439static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
440#endif
441int omap_mcbsp_request(unsigned int id); 373int omap_mcbsp_request(unsigned int id);
442void omap_mcbsp_free(unsigned int id); 374void omap_mcbsp_free(unsigned int id);
443void omap_mcbsp_start(unsigned int id, int tx, int rx); 375void omap_mcbsp_start(unsigned int id, int tx, int rx);
@@ -453,21 +385,11 @@ void omap2_mcbsp1_mux_fsr_src(u8 mux);
453int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); 385int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
454int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream); 386int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
455 387
456#ifdef CONFIG_ARCH_OMAP3
457/* Sidetone specific API */ 388/* Sidetone specific API */
458int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); 389int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
459int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain); 390int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
460int omap_st_enable(unsigned int id); 391int omap_st_enable(unsigned int id);
461int omap_st_disable(unsigned int id); 392int omap_st_disable(unsigned int id);
462int omap_st_is_enabled(unsigned int id); 393int omap_st_is_enabled(unsigned int id);
463#else
464static inline int omap_st_set_chgain(unsigned int id, int channel,
465 s16 chgain) { return 0; }
466static inline int omap_st_get_chgain(unsigned int id, int channel,
467 s16 *chgain) { return 0; }
468static inline int omap_st_enable(unsigned int id) { return 0; }
469static inline int omap_st_disable(unsigned int id) { return 0; }
470static inline int omap_st_is_enabled(unsigned int id) { return 0; }
471#endif
472 394
473#endif 395#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index ee405b36df4b..d4d9b96f961e 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -68,7 +68,7 @@ extern struct device omap_device_parent;
68 * 68 *
69 */ 69 */
70struct omap_device { 70struct omap_device {
71 struct platform_device pdev; 71 struct platform_device *pdev;
72 struct omap_hwmod **hwmods; 72 struct omap_hwmod **hwmods;
73 struct omap_device_pm_latency *pm_lats; 73 struct omap_device_pm_latency *pm_lats;
74 u32 dev_wakeup_lat; 74 u32 dev_wakeup_lat;
@@ -88,24 +88,18 @@ int omap_device_shutdown(struct platform_device *pdev);
88 88
89/* Core code interface */ 89/* Core code interface */
90 90
91int omap_device_count_resources(struct omap_device *od); 91struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
92int omap_device_fill_resources(struct omap_device *od, struct resource *res);
93
94struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
95 struct omap_hwmod *oh, void *pdata, 92 struct omap_hwmod *oh, void *pdata,
96 int pdata_len, 93 int pdata_len,
97 struct omap_device_pm_latency *pm_lats, 94 struct omap_device_pm_latency *pm_lats,
98 int pm_lats_cnt, int is_early_device); 95 int pm_lats_cnt, int is_early_device);
99 96
100struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, 97struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
101 struct omap_hwmod **oh, int oh_cnt, 98 struct omap_hwmod **oh, int oh_cnt,
102 void *pdata, int pdata_len, 99 void *pdata, int pdata_len,
103 struct omap_device_pm_latency *pm_lats, 100 struct omap_device_pm_latency *pm_lats,
104 int pm_lats_cnt, int is_early_device); 101 int pm_lats_cnt, int is_early_device);
105 102
106int omap_device_register(struct omap_device *od);
107int omap_early_device_register(struct omap_device *od);
108
109void __iomem *omap_device_get_rt_va(struct omap_device *od); 103void __iomem *omap_device_get_rt_va(struct omap_device *od);
110 104
111/* OMAP PM interface */ 105/* OMAP PM interface */
@@ -122,11 +116,6 @@ int omap_device_enable_hwmods(struct omap_device *od);
122int omap_device_disable_clocks(struct omap_device *od); 116int omap_device_disable_clocks(struct omap_device *od);
123int omap_device_enable_clocks(struct omap_device *od); 117int omap_device_enable_clocks(struct omap_device *od);
124 118
125static inline void omap_device_disable_idle_on_suspend(struct omap_device *od)
126{
127 od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
128}
129
130/* 119/*
131 * Entries should be kept in latency order ascending 120 * Entries should be kept in latency order ascending
132 * 121 *
@@ -157,6 +146,17 @@ struct omap_device_pm_latency {
157#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1) 146#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
158 147
159/* Get omap_device pointer from platform_device pointer */ 148/* Get omap_device pointer from platform_device pointer */
160#define to_omap_device(x) container_of((x), struct omap_device, pdev) 149static inline struct omap_device *to_omap_device(struct platform_device *pdev)
150{
151 return pdev ? pdev->archdata.od : NULL;
152}
153
154static inline
155void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
156{
157 struct omap_device *od = to_omap_device(pdev);
158
159 od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
160}
161 161
162#endif 162#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 0e329ca88a70..9115aedd2124 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -496,7 +496,6 @@ struct omap_hwmod_class {
496 * @_state: internal-use hwmod state 496 * @_state: internal-use hwmod state
497 * @_postsetup_state: internal-use state to leave the hwmod in after _setup() 497 * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
498 * @flags: hwmod flags (documented below) 498 * @flags: hwmod flags (documented below)
499 * @omap_chip: OMAP chips this hwmod is present on
500 * @_lock: spinlock serializing operations on this hwmod 499 * @_lock: spinlock serializing operations on this hwmod
501 * @node: list node for hwmod list (internal use) 500 * @node: list node for hwmod list (internal use)
502 * 501 *
@@ -545,7 +544,6 @@ struct omap_hwmod {
545 u8 _int_flags; 544 u8 _int_flags;
546 u8 _state; 545 u8 _state;
547 u8 _postsetup_state; 546 u8 _postsetup_state;
548 const struct omap_chip_id omap_chip;
549}; 547};
550 548
551int omap_hwmod_register(struct omap_hwmod **ohs); 549int omap_hwmod_register(struct omap_hwmod **ohs);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 6c62af108710..4b15cd7926d7 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -24,45 +24,40 @@
24#include <linux/slab.h> 24#include <linux/slab.h>
25 25
26#include <plat/mcbsp.h> 26#include <plat/mcbsp.h>
27#include <plat/omap_device.h>
28#include <linux/pm_runtime.h> 27#include <linux/pm_runtime.h>
29 28
30/* XXX These "sideways" includes are a sign that something is wrong */
31#include "../mach-omap2/cm2xxx_3xxx.h"
32#include "../mach-omap2/cm-regbits-34xx.h"
33
34struct omap_mcbsp **mcbsp_ptr; 29struct omap_mcbsp **mcbsp_ptr;
35int omap_mcbsp_count, omap_mcbsp_cache_size; 30int omap_mcbsp_count;
31
32#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
33#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
36 34
37static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) 35static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
38{ 36{
39 if (cpu_class_is_omap1()) { 37 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
40 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; 38
41 __raw_writew((u16)val, mcbsp->io_base + reg); 39 if (mcbsp->pdata->reg_size == 2) {
42 } else if (cpu_is_omap2420()) { 40 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
43 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val; 41 __raw_writew((u16)val, addr);
44 __raw_writew((u16)val, mcbsp->io_base + reg);
45 } else { 42 } else {
46 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val; 43 ((u32 *)mcbsp->reg_cache)[reg] = val;
47 __raw_writel(val, mcbsp->io_base + reg); 44 __raw_writel(val, addr);
48 } 45 }
49} 46}
50 47
51static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) 48static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
52{ 49{
53 if (cpu_class_is_omap1()) { 50 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
54 return !from_cache ? __raw_readw(mcbsp->io_base + reg) : 51
55 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)]; 52 if (mcbsp->pdata->reg_size == 2) {
56 } else if (cpu_is_omap2420()) { 53 return !from_cache ? __raw_readw(addr) :
57 return !from_cache ? __raw_readw(mcbsp->io_base + reg) : 54 ((u16 *)mcbsp->reg_cache)[reg];
58 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
59 } else { 55 } else {
60 return !from_cache ? __raw_readl(mcbsp->io_base + reg) : 56 return !from_cache ? __raw_readl(addr) :
61 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)]; 57 ((u32 *)mcbsp->reg_cache)[reg];
62 } 58 }
63} 59}
64 60
65#ifdef CONFIG_ARCH_OMAP3
66static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) 61static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
67{ 62{
68 __raw_writel(val, mcbsp->st_data->io_base_st + reg); 63 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
@@ -72,7 +67,6 @@ static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
72{ 67{
73 return __raw_readl(mcbsp->st_data->io_base_st + reg); 68 return __raw_readl(mcbsp->st_data->io_base_st + reg);
74} 69}
75#endif
76 70
77#define MCBSP_READ(mcbsp, reg) \ 71#define MCBSP_READ(mcbsp, reg) \
78 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0) 72 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
@@ -187,7 +181,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
187 MCBSP_WRITE(mcbsp, MCR2, config->mcr2); 181 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
188 MCBSP_WRITE(mcbsp, MCR1, config->mcr1); 182 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
189 MCBSP_WRITE(mcbsp, PCR0, config->pcr0); 183 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
190 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 184 if (mcbsp->pdata->has_ccr) {
191 MCBSP_WRITE(mcbsp, XCCR, config->xccr); 185 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
192 MCBSP_WRITE(mcbsp, RCCR, config->rccr); 186 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
193 } 187 }
@@ -239,46 +233,28 @@ int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
239 } 233 }
240 mcbsp = id_to_mcbsp_ptr(id); 234 mcbsp = id_to_mcbsp_ptr(id);
241 235
242 data_reg = mcbsp->phys_dma_base; 236 if (mcbsp->pdata->reg_size == 2) {
243
244 if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
245 if (stream) 237 if (stream)
246 data_reg += OMAP_MCBSP_REG_DRR1; 238 data_reg = OMAP_MCBSP_REG_DRR1;
247 else 239 else
248 data_reg += OMAP_MCBSP_REG_DXR1; 240 data_reg = OMAP_MCBSP_REG_DXR1;
249 } else { 241 } else {
250 if (stream) 242 if (stream)
251 data_reg += OMAP_MCBSP_REG_DRR; 243 data_reg = OMAP_MCBSP_REG_DRR;
252 else 244 else
253 data_reg += OMAP_MCBSP_REG_DXR; 245 data_reg = OMAP_MCBSP_REG_DXR;
254 } 246 }
255 247
256 return data_reg; 248 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
257} 249}
258EXPORT_SYMBOL(omap_mcbsp_dma_reg_params); 250EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
259 251
260#ifdef CONFIG_ARCH_OMAP3
261static struct omap_device *find_omap_device_by_dev(struct device *dev)
262{
263 struct platform_device *pdev = container_of(dev,
264 struct platform_device, dev);
265 return container_of(pdev, struct omap_device, pdev);
266}
267
268static void omap_st_on(struct omap_mcbsp *mcbsp) 252static void omap_st_on(struct omap_mcbsp *mcbsp)
269{ 253{
270 unsigned int w; 254 unsigned int w;
271 struct omap_device *od;
272 255
273 od = find_omap_device_by_dev(mcbsp->dev); 256 if (mcbsp->pdata->enable_st_clock)
274 257 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
275 /*
276 * Sidetone uses McBSP ICLK - which must not idle when sidetones
277 * are enabled or sidetones start sounding ugly.
278 */
279 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
280 w &= ~(1 << (mcbsp->id - 2));
281 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
282 258
283 /* Enable McBSP Sidetone */ 259 /* Enable McBSP Sidetone */
284 w = MCBSP_READ(mcbsp, SSELCR); 260 w = MCBSP_READ(mcbsp, SSELCR);
@@ -292,9 +268,6 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
292static void omap_st_off(struct omap_mcbsp *mcbsp) 268static void omap_st_off(struct omap_mcbsp *mcbsp)
293{ 269{
294 unsigned int w; 270 unsigned int w;
295 struct omap_device *od;
296
297 od = find_omap_device_by_dev(mcbsp->dev);
298 271
299 w = MCBSP_ST_READ(mcbsp, SSELCR); 272 w = MCBSP_ST_READ(mcbsp, SSELCR);
300 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN)); 273 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
@@ -302,17 +275,13 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
302 w = MCBSP_READ(mcbsp, SSELCR); 275 w = MCBSP_READ(mcbsp, SSELCR);
303 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); 276 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
304 277
305 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); 278 if (mcbsp->pdata->enable_st_clock)
306 w |= 1 << (mcbsp->id - 2); 279 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
307 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
308} 280}
309 281
310static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) 282static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
311{ 283{
312 u16 val, i; 284 u16 val, i;
313 struct omap_device *od;
314
315 od = find_omap_device_by_dev(mcbsp->dev);
316 285
317 val = MCBSP_ST_READ(mcbsp, SSELCR); 286 val = MCBSP_ST_READ(mcbsp, SSELCR);
318 287
@@ -340,9 +309,6 @@ static void omap_st_chgain(struct omap_mcbsp *mcbsp)
340{ 309{
341 u16 w; 310 u16 w;
342 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 311 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
343 struct omap_device *od;
344
345 od = find_omap_device_by_dev(mcbsp->dev);
346 312
347 w = MCBSP_ST_READ(mcbsp, SSELCR); 313 w = MCBSP_ST_READ(mcbsp, SSELCR);
348 314
@@ -525,14 +491,13 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
525{ 491{
526 struct omap_mcbsp *mcbsp; 492 struct omap_mcbsp *mcbsp;
527 493
528 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
529 return;
530
531 if (!omap_mcbsp_check_valid_id(id)) { 494 if (!omap_mcbsp_check_valid_id(id)) {
532 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 495 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
533 return; 496 return;
534 } 497 }
535 mcbsp = id_to_mcbsp_ptr(id); 498 mcbsp = id_to_mcbsp_ptr(id);
499 if (mcbsp->pdata->buffer_size == 0)
500 return;
536 501
537 if (threshold && threshold <= mcbsp->max_tx_thres) 502 if (threshold && threshold <= mcbsp->max_tx_thres)
538 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); 503 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
@@ -548,14 +513,13 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
548{ 513{
549 struct omap_mcbsp *mcbsp; 514 struct omap_mcbsp *mcbsp;
550 515
551 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
552 return;
553
554 if (!omap_mcbsp_check_valid_id(id)) { 516 if (!omap_mcbsp_check_valid_id(id)) {
555 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 517 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
556 return; 518 return;
557 } 519 }
558 mcbsp = id_to_mcbsp_ptr(id); 520 mcbsp = id_to_mcbsp_ptr(id);
521 if (mcbsp->pdata->buffer_size == 0)
522 return;
559 523
560 if (threshold && threshold <= mcbsp->max_rx_thres) 524 if (threshold && threshold <= mcbsp->max_rx_thres)
561 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); 525 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
@@ -625,6 +589,8 @@ u16 omap_mcbsp_get_tx_delay(unsigned int id)
625 return -ENODEV; 589 return -ENODEV;
626 } 590 }
627 mcbsp = id_to_mcbsp_ptr(id); 591 mcbsp = id_to_mcbsp_ptr(id);
592 if (mcbsp->pdata->buffer_size == 0)
593 return 0;
628 594
629 /* Returns the number of free locations in the buffer */ 595 /* Returns the number of free locations in the buffer */
630 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); 596 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
@@ -648,6 +614,8 @@ u16 omap_mcbsp_get_rx_delay(unsigned int id)
648 return -ENODEV; 614 return -ENODEV;
649 } 615 }
650 mcbsp = id_to_mcbsp_ptr(id); 616 mcbsp = id_to_mcbsp_ptr(id);
617 if (mcbsp->pdata->buffer_size == 0)
618 return 0;
651 619
652 /* Returns the number of used locations in the buffer */ 620 /* Returns the number of used locations in the buffer */
653 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT); 621 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
@@ -683,46 +651,6 @@ int omap_mcbsp_get_dma_op_mode(unsigned int id)
683} 651}
684EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode); 652EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
685 653
686static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
687{
688 struct omap_device *od;
689
690 od = find_omap_device_by_dev(mcbsp->dev);
691 /*
692 * Enable wakup behavior, smart idle and all wakeups
693 * REVISIT: some wakeups may be unnecessary
694 */
695 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
696 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
697 }
698}
699
700static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
701{
702 struct omap_device *od;
703
704 od = find_omap_device_by_dev(mcbsp->dev);
705
706 /*
707 * Disable wakup behavior, smart idle and all wakeups
708 */
709 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
710 /*
711 * HW bug workaround - If no_idle mode is taken, we need to
712 * go to smart_idle before going to always_idle, or the
713 * device will not hit retention anymore.
714 */
715
716 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
717 }
718}
719#else
720static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
721static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
722static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
723static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
724#endif
725
726int omap_mcbsp_request(unsigned int id) 654int omap_mcbsp_request(unsigned int id)
727{ 655{
728 struct omap_mcbsp *mcbsp; 656 struct omap_mcbsp *mcbsp;
@@ -735,7 +663,7 @@ int omap_mcbsp_request(unsigned int id)
735 } 663 }
736 mcbsp = id_to_mcbsp_ptr(id); 664 mcbsp = id_to_mcbsp_ptr(id);
737 665
738 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL); 666 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
739 if (!reg_cache) { 667 if (!reg_cache) {
740 return -ENOMEM; 668 return -ENOMEM;
741 } 669 }
@@ -757,8 +685,9 @@ int omap_mcbsp_request(unsigned int id)
757 685
758 pm_runtime_get_sync(mcbsp->dev); 686 pm_runtime_get_sync(mcbsp->dev);
759 687
760 /* Do procedure specific to omap34xx arch, if applicable */ 688 /* Enable wakeup behavior */
761 omap34xx_mcbsp_request(mcbsp); 689 if (mcbsp->pdata->has_wakeup)
690 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
762 691
763 /* 692 /*
764 * Make sure that transmitter, receiver and sample-rate generator are 693 * Make sure that transmitter, receiver and sample-rate generator are
@@ -795,8 +724,9 @@ err_clk_disable:
795 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) 724 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
796 mcbsp->pdata->ops->free(id); 725 mcbsp->pdata->ops->free(id);
797 726
798 /* Do procedure specific to omap34xx arch, if applicable */ 727 /* Disable wakeup behavior */
799 omap34xx_mcbsp_free(mcbsp); 728 if (mcbsp->pdata->has_wakeup)
729 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
800 730
801 pm_runtime_put_sync(mcbsp->dev); 731 pm_runtime_put_sync(mcbsp->dev);
802 732
@@ -825,8 +755,9 @@ void omap_mcbsp_free(unsigned int id)
825 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) 755 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
826 mcbsp->pdata->ops->free(id); 756 mcbsp->pdata->ops->free(id);
827 757
828 /* Do procedure specific to omap34xx arch, if applicable */ 758 /* Disable wakeup behavior */
829 omap34xx_mcbsp_free(mcbsp); 759 if (mcbsp->pdata->has_wakeup)
760 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
830 761
831 pm_runtime_put_sync(mcbsp->dev); 762 pm_runtime_put_sync(mcbsp->dev);
832 763
@@ -866,7 +797,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
866 } 797 }
867 mcbsp = id_to_mcbsp_ptr(id); 798 mcbsp = id_to_mcbsp_ptr(id);
868 799
869 if (cpu_is_omap34xx()) 800 if (mcbsp->st_data)
870 omap_st_start(mcbsp); 801 omap_st_start(mcbsp);
871 802
872 /* Only enable SRG, if McBSP is master */ 803 /* Only enable SRG, if McBSP is master */
@@ -904,7 +835,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
904 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); 835 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
905 } 836 }
906 837
907 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 838 if (mcbsp->pdata->has_ccr) {
908 /* Release the transmitter and receiver */ 839 /* Release the transmitter and receiver */
909 w = MCBSP_READ_CACHE(mcbsp, XCCR); 840 w = MCBSP_READ_CACHE(mcbsp, XCCR);
910 w &= ~(tx ? XDISABLE : 0); 841 w &= ~(tx ? XDISABLE : 0);
@@ -934,7 +865,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
934 865
935 /* Reset transmitter */ 866 /* Reset transmitter */
936 tx &= 1; 867 tx &= 1;
937 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 868 if (mcbsp->pdata->has_ccr) {
938 w = MCBSP_READ_CACHE(mcbsp, XCCR); 869 w = MCBSP_READ_CACHE(mcbsp, XCCR);
939 w |= (tx ? XDISABLE : 0); 870 w |= (tx ? XDISABLE : 0);
940 MCBSP_WRITE(mcbsp, XCCR, w); 871 MCBSP_WRITE(mcbsp, XCCR, w);
@@ -944,7 +875,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
944 875
945 /* Reset receiver */ 876 /* Reset receiver */
946 rx &= 1; 877 rx &= 1;
947 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 878 if (mcbsp->pdata->has_ccr) {
948 w = MCBSP_READ_CACHE(mcbsp, RCCR); 879 w = MCBSP_READ_CACHE(mcbsp, RCCR);
949 w |= (rx ? RDISABLE : 0); 880 w |= (rx ? RDISABLE : 0);
950 MCBSP_WRITE(mcbsp, RCCR, w); 881 MCBSP_WRITE(mcbsp, RCCR, w);
@@ -961,39 +892,72 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
961 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); 892 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
962 } 893 }
963 894
964 if (cpu_is_omap34xx()) 895 if (mcbsp->st_data)
965 omap_st_stop(mcbsp); 896 omap_st_stop(mcbsp);
966} 897}
967EXPORT_SYMBOL(omap_mcbsp_stop); 898EXPORT_SYMBOL(omap_mcbsp_stop);
968 899
969/*
970 * The following functions are only required on an OMAP1-only build.
971 * mach-omap2/mcbsp.c contains the real functions
972 */
973#ifndef CONFIG_ARCH_OMAP2PLUS
974int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) 900int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
975{ 901{
976 WARN(1, "%s: should never be called on an OMAP1-only kernel\n", 902 struct omap_mcbsp *mcbsp;
977 __func__); 903 const char *src;
978 return -EINVAL; 904
905 if (!omap_mcbsp_check_valid_id(id)) {
906 pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
907 return -EINVAL;
908 }
909 mcbsp = id_to_mcbsp_ptr(id);
910
911 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
912 src = "clks_ext";
913 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
914 src = "clks_fclk";
915 else
916 return -EINVAL;
917
918 if (mcbsp->pdata->set_clk_src)
919 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
920 else
921 return -EINVAL;
979} 922}
923EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
980 924
981void omap2_mcbsp1_mux_clkr_src(u8 mux) 925void omap2_mcbsp1_mux_clkr_src(u8 mux)
982{ 926{
983 WARN(1, "%s: should never be called on an OMAP1-only kernel\n", 927 struct omap_mcbsp *mcbsp;
984 __func__); 928 const char *src;
985 return; 929
930 if (mux == CLKR_SRC_CLKR)
931 src = "clkr";
932 else if (mux == CLKR_SRC_CLKX)
933 src = "clkx";
934 else
935 return;
936
937 mcbsp = id_to_mcbsp_ptr(0);
938 if (mcbsp->pdata->mux_signal)
939 mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src);
986} 940}
941EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
987 942
988void omap2_mcbsp1_mux_fsr_src(u8 mux) 943void omap2_mcbsp1_mux_fsr_src(u8 mux)
989{ 944{
990 WARN(1, "%s: should never be called on an OMAP1-only kernel\n", 945 struct omap_mcbsp *mcbsp;
991 __func__); 946 const char *src;
992 return; 947
948 if (mux == FSR_SRC_FSR)
949 src = "fsr";
950 else if (mux == FSR_SRC_FSX)
951 src = "fsx";
952 else
953 return;
954
955 mcbsp = id_to_mcbsp_ptr(0);
956 if (mcbsp->pdata->mux_signal)
957 mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src);
993} 958}
994#endif 959EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
995 960
996#ifdef CONFIG_ARCH_OMAP3
997#define max_thres(m) (mcbsp->pdata->buffer_size) 961#define max_thres(m) (mcbsp->pdata->buffer_size)
998#define valid_threshold(m, val) ((val) <= max_thres(m)) 962#define valid_threshold(m, val) ((val) <= max_thres(m))
999#define THRESHOLD_PROP_BUILDER(prop) \ 963#define THRESHOLD_PROP_BUILDER(prop) \
@@ -1084,6 +1048,17 @@ unlock:
1084 1048
1085static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store); 1049static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1086 1050
1051static const struct attribute *additional_attrs[] = {
1052 &dev_attr_max_tx_thres.attr,
1053 &dev_attr_max_rx_thres.attr,
1054 &dev_attr_dma_op_mode.attr,
1055 NULL,
1056};
1057
1058static const struct attribute_group additional_attr_group = {
1059 .attrs = (struct attribute **)additional_attrs,
1060};
1061
1087static ssize_t st_taps_show(struct device *dev, 1062static ssize_t st_taps_show(struct device *dev,
1088 struct device_attribute *attr, char *buf) 1063 struct device_attribute *attr, char *buf)
1089{ 1064{
@@ -1142,27 +1117,6 @@ out:
1142 1117
1143static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store); 1118static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1144 1119
1145static const struct attribute *additional_attrs[] = {
1146 &dev_attr_max_tx_thres.attr,
1147 &dev_attr_max_rx_thres.attr,
1148 &dev_attr_dma_op_mode.attr,
1149 NULL,
1150};
1151
1152static const struct attribute_group additional_attr_group = {
1153 .attrs = (struct attribute **)additional_attrs,
1154};
1155
1156static inline int __devinit omap_additional_add(struct device *dev)
1157{
1158 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1159}
1160
1161static inline void __devexit omap_additional_remove(struct device *dev)
1162{
1163 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1164}
1165
1166static const struct attribute *sidetone_attrs[] = { 1120static const struct attribute *sidetone_attrs[] = {
1167 &dev_attr_st_taps.attr, 1121 &dev_attr_st_taps.attr,
1168 NULL, 1122 NULL,
@@ -1172,10 +1126,9 @@ static const struct attribute_group sidetone_attr_group = {
1172 .attrs = (struct attribute **)sidetone_attrs, 1126 .attrs = (struct attribute **)sidetone_attrs,
1173}; 1127};
1174 1128
1175static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) 1129static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
1130 struct resource *res)
1176{ 1131{
1177 struct platform_device *pdev;
1178 struct resource *res;
1179 struct omap_mcbsp_st_data *st_data; 1132 struct omap_mcbsp_st_data *st_data;
1180 int err; 1133 int err;
1181 1134
@@ -1185,9 +1138,6 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1185 goto err1; 1138 goto err1;
1186 } 1139 }
1187 1140
1188 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1189
1190 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1191 st_data->io_base_st = ioremap(res->start, resource_size(res)); 1141 st_data->io_base_st = ioremap(res->start, resource_size(res));
1192 if (!st_data->io_base_st) { 1142 if (!st_data->io_base_st) {
1193 err = -ENOMEM; 1143 err = -ENOMEM;
@@ -1214,59 +1164,10 @@ static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1214{ 1164{
1215 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 1165 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1216 1166
1217 if (st_data) { 1167 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1218 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group); 1168 iounmap(st_data->io_base_st);
1219 iounmap(st_data->io_base_st); 1169 kfree(st_data);
1220 kfree(st_data);
1221 }
1222}
1223
1224static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1225{
1226 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1227 if (cpu_is_omap34xx()) {
1228 /*
1229 * Initially configure the maximum thresholds to a safe value.
1230 * The McBSP FIFO usage with these values should not go under
1231 * 16 locations.
1232 * If the whole FIFO without safety buffer is used, than there
1233 * is a possibility that the DMA will be not able to push the
1234 * new data on time, causing channel shifts in runtime.
1235 */
1236 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1237 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1238 /*
1239 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1240 * for mcbsp2 instances.
1241 */
1242 if (omap_additional_add(mcbsp->dev))
1243 dev_warn(mcbsp->dev,
1244 "Unable to create additional controls\n");
1245
1246 if (mcbsp->id == 2 || mcbsp->id == 3)
1247 if (omap_st_add(mcbsp))
1248 dev_warn(mcbsp->dev,
1249 "Unable to create sidetone controls\n");
1250
1251 } else {
1252 mcbsp->max_tx_thres = -EINVAL;
1253 mcbsp->max_rx_thres = -EINVAL;
1254 }
1255}
1256
1257static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1258{
1259 if (cpu_is_omap34xx()) {
1260 omap_additional_remove(mcbsp->dev);
1261
1262 if (mcbsp->id == 2 || mcbsp->id == 3)
1263 omap_st_remove(mcbsp);
1264 }
1265} 1170}
1266#else
1267static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1268static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1269#endif /* CONFIG_ARCH_OMAP3 */
1270 1171
1271/* 1172/*
1272 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 1173 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
@@ -1316,7 +1217,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1316 } 1217 }
1317 } 1218 }
1318 mcbsp->phys_base = res->start; 1219 mcbsp->phys_base = res->start;
1319 omap_mcbsp_cache_size = resource_size(res); 1220 mcbsp->reg_cache_size = resource_size(res);
1320 mcbsp->io_base = ioremap(res->start, resource_size(res)); 1221 mcbsp->io_base = ioremap(res->start, resource_size(res));
1321 if (!mcbsp->io_base) { 1222 if (!mcbsp->io_base) {
1322 ret = -ENOMEM; 1223 ret = -ENOMEM;
@@ -1364,15 +1265,52 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1364 mcbsp->pdata = pdata; 1265 mcbsp->pdata = pdata;
1365 mcbsp->dev = &pdev->dev; 1266 mcbsp->dev = &pdev->dev;
1366 mcbsp_ptr[id] = mcbsp; 1267 mcbsp_ptr[id] = mcbsp;
1367 mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
1368 platform_set_drvdata(pdev, mcbsp); 1268 platform_set_drvdata(pdev, mcbsp);
1369 pm_runtime_enable(mcbsp->dev); 1269 pm_runtime_enable(mcbsp->dev);
1370 1270
1371 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */ 1271 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1372 omap34xx_device_init(mcbsp); 1272 if (mcbsp->pdata->buffer_size) {
1273 /*
1274 * Initially configure the maximum thresholds to a safe value.
1275 * The McBSP FIFO usage with these values should not go under
1276 * 16 locations.
1277 * If the whole FIFO without safety buffer is used, than there
1278 * is a possibility that the DMA will be not able to push the
1279 * new data on time, causing channel shifts in runtime.
1280 */
1281 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1282 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1283
1284 ret = sysfs_create_group(&mcbsp->dev->kobj,
1285 &additional_attr_group);
1286 if (ret) {
1287 dev_err(mcbsp->dev,
1288 "Unable to create additional controls\n");
1289 goto err_thres;
1290 }
1291 } else {
1292 mcbsp->max_tx_thres = -EINVAL;
1293 mcbsp->max_rx_thres = -EINVAL;
1294 }
1295
1296 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1297 if (res) {
1298 ret = omap_st_add(mcbsp, res);
1299 if (ret) {
1300 dev_err(mcbsp->dev,
1301 "Unable to create sidetone controls\n");
1302 goto err_st;
1303 }
1304 }
1373 1305
1374 return 0; 1306 return 0;
1375 1307
1308err_st:
1309 if (mcbsp->pdata->buffer_size)
1310 sysfs_remove_group(&mcbsp->dev->kobj,
1311 &additional_attr_group);
1312err_thres:
1313 clk_put(mcbsp->fclk);
1376err_res: 1314err_res:
1377 iounmap(mcbsp->io_base); 1315 iounmap(mcbsp->io_base);
1378err_ioremap: 1316err_ioremap:
@@ -1392,7 +1330,12 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1392 mcbsp->pdata->ops->free) 1330 mcbsp->pdata->ops->free)
1393 mcbsp->pdata->ops->free(mcbsp->id); 1331 mcbsp->pdata->ops->free(mcbsp->id);
1394 1332
1395 omap34xx_device_exit(mcbsp); 1333 if (mcbsp->pdata->buffer_size)
1334 sysfs_remove_group(&mcbsp->dev->kobj,
1335 &additional_attr_group);
1336
1337 if (mcbsp->st_data)
1338 omap_st_remove(mcbsp);
1396 1339
1397 clk_put(mcbsp->fclk); 1340 clk_put(mcbsp->fclk);
1398 1341
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 02609eee0562..26aee5cc1fc1 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -94,6 +94,9 @@
94#define USE_WAKEUP_LAT 0 94#define USE_WAKEUP_LAT 0
95#define IGNORE_WAKEUP_LAT 1 95#define IGNORE_WAKEUP_LAT 1
96 96
97static int omap_device_register(struct platform_device *pdev);
98static int omap_early_device_register(struct platform_device *pdev);
99
97/* Private functions */ 100/* Private functions */
98 101
99/** 102/**
@@ -114,7 +117,7 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
114{ 117{
115 struct timespec a, b, c; 118 struct timespec a, b, c;
116 119
117 pr_debug("omap_device: %s: activating\n", od->pdev.name); 120 dev_dbg(&od->pdev->dev, "omap_device: activating\n");
118 121
119 while (od->pm_lat_level > 0) { 122 while (od->pm_lat_level > 0) {
120 struct omap_device_pm_latency *odpl; 123 struct omap_device_pm_latency *odpl;
@@ -138,25 +141,24 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
138 c = timespec_sub(b, a); 141 c = timespec_sub(b, a);
139 act_lat = timespec_to_ns(&c); 142 act_lat = timespec_to_ns(&c);
140 143
141 pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time " 144 dev_dbg(&od->pdev->dev,
142 "%llu nsec\n", od->pdev.name, od->pm_lat_level, 145 "omap_device: pm_lat %d: activate: elapsed time "
143 act_lat); 146 "%llu nsec\n", od->pm_lat_level, act_lat);
144 147
145 if (act_lat > odpl->activate_lat) { 148 if (act_lat > odpl->activate_lat) {
146 odpl->activate_lat_worst = act_lat; 149 odpl->activate_lat_worst = act_lat;
147 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { 150 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
148 odpl->activate_lat = act_lat; 151 odpl->activate_lat = act_lat;
149 pr_warning("omap_device: %s.%d: new worst case " 152 dev_dbg(&od->pdev->dev,
150 "activate latency %d: %llu\n", 153 "new worst case activate latency "
151 od->pdev.name, od->pdev.id, 154 "%d: %llu\n",
152 od->pm_lat_level, act_lat); 155 od->pm_lat_level, act_lat);
153 } else 156 } else
154 pr_warning("omap_device: %s.%d: activate " 157 dev_warn(&od->pdev->dev,
155 "latency %d higher than exptected. " 158 "activate latency %d "
156 "(%llu > %d)\n", 159 "higher than exptected. (%llu > %d)\n",
157 od->pdev.name, od->pdev.id, 160 od->pm_lat_level, act_lat,
158 od->pm_lat_level, act_lat, 161 odpl->activate_lat);
159 odpl->activate_lat);
160 } 162 }
161 163
162 od->dev_wakeup_lat -= odpl->activate_lat; 164 od->dev_wakeup_lat -= odpl->activate_lat;
@@ -183,7 +185,7 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
183{ 185{
184 struct timespec a, b, c; 186 struct timespec a, b, c;
185 187
186 pr_debug("omap_device: %s: deactivating\n", od->pdev.name); 188 dev_dbg(&od->pdev->dev, "omap_device: deactivating\n");
187 189
188 while (od->pm_lat_level < od->pm_lats_cnt) { 190 while (od->pm_lat_level < od->pm_lats_cnt) {
189 struct omap_device_pm_latency *odpl; 191 struct omap_device_pm_latency *odpl;
@@ -206,28 +208,26 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
206 c = timespec_sub(b, a); 208 c = timespec_sub(b, a);
207 deact_lat = timespec_to_ns(&c); 209 deact_lat = timespec_to_ns(&c);
208 210
209 pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time " 211 dev_dbg(&od->pdev->dev,
210 "%llu nsec\n", od->pdev.name, od->pm_lat_level, 212 "omap_device: pm_lat %d: deactivate: elapsed time "
211 deact_lat); 213 "%llu nsec\n", od->pm_lat_level, deact_lat);
212 214
213 if (deact_lat > odpl->deactivate_lat) { 215 if (deact_lat > odpl->deactivate_lat) {
214 odpl->deactivate_lat_worst = deact_lat; 216 odpl->deactivate_lat_worst = deact_lat;
215 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { 217 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
216 odpl->deactivate_lat = deact_lat; 218 odpl->deactivate_lat = deact_lat;
217 pr_warning("omap_device: %s.%d: new worst case " 219 dev_dbg(&od->pdev->dev,
218 "deactivate latency %d: %llu\n", 220 "new worst case deactivate latency "
219 od->pdev.name, od->pdev.id, 221 "%d: %llu\n",
220 od->pm_lat_level, deact_lat); 222 od->pm_lat_level, deact_lat);
221 } else 223 } else
222 pr_warning("omap_device: %s.%d: deactivate " 224 dev_warn(&od->pdev->dev,
223 "latency %d higher than exptected. " 225 "deactivate latency %d "
224 "(%llu > %d)\n", 226 "higher than exptected. (%llu > %d)\n",
225 od->pdev.name, od->pdev.id, 227 od->pm_lat_level, deact_lat,
226 od->pm_lat_level, deact_lat, 228 odpl->deactivate_lat);
227 odpl->deactivate_lat);
228 } 229 }
229 230
230
231 od->dev_wakeup_lat += odpl->activate_lat; 231 od->dev_wakeup_lat += odpl->activate_lat;
232 232
233 od->pm_lat_level++; 233 od->pm_lat_level++;
@@ -245,28 +245,27 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
245 if (!clk_alias || !clk_name) 245 if (!clk_alias || !clk_name)
246 return; 246 return;
247 247
248 pr_debug("omap_device: %s: Creating %s -> %s\n", 248 dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);
249 dev_name(&od->pdev.dev), clk_alias, clk_name);
250 249
251 r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias); 250 r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
252 if (!IS_ERR(r)) { 251 if (!IS_ERR(r)) {
253 pr_warning("omap_device: %s: alias %s already exists\n", 252 dev_warn(&od->pdev->dev,
254 dev_name(&od->pdev.dev), clk_alias); 253 "alias %s already exists\n", clk_alias);
255 clk_put(r); 254 clk_put(r);
256 return; 255 return;
257 } 256 }
258 257
259 r = omap_clk_get_by_name(clk_name); 258 r = omap_clk_get_by_name(clk_name);
260 if (IS_ERR(r)) { 259 if (IS_ERR(r)) {
261 pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n", 260 dev_err(&od->pdev->dev,
262 dev_name(&od->pdev.dev), clk_name); 261 "omap_clk_get_by_name for %s failed\n", clk_name);
263 return; 262 return;
264 } 263 }
265 264
266 l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev)); 265 l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev->dev));
267 if (!l) { 266 if (!l) {
268 pr_err("omap_device: %s: clkdev_alloc for %s failed\n", 267 dev_err(&od->pdev->dev,
269 dev_name(&od->pdev.dev), clk_alias); 268 "clkdev_alloc for %s failed\n", clk_alias);
270 return; 269 return;
271 } 270 }
272 271
@@ -343,7 +342,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
343 * much memory to allocate before calling 342 * much memory to allocate before calling
344 * omap_device_fill_resources(). Returns the count. 343 * omap_device_fill_resources(). Returns the count.
345 */ 344 */
346int omap_device_count_resources(struct omap_device *od) 345static int omap_device_count_resources(struct omap_device *od)
347{ 346{
348 int c = 0; 347 int c = 0;
349 int i; 348 int i;
@@ -352,7 +351,7 @@ int omap_device_count_resources(struct omap_device *od)
352 c += omap_hwmod_count_resources(od->hwmods[i]); 351 c += omap_hwmod_count_resources(od->hwmods[i]);
353 352
354 pr_debug("omap_device: %s: counted %d total resources across %d " 353 pr_debug("omap_device: %s: counted %d total resources across %d "
355 "hwmods\n", od->pdev.name, c, od->hwmods_cnt); 354 "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
356 355
357 return c; 356 return c;
358} 357}
@@ -374,7 +373,8 @@ int omap_device_count_resources(struct omap_device *od)
374 * functions to get device resources. Hacking around the existing 373 * functions to get device resources. Hacking around the existing
375 * platform_device code wastes memory. Returns 0. 374 * platform_device code wastes memory. Returns 0.
376 */ 375 */
377int omap_device_fill_resources(struct omap_device *od, struct resource *res) 376static int omap_device_fill_resources(struct omap_device *od,
377 struct resource *res)
378{ 378{
379 int c = 0; 379 int c = 0;
380 int i, r; 380 int i, r;
@@ -405,7 +405,7 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res)
405 * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise, 405 * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
406 * passes along the return value of omap_device_build_ss(). 406 * passes along the return value of omap_device_build_ss().
407 */ 407 */
408struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, 408struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
409 struct omap_hwmod *oh, void *pdata, 409 struct omap_hwmod *oh, void *pdata,
410 int pdata_len, 410 int pdata_len,
411 struct omap_device_pm_latency *pm_lats, 411 struct omap_device_pm_latency *pm_lats,
@@ -438,15 +438,15 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
438 * platform_device record. Returns an ERR_PTR() on error, or passes 438 * platform_device record. Returns an ERR_PTR() on error, or passes
439 * along the return value of omap_device_register(). 439 * along the return value of omap_device_register().
440 */ 440 */
441struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, 441struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
442 struct omap_hwmod **ohs, int oh_cnt, 442 struct omap_hwmod **ohs, int oh_cnt,
443 void *pdata, int pdata_len, 443 void *pdata, int pdata_len,
444 struct omap_device_pm_latency *pm_lats, 444 struct omap_device_pm_latency *pm_lats,
445 int pm_lats_cnt, int is_early_device) 445 int pm_lats_cnt, int is_early_device)
446{ 446{
447 int ret = -ENOMEM; 447 int ret = -ENOMEM;
448 struct platform_device *pdev;
448 struct omap_device *od; 449 struct omap_device *od;
449 char *pdev_name2;
450 struct resource *res = NULL; 450 struct resource *res = NULL;
451 int i, res_count; 451 int i, res_count;
452 struct omap_hwmod **hwmods; 452 struct omap_hwmod **hwmods;
@@ -457,72 +457,76 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
457 if (!pdata && pdata_len > 0) 457 if (!pdata && pdata_len > 0)
458 return ERR_PTR(-EINVAL); 458 return ERR_PTR(-EINVAL);
459 459
460 pdev = platform_device_alloc(pdev_name, pdev_id);
461 if (!pdev) {
462 ret = -ENOMEM;
463 goto odbs_exit;
464 }
465
460 pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name, 466 pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name,
461 oh_cnt); 467 oh_cnt);
462 468
463 od = kzalloc(sizeof(struct omap_device), GFP_KERNEL); 469 od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
464 if (!od) 470 if (!od) {
465 return ERR_PTR(-ENOMEM); 471 ret = -ENOMEM;
466 472 goto odbs_exit1;
473 }
467 od->hwmods_cnt = oh_cnt; 474 od->hwmods_cnt = oh_cnt;
468 475
469 hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, 476 hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt,
470 GFP_KERNEL); 477 GFP_KERNEL);
471 if (!hwmods) 478 if (!hwmods)
472 goto odbs_exit1; 479 goto odbs_exit2;
473 480
474 memcpy(hwmods, ohs, sizeof(struct omap_hwmod *) * oh_cnt); 481 memcpy(hwmods, ohs, sizeof(struct omap_hwmod *) * oh_cnt);
475 od->hwmods = hwmods; 482 od->hwmods = hwmods;
476 483 od->pdev = pdev;
477 pdev_name2 = kzalloc(strlen(pdev_name) + 1, GFP_KERNEL);
478 if (!pdev_name2)
479 goto odbs_exit2;
480 strcpy(pdev_name2, pdev_name);
481
482 od->pdev.name = pdev_name2;
483 od->pdev.id = pdev_id;
484 484
485 res_count = omap_device_count_resources(od); 485 res_count = omap_device_count_resources(od);
486 if (res_count > 0) { 486 if (res_count > 0) {
487 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL); 487 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
488 if (!res) 488 if (!res)
489 goto odbs_exit3; 489 goto odbs_exit3;
490 }
491 omap_device_fill_resources(od, res);
492 490
493 od->pdev.num_resources = res_count; 491 omap_device_fill_resources(od, res);
494 od->pdev.resource = res; 492
493 ret = platform_device_add_resources(pdev, res, res_count);
494 kfree(res);
495 495
496 ret = platform_device_add_data(&od->pdev, pdata, pdata_len); 496 if (ret)
497 goto odbs_exit3;
498 }
499
500 ret = platform_device_add_data(pdev, pdata, pdata_len);
497 if (ret) 501 if (ret)
498 goto odbs_exit4; 502 goto odbs_exit3;
499 503
500 od->pm_lats = pm_lats; 504 pdev->archdata.od = od;
501 od->pm_lats_cnt = pm_lats_cnt;
502 505
503 if (is_early_device) 506 if (is_early_device)
504 ret = omap_early_device_register(od); 507 ret = omap_early_device_register(pdev);
505 else 508 else
506 ret = omap_device_register(od); 509 ret = omap_device_register(pdev);
510 if (ret)
511 goto odbs_exit3;
512
513 od->pm_lats = pm_lats;
514 od->pm_lats_cnt = pm_lats_cnt;
507 515
508 for (i = 0; i < oh_cnt; i++) { 516 for (i = 0; i < oh_cnt; i++) {
509 hwmods[i]->od = od; 517 hwmods[i]->od = od;
510 _add_hwmod_clocks_clkdev(od, hwmods[i]); 518 _add_hwmod_clocks_clkdev(od, hwmods[i]);
511 } 519 }
512 520
513 if (ret) 521 return pdev;
514 goto odbs_exit4;
515
516 return od;
517 522
518odbs_exit4:
519 kfree(res);
520odbs_exit3: 523odbs_exit3:
521 kfree(pdev_name2);
522odbs_exit2:
523 kfree(hwmods); 524 kfree(hwmods);
524odbs_exit1: 525odbs_exit2:
525 kfree(od); 526 kfree(od);
527odbs_exit1:
528 platform_device_put(pdev);
529odbs_exit:
526 530
527 pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret); 531 pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
528 532
@@ -538,11 +542,11 @@ odbs_exit1:
538 * platform_early_add_device() on the underlying platform_device. 542 * platform_early_add_device() on the underlying platform_device.
539 * Returns 0 by default. 543 * Returns 0 by default.
540 */ 544 */
541int omap_early_device_register(struct omap_device *od) 545static int omap_early_device_register(struct platform_device *pdev)
542{ 546{
543 struct platform_device *devices[1]; 547 struct platform_device *devices[1];
544 548
545 devices[0] = &(od->pdev); 549 devices[0] = pdev;
546 early_platform_add_devices(devices, 1); 550 early_platform_add_devices(devices, 1);
547 return 0; 551 return 0;
548} 552}
@@ -638,13 +642,13 @@ static struct dev_pm_domain omap_device_pm_domain = {
638 * platform_device_register() on the underlying platform_device. 642 * platform_device_register() on the underlying platform_device.
639 * Returns the return value of platform_device_register(). 643 * Returns the return value of platform_device_register().
640 */ 644 */
641int omap_device_register(struct omap_device *od) 645static int omap_device_register(struct platform_device *pdev)
642{ 646{
643 pr_debug("omap_device: %s: registering\n", od->pdev.name); 647 pr_debug("omap_device: %s: registering\n", pdev->name);
644 648
645 od->pdev.dev.parent = &omap_device_parent; 649 pdev->dev.parent = &omap_device_parent;
646 od->pdev.dev.pm_domain = &omap_device_pm_domain; 650 pdev->dev.pm_domain = &omap_device_pm_domain;
647 return platform_device_register(&od->pdev); 651 return platform_device_add(pdev);
648} 652}
649 653
650 654
@@ -671,8 +675,9 @@ int omap_device_enable(struct platform_device *pdev)
671 od = to_omap_device(pdev); 675 od = to_omap_device(pdev);
672 676
673 if (od->_state == OMAP_DEVICE_STATE_ENABLED) { 677 if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
674 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", 678 dev_warn(&pdev->dev,
675 od->pdev.name, od->pdev.id, __func__, od->_state); 679 "omap_device: %s() called from invalid state %d\n",
680 __func__, od->_state);
676 return -EINVAL; 681 return -EINVAL;
677 } 682 }
678 683
@@ -710,8 +715,9 @@ int omap_device_idle(struct platform_device *pdev)
710 od = to_omap_device(pdev); 715 od = to_omap_device(pdev);
711 716
712 if (od->_state != OMAP_DEVICE_STATE_ENABLED) { 717 if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
713 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", 718 dev_warn(&pdev->dev,
714 od->pdev.name, od->pdev.id, __func__, od->_state); 719 "omap_device: %s() called from invalid state %d\n",
720 __func__, od->_state);
715 return -EINVAL; 721 return -EINVAL;
716 } 722 }
717 723
@@ -742,8 +748,9 @@ int omap_device_shutdown(struct platform_device *pdev)
742 748
743 if (od->_state != OMAP_DEVICE_STATE_ENABLED && 749 if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
744 od->_state != OMAP_DEVICE_STATE_IDLE) { 750 od->_state != OMAP_DEVICE_STATE_IDLE) {
745 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", 751 dev_warn(&pdev->dev,
746 od->pdev.name, od->pdev.id, __func__, od->_state); 752 "omap_device: %s() called from invalid state %d\n",
753 __func__, od->_state);
747 return -EINVAL; 754 return -EINVAL;
748 } 755 }
749 756
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 09:29:58 -0400