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-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/dma.c59
-rw-r--r--arch/arm/plat-omap/include/plat/board.h38
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h20
-rw-r--r--arch/arm/plat-omap/include/plat/dsp.h3
-rw-r--r--arch/arm/plat-omap/include/plat/mux.h2
-rw-r--r--arch/arm/plat-omap/include/plat/omap730.h102
-rw-r--r--arch/arm/plat-omap/include/plat/omap850.h102
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h2
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h4
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h6
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h196
-rw-r--r--arch/arm/plat-omap/mailbox.c13
-rw-r--r--arch/arm/plat-omap/usb.c145
15 files changed, 58 insertions, 638 deletions
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index ed8605f01155..6d87532871cd 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
7 usb.o fb.o counter_32k.o 7 fb.o counter_32k.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index cb16ade437cb..7fe626761e53 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -573,22 +573,25 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
573 573
574static inline void omap_enable_channel_irq(int lch) 574static inline void omap_enable_channel_irq(int lch)
575{ 575{
576 u32 status;
577
578 /* Clear CSR */ 576 /* Clear CSR */
579 if (cpu_class_is_omap1()) 577 if (cpu_class_is_omap1())
580 status = p->dma_read(CSR, lch); 578 p->dma_read(CSR, lch);
581 else if (cpu_class_is_omap2()) 579 else
582 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); 580 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
583 581
584 /* Enable some nice interrupts. */ 582 /* Enable some nice interrupts. */
585 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); 583 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
586} 584}
587 585
588static void omap_disable_channel_irq(int lch) 586static inline void omap_disable_channel_irq(int lch)
589{ 587{
590 if (cpu_class_is_omap2()) 588 /* disable channel interrupts */
591 p->dma_write(0, CICR, lch); 589 p->dma_write(0, CICR, lch);
590 /* Clear CSR */
591 if (cpu_class_is_omap1())
592 p->dma_read(CSR, lch);
593 else
594 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
592} 595}
593 596
594void omap_enable_dma_irq(int lch, u16 bits) 597void omap_enable_dma_irq(int lch, u16 bits)
@@ -632,14 +635,14 @@ static inline void disable_lnk(int lch)
632 l = p->dma_read(CLNK_CTRL, lch); 635 l = p->dma_read(CLNK_CTRL, lch);
633 636
634 /* Disable interrupts */ 637 /* Disable interrupts */
638 omap_disable_channel_irq(lch);
639
635 if (cpu_class_is_omap1()) { 640 if (cpu_class_is_omap1()) {
636 p->dma_write(0, CICR, lch);
637 /* Set the STOP_LNK bit */ 641 /* Set the STOP_LNK bit */
638 l |= 1 << 14; 642 l |= 1 << 14;
639 } 643 }
640 644
641 if (cpu_class_is_omap2()) { 645 if (cpu_class_is_omap2()) {
642 omap_disable_channel_irq(lch);
643 /* Clear the ENABLE_LNK bit */ 646 /* Clear the ENABLE_LNK bit */
644 l &= ~(1 << 15); 647 l &= ~(1 << 15);
645 } 648 }
@@ -657,6 +660,9 @@ static inline void omap2_enable_irq_lch(int lch)
657 return; 660 return;
658 661
659 spin_lock_irqsave(&dma_chan_lock, flags); 662 spin_lock_irqsave(&dma_chan_lock, flags);
663 /* clear IRQ STATUS */
664 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
665 /* Enable interrupt */
660 val = p->dma_read(IRQENABLE_L0, lch); 666 val = p->dma_read(IRQENABLE_L0, lch);
661 val |= 1 << lch; 667 val |= 1 << lch;
662 p->dma_write(val, IRQENABLE_L0, lch); 668 p->dma_write(val, IRQENABLE_L0, lch);
@@ -672,9 +678,12 @@ static inline void omap2_disable_irq_lch(int lch)
672 return; 678 return;
673 679
674 spin_lock_irqsave(&dma_chan_lock, flags); 680 spin_lock_irqsave(&dma_chan_lock, flags);
681 /* Disable interrupt */
675 val = p->dma_read(IRQENABLE_L0, lch); 682 val = p->dma_read(IRQENABLE_L0, lch);
676 val &= ~(1 << lch); 683 val &= ~(1 << lch);
677 p->dma_write(val, IRQENABLE_L0, lch); 684 p->dma_write(val, IRQENABLE_L0, lch);
685 /* clear IRQ STATUS */
686 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
678 spin_unlock_irqrestore(&dma_chan_lock, flags); 687 spin_unlock_irqrestore(&dma_chan_lock, flags);
679} 688}
680 689
@@ -745,11 +754,8 @@ int omap_request_dma(int dev_id, const char *dev_name,
745 } 754 }
746 755
747 if (cpu_class_is_omap2()) { 756 if (cpu_class_is_omap2()) {
748 omap2_enable_irq_lch(free_ch);
749 omap_enable_channel_irq(free_ch); 757 omap_enable_channel_irq(free_ch);
750 /* Clear the CSR register and IRQ status register */ 758 omap2_enable_irq_lch(free_ch);
751 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
752 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
753 } 759 }
754 760
755 *dma_ch_out = free_ch; 761 *dma_ch_out = free_ch;
@@ -768,27 +774,19 @@ void omap_free_dma(int lch)
768 return; 774 return;
769 } 775 }
770 776
771 if (cpu_class_is_omap1()) { 777 /* Disable interrupt for logical channel */
772 /* Disable all DMA interrupts for the channel. */ 778 if (cpu_class_is_omap2())
773 p->dma_write(0, CICR, lch);
774 /* Make sure the DMA transfer is stopped. */
775 p->dma_write(0, CCR, lch);
776 }
777
778 if (cpu_class_is_omap2()) {
779 omap2_disable_irq_lch(lch); 779 omap2_disable_irq_lch(lch);
780 780
781 /* Clear the CSR register and IRQ status register */ 781 /* Disable all DMA interrupts for the channel. */
782 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); 782 omap_disable_channel_irq(lch);
783 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
784 783
785 /* Disable all DMA interrupts for the channel. */ 784 /* Make sure the DMA transfer is stopped. */
786 p->dma_write(0, CICR, lch); 785 p->dma_write(0, CCR, lch);
787 786
788 /* Make sure the DMA transfer is stopped. */ 787 /* Clear registers */
789 p->dma_write(0, CCR, lch); 788 if (cpu_class_is_omap2())
790 omap_clear_dma(lch); 789 omap_clear_dma(lch);
791 }
792 790
793 spin_lock_irqsave(&dma_chan_lock, flags); 791 spin_lock_irqsave(&dma_chan_lock, flags);
794 dma_chan[lch].dev_id = -1; 792 dma_chan[lch].dev_id = -1;
@@ -943,8 +941,7 @@ void omap_stop_dma(int lch)
943 u32 l; 941 u32 l;
944 942
945 /* Disable all interrupts on the channel */ 943 /* Disable all interrupts on the channel */
946 if (cpu_class_is_omap1()) 944 omap_disable_channel_irq(lch);
947 p->dma_write(0, CICR, lch);
948 945
949 l = p->dma_read(CCR, lch); 946 l = p->dma_read(CCR, lch);
950 if (IS_DMA_ERRATA(DMA_ERRATA_i541) && 947 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 4814c5b65306..e62f20a5c0af 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -57,44 +57,6 @@ struct omap_camera_sensor_config {
57 int (*power_off)(void * data); 57 int (*power_off)(void * data);
58}; 58};
59 59
60struct omap_usb_config {
61 /* Configure drivers according to the connectors on your board:
62 * - "A" connector (rectagular)
63 * ... for host/OHCI use, set "register_host".
64 * - "B" connector (squarish) or "Mini-B"
65 * ... for device/gadget use, set "register_dev".
66 * - "Mini-AB" connector (very similar to Mini-B)
67 * ... for OTG use as device OR host, initialize "otg"
68 */
69 unsigned register_host:1;
70 unsigned register_dev:1;
71 u8 otg; /* port number, 1-based: usb1 == 2 */
72
73 u8 hmc_mode;
74
75 /* implicitly true if otg: host supports remote wakeup? */
76 u8 rwc;
77
78 /* signaling pins used to talk to transceiver on usbN:
79 * 0 == usbN unused
80 * 2 == usb0-only, using internal transceiver
81 * 3 == 3 wire bidirectional
82 * 4 == 4 wire bidirectional
83 * 6 == 6 wire unidirectional (or TLL)
84 */
85 u8 pins[3];
86
87 struct platform_device *udc_device;
88 struct platform_device *ohci_device;
89 struct platform_device *otg_device;
90
91 u32 (*usb0_init)(unsigned nwires, unsigned is_device);
92 u32 (*usb1_init)(unsigned nwires);
93 u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
94
95 int (*ocpi_enable)(void);
96};
97
98struct omap_lcd_config { 60struct omap_lcd_config {
99 char panel_name[16]; 61 char panel_name[16];
100 char ctrl_name[16]; 62 char ctrl_name[16];
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index d0ef57c1d71b..656b9862279e 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -156,7 +156,6 @@ struct dpll_data {
156 u8 min_divider; 156 u8 min_divider;
157 u16 max_divider; 157 u16 max_divider;
158 u8 modes; 158 u8 modes;
159#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
160 void __iomem *autoidle_reg; 159 void __iomem *autoidle_reg;
161 void __iomem *idlest_reg; 160 void __iomem *idlest_reg;
162 u32 autoidle_mask; 161 u32 autoidle_mask;
@@ -167,7 +166,6 @@ struct dpll_data {
167 u8 auto_recal_bit; 166 u8 auto_recal_bit;
168 u8 recal_en_bit; 167 u8 recal_en_bit;
169 u8 recal_st_bit; 168 u8 recal_st_bit;
170# endif
171 u8 flags; 169 u8 flags;
172}; 170};
173 171
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index de6c0a08f461..430081ac0c47 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -238,9 +238,7 @@ IS_AM_SUBCLASS(335x, 0x335)
238/* 238/*
239 * Macros to detect individual cpu types. 239 * Macros to detect individual cpu types.
240 * These are only rarely needed. 240 * These are only rarely needed.
241 * cpu_is_omap330(): True for OMAP330 241 * cpu_is_omap310(): True for OMAP310
242 * cpu_is_omap730(): True for OMAP730
243 * cpu_is_omap850(): True for OMAP850
244 * cpu_is_omap1510(): True for OMAP1510 242 * cpu_is_omap1510(): True for OMAP1510
245 * cpu_is_omap1610(): True for OMAP1610 243 * cpu_is_omap1610(): True for OMAP1610
246 * cpu_is_omap1611(): True for OMAP1611 244 * cpu_is_omap1611(): True for OMAP1611
@@ -262,8 +260,6 @@ static inline int is_omap ##type (void) \
262} 260}
263 261
264IS_OMAP_TYPE(310, 0x0310) 262IS_OMAP_TYPE(310, 0x0310)
265IS_OMAP_TYPE(730, 0x0730)
266IS_OMAP_TYPE(850, 0x0850)
267IS_OMAP_TYPE(1510, 0x1510) 263IS_OMAP_TYPE(1510, 0x1510)
268IS_OMAP_TYPE(1610, 0x1610) 264IS_OMAP_TYPE(1610, 0x1610)
269IS_OMAP_TYPE(1611, 0x1611) 265IS_OMAP_TYPE(1611, 0x1611)
@@ -277,8 +273,6 @@ IS_OMAP_TYPE(2430, 0x2430)
277IS_OMAP_TYPE(3430, 0x3430) 273IS_OMAP_TYPE(3430, 0x3430)
278 274
279#define cpu_is_omap310() 0 275#define cpu_is_omap310() 0
280#define cpu_is_omap730() 0
281#define cpu_is_omap850() 0
282#define cpu_is_omap1510() 0 276#define cpu_is_omap1510() 0
283#define cpu_is_omap1610() 0 277#define cpu_is_omap1610() 0
284#define cpu_is_omap5912() 0 278#define cpu_is_omap5912() 0
@@ -294,19 +288,9 @@ IS_OMAP_TYPE(3430, 0x3430)
294 288
295/* 289/*
296 * Whether we have MULTI_OMAP1 or not, we still need to distinguish 290 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
297 * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710. 291 * between 310 vs. 1510 and 1611B/5912 vs. 1710.
298 */ 292 */
299 293
300#if defined(CONFIG_ARCH_OMAP730)
301# undef cpu_is_omap730
302# define cpu_is_omap730() is_omap730()
303#endif
304
305#if defined(CONFIG_ARCH_OMAP850)
306# undef cpu_is_omap850
307# define cpu_is_omap850() is_omap850()
308#endif
309
310#if defined(CONFIG_ARCH_OMAP15XX) 294#if defined(CONFIG_ARCH_OMAP15XX)
311# undef cpu_is_omap310 295# undef cpu_is_omap310
312# undef cpu_is_omap1510 296# undef cpu_is_omap1510
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h
index 9c604b390f9f..5927709b1908 100644
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ b/arch/arm/plat-omap/include/plat/dsp.h
@@ -18,6 +18,9 @@ struct omap_dsp_platform_data {
18 u32 (*dsp_cm_read)(s16 , u16); 18 u32 (*dsp_cm_read)(s16 , u16);
19 u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16); 19 u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
20 20
21 void (*set_bootaddr)(u32);
22 void (*set_bootmode)(u8);
23
21 phys_addr_t phys_mempool_base; 24 phys_addr_t phys_mempool_base;
22 phys_addr_t phys_mempool_size; 25 phys_addr_t phys_mempool_size;
23}; 26};
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index aeba71796ad9..323948959200 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -99,7 +99,7 @@
99 99
100/* 100/*
101 * OMAP730/850 has a slightly different config for the pin mux. 101 * OMAP730/850 has a slightly different config for the pin mux.
102 * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and 102 * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and
103 * not the FUNC_MUX_CTRL_x regs from hardware.h 103 * not the FUNC_MUX_CTRL_x regs from hardware.h
104 * - for pull-up/down, only has one enable bit which is is in the same register 104 * - for pull-up/down, only has one enable bit which is is in the same register
105 * as mux config 105 * as mux config
diff --git a/arch/arm/plat-omap/include/plat/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h
deleted file mode 100644
index 14272bc1a6fd..000000000000
--- a/arch/arm/plat-omap/include/plat/omap730.h
+++ /dev/null
@@ -1,102 +0,0 @@
1/* arch/arm/plat-omap/include/mach/omap730.h
2 *
3 * Hardware definitions for TI OMAP730 processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP730_H
29#define __ASM_ARCH_OMAP730_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP730_DSP_BASE 0xE0000000
40#define OMAP730_DSP_SIZE 0x50000
41#define OMAP730_DSP_START 0xE0000000
42
43#define OMAP730_DSPREG_BASE 0xE1000000
44#define OMAP730_DSPREG_SIZE SZ_128K
45#define OMAP730_DSPREG_START 0xE1000000
46
47/*
48 * ----------------------------------------------------------------------------
49 * OMAP730 specific configuration registers
50 * ----------------------------------------------------------------------------
51 */
52#define OMAP730_CONFIG_BASE 0xfffe1000
53#define OMAP730_IO_CONF_0 0xfffe1070
54#define OMAP730_IO_CONF_1 0xfffe1074
55#define OMAP730_IO_CONF_2 0xfffe1078
56#define OMAP730_IO_CONF_3 0xfffe107c
57#define OMAP730_IO_CONF_4 0xfffe1080
58#define OMAP730_IO_CONF_5 0xfffe1084
59#define OMAP730_IO_CONF_6 0xfffe1088
60#define OMAP730_IO_CONF_7 0xfffe108c
61#define OMAP730_IO_CONF_8 0xfffe1090
62#define OMAP730_IO_CONF_9 0xfffe1094
63#define OMAP730_IO_CONF_10 0xfffe1098
64#define OMAP730_IO_CONF_11 0xfffe109c
65#define OMAP730_IO_CONF_12 0xfffe10a0
66#define OMAP730_IO_CONF_13 0xfffe10a4
67
68#define OMAP730_MODE_1 0xfffe1010
69#define OMAP730_MODE_2 0xfffe1014
70
71/* CSMI specials: in terms of base + offset */
72#define OMAP730_MODE2_OFFSET 0x14
73
74/*
75 * ----------------------------------------------------------------------------
76 * OMAP730 traffic controller configuration registers
77 * ----------------------------------------------------------------------------
78 */
79#define OMAP730_FLASH_CFG_0 0xfffecc10
80#define OMAP730_FLASH_ACFG_0 0xfffecc50
81#define OMAP730_FLASH_CFG_1 0xfffecc14
82#define OMAP730_FLASH_ACFG_1 0xfffecc54
83
84/*
85 * ----------------------------------------------------------------------------
86 * OMAP730 DSP control registers
87 * ----------------------------------------------------------------------------
88 */
89#define OMAP730_ICR_BASE 0xfffbb800
90#define OMAP730_DSP_M_CTL 0xfffbb804
91#define OMAP730_DSP_MMU_BASE 0xfffed200
92
93/*
94 * ----------------------------------------------------------------------------
95 * OMAP730 PCC_UPLD configuration registers
96 * ----------------------------------------------------------------------------
97 */
98#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900)
99#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
100
101#endif /* __ASM_ARCH_OMAP730_H */
102
diff --git a/arch/arm/plat-omap/include/plat/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h
deleted file mode 100644
index c33f67981712..000000000000
--- a/arch/arm/plat-omap/include/plat/omap850.h
+++ /dev/null
@@ -1,102 +0,0 @@
1/* arch/arm/plat-omap/include/mach/omap850.h
2 *
3 * Hardware definitions for TI OMAP850 processor.
4 *
5 * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP850_H
29#define __ASM_ARCH_OMAP850_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP850_DSP_BASE 0xE0000000
40#define OMAP850_DSP_SIZE 0x50000
41#define OMAP850_DSP_START 0xE0000000
42
43#define OMAP850_DSPREG_BASE 0xE1000000
44#define OMAP850_DSPREG_SIZE SZ_128K
45#define OMAP850_DSPREG_START 0xE1000000
46
47/*
48 * ----------------------------------------------------------------------------
49 * OMAP850 specific configuration registers
50 * ----------------------------------------------------------------------------
51 */
52#define OMAP850_CONFIG_BASE 0xfffe1000
53#define OMAP850_IO_CONF_0 0xfffe1070
54#define OMAP850_IO_CONF_1 0xfffe1074
55#define OMAP850_IO_CONF_2 0xfffe1078
56#define OMAP850_IO_CONF_3 0xfffe107c
57#define OMAP850_IO_CONF_4 0xfffe1080
58#define OMAP850_IO_CONF_5 0xfffe1084
59#define OMAP850_IO_CONF_6 0xfffe1088
60#define OMAP850_IO_CONF_7 0xfffe108c
61#define OMAP850_IO_CONF_8 0xfffe1090
62#define OMAP850_IO_CONF_9 0xfffe1094
63#define OMAP850_IO_CONF_10 0xfffe1098
64#define OMAP850_IO_CONF_11 0xfffe109c
65#define OMAP850_IO_CONF_12 0xfffe10a0
66#define OMAP850_IO_CONF_13 0xfffe10a4
67
68#define OMAP850_MODE_1 0xfffe1010
69#define OMAP850_MODE_2 0xfffe1014
70
71/* CSMI specials: in terms of base + offset */
72#define OMAP850_MODE2_OFFSET 0x14
73
74/*
75 * ----------------------------------------------------------------------------
76 * OMAP850 traffic controller configuration registers
77 * ----------------------------------------------------------------------------
78 */
79#define OMAP850_FLASH_CFG_0 0xfffecc10
80#define OMAP850_FLASH_ACFG_0 0xfffecc50
81#define OMAP850_FLASH_CFG_1 0xfffecc14
82#define OMAP850_FLASH_ACFG_1 0xfffecc54
83
84/*
85 * ----------------------------------------------------------------------------
86 * OMAP850 DSP control registers
87 * ----------------------------------------------------------------------------
88 */
89#define OMAP850_ICR_BASE 0xfffbb800
90#define OMAP850_DSP_M_CTL 0xfffbb804
91#define OMAP850_DSP_MMU_BASE 0xfffed200
92
93/*
94 * ----------------------------------------------------------------------------
95 * OMAP850 PCC_UPLD configuration registers
96 * ----------------------------------------------------------------------------
97 */
98#define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900)
99#define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
100
101#endif /* __ASM_ARCH_OMAP850_H */
102
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index c835b7194ff5..a8ecc53b3670 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -629,6 +629,8 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
629 629
630int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); 630int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
631 631
632extern void __init omap_hwmod_init(void);
633
632/* 634/*
633 * Chip variant-specific hwmod init routines - XXX should be converted 635 * Chip variant-specific hwmod init routines - XXX should be converted
634 * to use initcalls once the initial boot ordering is straightened out 636 * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index b073e5f2b190..28e2d250c2fd 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -60,6 +60,9 @@
60/* AM3505/3517 UART4 */ 60/* AM3505/3517 UART4 */
61#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ 61#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
62 62
63/* AM33XX serial port */
64#define AM33XX_UART1_BASE 0x44E09000
65
63/* External port on Zoom2/3 */ 66/* External port on Zoom2/3 */
64#define ZOOM_UART_BASE 0x10000000 67#define ZOOM_UART_BASE 0x10000000
65#define ZOOM_UART_VIRT 0xfa400000 68#define ZOOM_UART_VIRT 0xfa400000
@@ -93,6 +96,7 @@
93#define TI81XXUART1 81 96#define TI81XXUART1 81
94#define TI81XXUART2 82 97#define TI81XXUART2 82
95#define TI81XXUART3 83 98#define TI81XXUART3 83
99#define AM33XXUART1 84
96#define ZOOM_UART 95 /* Only on zoom2/3 */ 100#define ZOOM_UART 95 /* Only on zoom2/3 */
97 101
98/* This is only used by 8250.c for omap1510 */ 102/* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index cc3f11ba7a99..ac4323390213 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -103,6 +103,10 @@ static inline void flush(void)
103 _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ 103 _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
104 TI81XXUART##p) 104 TI81XXUART##p)
105 105
106#define DEBUG_LL_AM33XX(p, mach) \
107 _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
108 AM33XXUART##p)
109
106static inline void __arch_decomp_setup(unsigned long arch_id) 110static inline void __arch_decomp_setup(unsigned long arch_id)
107{ 111{
108 int port = 0; 112 int port = 0;
@@ -183,6 +187,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
183 /* TI8148 base boards using UART1 */ 187 /* TI8148 base boards using UART1 */
184 DEBUG_LL_TI81XX(1, ti8148evm); 188 DEBUG_LL_TI81XX(1, ti8148evm);
185 189
190 /* AM33XX base boards using UART1 */
191 DEBUG_LL_AM33XX(1, am335xevm);
186 } while (0); 192 } while (0);
187} 193}
188 194
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 762eeb0626c1..548a4c8d63df 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -44,6 +44,8 @@ struct usbhs_omap_board_data {
44 struct regulator *regulator[OMAP3_HS_USB_PORTS]; 44 struct regulator *regulator[OMAP3_HS_USB_PORTS];
45}; 45};
46 46
47#ifdef CONFIG_ARCH_OMAP2PLUS
48
47struct ehci_hcd_omap_platform_data { 49struct ehci_hcd_omap_platform_data {
48 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; 50 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
49 int reset_gpio_port[OMAP3_HS_USB_PORTS]; 51 int reset_gpio_port[OMAP3_HS_USB_PORTS];
@@ -64,26 +66,6 @@ struct usbhs_omap_platform_data {
64}; 66};
65/*-------------------------------------------------------------------------*/ 67/*-------------------------------------------------------------------------*/
66 68
67#define OMAP1_OTG_BASE 0xfffb0400
68#define OMAP1_UDC_BASE 0xfffb4000
69#define OMAP1_OHCI_BASE 0xfffba000
70
71#define OMAP2_OHCI_BASE 0x4805e000
72#define OMAP2_UDC_BASE 0x4805e200
73#define OMAP2_OTG_BASE 0x4805e300
74
75#ifdef CONFIG_ARCH_OMAP1
76
77#define OTG_BASE OMAP1_OTG_BASE
78#define UDC_BASE OMAP1_UDC_BASE
79#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
80
81#else
82
83#define OTG_BASE OMAP2_OTG_BASE
84#define UDC_BASE OMAP2_UDC_BASE
85#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
86
87struct omap_musb_board_data { 69struct omap_musb_board_data {
88 u8 interface_type; 70 u8 interface_type;
89 u8 mode; 71 u8 mode;
@@ -107,44 +89,6 @@ extern int omap4430_phy_init(struct device *dev);
107extern int omap4430_phy_exit(struct device *dev); 89extern int omap4430_phy_exit(struct device *dev);
108extern int omap4430_phy_suspend(struct device *dev, int suspend); 90extern int omap4430_phy_suspend(struct device *dev, int suspend);
109 91
110/*
111 * NOTE: Please update omap USB drivers to use ioremap + read/write
112 */
113
114#define OMAP2_L4_IO_OFFSET 0xb2000000
115#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
116
117static inline u8 omap_readb(u32 pa)
118{
119 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
120}
121
122static inline u16 omap_readw(u32 pa)
123{
124 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
125}
126
127static inline u32 omap_readl(u32 pa)
128{
129 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
130}
131
132static inline void omap_writeb(u8 v, u32 pa)
133{
134 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
135}
136
137
138static inline void omap_writew(u16 v, u32 pa)
139{
140 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
141}
142
143static inline void omap_writel(u32 v, u32 pa)
144{
145 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
146}
147
148#endif 92#endif
149 93
150extern void am35x_musb_reset(void); 94extern void am35x_musb_reset(void);
@@ -153,142 +97,6 @@ extern void am35x_musb_clear_irq(void);
153extern void am35x_set_mode(u8 musb_mode); 97extern void am35x_set_mode(u8 musb_mode);
154extern void ti81xx_musb_phy_power(u8 on); 98extern void ti81xx_musb_phy_power(u8 on);
155 99
156/*
157 * FIXME correct answer depends on hmc_mode,
158 * as does (on omap1) any nonzero value for config->otg port number
159 */
160#ifdef CONFIG_USB_GADGET_OMAP
161#define is_usb0_device(config) 1
162#else
163#define is_usb0_device(config) 0
164#endif
165
166void omap_otg_init(struct omap_usb_config *config);
167
168#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
169void omap1_usb_init(struct omap_usb_config *pdata);
170#else
171static inline void omap1_usb_init(struct omap_usb_config *pdata)
172{
173}
174#endif
175
176#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
177void omap2_usbfs_init(struct omap_usb_config *pdata);
178#else
179static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
180{
181}
182#endif
183
184/*-------------------------------------------------------------------------*/
185
186/*
187 * OTG and transceiver registers, for OMAPs starting with ARM926
188 */
189#define OTG_REV (OTG_BASE + 0x00)
190#define OTG_SYSCON_1 (OTG_BASE + 0x04)
191# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
192# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
193# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
194# define OTG_IDLE_EN (1 << 15)
195# define HST_IDLE_EN (1 << 14)
196# define DEV_IDLE_EN (1 << 13)
197# define OTG_RESET_DONE (1 << 2)
198# define OTG_SOFT_RESET (1 << 1)
199#define OTG_SYSCON_2 (OTG_BASE + 0x08)
200# define OTG_EN (1 << 31)
201# define USBX_SYNCHRO (1 << 30)
202# define OTG_MST16 (1 << 29)
203# define SRP_GPDATA (1 << 28)
204# define SRP_GPDVBUS (1 << 27)
205# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
206# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
207# define B_ASE_BRST(w) (((w)>>16)&0x07)
208# define SRP_DPW (1 << 14)
209# define SRP_DATA (1 << 13)
210# define SRP_VBUS (1 << 12)
211# define OTG_PADEN (1 << 10)
212# define HMC_PADEN (1 << 9)
213# define UHOST_EN (1 << 8)
214# define HMC_TLLSPEED (1 << 7)
215# define HMC_TLLATTACH (1 << 6)
216# define OTG_HMC(w) (((w)>>0)&0x3f)
217#define OTG_CTRL (OTG_BASE + 0x0c)
218# define OTG_USB2_EN (1 << 29)
219# define OTG_USB2_DP (1 << 28)
220# define OTG_USB2_DM (1 << 27)
221# define OTG_USB1_EN (1 << 26)
222# define OTG_USB1_DP (1 << 25)
223# define OTG_USB1_DM (1 << 24)
224# define OTG_USB0_EN (1 << 23)
225# define OTG_USB0_DP (1 << 22)
226# define OTG_USB0_DM (1 << 21)
227# define OTG_ASESSVLD (1 << 20)
228# define OTG_BSESSEND (1 << 19)
229# define OTG_BSESSVLD (1 << 18)
230# define OTG_VBUSVLD (1 << 17)
231# define OTG_ID (1 << 16)
232# define OTG_DRIVER_SEL (1 << 15)
233# define OTG_A_SETB_HNPEN (1 << 12)
234# define OTG_A_BUSREQ (1 << 11)
235# define OTG_B_HNPEN (1 << 9)
236# define OTG_B_BUSREQ (1 << 8)
237# define OTG_BUSDROP (1 << 7)
238# define OTG_PULLDOWN (1 << 5)
239# define OTG_PULLUP (1 << 4)
240# define OTG_DRV_VBUS (1 << 3)
241# define OTG_PD_VBUS (1 << 2)
242# define OTG_PU_VBUS (1 << 1)
243# define OTG_PU_ID (1 << 0)
244#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
245# define DRIVER_SWITCH (1 << 15)
246# define A_VBUS_ERR (1 << 13)
247# define A_REQ_TMROUT (1 << 12)
248# define A_SRP_DETECT (1 << 11)
249# define B_HNP_FAIL (1 << 10)
250# define B_SRP_TMROUT (1 << 9)
251# define B_SRP_DONE (1 << 8)
252# define B_SRP_STARTED (1 << 7)
253# define OPRT_CHG (1 << 0)
254#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
255 // same bits as in IRQ_EN
256#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
257# define OTGVPD (1 << 14)
258# define OTGVPU (1 << 13)
259# define OTGPUID (1 << 12)
260# define USB2VDR (1 << 10)
261# define USB2PDEN (1 << 9)
262# define USB2PUEN (1 << 8)
263# define USB1VDR (1 << 6)
264# define USB1PDEN (1 << 5)
265# define USB1PUEN (1 << 4)
266# define USB0VDR (1 << 2)
267# define USB0PDEN (1 << 1)
268# define USB0PUEN (1 << 0)
269#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
270#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
271
272/*-------------------------------------------------------------------------*/
273
274/* OMAP1 */
275#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
276# define CONF_USB2_UNI_R (1 << 8)
277# define CONF_USB1_UNI_R (1 << 7)
278# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
279# define CONF_USB0_ISOLATE_R (1 << 3)
280# define CONF_USB_PWRDN_DM_R (1 << 2)
281# define CONF_USB_PWRDN_DP_R (1 << 1)
282
283/* OMAP2 */
284# define USB_UNIDIR 0x0
285# define USB_UNIDIR_TLL 0x1
286# define USB_BIDIR 0x2
287# define USB_BIDIR_TLL 0x3
288# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
289# define USBT2TLL5PI (1 << 17)
290# define USB0PUENACTLOI (1 << 16)
291# define USBSTANDBYCTRL (1 << 15)
292/* AM35x */ 100/* AM35x */
293/* USB 2.0 PHY Control */ 101/* USB 2.0 PHY Control */
294#define CONF2_PHY_GPIOMODE (1 << 23) 102#define CONF2_PHY_GPIOMODE (1 << 23)
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index ad32621aa52e..5e13c3884aa4 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -282,6 +282,8 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
282 } 282 }
283 mbox->rxq = mq; 283 mbox->rxq = mq;
284 mq->mbox = mbox; 284 mq->mbox = mbox;
285
286 omap_mbox_enable_irq(mbox, IRQ_RX);
285 } 287 }
286 mutex_unlock(&mbox_configured_lock); 288 mutex_unlock(&mbox_configured_lock);
287 return 0; 289 return 0;
@@ -305,6 +307,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
305 mutex_lock(&mbox_configured_lock); 307 mutex_lock(&mbox_configured_lock);
306 308
307 if (!--mbox->use_count) { 309 if (!--mbox->use_count) {
310 omap_mbox_disable_irq(mbox, IRQ_RX);
308 free_irq(mbox->irq, mbox); 311 free_irq(mbox->irq, mbox);
309 tasklet_kill(&mbox->txq->tasklet); 312 tasklet_kill(&mbox->txq->tasklet);
310 flush_work_sync(&mbox->rxq->work); 313 flush_work_sync(&mbox->rxq->work);
@@ -338,13 +341,15 @@ struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
338 if (!mbox) 341 if (!mbox)
339 return ERR_PTR(-ENOENT); 342 return ERR_PTR(-ENOENT);
340 343
341 ret = omap_mbox_startup(mbox);
342 if (ret)
343 return ERR_PTR(-ENODEV);
344
345 if (nb) 344 if (nb)
346 blocking_notifier_chain_register(&mbox->notifier, nb); 345 blocking_notifier_chain_register(&mbox->notifier, nb);
347 346
347 ret = omap_mbox_startup(mbox);
348 if (ret) {
349 blocking_notifier_chain_unregister(&mbox->notifier, nb);
350 return ERR_PTR(-ENODEV);
351 }
352
348 return mbox; 353 return mbox;
349} 354}
350EXPORT_SYMBOL(omap_mbox_get); 355EXPORT_SYMBOL(omap_mbox_get);
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
deleted file mode 100644
index daa0327381b5..000000000000
--- a/arch/arm/plat-omap/usb.c
+++ /dev/null
@@ -1,145 +0,0 @@
1 /*
2 * arch/arm/plat-omap/usb.c -- platform level USB initialization
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#undef DEBUG
22
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28
29#include <plat/usb.h>
30#include <plat/board.h>
31
32#include <mach/hardware.h>
33
34#ifdef CONFIG_ARCH_OMAP_OTG
35
36void __init
37omap_otg_init(struct omap_usb_config *config)
38{
39 u32 syscon;
40 int alt_pingroup = 0;
41
42 /* NOTE: no bus or clock setup (yet?) */
43
44 syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
45 if (!(syscon & OTG_RESET_DONE))
46 pr_debug("USB resets not complete?\n");
47
48 //omap_writew(0, OTG_IRQ_EN);
49
50 /* pin muxing and transceiver pinouts */
51 if (config->pins[0] > 2) /* alt pingroup 2 */
52 alt_pingroup = 1;
53 syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
54 syscon |= config->usb1_init(config->pins[1]);
55 syscon |= config->usb2_init(config->pins[2], alt_pingroup);
56 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
57 omap_writel(syscon, OTG_SYSCON_1);
58
59 syscon = config->hmc_mode;
60 syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
61#ifdef CONFIG_USB_OTG
62 if (config->otg)
63 syscon |= OTG_EN;
64#endif
65 if (cpu_class_is_omap1())
66 pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
67 omap_readl(USB_TRANSCEIVER_CTRL));
68 pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
69 omap_writel(syscon, OTG_SYSCON_2);
70
71 printk("USB: hmc %d", config->hmc_mode);
72 if (!alt_pingroup)
73 printk(", usb2 alt %d wires", config->pins[2]);
74 else if (config->pins[0])
75 printk(", usb0 %d wires%s", config->pins[0],
76 is_usb0_device(config) ? " (dev)" : "");
77 if (config->pins[1])
78 printk(", usb1 %d wires", config->pins[1]);
79 if (!alt_pingroup && config->pins[2])
80 printk(", usb2 %d wires", config->pins[2]);
81 if (config->otg)
82 printk(", Mini-AB on usb%d", config->otg - 1);
83 printk("\n");
84
85 if (cpu_class_is_omap1()) {
86 u16 w;
87
88 /* leave USB clocks/controllers off until needed */
89 w = omap_readw(ULPD_SOFT_REQ);
90 w &= ~SOFT_USB_CLK_REQ;
91 omap_writew(w, ULPD_SOFT_REQ);
92
93 w = omap_readw(ULPD_CLOCK_CTRL);
94 w &= ~USB_MCLK_EN;
95 w |= DIS_USB_PVCI_CLK;
96 omap_writew(w, ULPD_CLOCK_CTRL);
97 }
98 syscon = omap_readl(OTG_SYSCON_1);
99 syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
100
101#ifdef CONFIG_USB_GADGET_OMAP
102 if (config->otg || config->register_dev) {
103 struct platform_device *udc_device = config->udc_device;
104 int status;
105
106 syscon &= ~DEV_IDLE_EN;
107 udc_device->dev.platform_data = config;
108 status = platform_device_register(udc_device);
109 if (status)
110 pr_debug("can't register UDC device, %d\n", status);
111 }
112#endif
113
114#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
115 if (config->otg || config->register_host) {
116 struct platform_device *ohci_device = config->ohci_device;
117 int status;
118
119 syscon &= ~HST_IDLE_EN;
120 ohci_device->dev.platform_data = config;
121 status = platform_device_register(ohci_device);
122 if (status)
123 pr_debug("can't register OHCI device, %d\n", status);
124 }
125#endif
126
127#ifdef CONFIG_USB_OTG
128 if (config->otg) {
129 struct platform_device *otg_device = config->otg_device;
130 int status;
131
132 syscon &= ~OTG_IDLE_EN;
133 otg_device->dev.platform_data = config;
134 status = platform_device_register(otg_device);
135 if (status)
136 pr_debug("can't register OTG device, %d\n", status);
137 }
138#endif
139 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
140 omap_writel(syscon, OTG_SYSCON_1);
141}
142
143#else
144void omap_otg_init(struct omap_usb_config *config) {}
145#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 07:17:41 -0400