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-rw-r--r--arch/arm/plat-omap/Kconfig33
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/common.c40
-rw-r--r--arch/arm/plat-omap/devices.c22
-rw-r--r--arch/arm/plat-omap/dma.c8
-rw-r--r--arch/arm/plat-omap/dmtimer.c2
-rw-r--r--arch/arm/plat-omap/gpio.c70
-rw-r--r--arch/arm/plat-omap/include/mach/board-2430sdp.h6
-rw-r--r--arch/arm/plat-omap/include/mach/board-apollon.h6
-rw-r--r--arch/arm/plat-omap/include/mach/board-h4.h5
-rw-r--r--arch/arm/plat-omap/include/mach/board-ldp.h36
-rw-r--r--arch/arm/plat-omap/include/mach/board-omap3beagle.h33
-rw-r--r--arch/arm/plat-omap/include/mach/board-overo.h26
-rw-r--r--arch/arm/plat-omap/include/mach/board.h2
-rw-r--r--arch/arm/plat-omap/include/mach/clock.h3
-rw-r--r--arch/arm/plat-omap/include/mach/clockdomain.h106
-rw-r--r--arch/arm/plat-omap/include/mach/common.h3
-rw-r--r--arch/arm/plat-omap/include/mach/control.h23
-rw-r--r--arch/arm/plat-omap/include/mach/cpu.h5
-rw-r--r--arch/arm/plat-omap/include/mach/debug-macro.S12
-rw-r--r--arch/arm/plat-omap/include/mach/entry-macro.S12
-rw-r--r--arch/arm/plat-omap/include/mach/fpga.h12
-rw-r--r--arch/arm/plat-omap/include/mach/gpio.h4
-rw-r--r--arch/arm/plat-omap/include/mach/gpmc.h12
-rw-r--r--arch/arm/plat-omap/include/mach/hardware.h12
-rw-r--r--arch/arm/plat-omap/include/mach/io.h59
-rw-r--r--arch/arm/plat-omap/include/mach/irqs.h59
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h44
-rw-r--r--arch/arm/plat-omap/include/mach/memory.h2
-rw-r--r--arch/arm/plat-omap/include/mach/mux.h180
-rw-r--r--arch/arm/plat-omap/include/mach/omap1510.h2
-rw-r--r--arch/arm/plat-omap/include/mach/omap16xx.h7
-rw-r--r--arch/arm/plat-omap/include/mach/omap24xx.h2
-rw-r--r--arch/arm/plat-omap/include/mach/omapfb.h3
-rw-r--r--arch/arm/plat-omap/include/mach/pm.h7
-rw-r--r--arch/arm/plat-omap/include/mach/powerdomain.h166
-rw-r--r--arch/arm/plat-omap/include/mach/sdrc.h8
-rw-r--r--arch/arm/plat-omap/include/mach/serial.h18
-rw-r--r--arch/arm/plat-omap/include/mach/sram.h10
-rw-r--r--arch/arm/plat-omap/include/mach/system.h2
-rw-r--r--arch/arm/plat-omap/io.c107
-rw-r--r--arch/arm/plat-omap/mcbsp.c431
-rw-r--r--arch/arm/plat-omap/sram.c53
43 files changed, 1277 insertions, 378 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index b917206ee906..a94f0c44ebc8 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -15,6 +15,9 @@ config ARCH_OMAP1
15config ARCH_OMAP2 15config ARCH_OMAP2
16 bool "TI OMAP2" 16 bool "TI OMAP2"
17 17
18config ARCH_OMAP3
19 bool "TI OMAP3"
20
18endchoice 21endchoice
19 22
20comment "OMAP Feature Selections" 23comment "OMAP Feature Selections"
@@ -29,6 +32,30 @@ config OMAP_DEBUG_LEDS
29 depends on OMAP_DEBUG_DEVICES 32 depends on OMAP_DEBUG_DEVICES
30 default y if LEDS || LEDS_OMAP_DEBUG 33 default y if LEDS || LEDS_OMAP_DEBUG
31 34
35config OMAP_DEBUG_POWERDOMAIN
36 bool "Emit debug messages from powerdomain layer"
37 depends on ARCH_OMAP2 || ARCH_OMAP3
38 default n
39 help
40 Say Y here if you want to compile in powerdomain layer
41 debugging messages for OMAP2/3. These messages can
42 provide more detail as to why some powerdomain calls
43 may be failing, and will also emit a descriptive message
44 for every powerdomain register write. However, the
45 extra detail costs some memory.
46
47config OMAP_DEBUG_CLOCKDOMAIN
48 bool "Emit debug messages from clockdomain layer"
49 depends on ARCH_OMAP2 || ARCH_OMAP3
50 default n
51 help
52 Say Y here if you want to compile in clockdomain layer
53 debugging messages for OMAP2/3. These messages can
54 provide more detail as to why some clockdomain calls
55 may be failing, and will also emit a descriptive message
56 for every clockdomain register write. However, the
57 extra detail costs some memory.
58
32config OMAP_RESET_CLOCKS 59config OMAP_RESET_CLOCKS
33 bool "Reset unused clocks during boot" 60 bool "Reset unused clocks during boot"
34 depends on ARCH_OMAP 61 depends on ARCH_OMAP
@@ -88,13 +115,13 @@ config OMAP_MPU_TIMER
88 115
89config OMAP_32K_TIMER 116config OMAP_32K_TIMER
90 bool "Use 32KHz timer" 117 bool "Use 32KHz timer"
91 depends on ARCH_OMAP16XX || ARCH_OMAP24XX 118 depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
92 help 119 help
93 Select this option if you want to enable the OMAP 32KHz timer. 120 Select this option if you want to enable the OMAP 32KHz timer.
94 This timer saves power compared to the OMAP_MPU_TIMER, and has 121 This timer saves power compared to the OMAP_MPU_TIMER, and has
95 support for no tick during idle. The 32KHz timer provides less 122 support for no tick during idle. The 32KHz timer provides less
96 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is 123 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
97 currently only available for OMAP16XX and 24XX. 124 currently only available for OMAP16XX, 24XX and 34XX.
98 125
99endchoice 126endchoice
100 127
@@ -109,7 +136,7 @@ config OMAP_32K_TIMER_HZ
109 136
110config OMAP_DM_TIMER 137config OMAP_DM_TIMER
111 bool "Use dual-mode timer" 138 bool "Use dual-mode timer"
112 depends on ARCH_OMAP16XX || ARCH_OMAP24XX 139 depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
113 help 140 help
114 Select this option if you want to use OMAP Dual-Mode timers. 141 Select this option if you want to use OMAP Dual-Mode timers.
115 142
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 2c4051cc79a1..deaff58878a2 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
7 usb.o fb.o 7 usb.o fb.o io.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 8bdf0ead0cf3..0843b8882f93 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -248,6 +248,7 @@ static struct omap_globals *omap2_globals;
248 248
249static void __init __omap2_set_globals(void) 249static void __init __omap2_set_globals(void)
250{ 250{
251 omap2_set_globals_tap(omap2_globals);
251 omap2_set_globals_memory(omap2_globals); 252 omap2_set_globals_memory(omap2_globals);
252 omap2_set_globals_control(omap2_globals); 253 omap2_set_globals_control(omap2_globals);
253 omap2_set_globals_prcm(omap2_globals); 254 omap2_set_globals_prcm(omap2_globals);
@@ -258,12 +259,13 @@ static void __init __omap2_set_globals(void)
258#if defined(CONFIG_ARCH_OMAP2420) 259#if defined(CONFIG_ARCH_OMAP2420)
259 260
260static struct omap_globals omap242x_globals = { 261static struct omap_globals omap242x_globals = {
261 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000), 262 .class = OMAP242X_CLASS,
262 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE), 263 .tap = OMAP2_IO_ADDRESS(0x48014000),
263 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE), 264 .sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
264 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE), 265 .sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
265 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE), 266 .ctrl = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
266 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE), 267 .prm = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
268 .cm = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
267}; 269};
268 270
269void __init omap2_set_globals_242x(void) 271void __init omap2_set_globals_242x(void)
@@ -276,12 +278,13 @@ void __init omap2_set_globals_242x(void)
276#if defined(CONFIG_ARCH_OMAP2430) 278#if defined(CONFIG_ARCH_OMAP2430)
277 279
278static struct omap_globals omap243x_globals = { 280static struct omap_globals omap243x_globals = {
279 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000), 281 .class = OMAP243X_CLASS,
280 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE), 282 .tap = OMAP2_IO_ADDRESS(0x4900a000),
281 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE), 283 .sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
282 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE), 284 .sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
283 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE), 285 .ctrl = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
284 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE), 286 .prm = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
287 .cm = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
285}; 288};
286 289
287void __init omap2_set_globals_243x(void) 290void __init omap2_set_globals_243x(void)
@@ -294,12 +297,13 @@ void __init omap2_set_globals_243x(void)
294#if defined(CONFIG_ARCH_OMAP3430) 297#if defined(CONFIG_ARCH_OMAP3430)
295 298
296static struct omap_globals omap343x_globals = { 299static struct omap_globals omap343x_globals = {
297 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000), 300 .class = OMAP343X_CLASS,
298 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE), 301 .tap = OMAP2_IO_ADDRESS(0x4830A000),
299 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE), 302 .sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
300 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE), 303 .sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
301 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE), 304 .ctrl = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
302 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE), 305 .prm = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
306 .cm = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
303}; 307};
304 308
305void __init omap2_set_globals_343x(void) 309void __init omap2_set_globals_343x(void)
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index b38410f26203..25232b281e1e 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -20,17 +20,17 @@
20#include <asm/mach/map.h> 20#include <asm/mach/map.h>
21 21
22#include <mach/tc.h> 22#include <mach/tc.h>
23#include <mach/control.h>
23#include <mach/board.h> 24#include <mach/board.h>
24#include <mach/mmc.h> 25#include <mach/mmc.h>
25#include <mach/mux.h> 26#include <mach/mux.h>
26#include <mach/gpio.h> 27#include <mach/gpio.h>
27#include <mach/menelaus.h> 28#include <mach/menelaus.h>
28#include <mach/mcbsp.h> 29#include <mach/mcbsp.h>
30#include <mach/dsp_common.h>
29 31
30#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) 32#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
31 33
32#include "../plat-omap/dsp/dsp_common.h"
33
34static struct dsp_platform_data dsp_pdata = { 34static struct dsp_platform_data dsp_pdata = {
35 .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list), 35 .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
36}; 36};
@@ -76,7 +76,7 @@ int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
76{ 76{
77 static DEFINE_MUTEX(dsp_pdata_lock); 77 static DEFINE_MUTEX(dsp_pdata_lock);
78 78
79 mutex_init(&kdev->lock); 79 spin_lock_init(&kdev->lock);
80 80
81 mutex_lock(&dsp_pdata_lock); 81 mutex_lock(&dsp_pdata_lock);
82 list_add_tail(&kdev->entry, &dsp_pdata.kdev_list); 82 list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
@@ -95,6 +95,10 @@ static inline void omap_init_dsp(void) { }
95 95
96static void omap_init_kp(void) 96static void omap_init_kp(void)
97{ 97{
98 /* 2430 and 34xx keypad is on TWL4030 */
99 if (cpu_is_omap2430() || cpu_is_omap34xx())
100 return;
101
98 if (machine_is_omap_h2() || machine_is_omap_h3()) { 102 if (machine_is_omap_h2() || machine_is_omap_h3()) {
99 omap_cfg_reg(F18_1610_KBC0); 103 omap_cfg_reg(F18_1610_KBC0);
100 omap_cfg_reg(D20_1610_KBC1); 104 omap_cfg_reg(D20_1610_KBC1);
@@ -156,13 +160,6 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
156{ 160{
157 int i; 161 int i;
158 162
159 if (size > OMAP_MAX_MCBSP_COUNT) {
160 printk(KERN_WARNING "Registered too many McBSPs platform_data."
161 " Using maximum (%d) available.\n",
162 OMAP_MAX_MCBSP_COUNT);
163 size = OMAP_MAX_MCBSP_COUNT;
164 }
165
166 omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *), 163 omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
167 GFP_KERNEL); 164 GFP_KERNEL);
168 if (!omap_mcbsp_devices) { 165 if (!omap_mcbsp_devices) {
@@ -538,10 +535,6 @@ static inline void omap_init_rng(void) {}
538 */ 535 */
539static int __init omap_init_devices(void) 536static int __init omap_init_devices(void)
540{ 537{
541/*
542 * Need to enable relevant once for 2430 SDP
543 */
544#ifndef CONFIG_MACH_OMAP_2430SDP
545 /* please keep these calls, and their implementations above, 538 /* please keep these calls, and their implementations above,
546 * in alphabetical order so they're easier to sort through. 539 * in alphabetical order so they're easier to sort through.
547 */ 540 */
@@ -551,7 +544,6 @@ static int __init omap_init_devices(void)
551 omap_init_uwire(); 544 omap_init_uwire();
552 omap_init_wdt(); 545 omap_init_wdt();
553 omap_init_rng(); 546 omap_init_rng();
554#endif
555 return 0; 547 return 0;
556} 548}
557arch_initcall(omap_init_devices); 549arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index a63b644ad305..50f8b4ad9a09 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1233,7 +1233,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1233 /* request and reserve DMA channels for the chain */ 1233 /* request and reserve DMA channels for the chain */
1234 for (i = 0; i < no_of_chans; i++) { 1234 for (i = 0; i < no_of_chans; i++) {
1235 err = omap_request_dma(dev_id, dev_name, 1235 err = omap_request_dma(dev_id, dev_name,
1236 callback, 0, &channels[i]); 1236 callback, NULL, &channels[i]);
1237 if (err < 0) { 1237 if (err < 0) {
1238 int j; 1238 int j;
1239 for (j = 0; j < i; j++) 1239 for (j = 0; j < i; j++)
@@ -2297,13 +2297,13 @@ static int __init omap_init_dma(void)
2297 int ch, r; 2297 int ch, r;
2298 2298
2299 if (cpu_class_is_omap1()) { 2299 if (cpu_class_is_omap1()) {
2300 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE); 2300 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2301 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; 2301 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2302 } else if (cpu_is_omap24xx()) { 2302 } else if (cpu_is_omap24xx()) {
2303 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE); 2303 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2304 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; 2304 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2305 } else if (cpu_is_omap34xx()) { 2305 } else if (cpu_is_omap34xx()) {
2306 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE); 2306 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2307 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; 2307 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2308 } else { 2308 } else {
2309 pr_err("DMA init failed for unsupported omap\n"); 2309 pr_err("DMA init failed for unsupported omap\n");
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 606fcffdcefc..963c31cd1541 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -693,7 +693,7 @@ int __init omap_dm_timer_init(void)
693 693
694 for (i = 0; i < dm_timer_count; i++) { 694 for (i = 0; i < dm_timer_count; i++) {
695 timer = &dm_timers[i]; 695 timer = &dm_timers[i];
696 timer->io_base = (void __iomem *)io_p2v(timer->phys_base); 696 timer->io_base = IO_ADDRESS(timer->phys_base);
697#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 697#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
698 if (cpu_class_is_omap2()) { 698 if (cpu_class_is_omap2()) {
699 char clk_name[16]; 699 char clk_name[16];
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 5935ae4e550b..8679fbca6bbe 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -28,7 +28,7 @@
28/* 28/*
29 * OMAP1510 GPIO registers 29 * OMAP1510 GPIO registers
30 */ 30 */
31#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000 31#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32#define OMAP1510_GPIO_DATA_INPUT 0x00 32#define OMAP1510_GPIO_DATA_INPUT 0x00
33#define OMAP1510_GPIO_DATA_OUTPUT 0x04 33#define OMAP1510_GPIO_DATA_OUTPUT 0x04
34#define OMAP1510_GPIO_DIR_CONTROL 0x08 34#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -42,10 +42,10 @@
42/* 42/*
43 * OMAP1610 specific GPIO registers 43 * OMAP1610 specific GPIO registers
44 */ 44 */
45#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400 45#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00 46#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400 47#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00 48#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49#define OMAP1610_GPIO_REVISION 0x0000 49#define OMAP1610_GPIO_REVISION 0x0000
50#define OMAP1610_GPIO_SYSCONFIG 0x0010 50#define OMAP1610_GPIO_SYSCONFIG 0x0010
51#define OMAP1610_GPIO_SYSSTATUS 0x0014 51#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -67,12 +67,12 @@
67/* 67/*
68 * OMAP730 specific GPIO registers 68 * OMAP730 specific GPIO registers
69 */ 69 */
70#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000 70#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800 71#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000 72#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800 73#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000 74#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800 75#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76#define OMAP730_GPIO_DATA_INPUT 0x00 76#define OMAP730_GPIO_DATA_INPUT 0x00
77#define OMAP730_GPIO_DATA_OUTPUT 0x04 77#define OMAP730_GPIO_DATA_OUTPUT 0x04
78#define OMAP730_GPIO_DIR_CONTROL 0x08 78#define OMAP730_GPIO_DIR_CONTROL 0x08
@@ -83,16 +83,16 @@
83/* 83/*
84 * omap24xx specific GPIO registers 84 * omap24xx specific GPIO registers
85 */ 85 */
86#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000 86#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000 87#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000 88#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000 89#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
90 90
91#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000 91#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000 92#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000 93#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000 94#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000 95#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
96 96
97#define OMAP24XX_GPIO_REVISION 0x0000 97#define OMAP24XX_GPIO_REVISION 0x0000
98#define OMAP24XX_GPIO_SYSCONFIG 0x0010 98#define OMAP24XX_GPIO_SYSCONFIG 0x0010
@@ -122,13 +122,14 @@
122 * omap34xx specific GPIO registers 122 * omap34xx specific GPIO registers
123 */ 123 */
124 124
125#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000 125#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
126#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000 126#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
127#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000 127#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
128#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000 128#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
129#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000 129#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
130#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000 130#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
131 131
132#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
132 133
133struct gpio_bank { 134struct gpio_bank {
134 void __iomem *base; 135 void __iomem *base;
@@ -160,7 +161,7 @@ struct gpio_bank {
160 161
161#ifdef CONFIG_ARCH_OMAP16XX 162#ifdef CONFIG_ARCH_OMAP16XX
162static struct gpio_bank gpio_bank_1610[5] = { 163static struct gpio_bank gpio_bank_1610[5] = {
163 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, 164 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
164 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, 165 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, 166 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, 167 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
@@ -170,14 +171,14 @@ static struct gpio_bank gpio_bank_1610[5] = {
170 171
171#ifdef CONFIG_ARCH_OMAP15XX 172#ifdef CONFIG_ARCH_OMAP15XX
172static struct gpio_bank gpio_bank_1510[2] = { 173static struct gpio_bank gpio_bank_1510[2] = {
173 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 174 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
174 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } 175 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
175}; 176};
176#endif 177#endif
177 178
178#ifdef CONFIG_ARCH_OMAP730 179#ifdef CONFIG_ARCH_OMAP730
179static struct gpio_bank gpio_bank_730[7] = { 180static struct gpio_bank gpio_bank_730[7] = {
180 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 181 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
181 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, 182 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
182 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, 183 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
183 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, 184 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
@@ -1389,7 +1390,7 @@ static int __init _omap_gpio_init(void)
1389 1390
1390 gpio_bank_count = 5; 1391 gpio_bank_count = 5;
1391 gpio_bank = gpio_bank_1610; 1392 gpio_bank = gpio_bank_1610;
1392 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); 1393 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1393 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", 1394 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1394 (rev >> 4) & 0x0f, rev & 0x0f); 1395 (rev >> 4) & 0x0f, rev & 0x0f);
1395 } 1396 }
@@ -1408,7 +1409,7 @@ static int __init _omap_gpio_init(void)
1408 1409
1409 gpio_bank_count = 4; 1410 gpio_bank_count = 4;
1410 gpio_bank = gpio_bank_242x; 1411 gpio_bank = gpio_bank_242x;
1411 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1412 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1412 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", 1413 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1413 (rev >> 4) & 0x0f, rev & 0x0f); 1414 (rev >> 4) & 0x0f, rev & 0x0f);
1414 } 1415 }
@@ -1417,7 +1418,7 @@ static int __init _omap_gpio_init(void)
1417 1418
1418 gpio_bank_count = 5; 1419 gpio_bank_count = 5;
1419 gpio_bank = gpio_bank_243x; 1420 gpio_bank = gpio_bank_243x;
1420 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1421 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1421 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", 1422 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1422 (rev >> 4) & 0x0f, rev & 0x0f); 1423 (rev >> 4) & 0x0f, rev & 0x0f);
1423 } 1424 }
@@ -1428,7 +1429,7 @@ static int __init _omap_gpio_init(void)
1428 1429
1429 gpio_bank_count = OMAP34XX_NR_GPIOS; 1430 gpio_bank_count = OMAP34XX_NR_GPIOS;
1430 gpio_bank = gpio_bank_34xx; 1431 gpio_bank = gpio_bank_34xx;
1431 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1432 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1432 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", 1433 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1433 (rev >> 4) & 0x0f, rev & 0x0f); 1434 (rev >> 4) & 0x0f, rev & 0x0f);
1434 } 1435 }
@@ -1437,10 +1438,9 @@ static int __init _omap_gpio_init(void)
1437 int j, gpio_count = 16; 1438 int j, gpio_count = 16;
1438 1439
1439 bank = &gpio_bank[i]; 1440 bank = &gpio_bank[i];
1440 bank->base = IO_ADDRESS(bank->base);
1441 spin_lock_init(&bank->lock); 1441 spin_lock_init(&bank->lock);
1442 if (bank_is_mpuio(bank)) 1442 if (bank_is_mpuio(bank))
1443 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); 1443 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1444 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { 1444 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1445 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); 1445 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1446 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); 1446 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
diff --git a/arch/arm/plat-omap/include/mach/board-2430sdp.h b/arch/arm/plat-omap/include/mach/board-2430sdp.h
index cf1dc0223949..10d449ea7ed0 100644
--- a/arch/arm/plat-omap/include/mach/board-2430sdp.h
+++ b/arch/arm/plat-omap/include/mach/board-2430sdp.h
@@ -30,10 +30,12 @@
30#define __ASM_ARCH_OMAP_2430SDP_H 30#define __ASM_ARCH_OMAP_2430SDP_H
31 31
32/* Placeholder for 2430SDP specific defines */ 32/* Placeholder for 2430SDP specific defines */
33#define OMAP24XX_ETHR_START 0x08000300 33#define OMAP24XX_ETHR_START 0x08000300
34#define OMAP24XX_ETHR_GPIO_IRQ 149 34#define OMAP24XX_ETHR_GPIO_IRQ 149
35#define SDP2430_CS0_BASE 0x04000000 35#define SDP2430_CS0_BASE 0x04000000
36 36
37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ 37/* Function prototypes */
38extern void sdp2430_flash_init(void);
39extern void sdp2430_usb_init(void);
38 40
39#endif /* __ASM_ARCH_OMAP_2430SDP_H */ 41#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h
index d6f2a8e963d5..731c858cf3fe 100644
--- a/arch/arm/plat-omap/include/mach/board-apollon.h
+++ b/arch/arm/plat-omap/include/mach/board-apollon.h
@@ -31,6 +31,12 @@
31 31
32extern void apollon_mmc_init(void); 32extern void apollon_mmc_init(void);
33 33
34static inline int apollon_plus(void)
35{
36 /* The apollon plus has IDCODE revision 5 */
37 return system_rev & 0xc0;
38}
39
34/* Placeholder for APOLLON specific defines */ 40/* Placeholder for APOLLON specific defines */
35#define APOLLON_ETHR_GPIO_IRQ 74 41#define APOLLON_ETHR_GPIO_IRQ 74
36 42
diff --git a/arch/arm/plat-omap/include/mach/board-h4.h b/arch/arm/plat-omap/include/mach/board-h4.h
index 1470cd3e519b..7c3fa0f0a65e 100644
--- a/arch/arm/plat-omap/include/mach/board-h4.h
+++ b/arch/arm/plat-omap/include/mach/board-h4.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/board-h4.h 2 * arch/arm/plat-omap/include/mach/board-h4.h
3 * 3 *
4 * Hardware definitions for TI OMAP1610 H4 board. 4 * Hardware definitions for TI OMAP2420 H4 board.
5 * 5 *
6 * Initial creation by Dirk Behme <dirk.behme@de.bosch.com> 6 * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
7 * 7 *
@@ -29,6 +29,9 @@
29#ifndef __ASM_ARCH_OMAP_H4_H 29#ifndef __ASM_ARCH_OMAP_H4_H
30#define __ASM_ARCH_OMAP_H4_H 30#define __ASM_ARCH_OMAP_H4_H
31 31
32/* MMC Prototypes */
33extern void h4_mmc_init(void);
34
32/* Placeholder for H4 specific defines */ 35/* Placeholder for H4 specific defines */
33#define OMAP24XX_ETHR_GPIO_IRQ 92 36#define OMAP24XX_ETHR_GPIO_IRQ 92
34#endif /* __ASM_ARCH_OMAP_H4_H */ 37#endif /* __ASM_ARCH_OMAP_H4_H */
diff --git a/arch/arm/plat-omap/include/mach/board-ldp.h b/arch/arm/plat-omap/include/mach/board-ldp.h
new file mode 100644
index 000000000000..66e2746c04ca
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-ldp.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/plat-omap/include/mach/board-ldp.h
3 *
4 * Hardware definitions for TI OMAP3 LDP.
5 *
6 * Copyright (C) 2008 Texas Instruments Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_LDP_H
30#define __ASM_ARCH_OMAP_LDP_H
31
32extern void twl4030_bci_battery_init(void);
33
34#define TWL4030_IRQNUM INT_34XX_SYS_NIRQ
35
36#endif /* __ASM_ARCH_OMAP_LDP_H */
diff --git a/arch/arm/plat-omap/include/mach/board-omap3beagle.h b/arch/arm/plat-omap/include/mach/board-omap3beagle.h
new file mode 100644
index 000000000000..3080d52d877a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-omap3beagle.h
@@ -0,0 +1,33 @@
1/*
2 * arch/arm/plat-omap/include/mach/board-omap3beagle.h
3 *
4 * Hardware definitions for TI OMAP3 BEAGLE.
5 *
6 * Initial creation by Syed Mohammed Khasim <khasim@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP3_BEAGLE_H
30#define __ASM_ARCH_OMAP3_BEAGLE_H
31
32#endif /* __ASM_ARCH_OMAP3_BEAGLE_H */
33
diff --git a/arch/arm/plat-omap/include/mach/board-overo.h b/arch/arm/plat-omap/include/mach/board-overo.h
new file mode 100644
index 000000000000..7ecae66966d1
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-overo.h
@@ -0,0 +1,26 @@
1/*
2 * board-overo.h (Gumstix Overo)
3 *
4 * Initial code: Steve Sakoman <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 675 Mass Ave, Cambridge, MA 02139, USA.
14 */
15
16#ifndef __ASM_ARCH_OVERO_H
17#define __ASM_ARCH_OVERO_H
18
19#define OVERO_GPIO_BT_XGATE 15
20#define OVERO_GPIO_W2W_NRESET 16
21#define OVERO_GPIO_BT_NRESET 164
22#define OVERO_GPIO_USBH_CPEN 168
23#define OVERO_GPIO_USBH_NRESET 183
24
25#endif /* ____ASM_ARCH_OVERO_H */
26
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h
index 54445642f35d..c23c12ccb353 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/mach/board.h
@@ -45,6 +45,8 @@ struct omap_mmc_conf {
45 unsigned cover:1; 45 unsigned cover:1;
46 /* 4 wire signaling is optional, and is only used for SD/SDIO */ 46 /* 4 wire signaling is optional, and is only used for SD/SDIO */
47 unsigned wire4:1; 47 unsigned wire4:1;
48 /* use the internal clock */
49 unsigned internal_clock:1;
48 s16 power_pin; 50 s16 power_pin;
49 s16 switch_pin; 51 s16 switch_pin;
50 s16 wp_pin; 52 s16 wp_pin;
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 92f7c7238fcd..719298554ed7 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -15,6 +15,7 @@
15 15
16struct module; 16struct module;
17struct clk; 17struct clk;
18struct clockdomain;
18 19
19#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 20#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
20 21
@@ -79,6 +80,8 @@ struct clk {
79 u32 clksel_mask; 80 u32 clksel_mask;
80 const struct clksel *clksel; 81 const struct clksel *clksel;
81 struct dpll_data *dpll_data; 82 struct dpll_data *dpll_data;
83 const char *clkdm_name;
84 struct clockdomain *clkdm;
82#else 85#else
83 __u8 rate_offset; 86 __u8 rate_offset;
84 __u8 src_offset; 87 __u8 src_offset;
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h
new file mode 100644
index 000000000000..1f51f0173784
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/clockdomain.h
@@ -0,0 +1,106 @@
1/*
2 * linux/include/asm-arm/arch-omap/clockdomain.h
3 *
4 * OMAP2/3 clockdomain framework functions
5 *
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
17#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
18
19#include <mach/powerdomain.h>
20#include <mach/clock.h>
21#include <mach/cpu.h>
22
23/* Clockdomain capability flags */
24#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
25#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
26#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
27#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
28
29#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
30#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
31#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
32
33/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
34#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
35#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
36
37/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
38#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
39#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
40#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
41#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
42
43/*
44 * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
45 * and sleepdeps added when a powerdomain should stay active in hwsup mode;
46 * and conversely, removed when the powerdomain should be allowed to go
47 * inactive in hwsup mode.
48 */
49struct clkdm_pwrdm_autodep {
50
51 /* Name of the powerdomain to add a wkdep/sleepdep on */
52 const char *pwrdm_name;
53
54 /* Powerdomain pointer (looked up at clkdm_init() time) */
55 struct powerdomain *pwrdm;
56
57 /* OMAP chip types that this clockdomain dep is valid on */
58 const struct omap_chip_id omap_chip;
59
60};
61
62struct clockdomain {
63
64 /* Clockdomain name */
65 const char *name;
66
67 /* Powerdomain enclosing this clockdomain */
68 const char *pwrdm_name;
69
70 /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
71 const u16 clktrctrl_mask;
72
73 /* Clockdomain capability flags */
74 const u8 flags;
75
76 /* OMAP chip types that this clockdomain is valid on */
77 const struct omap_chip_id omap_chip;
78
79 /* Usecount tracking */
80 atomic_t usecount;
81
82 /* Powerdomain pointer assigned at clkdm_register() */
83 struct powerdomain *pwrdm;
84
85 struct list_head node;
86
87};
88
89void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
90int clkdm_register(struct clockdomain *clkdm);
91int clkdm_unregister(struct clockdomain *clkdm);
92struct clockdomain *clkdm_lookup(const char *name);
93
94int clkdm_for_each(int (*fn)(struct clockdomain *clkdm));
95struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
96
97void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
98void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
99
100int omap2_clkdm_wakeup(struct clockdomain *clkdm);
101int omap2_clkdm_sleep(struct clockdomain *clkdm);
102
103int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
104int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
105
106#endif
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h
index 06093112b665..ef70e2b0f054 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/mach/common.h
@@ -34,6 +34,7 @@ struct sys_timer;
34extern void omap_map_common_io(void); 34extern void omap_map_common_io(void);
35extern struct sys_timer omap_timer; 35extern struct sys_timer omap_timer;
36extern void omap_serial_init(void); 36extern void omap_serial_init(void);
37extern void omap_serial_enable_clocks(int enable);
37#ifdef CONFIG_I2C_OMAP 38#ifdef CONFIG_I2C_OMAP
38extern int omap_register_i2c_bus(int bus_id, u32 clkrate, 39extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
39 struct i2c_board_info const *info, 40 struct i2c_board_info const *info,
@@ -49,6 +50,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
49 50
50/* IO bases for various OMAP processors */ 51/* IO bases for various OMAP processors */
51struct omap_globals { 52struct omap_globals {
53 u32 class; /* OMAP class to detect */
52 void __iomem *tap; /* Control module ID code */ 54 void __iomem *tap; /* Control module ID code */
53 void __iomem *sdrc; /* SDRAM Controller */ 55 void __iomem *sdrc; /* SDRAM Controller */
54 void __iomem *sms; /* SDRAM Memory Scheduler */ 56 void __iomem *sms; /* SDRAM Memory Scheduler */
@@ -62,6 +64,7 @@ void omap2_set_globals_243x(void);
62void omap2_set_globals_343x(void); 64void omap2_set_globals_343x(void);
63 65
64/* These get called from omap2_set_globals_xxxx(), do not call these */ 66/* These get called from omap2_set_globals_xxxx(), do not call these */
67void omap2_set_globals_tap(struct omap_globals *);
65void omap2_set_globals_memory(struct omap_globals *); 68void omap2_set_globals_memory(struct omap_globals *);
66void omap2_set_globals_control(struct omap_globals *); 69void omap2_set_globals_control(struct omap_globals *);
67void omap2_set_globals_prcm(struct omap_globals *); 70void omap2_set_globals_prcm(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index e3fd62d9a995..dc9886760577 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -1,13 +1,10 @@
1#ifndef __ASM_ARCH_CONTROL_H
2#define __ASM_ARCH_CONTROL_H
3
4/* 1/*
5 * arch/arm/plat-omap/include/mach/control.h 2 * arch/arm/plat-omap/include/mach/control.h
6 * 3 *
7 * OMAP2/3 System Control Module definitions 4 * OMAP2/3 System Control Module definitions
8 * 5 *
9 * Copyright (C) 2007 Texas Instruments, Inc. 6 * Copyright (C) 2007-2008 Texas Instruments, Inc.
10 * Copyright (C) 2007 Nokia Corporation 7 * Copyright (C) 2007-2008 Nokia Corporation
11 * 8 *
12 * Written by Paul Walmsley 9 * Written by Paul Walmsley
13 * 10 *
@@ -16,14 +13,23 @@
16 * the Free Software Foundation. 13 * the Free Software Foundation.
17 */ 14 */
18 15
16#ifndef __ASM_ARCH_CONTROL_H
17#define __ASM_ARCH_CONTROL_H
18
19#include <mach/io.h> 19#include <mach/io.h>
20 20
21#ifndef __ASSEMBLY__
21#define OMAP242X_CTRL_REGADDR(reg) \ 22#define OMAP242X_CTRL_REGADDR(reg) \
22 (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 23 IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
23#define OMAP243X_CTRL_REGADDR(reg) \ 24#define OMAP243X_CTRL_REGADDR(reg) \
24 (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 25 IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
25#define OMAP343X_CTRL_REGADDR(reg) \ 26#define OMAP343X_CTRL_REGADDR(reg) \
26 (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 27 IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#else
29#define OMAP242X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
30#define OMAP243X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
31#define OMAP343X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
32#endif /* __ASSEMBLY__ */
27 33
28/* 34/*
29 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 35 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
@@ -134,6 +140,7 @@
134#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 140#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
135#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 141#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
136#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 142#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
143#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
137 144
138/* 145/*
139 * REVISIT: This list of registers is not comprehensive - there are more 146 * REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 05aee0eda34f..e0464187209d 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -346,9 +346,14 @@ IS_OMAP_TYPE(3430, 0x3430)
346 get_sil_revision(system_rev) 346 get_sil_revision(system_rev)
347 347
348/* Various silicon macros defined here */ 348/* Various silicon macros defined here */
349#define OMAP242X_CLASS 0x24200000
349#define OMAP2420_REV_ES1_0 0x24200000 350#define OMAP2420_REV_ES1_0 0x24200000
350#define OMAP2420_REV_ES2_0 0x24201000 351#define OMAP2420_REV_ES2_0 0x24201000
352
353#define OMAP243X_CLASS 0x24300000
351#define OMAP2430_REV_ES1_0 0x24300000 354#define OMAP2430_REV_ES1_0 0x24300000
355
356#define OMAP343X_CLASS 0x34300000
352#define OMAP3430_REV_ES1_0 0x34300000 357#define OMAP3430_REV_ES1_0 0x34300000
353#define OMAP3430_REV_ES2_0 0x34301000 358#define OMAP3430_REV_ES2_0 0x34301000
354#define OMAP3430_REV_ES2_1 0x34302000 359#define OMAP3430_REV_ES2_1 0x34302000
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
index 1b0039bdeb4e..1b11f5c6a2d9 100644
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ b/arch/arm/plat-omap/include/mach/debug-macro.S
@@ -35,6 +35,18 @@
35#ifdef CONFIG_OMAP_LL_DEBUG_UART3 35#ifdef CONFIG_OMAP_LL_DEBUG_UART3
36 add \rx, \rx, #0x00004000 @ UART 3 36 add \rx, \rx, #0x00004000 @ UART 3
37#endif 37#endif
38
39#elif CONFIG_ARCH_OMAP3
40 moveq \rx, #0x48000000 @ physical base address
41 movne \rx, #0xd8000000 @ virtual base
42 orr \rx, \rx, #0x0006a000
43#ifdef CONFIG_OMAP_LL_DEBUG_UART2
44 add \rx, \rx, #0x00002000 @ UART 2
45#endif
46#ifdef CONFIG_OMAP_LL_DEBUG_UART3
47 add \rx, \rx, #0x00fb0000 @ UART 3
48 add \rx, \rx, #0x00006000
49#endif
38#endif 50#endif
39 .endm 51 .endm
40 52
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index d4e9043bf201..030118ee204a 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -55,9 +55,17 @@
551510: 551510:
56 .endm 56 .endm
57 57
58#elif defined(CONFIG_ARCH_OMAP24XX) 58#endif
59#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
59 60
61#if defined(CONFIG_ARCH_OMAP24XX)
60#include <mach/omap24xx.h> 62#include <mach/omap24xx.h>
63#endif
64#if defined(CONFIG_ARCH_OMAP34XX)
65#include <mach/omap34xx.h>
66#endif
67
68#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt number */
61 69
62 .macro disable_fiq 70 .macro disable_fiq
63 .endm 71 .endm
@@ -79,7 +87,7 @@
79 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ 87 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
80 cmp \irqnr, #0x0 88 cmp \irqnr, #0x0
812222: 892222:
82 ldrne \irqnr, [\base, #IRQ_SIR_IRQ] 90 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
83 91
84 .endm 92 .endm
85 93
diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/mach/fpga.h
index c92e4b42b289..f1864a652f7a 100644
--- a/arch/arm/plat-omap/include/mach/fpga.h
+++ b/arch/arm/plat-omap/include/mach/fpga.h
@@ -34,9 +34,9 @@ extern void omap1510_fpga_init_irq(void);
34 * --------------------------------------------------------------------------- 34 * ---------------------------------------------------------------------------
35 */ 35 */
36/* maps in the FPGA registers and the ETHR registers */ 36/* maps in the FPGA registers and the ETHR registers */
37#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ 37#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ 38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ 39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
40 40
41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) 41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ 42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
@@ -85,9 +85,9 @@ struct h2p2_dbg_fpga {
85 * OMAP-1510 FPGA 85 * OMAP-1510 FPGA
86 * --------------------------------------------------------------------------- 86 * ---------------------------------------------------------------------------
87 */ 87 */
88#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */ 88#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
89#define OMAP1510_FPGA_SIZE SZ_4K 89#define OMAP1510_FPGA_SIZE SZ_4K
90#define OMAP1510_FPGA_START 0x08000000 /* Physical */ 90#define OMAP1510_FPGA_START 0x08000000 /* PA */
91 91
92/* Revision */ 92/* Revision */
93#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) 93#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 8c71e288860f..98e9008b7e9d 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -29,7 +29,7 @@
29#include <linux/io.h> 29#include <linux/io.h>
30#include <mach/irqs.h> 30#include <mach/irqs.h>
31 31
32#define OMAP_MPUIO_BASE (void __iomem *)0xfffb5000 32#define OMAP_MPUIO_BASE 0xfffb5000
33 33
34#ifdef CONFIG_ARCH_OMAP730 34#ifdef CONFIG_ARCH_OMAP730
35#define OMAP_MPUIO_INPUT_LATCH 0x00 35#define OMAP_MPUIO_INPUT_LATCH 0x00
@@ -76,6 +76,8 @@ extern void omap_free_gpio(int gpio);
76extern void omap_set_gpio_direction(int gpio, int is_input); 76extern void omap_set_gpio_direction(int gpio, int is_input);
77extern void omap_set_gpio_dataout(int gpio, int enable); 77extern void omap_set_gpio_dataout(int gpio, int enable);
78extern int omap_get_gpio_datain(int gpio); 78extern int omap_get_gpio_datain(int gpio);
79extern void omap2_gpio_prepare_for_retention(void);
80extern void omap2_gpio_resume_after_retention(void);
79extern void omap_set_gpio_debounce(int gpio, int enable); 81extern void omap_set_gpio_debounce(int gpio, int enable);
80extern void omap_set_gpio_debounce_time(int gpio, int enable); 82extern void omap_set_gpio_debounce_time(int gpio, int enable);
81 83
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h
index 6a8e07ffc2d0..45b678439bb7 100644
--- a/arch/arm/plat-omap/include/mach/gpmc.h
+++ b/arch/arm/plat-omap/include/mach/gpmc.h
@@ -11,6 +11,9 @@
11#ifndef __OMAP2_GPMC_H 11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H 12#define __OMAP2_GPMC_H
13 13
14/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8
16
14#define GPMC_CS_CONFIG1 0x00 17#define GPMC_CS_CONFIG1 0x00
15#define GPMC_CS_CONFIG2 0x04 18#define GPMC_CS_CONFIG2 0x04
16#define GPMC_CS_CONFIG3 0x08 19#define GPMC_CS_CONFIG3 0x08
@@ -22,6 +25,9 @@
22#define GPMC_CS_NAND_ADDRESS 0x20 25#define GPMC_CS_NAND_ADDRESS 0x20
23#define GPMC_CS_NAND_DATA 0x24 26#define GPMC_CS_NAND_DATA 0x24
24 27
28#define GPMC_CONFIG 0x50
29#define GPMC_STATUS 0x54
30
25#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 31#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
26#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 32#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
27#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 33#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
@@ -78,9 +84,14 @@ struct gpmc_timings {
78 u16 access; /* Start-cycle to first data valid delay */ 84 u16 access; /* Start-cycle to first data valid delay */
79 u16 rd_cycle; /* Total read cycle time */ 85 u16 rd_cycle; /* Total read cycle time */
80 u16 wr_cycle; /* Total write cycle time */ 86 u16 wr_cycle; /* Total write cycle time */
87
88 /* The following are only on OMAP3430 */
89 u16 wr_access; /* WRACCESSTIME */
90 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
81}; 91};
82 92
83extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); 93extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
94extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
84extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); 95extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
85extern unsigned long gpmc_get_fclk_period(void); 96extern unsigned long gpmc_get_fclk_period(void);
86 97
@@ -92,5 +103,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
92extern void gpmc_cs_free(int cs); 103extern void gpmc_cs_free(int cs);
93extern int gpmc_cs_set_reserved(int cs, int reserved); 104extern int gpmc_cs_set_reserved(int cs, int reserved);
94extern int gpmc_cs_reserved(int cs); 105extern int gpmc_cs_reserved(int cs);
106extern void gpmc_init(void);
95 107
96#endif 108#endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 07f5d7f21528..6589ddbb63b2 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -89,7 +89,7 @@
89#define DPLL_CTL (0xfffecf00) 89#define DPLL_CTL (0xfffecf00)
90 90
91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ 91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
92#define DSP_CONFIG_REG_BASE (0xe1008000) 92#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) 93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) 94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) 95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
@@ -282,8 +282,8 @@
282 282
283#include "omap730.h" 283#include "omap730.h"
284#include "omap1510.h" 284#include "omap1510.h"
285#include "omap24xx.h"
286#include "omap16xx.h" 285#include "omap16xx.h"
286#include "omap24xx.h"
287#include "omap34xx.h" 287#include "omap34xx.h"
288 288
289#ifndef __ASSEMBLER__ 289#ifndef __ASSEMBLER__
@@ -322,6 +322,14 @@
322#include "board-2430sdp.h" 322#include "board-2430sdp.h"
323#endif 323#endif
324 324
325#ifdef CONFIG_MACH_OMAP3_BEAGLE
326#include "board-omap3beagle.h"
327#endif
328
329#ifdef CONFIG_MACH_OMAP_LDP
330#include "board-ldp.h"
331#endif
332
325#ifdef CONFIG_MACH_OMAP_APOLLON 333#ifdef CONFIG_MACH_OMAP_APOLLON
326#include "board-apollon.h" 334#include "board-apollon.h"
327#endif 335#endif
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 2a30b7d88cde..adc83b7b8205 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -55,14 +55,13 @@
55 55
56#if defined(CONFIG_ARCH_OMAP1) 56#if defined(CONFIG_ARCH_OMAP1)
57 57
58#define IO_PHYS 0xFFFB0000 58#define IO_PHYS 0xFFFB0000
59#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ 59#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
60#define IO_SIZE 0x40000 60#define IO_SIZE 0x40000
61#define IO_VIRT (IO_PHYS - IO_OFFSET) 61#define IO_VIRT (IO_PHYS - IO_OFFSET)
62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET) 62#define __IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET) 63#define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
64#define io_p2v(pa) ((pa) - IO_OFFSET) 64#define io_v2p(va) ((va) + IO_OFFSET)
65#define io_v2p(va) ((va) + IO_OFFSET)
66 65
67#elif defined(CONFIG_ARCH_OMAP2) 66#elif defined(CONFIG_ARCH_OMAP2)
68 67
@@ -74,7 +73,6 @@
74#define L4_24XX_VIRT 0xd8000000 73#define L4_24XX_VIRT 0xd8000000
75#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 74#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
76 75
77#ifdef CONFIG_ARCH_OMAP2430
78#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ 76#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
79#define L4_WK_243X_VIRT 0xd9000000 77#define L4_WK_243X_VIRT 0xd9000000
80#define L4_WK_243X_SIZE SZ_1M 78#define L4_WK_243X_SIZE SZ_1M
@@ -88,13 +86,10 @@
88#define OMAP243X_SMS_VIRT 0xFC000000 86#define OMAP243X_SMS_VIRT 0xFC000000
89#define OMAP243X_SMS_SIZE SZ_1M 87#define OMAP243X_SMS_SIZE SZ_1M
90 88
91#endif 89#define IO_OFFSET 0x90000000
92 90#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
93#define IO_OFFSET 0x90000000 91#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
94#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 92#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
95#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
96#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
97#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
98 93
99/* DSP */ 94/* DSP */
100#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */ 95#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
@@ -149,9 +144,8 @@
149 144
150 145
151#define IO_OFFSET 0x90000000 146#define IO_OFFSET 0x90000000
152#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 147#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
153#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 148#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
154#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
155#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ 149#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
156 150
157/* DSP */ 151/* DSP */
@@ -167,7 +161,14 @@
167 161
168#endif 162#endif
169 163
170#ifndef __ASSEMBLER__ 164#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
165#define OMAP1_IO_ADDRESS(pa) IOMEM(__OMAP1_IO_ADDRESS(pa))
166#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
167
168#ifdef __ASSEMBLER__
169#define IOMEM(x) x
170#else
171#define IOMEM(x) ((void __force __iomem *)(x))
171 172
172/* 173/*
173 * Functions to access the OMAP IO region 174 * Functions to access the OMAP IO region
@@ -178,13 +179,13 @@
178 * - DO NOT use hardcoded virtual addresses to allow changing the 179 * - DO NOT use hardcoded virtual addresses to allow changing the
179 * IO address space again if needed 180 * IO address space again if needed
180 */ 181 */
181#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) 182#define omap_readb(a) __raw_readb(IO_ADDRESS(a))
182#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) 183#define omap_readw(a) __raw_readw(IO_ADDRESS(a))
183#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) 184#define omap_readl(a) __raw_readl(IO_ADDRESS(a))
184 185
185#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) 186#define omap_writeb(v,a) __raw_writeb(v, IO_ADDRESS(a))
186#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) 187#define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a))
187#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) 188#define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a))
188 189
189extern void omap1_map_common_io(void); 190extern void omap1_map_common_io(void);
190extern void omap1_init_common_hw(void); 191extern void omap1_init_common_hw(void);
@@ -192,6 +193,12 @@ extern void omap1_init_common_hw(void);
192extern void omap2_map_common_io(void); 193extern void omap2_map_common_io(void);
193extern void omap2_init_common_hw(void); 194extern void omap2_init_common_hw(void);
194 195
196#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
197#define __arch_iounmap(v) omap_iounmap(v)
198
199void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
200void omap_iounmap(volatile void __iomem *addr);
201
195#endif 202#endif
196 203
197#endif 204#endif
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 62aa7dfb9464..a2929ac8c687 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -125,6 +125,7 @@
125#define INT_UART2 (15 + IH2_BASE) 125#define INT_UART2 (15 + IH2_BASE)
126#define INT_BT_MCSI1TX (16 + IH2_BASE) 126#define INT_BT_MCSI1TX (16 + IH2_BASE)
127#define INT_BT_MCSI1RX (17 + IH2_BASE) 127#define INT_BT_MCSI1RX (17 + IH2_BASE)
128#define INT_SOSSI_MATCH (19 + IH2_BASE)
128#define INT_USB_W2FC (20 + IH2_BASE) 129#define INT_USB_W2FC (20 + IH2_BASE)
129#define INT_1WIRE (21 + IH2_BASE) 130#define INT_1WIRE (21 + IH2_BASE)
130#define INT_OS_TIMER (22 + IH2_BASE) 131#define INT_OS_TIMER (22 + IH2_BASE)
@@ -176,6 +177,7 @@
176#define INT_1610_DMA_CH14 (61 + IH2_BASE) 177#define INT_1610_DMA_CH14 (61 + IH2_BASE)
177#define INT_1610_DMA_CH15 (62 + IH2_BASE) 178#define INT_1610_DMA_CH15 (62 + IH2_BASE)
178#define INT_1610_NAND (63 + IH2_BASE) 179#define INT_1610_NAND (63 + IH2_BASE)
180#define INT_1610_SHA1MD5 (91 + IH2_BASE)
179 181
180/* 182/*
181 * OMAP-730 specific IRQ numbers for interrupt handler 2 183 * OMAP-730 specific IRQ numbers for interrupt handler 2
@@ -263,12 +265,18 @@
263#define INT_24XX_GPTIMER10 46 265#define INT_24XX_GPTIMER10 46
264#define INT_24XX_GPTIMER11 47 266#define INT_24XX_GPTIMER11 47
265#define INT_24XX_GPTIMER12 48 267#define INT_24XX_GPTIMER12 48
268#define INT_24XX_SHA1MD5 51
269#define INT_24XX_MCBSP4_IRQ_TX 54
270#define INT_24XX_MCBSP4_IRQ_RX 55
266#define INT_24XX_I2C1_IRQ 56 271#define INT_24XX_I2C1_IRQ 56
267#define INT_24XX_I2C2_IRQ 57 272#define INT_24XX_I2C2_IRQ 57
273#define INT_24XX_HDQ_IRQ 58
268#define INT_24XX_MCBSP1_IRQ_TX 59 274#define INT_24XX_MCBSP1_IRQ_TX 59
269#define INT_24XX_MCBSP1_IRQ_RX 60 275#define INT_24XX_MCBSP1_IRQ_RX 60
270#define INT_24XX_MCBSP2_IRQ_TX 62 276#define INT_24XX_MCBSP2_IRQ_TX 62
271#define INT_24XX_MCBSP2_IRQ_RX 63 277#define INT_24XX_MCBSP2_IRQ_RX 63
278#define INT_24XX_SPI1_IRQ 65
279#define INT_24XX_SPI2_IRQ 66
272#define INT_24XX_UART1_IRQ 72 280#define INT_24XX_UART1_IRQ 72
273#define INT_24XX_UART2_IRQ 73 281#define INT_24XX_UART2_IRQ 73
274#define INT_24XX_UART3_IRQ 74 282#define INT_24XX_UART3_IRQ 74
@@ -278,7 +286,58 @@
278#define INT_24XX_USB_IRQ_HGEN 78 286#define INT_24XX_USB_IRQ_HGEN 78
279#define INT_24XX_USB_IRQ_HSOF 79 287#define INT_24XX_USB_IRQ_HSOF 79
280#define INT_24XX_USB_IRQ_OTG 80 288#define INT_24XX_USB_IRQ_OTG 80
289#define INT_24XX_MCBSP5_IRQ_TX 81
290#define INT_24XX_MCBSP5_IRQ_RX 82
281#define INT_24XX_MMC_IRQ 83 291#define INT_24XX_MMC_IRQ 83
292#define INT_24XX_MMC2_IRQ 86
293#define INT_24XX_MCBSP3_IRQ_TX 89
294#define INT_24XX_MCBSP3_IRQ_RX 90
295#define INT_24XX_SPI3_IRQ 91
296
297#define INT_243X_MCBSP2_IRQ 16
298#define INT_243X_MCBSP3_IRQ 17
299#define INT_243X_MCBSP4_IRQ 18
300#define INT_243X_MCBSP5_IRQ 19
301#define INT_243X_MCBSP1_IRQ 64
302#define INT_243X_HS_USB_MC 92
303#define INT_243X_HS_USB_DMA 93
304#define INT_243X_CARKIT_IRQ 94
305
306#define INT_34XX_BENCH_MPU_EMUL 3
307#define INT_34XX_ST_MCBSP2_IRQ 4
308#define INT_34XX_ST_MCBSP3_IRQ 5
309#define INT_34XX_SSM_ABORT_IRQ 6
310#define INT_34XX_SYS_NIRQ 7
311#define INT_34XX_D2D_FW_IRQ 8
312#define INT_34XX_PRCM_MPU_IRQ 11
313#define INT_34XX_MCBSP1_IRQ 16
314#define INT_34XX_MCBSP2_IRQ 17
315#define INT_34XX_MCBSP3_IRQ 22
316#define INT_34XX_MCBSP4_IRQ 23
317#define INT_34XX_CAM_IRQ 24
318#define INT_34XX_MCBSP5_IRQ 27
319#define INT_34XX_GPIO_BANK1 29
320#define INT_34XX_GPIO_BANK2 30
321#define INT_34XX_GPIO_BANK3 31
322#define INT_34XX_GPIO_BANK4 32
323#define INT_34XX_GPIO_BANK5 33
324#define INT_34XX_GPIO_BANK6 34
325#define INT_34XX_USIM_IRQ 35
326#define INT_34XX_WDT3_IRQ 36
327#define INT_34XX_SPI4_IRQ 48
328#define INT_34XX_SHA1MD52_IRQ 49
329#define INT_34XX_FPKA_READY_IRQ 50
330#define INT_34XX_SHA1MD51_IRQ 51
331#define INT_34XX_RNG_IRQ 52
332#define INT_34XX_I2C3_IRQ 61
333#define INT_34XX_FPKA_ERROR_IRQ 64
334#define INT_34XX_PBIAS_IRQ 75
335#define INT_34XX_OHCI_IRQ 76
336#define INT_34XX_EHCI_IRQ 77
337#define INT_34XX_TLL_IRQ 78
338#define INT_34XX_PARTHASH_IRQ 79
339#define INT_34XX_MMC3_IRQ 94
340#define INT_34XX_GPT12_IRQ 95
282 341
283#define INT_34XX_BENCH_MPU_EMUL 3 342#define INT_34XX_BENCH_MPU_EMUL 3
284 343
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index 8fdb95e26fcd..6a0d1a0a24a7 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -43,9 +43,15 @@
43 43
44#define OMAP24XX_MCBSP1_BASE 0x48074000 44#define OMAP24XX_MCBSP1_BASE 0x48074000
45#define OMAP24XX_MCBSP2_BASE 0x48076000 45#define OMAP24XX_MCBSP2_BASE 0x48076000
46#define OMAP2430_MCBSP3_BASE 0x4808c000
47#define OMAP2430_MCBSP4_BASE 0x4808e000
48#define OMAP2430_MCBSP5_BASE 0x48096000
46 49
47#define OMAP34XX_MCBSP1_BASE 0x48074000 50#define OMAP34XX_MCBSP1_BASE 0x48074000
48#define OMAP34XX_MCBSP2_BASE 0x49022000 51#define OMAP34XX_MCBSP2_BASE 0x49022000
52#define OMAP34XX_MCBSP3_BASE 0x49024000
53#define OMAP34XX_MCBSP4_BASE 0x49026000
54#define OMAP34XX_MCBSP5_BASE 0x48096000
49 55
50#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 56#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
51 57
@@ -81,9 +87,6 @@
81#define OMAP_MCBSP_REG_XCERG 0x3A 87#define OMAP_MCBSP_REG_XCERG 0x3A
82#define OMAP_MCBSP_REG_XCERH 0x3C 88#define OMAP_MCBSP_REG_XCERH 0x3C
83 89
84#define OMAP_MAX_MCBSP_COUNT 3
85#define MAX_MCBSP_CLOCKS 3
86
87#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) 90#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
88#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) 91#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
89 92
@@ -91,12 +94,14 @@
91#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX 94#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
92#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX 95#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
93 96
94#elif defined(CONFIG_ARCH_OMAP24XX) 97#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
95 98
96#define OMAP_MCBSP_REG_DRR2 0x00 99#define OMAP_MCBSP_REG_DRR2 0x00
97#define OMAP_MCBSP_REG_DRR1 0x04 100#define OMAP_MCBSP_REG_DRR1 0x04
98#define OMAP_MCBSP_REG_DXR2 0x08 101#define OMAP_MCBSP_REG_DXR2 0x08
99#define OMAP_MCBSP_REG_DXR1 0x0C 102#define OMAP_MCBSP_REG_DXR1 0x0C
103#define OMAP_MCBSP_REG_DRR 0x00
104#define OMAP_MCBSP_REG_DXR 0x08
100#define OMAP_MCBSP_REG_SPCR2 0x10 105#define OMAP_MCBSP_REG_SPCR2 0x10
101#define OMAP_MCBSP_REG_SPCR1 0x14 106#define OMAP_MCBSP_REG_SPCR1 0x14
102#define OMAP_MCBSP_REG_RCR2 0x18 107#define OMAP_MCBSP_REG_RCR2 0x18
@@ -124,9 +129,9 @@
124#define OMAP_MCBSP_REG_RCERH 0x70 129#define OMAP_MCBSP_REG_RCERH 0x70
125#define OMAP_MCBSP_REG_XCERG 0x74 130#define OMAP_MCBSP_REG_XCERG 0x74
126#define OMAP_MCBSP_REG_XCERH 0x78 131#define OMAP_MCBSP_REG_XCERH 0x78
127 132#define OMAP_MCBSP_REG_SYSCON 0x8C
128#define OMAP_MAX_MCBSP_COUNT 2 133#define OMAP_MCBSP_REG_XCCR 0xAC
129#define MAX_MCBSP_CLOCKS 2 134#define OMAP_MCBSP_REG_RCCR 0xB0
130 135
131#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) 136#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
132#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) 137#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -137,10 +142,6 @@
137 142
138#endif 143#endif
139 144
140#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
141#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
142
143
144/************************** McBSP SPCR1 bit definitions ***********************/ 145/************************** McBSP SPCR1 bit definitions ***********************/
145#define RRST 0x0001 146#define RRST 0x0001
146#define RRDY 0x0002 147#define RRDY 0x0002
@@ -151,6 +152,7 @@
151#define DXENA 0x0080 152#define DXENA 0x0080
152#define CLKSTP(value) ((value)<<11) /* bits 11:12 */ 153#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
153#define RJUST(value) ((value)<<13) /* bits 13:14 */ 154#define RJUST(value) ((value)<<13) /* bits 13:14 */
155#define ALB 0x8000
154#define DLB 0x8000 156#define DLB 0x8000
155 157
156/************************** McBSP SPCR2 bit definitions ***********************/ 158/************************** McBSP SPCR2 bit definitions ***********************/
@@ -228,6 +230,17 @@
228#define XPABLK(value) ((value)<<5) /* Bits 5:6 */ 230#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
229#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */ 231#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
230 232
233/*********************** McBSP XCCR bit definitions *************************/
234#define DILB 0x0020
235#define XDMAEN 0x0008
236#define XDISABLE 0x0001
237
238/********************** McBSP RCCR bit definitions *************************/
239#define RDMAEN 0x0008
240#define RDISABLE 0x0001
241
242/********************** McBSP SYSCONFIG bit definitions ********************/
243#define SOFTRST 0x0002
231 244
232/* we don't do multichannel for now */ 245/* we don't do multichannel for now */
233struct omap_mcbsp_reg_cfg { 246struct omap_mcbsp_reg_cfg {
@@ -260,6 +273,8 @@ typedef enum {
260 OMAP_MCBSP1 = 0, 273 OMAP_MCBSP1 = 0,
261 OMAP_MCBSP2, 274 OMAP_MCBSP2,
262 OMAP_MCBSP3, 275 OMAP_MCBSP3,
276 OMAP_MCBSP4,
277 OMAP_MCBSP5
263} omap_mcbsp_id; 278} omap_mcbsp_id;
264 279
265typedef int __bitwise omap_mcbsp_io_type_t; 280typedef int __bitwise omap_mcbsp_io_type_t;
@@ -311,12 +326,10 @@ struct omap_mcbsp_spi_cfg {
311struct omap_mcbsp_ops { 326struct omap_mcbsp_ops {
312 void (*request)(unsigned int); 327 void (*request)(unsigned int);
313 void (*free)(unsigned int); 328 void (*free)(unsigned int);
314 int (*check)(unsigned int);
315}; 329};
316 330
317struct omap_mcbsp_platform_data { 331struct omap_mcbsp_platform_data {
318 unsigned long phys_base; 332 unsigned long phys_base;
319 u32 virt_base;
320 u8 dma_rx_sync, dma_tx_sync; 333 u8 dma_rx_sync, dma_tx_sync;
321 u16 rx_irq, tx_irq; 334 u16 rx_irq, tx_irq;
322 struct omap_mcbsp_ops *ops; 335 struct omap_mcbsp_ops *ops;
@@ -326,7 +339,7 @@ struct omap_mcbsp_platform_data {
326struct omap_mcbsp { 339struct omap_mcbsp {
327 struct device *dev; 340 struct device *dev;
328 unsigned long phys_base; 341 unsigned long phys_base;
329 u32 io_base; 342 void __iomem *io_base;
330 u8 id; 343 u8 id;
331 u8 free; 344 u8 free;
332 omap_mcbsp_word_length rx_word_length; 345 omap_mcbsp_word_length rx_word_length;
@@ -354,6 +367,8 @@ struct omap_mcbsp {
354 struct omap_mcbsp_platform_data *pdata; 367 struct omap_mcbsp_platform_data *pdata;
355 struct clk *clk; 368 struct clk *clk;
356}; 369};
370extern struct omap_mcbsp **mcbsp_ptr;
371extern int omap_mcbsp_count;
357 372
358int omap_mcbsp_init(void); 373int omap_mcbsp_init(void);
359void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 374void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
@@ -378,5 +393,6 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
378/* Polled read/write functions */ 393/* Polled read/write functions */
379int omap_mcbsp_pollread(unsigned int id, u16 * buf); 394int omap_mcbsp_pollread(unsigned int id, u16 * buf);
380int omap_mcbsp_pollwrite(unsigned int id, u16 buf); 395int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
396int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
381 397
382#endif 398#endif
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
index a325caf80d04..d40cac60b959 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -38,7 +38,7 @@
38 */ 38 */
39#if defined(CONFIG_ARCH_OMAP1) 39#if defined(CONFIG_ARCH_OMAP1)
40#define PHYS_OFFSET UL(0x10000000) 40#define PHYS_OFFSET UL(0x10000000)
41#elif defined(CONFIG_ARCH_OMAP2) 41#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
42#define PHYS_OFFSET UL(0x80000000) 42#define PHYS_OFFSET UL(0x80000000)
43#endif 43#endif
44 44
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 614b2c1327c7..6bbf1789bed5 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -125,20 +125,64 @@
125 .pu_pd_val = pull_mode, \ 125 .pu_pd_val = pull_mode, \
126}, 126},
127 127
128 128/* 24xx/34xx mux bit defines */
129#define PULL_DISABLED 0 129#define OMAP2_PULL_ENA (1 << 3)
130#define PULL_ENABLED 1 130#define OMAP2_PULL_UP (1 << 4)
131 131#define OMAP2_ALTELECTRICALSEL (1 << 5)
132#define PULL_DOWN 0 132
133#define PULL_UP 1 133/* 34xx specific mux bit defines */
134#define OMAP3_INPUT_EN (1 << 8)
135#define OMAP3_OFF_EN (1 << 9)
136#define OMAP3_OFFOUT_EN (1 << 10)
137#define OMAP3_OFFOUT_VAL (1 << 11)
138#define OMAP3_OFF_PULL_EN (1 << 12)
139#define OMAP3_OFF_PULL_UP (1 << 13)
140#define OMAP3_WAKEUP_EN (1 << 14)
141
142/* 34xx mux mode options for each pin. See TRM for options */
143#define OMAP34XX_MUX_MODE0 0
144#define OMAP34XX_MUX_MODE1 1
145#define OMAP34XX_MUX_MODE2 2
146#define OMAP34XX_MUX_MODE3 3
147#define OMAP34XX_MUX_MODE4 4
148#define OMAP34XX_MUX_MODE5 5
149#define OMAP34XX_MUX_MODE6 6
150#define OMAP34XX_MUX_MODE7 7
151
152/* 34xx active pin states */
153#define OMAP34XX_PIN_OUTPUT 0
154#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
155#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
156 | OMAP2_PULL_UP)
157#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
158
159/* 34xx off mode states */
160#define OMAP34XX_PIN_OFF_NONE 0
161#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
162 | OMAP3_OFFOUT_VAL)
163#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
164#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
165 | OMAP3_OFF_PULL_UP)
166#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
167#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
168
169#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
170 .name = desc, \
171 .debug = 0, \
172 .mux_reg = reg_offset, \
173 .mux_val = mux_value \
174},
134 175
135struct pin_config { 176struct pin_config {
136 char *name; 177 char *name;
137 unsigned char busy; 178 const unsigned int mux_reg;
138 unsigned char debug; 179 unsigned char debug;
139 180
140 const char *mux_reg_name; 181#if defined(CONFIG_ARCH_OMAP34XX)
141 const unsigned int mux_reg; 182 u16 mux_val; /* Wake-up, off mode, pull, mux mode */
183#endif
184
185#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
142 const unsigned char mask_offset; 186 const unsigned char mask_offset;
143 const unsigned char mask; 187 const unsigned char mask;
144 188
@@ -150,6 +194,12 @@ struct pin_config {
150 const char *pu_pd_name; 194 const char *pu_pd_name;
151 const unsigned int pu_pd_reg; 195 const unsigned int pu_pd_reg;
152 const unsigned char pu_pd_val; 196 const unsigned char pu_pd_val;
197#endif
198
199#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
200 const char *mux_reg_name;
201#endif
202
153}; 203};
154 204
155enum omap730_index { 205enum omap730_index {
@@ -593,6 +643,114 @@ enum omap24xx_index {
593 643
594}; 644};
595 645
646enum omap34xx_index {
647 /* 34xx I2C */
648 K21_34XX_I2C1_SCL,
649 J21_34XX_I2C1_SDA,
650 AF15_34XX_I2C2_SCL,
651 AE15_34XX_I2C2_SDA,
652 AF14_34XX_I2C3_SCL,
653 AG14_34XX_I2C3_SDA,
654 AD26_34XX_I2C4_SCL,
655 AE26_34XX_I2C4_SDA,
656
657 /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
658 Y8_3430_USB1HS_PHY_CLK,
659 Y9_3430_USB1HS_PHY_STP,
660 AA14_3430_USB1HS_PHY_DIR,
661 AA11_3430_USB1HS_PHY_NXT,
662 W13_3430_USB1HS_PHY_DATA0,
663 W12_3430_USB1HS_PHY_DATA1,
664 W11_3430_USB1HS_PHY_DATA2,
665 Y11_3430_USB1HS_PHY_DATA3,
666 W9_3430_USB1HS_PHY_DATA4,
667 Y12_3430_USB1HS_PHY_DATA5,
668 W8_3430_USB1HS_PHY_DATA6,
669 Y13_3430_USB1HS_PHY_DATA7,
670
671 /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
672 AA8_3430_USB2HS_PHY_CLK,
673 AA10_3430_USB2HS_PHY_STP,
674 AA9_3430_USB2HS_PHY_DIR,
675 AB11_3430_USB2HS_PHY_NXT,
676 AB10_3430_USB2HS_PHY_DATA0,
677 AB9_3430_USB2HS_PHY_DATA1,
678 W3_3430_USB2HS_PHY_DATA2,
679 T4_3430_USB2HS_PHY_DATA3,
680 T3_3430_USB2HS_PHY_DATA4,
681 R3_3430_USB2HS_PHY_DATA5,
682 R4_3430_USB2HS_PHY_DATA6,
683 T2_3430_USB2HS_PHY_DATA7,
684
685
686 /* TLL - HSUSB: 12-pin TLL Port 1*/
687 Y8_3430_USB1HS_TLL_CLK,
688 Y9_3430_USB1HS_TLL_STP,
689 AA14_3430_USB1HS_TLL_DIR,
690 AA11_3430_USB1HS_TLL_NXT,
691 W13_3430_USB1HS_TLL_DATA0,
692 W12_3430_USB1HS_TLL_DATA1,
693 W11_3430_USB1HS_TLL_DATA2,
694 Y11_3430_USB1HS_TLL_DATA3,
695 W9_3430_USB1HS_TLL_DATA4,
696 Y12_3430_USB1HS_TLL_DATA5,
697 W8_3430_USB1HS_TLL_DATA6,
698 Y13_3430_USB1HS_TLL_DATA7,
699
700 /* TLL - HSUSB: 12-pin TLL Port 2*/
701 AA8_3430_USB2HS_TLL_CLK,
702 AA10_3430_USB2HS_TLL_STP,
703 AA9_3430_USB2HS_TLL_DIR,
704 AB11_3430_USB2HS_TLL_NXT,
705 AB10_3430_USB2HS_TLL_DATA0,
706 AB9_3430_USB2HS_TLL_DATA1,
707 W3_3430_USB2HS_TLL_DATA2,
708 T4_3430_USB2HS_TLL_DATA3,
709 T3_3430_USB2HS_TLL_DATA4,
710 R3_3430_USB2HS_TLL_DATA5,
711 R4_3430_USB2HS_TLL_DATA6,
712 T2_3430_USB2HS_TLL_DATA7,
713
714 /* TLL - HSUSB: 12-pin TLL Port 3*/
715 AA6_3430_USB3HS_TLL_CLK,
716 AB3_3430_USB3HS_TLL_STP,
717 AA3_3430_USB3HS_TLL_DIR,
718 Y3_3430_USB3HS_TLL_NXT,
719 AA5_3430_USB3HS_TLL_DATA0,
720 Y4_3430_USB3HS_TLL_DATA1,
721 Y5_3430_USB3HS_TLL_DATA2,
722 W5_3430_USB3HS_TLL_DATA3,
723 AB12_3430_USB3HS_TLL_DATA4,
724 AB13_3430_USB3HS_TLL_DATA5,
725 AA13_3430_USB3HS_TLL_DATA6,
726 AA12_3430_USB3HS_TLL_DATA7,
727
728 /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
729 AF10_3430_USB1FS_PHY_MM1_RXDP,
730 AG9_3430_USB1FS_PHY_MM1_RXDM,
731 W13_3430_USB1FS_PHY_MM1_RXRCV,
732 W12_3430_USB1FS_PHY_MM1_TXSE0,
733 W11_3430_USB1FS_PHY_MM1_TXDAT,
734 Y11_3430_USB1FS_PHY_MM1_TXEN_N,
735
736 /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
737 AF7_3430_USB2FS_PHY_MM2_RXDP,
738 AH7_3430_USB2FS_PHY_MM2_RXDM,
739 AB10_3430_USB2FS_PHY_MM2_RXRCV,
740 AB9_3430_USB2FS_PHY_MM2_TXSE0,
741 W3_3430_USB2FS_PHY_MM2_TXDAT,
742 T4_3430_USB2FS_PHY_MM2_TXEN_N,
743
744 /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
745 AH3_3430_USB3FS_PHY_MM3_RXDP,
746 AE3_3430_USB3FS_PHY_MM3_RXDM,
747 AD1_3430_USB3FS_PHY_MM3_RXRCV,
748 AE1_3430_USB3FS_PHY_MM3_TXSE0,
749 AD2_3430_USB3FS_PHY_MM3_TXDAT,
750 AC1_3430_USB3FS_PHY_MM3_TXEN_N,
751
752};
753
596struct omap_mux_cfg { 754struct omap_mux_cfg {
597 struct pin_config *pins; 755 struct pin_config *pins;
598 unsigned long size; 756 unsigned long size;
diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/mach/omap1510.h
index 505a38af8b22..d24004668138 100644
--- a/arch/arm/plat-omap/include/mach/omap1510.h
+++ b/arch/arm/plat-omap/include/mach/omap1510.h
@@ -44,5 +44,7 @@
44#define OMAP1510_DSPREG_SIZE SZ_128K 44#define OMAP1510_DSPREG_SIZE SZ_128K
45#define OMAP1510_DSPREG_START 0xE1000000 45#define OMAP1510_DSPREG_START 0xE1000000
46 46
47#define OMAP1510_DSP_MMU_BASE (0xfffed200)
48
47#endif /* __ASM_ARCH_OMAP15XX_H */ 49#endif /* __ASM_ARCH_OMAP15XX_H */
48 50
diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/mach/omap16xx.h
index c6c93afb2788..0e69b504c25f 100644
--- a/arch/arm/plat-omap/include/mach/omap16xx.h
+++ b/arch/arm/plat-omap/include/mach/omap16xx.h
@@ -44,6 +44,11 @@
44#define OMAP16XX_DSPREG_SIZE SZ_128K 44#define OMAP16XX_DSPREG_SIZE SZ_128K
45#define OMAP16XX_DSPREG_START 0xE1000000 45#define OMAP16XX_DSPREG_START 0xE1000000
46 46
47#define OMAP16XX_SEC_BASE 0xFFFE4000
48#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
49#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
50#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
51
47/* 52/*
48 * --------------------------------------------------------------------------- 53 * ---------------------------------------------------------------------------
49 * Interrupts 54 * Interrupts
@@ -190,7 +195,7 @@
190#define WSPR_DISABLE_0 (0x0000aaaa) 195#define WSPR_DISABLE_0 (0x0000aaaa)
191#define WSPR_DISABLE_1 (0x00005555) 196#define WSPR_DISABLE_1 (0x00005555)
192 197
193/* Mailbox */ 198#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
194#define OMAP16XX_MAILBOX_BASE (0xfffcf000) 199#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
195 200
196#endif /* __ASM_ARCH_OMAP16XX_H */ 201#endif /* __ASM_ARCH_OMAP16XX_H */
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h
index bb8319d66e9f..24335d4932f5 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/mach/omap24xx.h
@@ -39,7 +39,6 @@
39/* interrupt controller */ 39/* interrupt controller */
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) 40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000 41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42#define IRQ_SIR_IRQ 0x0040
43 42
44#define OMAP2420_CTRL_BASE L4_24XX_BASE 43#define OMAP2420_CTRL_BASE L4_24XX_BASE
45#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
@@ -48,6 +47,7 @@
48#define OMAP2420_PRM_BASE OMAP2420_CM_BASE 47#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
49#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) 48#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
50#define OMAP2420_SMS_BASE 0x68008000 49#define OMAP2420_SMS_BASE 0x68008000
50#define OMAP2420_GPMC_BASE 0x6800a000
51 51
52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) 52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000) 53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
index cae037d13079..ec67fb428607 100644
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ b/arch/arm/plat-omap/include/mach/omapfb.h
@@ -62,6 +62,7 @@
62#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000 62#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
63#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000 63#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
64#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000 64#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
65#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
65#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000 66#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
66 67
67/* Values from DSP must map to lower 16-bits */ 68/* Values from DSP must map to lower 16-bits */
@@ -305,6 +306,7 @@ struct lcd_ctrl {
305 int screen_width, 306 int screen_width,
306 int pos_x, int pos_y, int width, 307 int pos_x, int pos_y, int width,
307 int height, int color_mode); 308 int height, int color_mode);
309 int (*set_rotate) (int angle);
308 int (*setup_mem) (int plane, size_t size, 310 int (*setup_mem) (int plane, size_t size,
309 int mem_type, unsigned long *paddr); 311 int mem_type, unsigned long *paddr);
310 int (*mmap) (struct fb_info *info, 312 int (*mmap) (struct fb_info *info,
@@ -374,6 +376,7 @@ extern struct lcd_ctrl omap1_lcd_ctrl;
374extern struct lcd_ctrl omap2_disp_ctrl; 376extern struct lcd_ctrl omap2_disp_ctrl;
375#endif 377#endif
376 378
379extern void omapfb_reserve_sdram(void);
377extern void omapfb_register_panel(struct lcd_panel *panel); 380extern void omapfb_register_panel(struct lcd_panel *panel);
378extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); 381extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
379extern void omapfb_notify_clients(struct omapfb_device *fbdev, 382extern void omapfb_notify_clients(struct omapfb_device *fbdev,
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
index bfa09325a5ff..768eb6e7abcf 100644
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ b/arch/arm/plat-omap/include/mach/pm.h
@@ -39,11 +39,11 @@
39 * Register and offset definitions to be used in PM assembler code 39 * Register and offset definitions to be used in PM assembler code
40 * ---------------------------------------------------------------------------- 40 * ----------------------------------------------------------------------------
41 */ 41 */
42#define CLKGEN_REG_ASM_BASE io_p2v(0xfffece00) 42#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET 0x04 43#define ARM_IDLECT1_ASM_OFFSET 0x04
44#define ARM_IDLECT2_ASM_OFFSET 0x08 44#define ARM_IDLECT2_ASM_OFFSET 0x08
45 45
46#define TCMIF_ASM_BASE io_p2v(0xfffecc00) 46#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET 0x0c 47#define EMIFS_CONFIG_ASM_OFFSET 0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
49 49
@@ -135,7 +135,8 @@ extern void omap_pm_suspend(void);
135extern void omap730_cpu_suspend(unsigned short, unsigned short); 135extern void omap730_cpu_suspend(unsigned short, unsigned short);
136extern void omap1510_cpu_suspend(unsigned short, unsigned short); 136extern void omap1510_cpu_suspend(unsigned short, unsigned short);
137extern void omap1610_cpu_suspend(unsigned short, unsigned short); 137extern void omap1610_cpu_suspend(unsigned short, unsigned short);
138extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision); 138extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
139 void __iomem *sdrc_power);
139extern void omap730_idle_loop_suspend(void); 140extern void omap730_idle_loop_suspend(void);
140extern void omap1510_idle_loop_suspend(void); 141extern void omap1510_idle_loop_suspend(void);
141extern void omap1610_idle_loop_suspend(void); 142extern void omap1610_idle_loop_suspend(void);
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
new file mode 100644
index 000000000000..2806a9c8e4d7
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -0,0 +1,166 @@
1/*
2 * OMAP2/3 powerdomain control
3 *
4 * Copyright (C) 2007-8 Texas Instruments, Inc.
5 * Copyright (C) 2007-8 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
15#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
16
17#include <linux/types.h>
18#include <linux/list.h>
19
20#include <asm/atomic.h>
21
22#include <mach/cpu.h>
23
24
25/* Powerdomain basic power states */
26#define PWRDM_POWER_OFF 0x0
27#define PWRDM_POWER_RET 0x1
28#define PWRDM_POWER_INACTIVE 0x2
29#define PWRDM_POWER_ON 0x3
30
31/* Powerdomain allowable state bitfields */
32#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
33 (1 << PWRDM_POWER_ON))
34
35#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_RET))
37
38#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
39
40
41/* Powerdomain flags */
42#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
43
44
45/*
46 * Number of memory banks that are power-controllable. On OMAP3430, the
47 * maximum is 4.
48 */
49#define PWRDM_MAX_MEM_BANKS 4
50
51/*
52 * Maximum number of clockdomains that can be associated with a powerdomain.
53 * CORE powerdomain is probably the worst case.
54 */
55#define PWRDM_MAX_CLKDMS 3
56
57/* XXX A completely arbitrary number. What is reasonable here? */
58#define PWRDM_TRANSITION_BAILOUT 100000
59
60struct clockdomain;
61struct powerdomain;
62
63/* Encodes dependencies between powerdomains - statically defined */
64struct pwrdm_dep {
65
66 /* Powerdomain name */
67 const char *pwrdm_name;
68
69 /* Powerdomain pointer - resolved by the powerdomain code */
70 struct powerdomain *pwrdm;
71
72 /* Flags to mark OMAP chip restrictions, etc. */
73 const struct omap_chip_id omap_chip;
74
75};
76
77struct powerdomain {
78
79 /* Powerdomain name */
80 const char *name;
81
82 /* the address offset from CM_BASE/PRM_BASE */
83 const s16 prcm_offs;
84
85 /* Used to represent the OMAP chip types containing this pwrdm */
86 const struct omap_chip_id omap_chip;
87
88 /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
89 const u8 dep_bit;
90
91 /* Powerdomains that can be told to wake this powerdomain up */
92 struct pwrdm_dep *wkdep_srcs;
93
94 /* Powerdomains that can be told to keep this pwrdm from inactivity */
95 struct pwrdm_dep *sleepdep_srcs;
96
97 /* Possible powerdomain power states */
98 const u8 pwrsts;
99
100 /* Possible logic power states when pwrdm in RETENTION */
101 const u8 pwrsts_logic_ret;
102
103 /* Powerdomain flags */
104 const u8 flags;
105
106 /* Number of software-controllable memory banks in this powerdomain */
107 const u8 banks;
108
109 /* Possible memory bank pwrstates when pwrdm in RETENTION */
110 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
111
112 /* Possible memory bank pwrstates when pwrdm is ON */
113 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
114
115 /* Clockdomains in this powerdomain */
116 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
117
118 struct list_head node;
119
120};
121
122
123void pwrdm_init(struct powerdomain **pwrdm_list);
124
125int pwrdm_register(struct powerdomain *pwrdm);
126int pwrdm_unregister(struct powerdomain *pwrdm);
127struct powerdomain *pwrdm_lookup(const char *name);
128
129int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
130
131int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
132int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
133int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
134 int (*fn)(struct powerdomain *pwrdm,
135 struct clockdomain *clkdm));
136
137int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
138int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
139int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
140int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
141int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
142int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
143
144int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
145
146int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
147int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
148int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
149int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
150
151int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
152int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
153int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
154
155int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
156int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
157int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
158int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
159
160int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
161int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
162bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
163
164int pwrdm_wait_transition(struct powerdomain *pwrdm);
165
166#endif
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index 787b7acec546..a98c6c3beb2c 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -25,6 +25,8 @@
25#define SDRC_DLLB_STATUS 0x06C 25#define SDRC_DLLB_STATUS 0x06C
26#define SDRC_POWER 0x070 26#define SDRC_POWER 0x070
27#define SDRC_MR_0 0x084 27#define SDRC_MR_0 0x084
28#define SDRC_ACTIM_CTRL_A_0 0x09c
29#define SDRC_ACTIM_CTRL_B_0 0x0a0
28#define SDRC_RFR_CTRL_0 0x0a4 30#define SDRC_RFR_CTRL_0 0x0a4
29 31
30/* 32/*
@@ -63,9 +65,9 @@
63 */ 65 */
64 66
65 67
66#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) 68#define OMAP242X_SMS_REGADDR(reg) IO_ADDRESS(OMAP2420_SMS_BASE + reg)
67#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) 69#define OMAP243X_SMS_REGADDR(reg) IO_ADDRESS(OMAP243X_SMS_BASE + reg)
68#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) 70#define OMAP343X_SMS_REGADDR(reg) IO_ADDRESS(OMAP343X_SMS_BASE + reg)
69 71
70/* SMS register offsets - read/write with sms_{read,write}_reg() */ 72/* SMS register offsets - read/write with sms_{read,write}_reg() */
71 73
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index cc6bfa51ccb5..8a676a04be48 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -20,18 +20,24 @@
20#define OMAP_UART1_BASE 0x4806a000 20#define OMAP_UART1_BASE 0x4806a000
21#define OMAP_UART2_BASE 0x4806c000 21#define OMAP_UART2_BASE 0x4806c000
22#define OMAP_UART3_BASE 0x4806e000 22#define OMAP_UART3_BASE 0x4806e000
23#elif defined(CONFIG_ARCH_OMAP3)
24/* OMAP3 serial ports */
25#define OMAP_UART1_BASE 0x4806a000
26#define OMAP_UART2_BASE 0x4806c000
27#define OMAP_UART3_BASE 0x49020000
23#endif 28#endif
24 29
25#define OMAP_MAX_NR_PORTS 3 30#define OMAP_MAX_NR_PORTS 3
26#define OMAP1510_BASE_BAUD (12000000/16) 31#define OMAP1510_BASE_BAUD (12000000/16)
27#define OMAP16XX_BASE_BAUD (48000000/16) 32#define OMAP16XX_BASE_BAUD (48000000/16)
33#define OMAP24XX_BASE_BAUD (48000000/16)
28 34
29#define is_omap_port(p) ({int __ret = 0; \ 35#define is_omap_port(pt) ({int __ret = 0; \
30 if (p == IO_ADDRESS(OMAP_UART1_BASE) || \ 36 if ((pt)->port.mapbase == OMAP_UART1_BASE || \
31 p == IO_ADDRESS(OMAP_UART2_BASE) || \ 37 (pt)->port.mapbase == OMAP_UART2_BASE || \
32 p == IO_ADDRESS(OMAP_UART3_BASE)) \ 38 (pt)->port.mapbase == OMAP_UART3_BASE) \
33 __ret = 1; \ 39 __ret = 1; \
34 __ret; \ 40 __ret; \
35 }) 41 })
36 42
37#endif 43#endif
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index e09323449981..ab35d622dcf5 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -21,6 +21,10 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21 u32 mem_type); 21 u32 mem_type);
22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
23 23
24extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25 u32 sdrc_actim_ctrla,
26 u32 sdrc_actim_ctrlb, u32 m2);
27
24/* Do not use these */ 28/* Do not use these */
25extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 29extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
26extern unsigned long omap1_sram_reprogram_clock_sz; 30extern unsigned long omap1_sram_reprogram_clock_sz;
@@ -53,4 +57,10 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
53 u32 mem_type); 57 u32 mem_type);
54extern unsigned long omap243x_sram_reprogram_sdrc_sz; 58extern unsigned long omap243x_sram_reprogram_sdrc_sz;
55 59
60
61extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
62 u32 sdrc_actim_ctrla,
63 u32 sdrc_actim_ctrlb, u32 m2);
64extern unsigned long omap3_sram_configure_core_dpll_sz;
65
56#endif 66#endif
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h
index 06a28c7b98de..06923f261545 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/mach/system.h
@@ -40,7 +40,7 @@ static inline void omap1_arch_reset(char mode)
40 40
41static inline void arch_reset(char mode) 41static inline void arch_reset(char mode)
42{ 42{
43 if (!cpu_is_omap24xx()) 43 if (!cpu_class_is_omap2())
44 omap1_arch_reset(mode); 44 omap1_arch_reset(mode);
45 else 45 else
46 omap_prcm_arch_reset(mode); 46 omap_prcm_arch_reset(mode);
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
new file mode 100644
index 000000000000..af326efc1ad3
--- /dev/null
+++ b/arch/arm/plat-omap/io.c
@@ -0,0 +1,107 @@
1#include <linux/module.h>
2#include <linux/io.h>
3#include <linux/mm.h>
4
5#include <mach/omap730.h>
6#include <mach/omap1510.h>
7#include <mach/omap16xx.h>
8#include <mach/omap24xx.h>
9#include <mach/omap34xx.h>
10
11#define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz)))
12#define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst)))
13
14/*
15 * Intercept ioremap() requests for addresses in our fixed mapping regions.
16 */
17void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
18{
19#ifdef CONFIG_ARCH_OMAP1
20 if (cpu_class_is_omap1()) {
21 if (BETWEEN(p, IO_PHYS, IO_SIZE))
22 return XLATE(p, IO_PHYS, IO_VIRT);
23 }
24 if (cpu_is_omap730()) {
25 if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
26 return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
27
28 if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE))
29 return XLATE(p, OMAP730_DSPREG_BASE,
30 OMAP730_DSPREG_START);
31 }
32 if (cpu_is_omap15xx()) {
33 if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
34 return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START);
35
36 if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE))
37 return XLATE(p, OMAP1510_DSPREG_BASE,
38 OMAP1510_DSPREG_START);
39 }
40 if (cpu_is_omap16xx()) {
41 if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE))
42 return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START);
43
44 if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE))
45 return XLATE(p, OMAP16XX_DSPREG_BASE,
46 OMAP16XX_DSPREG_START);
47 }
48#endif
49#ifdef CONFIG_ARCH_OMAP2
50 if (cpu_is_omap24xx()) {
51 if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
52 return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
53 if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
54 return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
55 }
56 if (cpu_is_omap2420()) {
57 if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
58 return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
59 if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
60 return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE);
61 if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
62 return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
63 }
64 if (cpu_is_omap2430()) {
65 if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
66 return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
67 if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
68 return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
69 if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
70 return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
71 if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
72 return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
73 }
74#endif
75#ifdef CONFIG_ARCH_OMAP3
76 if (cpu_is_omap34xx()) {
77 if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
78 return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
79 if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
80 return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
81 if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
82 return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
83 if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
84 return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
85 if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
86 return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT);
87 if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE))
88 return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT);
89 if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE))
90 return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT);
91 if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE))
92 return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
93 }
94#endif
95
96 return __arm_ioremap(p, size, type);
97}
98EXPORT_SYMBOL(omap_ioremap);
99
100void omap_iounmap(volatile void __iomem *addr)
101{
102 unsigned long virt = (unsigned long)addr;
103
104 if (virt >= VMALLOC_START && virt < VMALLOC_END)
105 __iounmap(addr);
106}
107EXPORT_SYMBOL(omap_iounmap);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 014d26574bb6..af33fc713e1a 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -27,43 +27,65 @@
27#include <mach/dma.h> 27#include <mach/dma.h>
28#include <mach/mcbsp.h> 28#include <mach/mcbsp.h>
29 29
30static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT]; 30struct omap_mcbsp **mcbsp_ptr;
31int omap_mcbsp_count;
31 32
32#define omap_mcbsp_check_valid_id(id) (mcbsp[id].pdata && \ 33void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
33 mcbsp[id].pdata->ops && \ 34{
34 mcbsp[id].pdata->ops->check && \ 35 if (cpu_class_is_omap1() || cpu_is_omap2420())
35 (mcbsp[id].pdata->ops->check(id) == 0)) 36 __raw_writew((u16)val, io_base + reg);
37 else
38 __raw_writel(val, io_base + reg);
39}
40
41int omap_mcbsp_read(void __iomem *io_base, u16 reg)
42{
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(io_base + reg);
45 else
46 return __raw_readl(io_base + reg);
47}
48
49#define OMAP_MCBSP_READ(base, reg) \
50 omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
51#define OMAP_MCBSP_WRITE(base, reg, val) \
52 omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
53
54#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
36 56
37static void omap_mcbsp_dump_reg(u8 id) 57static void omap_mcbsp_dump_reg(u8 id)
38{ 58{
39 dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id); 59 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
40 dev_dbg(mcbsp[id].dev, "DRR2: 0x%04x\n", 60
41 OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2)); 61 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
42 dev_dbg(mcbsp[id].dev, "DRR1: 0x%04x\n", 62 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
43 OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1)); 63 OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
44 dev_dbg(mcbsp[id].dev, "DXR2: 0x%04x\n", 64 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
45 OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2)); 65 OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
46 dev_dbg(mcbsp[id].dev, "DXR1: 0x%04x\n", 66 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
47 OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1)); 67 OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
48 dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n", 68 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
49 OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2)); 69 OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
50 dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n", 70 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
51 OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1)); 71 OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
52 dev_dbg(mcbsp[id].dev, "RCR2: 0x%04x\n", 72 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
53 OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2)); 73 OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
54 dev_dbg(mcbsp[id].dev, "RCR1: 0x%04x\n", 74 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
55 OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1)); 75 OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
56 dev_dbg(mcbsp[id].dev, "XCR2: 0x%04x\n", 76 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
57 OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2)); 77 OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
58 dev_dbg(mcbsp[id].dev, "XCR1: 0x%04x\n", 78 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
59 OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1)); 79 OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
60 dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n", 80 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
61 OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2)); 81 OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
62 dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n", 82 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1)); 83 OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
64 dev_dbg(mcbsp[id].dev, "PCR0: 0x%04x\n", 84 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0)); 85 OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
66 dev_dbg(mcbsp[id].dev, "***********************\n"); 86 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
87 OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
88 dev_dbg(mcbsp->dev, "***********************\n");
67} 89}
68 90
69static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) 91static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
@@ -126,16 +148,18 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
126 */ 148 */
127void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) 149void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
128{ 150{
129 u32 io_base; 151 struct omap_mcbsp *mcbsp;
152 void __iomem *io_base;
130 153
131 if (!omap_mcbsp_check_valid_id(id)) { 154 if (!omap_mcbsp_check_valid_id(id)) {
132 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 155 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
133 return; 156 return;
134 } 157 }
158 mcbsp = id_to_mcbsp_ptr(id);
135 159
136 io_base = mcbsp[id].io_base; 160 io_base = mcbsp->io_base;
137 dev_dbg(mcbsp[id].dev, "Configuring McBSP%d io_base: 0x%8x\n", 161 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
138 mcbsp[id].id, io_base); 162 mcbsp->id, mcbsp->phys_base);
139 163
140 /* We write the given config */ 164 /* We write the given config */
141 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2); 165 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
@@ -158,23 +182,26 @@ EXPORT_SYMBOL(omap_mcbsp_config);
158 */ 182 */
159int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type) 183int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
160{ 184{
185 struct omap_mcbsp *mcbsp;
186
161 if (!omap_mcbsp_check_valid_id(id)) { 187 if (!omap_mcbsp_check_valid_id(id)) {
162 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 188 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
163 return -ENODEV; 189 return -ENODEV;
164 } 190 }
191 mcbsp = id_to_mcbsp_ptr(id);
165 192
166 spin_lock(&mcbsp[id].lock); 193 spin_lock(&mcbsp->lock);
167 194
168 if (!mcbsp[id].free) { 195 if (!mcbsp->free) {
169 dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n", 196 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
170 mcbsp[id].id); 197 mcbsp->id);
171 spin_unlock(&mcbsp[id].lock); 198 spin_unlock(&mcbsp->lock);
172 return -EINVAL; 199 return -EINVAL;
173 } 200 }
174 201
175 mcbsp[id].io_type = io_type; 202 mcbsp->io_type = io_type;
176 203
177 spin_unlock(&mcbsp[id].lock); 204 spin_unlock(&mcbsp->lock);
178 205
179 return 0; 206 return 0;
180} 207}
@@ -182,53 +209,60 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type);
182 209
183int omap_mcbsp_request(unsigned int id) 210int omap_mcbsp_request(unsigned int id)
184{ 211{
212 struct omap_mcbsp *mcbsp;
185 int err; 213 int err;
186 214
187 if (!omap_mcbsp_check_valid_id(id)) { 215 if (!omap_mcbsp_check_valid_id(id)) {
188 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 216 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
189 return -ENODEV; 217 return -ENODEV;
190 } 218 }
219 mcbsp = id_to_mcbsp_ptr(id);
191 220
192 if (mcbsp[id].pdata->ops->request) 221 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
193 mcbsp[id].pdata->ops->request(id); 222 mcbsp->pdata->ops->request(id);
194 223
195 clk_enable(mcbsp[id].clk); 224 clk_enable(mcbsp->clk);
196 225
197 spin_lock(&mcbsp[id].lock); 226 spin_lock(&mcbsp->lock);
198 if (!mcbsp[id].free) { 227 if (!mcbsp->free) {
199 dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n", 228 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
200 mcbsp[id].id); 229 mcbsp->id);
201 spin_unlock(&mcbsp[id].lock); 230 spin_unlock(&mcbsp->lock);
202 return -1; 231 return -1;
203 } 232 }
204 233
205 mcbsp[id].free = 0; 234 mcbsp->free = 0;
206 spin_unlock(&mcbsp[id].lock); 235 spin_unlock(&mcbsp->lock);
236
237 /*
238 * Make sure that transmitter, receiver and sample-rate generator are
239 * not running before activating IRQs.
240 */
241 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
242 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
207 243
208 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) { 244 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
209 /* We need to get IRQs here */ 245 /* We need to get IRQs here */
210 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 246 init_completion(&mcbsp->tx_irq_completion);
211 0, "McBSP", (void *) (&mcbsp[id])); 247 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
248 0, "McBSP", (void *)mcbsp);
212 if (err != 0) { 249 if (err != 0) {
213 dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d " 250 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
214 "for McBSP%d\n", mcbsp[id].tx_irq, 251 "for McBSP%d\n", mcbsp->tx_irq,
215 mcbsp[id].id); 252 mcbsp->id);
216 return err; 253 return err;
217 } 254 }
218 255
219 init_completion(&(mcbsp[id].tx_irq_completion)); 256 init_completion(&mcbsp->rx_irq_completion);
220 257 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
221 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 258 0, "McBSP", (void *)mcbsp);
222 0, "McBSP", (void *) (&mcbsp[id]));
223 if (err != 0) { 259 if (err != 0) {
224 dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d " 260 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
225 "for McBSP%d\n", mcbsp[id].rx_irq, 261 "for McBSP%d\n", mcbsp->rx_irq,
226 mcbsp[id].id); 262 mcbsp->id);
227 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id])); 263 free_irq(mcbsp->tx_irq, (void *)mcbsp);
228 return err; 264 return err;
229 } 265 }
230
231 init_completion(&(mcbsp[id].rx_irq_completion));
232 } 266 }
233 267
234 return 0; 268 return 0;
@@ -237,31 +271,34 @@ EXPORT_SYMBOL(omap_mcbsp_request);
237 271
238void omap_mcbsp_free(unsigned int id) 272void omap_mcbsp_free(unsigned int id)
239{ 273{
274 struct omap_mcbsp *mcbsp;
275
240 if (!omap_mcbsp_check_valid_id(id)) { 276 if (!omap_mcbsp_check_valid_id(id)) {
241 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 277 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
242 return; 278 return;
243 } 279 }
280 mcbsp = id_to_mcbsp_ptr(id);
244 281
245 if (mcbsp[id].pdata->ops->free) 282 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
246 mcbsp[id].pdata->ops->free(id); 283 mcbsp->pdata->ops->free(id);
247 284
248 clk_disable(mcbsp[id].clk); 285 clk_disable(mcbsp->clk);
249 286
250 spin_lock(&mcbsp[id].lock); 287 spin_lock(&mcbsp->lock);
251 if (mcbsp[id].free) { 288 if (mcbsp->free) {
252 dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n", 289 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
253 mcbsp[id].id); 290 mcbsp->id);
254 spin_unlock(&mcbsp[id].lock); 291 spin_unlock(&mcbsp->lock);
255 return; 292 return;
256 } 293 }
257 294
258 mcbsp[id].free = 1; 295 mcbsp->free = 1;
259 spin_unlock(&mcbsp[id].lock); 296 spin_unlock(&mcbsp->lock);
260 297
261 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) { 298 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
262 /* Free IRQs */ 299 /* Free IRQs */
263 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id])); 300 free_irq(mcbsp->rx_irq, (void *)mcbsp);
264 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id])); 301 free_irq(mcbsp->tx_irq, (void *)mcbsp);
265 } 302 }
266} 303}
267EXPORT_SYMBOL(omap_mcbsp_free); 304EXPORT_SYMBOL(omap_mcbsp_free);
@@ -273,18 +310,19 @@ EXPORT_SYMBOL(omap_mcbsp_free);
273 */ 310 */
274void omap_mcbsp_start(unsigned int id) 311void omap_mcbsp_start(unsigned int id)
275{ 312{
276 u32 io_base; 313 struct omap_mcbsp *mcbsp;
314 void __iomem *io_base;
277 u16 w; 315 u16 w;
278 316
279 if (!omap_mcbsp_check_valid_id(id)) { 317 if (!omap_mcbsp_check_valid_id(id)) {
280 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 318 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
281 return; 319 return;
282 } 320 }
321 mcbsp = id_to_mcbsp_ptr(id);
322 io_base = mcbsp->io_base;
283 323
284 io_base = mcbsp[id].io_base; 324 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
285 325 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
286 mcbsp[id].rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
287 mcbsp[id].tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
288 326
289 /* Start the sample generator */ 327 /* Start the sample generator */
290 w = OMAP_MCBSP_READ(io_base, SPCR2); 328 w = OMAP_MCBSP_READ(io_base, SPCR2);
@@ -310,7 +348,8 @@ EXPORT_SYMBOL(omap_mcbsp_start);
310 348
311void omap_mcbsp_stop(unsigned int id) 349void omap_mcbsp_stop(unsigned int id)
312{ 350{
313 u32 io_base; 351 struct omap_mcbsp *mcbsp;
352 void __iomem *io_base;
314 u16 w; 353 u16 w;
315 354
316 if (!omap_mcbsp_check_valid_id(id)) { 355 if (!omap_mcbsp_check_valid_id(id)) {
@@ -318,7 +357,8 @@ void omap_mcbsp_stop(unsigned int id)
318 return; 357 return;
319 } 358 }
320 359
321 io_base = mcbsp[id].io_base; 360 mcbsp = id_to_mcbsp_ptr(id);
361 io_base = mcbsp->io_base;
322 362
323 /* Reset transmitter */ 363 /* Reset transmitter */
324 w = OMAP_MCBSP_READ(io_base, SPCR2); 364 w = OMAP_MCBSP_READ(io_base, SPCR2);
@@ -337,14 +377,17 @@ EXPORT_SYMBOL(omap_mcbsp_stop);
337/* polled mcbsp i/o operations */ 377/* polled mcbsp i/o operations */
338int omap_mcbsp_pollwrite(unsigned int id, u16 buf) 378int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
339{ 379{
340 u32 base; 380 struct omap_mcbsp *mcbsp;
381 void __iomem *base;
341 382
342 if (!omap_mcbsp_check_valid_id(id)) { 383 if (!omap_mcbsp_check_valid_id(id)) {
343 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 384 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
344 return -ENODEV; 385 return -ENODEV;
345 } 386 }
346 387
347 base = mcbsp[id].io_base; 388 mcbsp = id_to_mcbsp_ptr(id);
389 base = mcbsp->io_base;
390
348 writew(buf, base + OMAP_MCBSP_REG_DXR1); 391 writew(buf, base + OMAP_MCBSP_REG_DXR1);
349 /* if frame sync error - clear the error */ 392 /* if frame sync error - clear the error */
350 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) { 393 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
@@ -366,8 +409,8 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
366 (XRST), 409 (XRST),
367 base + OMAP_MCBSP_REG_SPCR2); 410 base + OMAP_MCBSP_REG_SPCR2);
368 udelay(10); 411 udelay(10);
369 dev_err(mcbsp[id].dev, "Could not write to" 412 dev_err(mcbsp->dev, "Could not write to"
370 " McBSP%d Register\n", mcbsp[id].id); 413 " McBSP%d Register\n", mcbsp->id);
371 return -2; 414 return -2;
372 } 415 }
373 } 416 }
@@ -379,14 +422,16 @@ EXPORT_SYMBOL(omap_mcbsp_pollwrite);
379 422
380int omap_mcbsp_pollread(unsigned int id, u16 *buf) 423int omap_mcbsp_pollread(unsigned int id, u16 *buf)
381{ 424{
382 u32 base; 425 struct omap_mcbsp *mcbsp;
426 void __iomem *base;
383 427
384 if (!omap_mcbsp_check_valid_id(id)) { 428 if (!omap_mcbsp_check_valid_id(id)) {
385 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 429 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
386 return -ENODEV; 430 return -ENODEV;
387 } 431 }
432 mcbsp = id_to_mcbsp_ptr(id);
388 433
389 base = mcbsp[id].io_base; 434 base = mcbsp->io_base;
390 /* if frame sync error - clear the error */ 435 /* if frame sync error - clear the error */
391 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) { 436 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
392 /* clear error */ 437 /* clear error */
@@ -407,8 +452,8 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
407 (RRST), 452 (RRST),
408 base + OMAP_MCBSP_REG_SPCR1); 453 base + OMAP_MCBSP_REG_SPCR1);
409 udelay(10); 454 udelay(10);
410 dev_err(mcbsp[id].dev, "Could not read from" 455 dev_err(mcbsp->dev, "Could not read from"
411 " McBSP%d Register\n", mcbsp[id].id); 456 " McBSP%d Register\n", mcbsp->id);
412 return -2; 457 return -2;
413 } 458 }
414 } 459 }
@@ -424,7 +469,8 @@ EXPORT_SYMBOL(omap_mcbsp_pollread);
424 */ 469 */
425void omap_mcbsp_xmit_word(unsigned int id, u32 word) 470void omap_mcbsp_xmit_word(unsigned int id, u32 word)
426{ 471{
427 u32 io_base; 472 struct omap_mcbsp *mcbsp;
473 void __iomem *io_base;
428 omap_mcbsp_word_length word_length; 474 omap_mcbsp_word_length word_length;
429 475
430 if (!omap_mcbsp_check_valid_id(id)) { 476 if (!omap_mcbsp_check_valid_id(id)) {
@@ -432,10 +478,11 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word)
432 return; 478 return;
433 } 479 }
434 480
435 io_base = mcbsp[id].io_base; 481 mcbsp = id_to_mcbsp_ptr(id);
436 word_length = mcbsp[id].tx_word_length; 482 io_base = mcbsp->io_base;
483 word_length = mcbsp->tx_word_length;
437 484
438 wait_for_completion(&(mcbsp[id].tx_irq_completion)); 485 wait_for_completion(&mcbsp->tx_irq_completion);
439 486
440 if (word_length > OMAP_MCBSP_WORD_16) 487 if (word_length > OMAP_MCBSP_WORD_16)
441 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16); 488 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
@@ -445,7 +492,8 @@ EXPORT_SYMBOL(omap_mcbsp_xmit_word);
445 492
446u32 omap_mcbsp_recv_word(unsigned int id) 493u32 omap_mcbsp_recv_word(unsigned int id)
447{ 494{
448 u32 io_base; 495 struct omap_mcbsp *mcbsp;
496 void __iomem *io_base;
449 u16 word_lsb, word_msb = 0; 497 u16 word_lsb, word_msb = 0;
450 omap_mcbsp_word_length word_length; 498 omap_mcbsp_word_length word_length;
451 499
@@ -453,11 +501,12 @@ u32 omap_mcbsp_recv_word(unsigned int id)
453 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 501 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
454 return -ENODEV; 502 return -ENODEV;
455 } 503 }
504 mcbsp = id_to_mcbsp_ptr(id);
456 505
457 word_length = mcbsp[id].rx_word_length; 506 word_length = mcbsp->rx_word_length;
458 io_base = mcbsp[id].io_base; 507 io_base = mcbsp->io_base;
459 508
460 wait_for_completion(&(mcbsp[id].rx_irq_completion)); 509 wait_for_completion(&mcbsp->rx_irq_completion);
461 510
462 if (word_length > OMAP_MCBSP_WORD_16) 511 if (word_length > OMAP_MCBSP_WORD_16)
463 word_msb = OMAP_MCBSP_READ(io_base, DRR2); 512 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
@@ -469,7 +518,8 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word);
469 518
470int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) 519int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
471{ 520{
472 u32 io_base; 521 struct omap_mcbsp *mcbsp;
522 void __iomem *io_base;
473 omap_mcbsp_word_length tx_word_length; 523 omap_mcbsp_word_length tx_word_length;
474 omap_mcbsp_word_length rx_word_length; 524 omap_mcbsp_word_length rx_word_length;
475 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 525 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
@@ -478,10 +528,10 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
478 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 528 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
479 return -ENODEV; 529 return -ENODEV;
480 } 530 }
481 531 mcbsp = id_to_mcbsp_ptr(id);
482 io_base = mcbsp[id].io_base; 532 io_base = mcbsp->io_base;
483 tx_word_length = mcbsp[id].tx_word_length; 533 tx_word_length = mcbsp->tx_word_length;
484 rx_word_length = mcbsp[id].rx_word_length; 534 rx_word_length = mcbsp->rx_word_length;
485 535
486 if (tx_word_length != rx_word_length) 536 if (tx_word_length != rx_word_length)
487 return -EINVAL; 537 return -EINVAL;
@@ -496,8 +546,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
496 udelay(10); 546 udelay(10);
497 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); 547 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
498 udelay(10); 548 udelay(10);
499 dev_err(mcbsp[id].dev, "McBSP%d transmitter not " 549 dev_err(mcbsp->dev, "McBSP%d transmitter not "
500 "ready\n", mcbsp[id].id); 550 "ready\n", mcbsp->id);
501 return -EAGAIN; 551 return -EAGAIN;
502 } 552 }
503 } 553 }
@@ -517,8 +567,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
517 udelay(10); 567 udelay(10);
518 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); 568 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
519 udelay(10); 569 udelay(10);
520 dev_err(mcbsp[id].dev, "McBSP%d receiver not " 570 dev_err(mcbsp->dev, "McBSP%d receiver not "
521 "ready\n", mcbsp[id].id); 571 "ready\n", mcbsp->id);
522 return -EAGAIN; 572 return -EAGAIN;
523 } 573 }
524 } 574 }
@@ -534,7 +584,9 @@ EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
534 584
535int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) 585int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
536{ 586{
537 u32 io_base, clock_word = 0; 587 struct omap_mcbsp *mcbsp;
588 u32 clock_word = 0;
589 void __iomem *io_base;
538 omap_mcbsp_word_length tx_word_length; 590 omap_mcbsp_word_length tx_word_length;
539 omap_mcbsp_word_length rx_word_length; 591 omap_mcbsp_word_length rx_word_length;
540 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 592 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
@@ -544,9 +596,11 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
544 return -ENODEV; 596 return -ENODEV;
545 } 597 }
546 598
547 io_base = mcbsp[id].io_base; 599 mcbsp = id_to_mcbsp_ptr(id);
548 tx_word_length = mcbsp[id].tx_word_length; 600 io_base = mcbsp->io_base;
549 rx_word_length = mcbsp[id].rx_word_length; 601
602 tx_word_length = mcbsp->tx_word_length;
603 rx_word_length = mcbsp->rx_word_length;
550 604
551 if (tx_word_length != rx_word_length) 605 if (tx_word_length != rx_word_length)
552 return -EINVAL; 606 return -EINVAL;
@@ -561,8 +615,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
561 udelay(10); 615 udelay(10);
562 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); 616 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
563 udelay(10); 617 udelay(10);
564 dev_err(mcbsp[id].dev, "McBSP%d transmitter not " 618 dev_err(mcbsp->dev, "McBSP%d transmitter not "
565 "ready\n", mcbsp[id].id); 619 "ready\n", mcbsp->id);
566 return -EAGAIN; 620 return -EAGAIN;
567 } 621 }
568 } 622 }
@@ -582,8 +636,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
582 udelay(10); 636 udelay(10);
583 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); 637 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
584 udelay(10); 638 udelay(10);
585 dev_err(mcbsp[id].dev, "McBSP%d receiver not " 639 dev_err(mcbsp->dev, "McBSP%d receiver not "
586 "ready\n", mcbsp[id].id); 640 "ready\n", mcbsp->id);
587 return -EAGAIN; 641 return -EAGAIN;
588 } 642 }
589 } 643 }
@@ -609,6 +663,7 @@ EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
609int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, 663int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
610 unsigned int length) 664 unsigned int length)
611{ 665{
666 struct omap_mcbsp *mcbsp;
612 int dma_tx_ch; 667 int dma_tx_ch;
613 int src_port = 0; 668 int src_port = 0;
614 int dest_port = 0; 669 int dest_port = 0;
@@ -618,50 +673,51 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
618 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 673 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
619 return -ENODEV; 674 return -ENODEV;
620 } 675 }
676 mcbsp = id_to_mcbsp_ptr(id);
621 677
622 if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", 678 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
623 omap_mcbsp_tx_dma_callback, 679 omap_mcbsp_tx_dma_callback,
624 &mcbsp[id], 680 mcbsp,
625 &dma_tx_ch)) { 681 &dma_tx_ch)) {
626 dev_err(mcbsp[id].dev, " Unable to request DMA channel for " 682 dev_err(mcbsp->dev, " Unable to request DMA channel for "
627 "McBSP%d TX. Trying IRQ based TX\n", 683 "McBSP%d TX. Trying IRQ based TX\n",
628 mcbsp[id].id); 684 mcbsp->id);
629 return -EAGAIN; 685 return -EAGAIN;
630 } 686 }
631 mcbsp[id].dma_tx_lch = dma_tx_ch; 687 mcbsp->dma_tx_lch = dma_tx_ch;
632 688
633 dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id, 689 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
634 dma_tx_ch); 690 dma_tx_ch);
635 691
636 init_completion(&(mcbsp[id].tx_dma_completion)); 692 init_completion(&mcbsp->tx_dma_completion);
637 693
638 if (cpu_class_is_omap1()) { 694 if (cpu_class_is_omap1()) {
639 src_port = OMAP_DMA_PORT_TIPB; 695 src_port = OMAP_DMA_PORT_TIPB;
640 dest_port = OMAP_DMA_PORT_EMIFF; 696 dest_port = OMAP_DMA_PORT_EMIFF;
641 } 697 }
642 if (cpu_class_is_omap2()) 698 if (cpu_class_is_omap2())
643 sync_dev = mcbsp[id].dma_tx_sync; 699 sync_dev = mcbsp->dma_tx_sync;
644 700
645 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch, 701 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
646 OMAP_DMA_DATA_TYPE_S16, 702 OMAP_DMA_DATA_TYPE_S16,
647 length >> 1, 1, 703 length >> 1, 1,
648 OMAP_DMA_SYNC_ELEMENT, 704 OMAP_DMA_SYNC_ELEMENT,
649 sync_dev, 0); 705 sync_dev, 0);
650 706
651 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch, 707 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
652 src_port, 708 src_port,
653 OMAP_DMA_AMODE_CONSTANT, 709 OMAP_DMA_AMODE_CONSTANT,
654 mcbsp[id].phys_base + OMAP_MCBSP_REG_DXR1, 710 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
655 0, 0); 711 0, 0);
656 712
657 omap_set_dma_src_params(mcbsp[id].dma_tx_lch, 713 omap_set_dma_src_params(mcbsp->dma_tx_lch,
658 dest_port, 714 dest_port,
659 OMAP_DMA_AMODE_POST_INC, 715 OMAP_DMA_AMODE_POST_INC,
660 buffer, 716 buffer,
661 0, 0); 717 0, 0);
662 718
663 omap_start_dma(mcbsp[id].dma_tx_lch); 719 omap_start_dma(mcbsp->dma_tx_lch);
664 wait_for_completion(&(mcbsp[id].tx_dma_completion)); 720 wait_for_completion(&mcbsp->tx_dma_completion);
665 721
666 return 0; 722 return 0;
667} 723}
@@ -670,6 +726,7 @@ EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
670int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, 726int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
671 unsigned int length) 727 unsigned int length)
672{ 728{
729 struct omap_mcbsp *mcbsp;
673 int dma_rx_ch; 730 int dma_rx_ch;
674 int src_port = 0; 731 int src_port = 0;
675 int dest_port = 0; 732 int dest_port = 0;
@@ -679,50 +736,51 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
679 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 736 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
680 return -ENODEV; 737 return -ENODEV;
681 } 738 }
739 mcbsp = id_to_mcbsp_ptr(id);
682 740
683 if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", 741 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
684 omap_mcbsp_rx_dma_callback, 742 omap_mcbsp_rx_dma_callback,
685 &mcbsp[id], 743 mcbsp,
686 &dma_rx_ch)) { 744 &dma_rx_ch)) {
687 dev_err(mcbsp[id].dev, "Unable to request DMA channel for " 745 dev_err(mcbsp->dev, "Unable to request DMA channel for "
688 "McBSP%d RX. Trying IRQ based RX\n", 746 "McBSP%d RX. Trying IRQ based RX\n",
689 mcbsp[id].id); 747 mcbsp->id);
690 return -EAGAIN; 748 return -EAGAIN;
691 } 749 }
692 mcbsp[id].dma_rx_lch = dma_rx_ch; 750 mcbsp->dma_rx_lch = dma_rx_ch;
693 751
694 dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id, 752 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
695 dma_rx_ch); 753 dma_rx_ch);
696 754
697 init_completion(&(mcbsp[id].rx_dma_completion)); 755 init_completion(&mcbsp->rx_dma_completion);
698 756
699 if (cpu_class_is_omap1()) { 757 if (cpu_class_is_omap1()) {
700 src_port = OMAP_DMA_PORT_TIPB; 758 src_port = OMAP_DMA_PORT_TIPB;
701 dest_port = OMAP_DMA_PORT_EMIFF; 759 dest_port = OMAP_DMA_PORT_EMIFF;
702 } 760 }
703 if (cpu_class_is_omap2()) 761 if (cpu_class_is_omap2())
704 sync_dev = mcbsp[id].dma_rx_sync; 762 sync_dev = mcbsp->dma_rx_sync;
705 763
706 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch, 764 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
707 OMAP_DMA_DATA_TYPE_S16, 765 OMAP_DMA_DATA_TYPE_S16,
708 length >> 1, 1, 766 length >> 1, 1,
709 OMAP_DMA_SYNC_ELEMENT, 767 OMAP_DMA_SYNC_ELEMENT,
710 sync_dev, 0); 768 sync_dev, 0);
711 769
712 omap_set_dma_src_params(mcbsp[id].dma_rx_lch, 770 omap_set_dma_src_params(mcbsp->dma_rx_lch,
713 src_port, 771 src_port,
714 OMAP_DMA_AMODE_CONSTANT, 772 OMAP_DMA_AMODE_CONSTANT,
715 mcbsp[id].phys_base + OMAP_MCBSP_REG_DRR1, 773 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
716 0, 0); 774 0, 0);
717 775
718 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch, 776 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
719 dest_port, 777 dest_port,
720 OMAP_DMA_AMODE_POST_INC, 778 OMAP_DMA_AMODE_POST_INC,
721 buffer, 779 buffer,
722 0, 0); 780 0, 0);
723 781
724 omap_start_dma(mcbsp[id].dma_rx_lch); 782 omap_start_dma(mcbsp->dma_rx_lch);
725 wait_for_completion(&(mcbsp[id].rx_dma_completion)); 783 wait_for_completion(&mcbsp->rx_dma_completion);
726 784
727 return 0; 785 return 0;
728} 786}
@@ -737,12 +795,14 @@ EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
737void omap_mcbsp_set_spi_mode(unsigned int id, 795void omap_mcbsp_set_spi_mode(unsigned int id,
738 const struct omap_mcbsp_spi_cfg *spi_cfg) 796 const struct omap_mcbsp_spi_cfg *spi_cfg)
739{ 797{
798 struct omap_mcbsp *mcbsp;
740 struct omap_mcbsp_reg_cfg mcbsp_cfg; 799 struct omap_mcbsp_reg_cfg mcbsp_cfg;
741 800
742 if (!omap_mcbsp_check_valid_id(id)) { 801 if (!omap_mcbsp_check_valid_id(id)) {
743 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 802 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
744 return; 803 return;
745 } 804 }
805 mcbsp = id_to_mcbsp_ptr(id);
746 806
747 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg)); 807 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
748 808
@@ -803,9 +863,10 @@ EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
803 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 863 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
804 * 730 has only 2 McBSP, and both of them are MPU peripherals. 864 * 730 has only 2 McBSP, and both of them are MPU peripherals.
805 */ 865 */
806static int __init omap_mcbsp_probe(struct platform_device *pdev) 866static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
807{ 867{
808 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; 868 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
869 struct omap_mcbsp *mcbsp;
809 int id = pdev->id - 1; 870 int id = pdev->id - 1;
810 int ret = 0; 871 int ret = 0;
811 872
@@ -818,47 +879,63 @@ static int __init omap_mcbsp_probe(struct platform_device *pdev)
818 879
819 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id); 880 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
820 881
821 if (id >= OMAP_MAX_MCBSP_COUNT) { 882 if (id >= omap_mcbsp_count) {
822 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id); 883 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
823 ret = -EINVAL; 884 ret = -EINVAL;
824 goto exit; 885 goto exit;
825 } 886 }
826 887
827 spin_lock_init(&mcbsp[id].lock); 888 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
828 mcbsp[id].id = id + 1; 889 if (!mcbsp) {
829 mcbsp[id].free = 1; 890 ret = -ENOMEM;
830 mcbsp[id].dma_tx_lch = -1; 891 goto exit;
831 mcbsp[id].dma_rx_lch = -1; 892 }
893 mcbsp_ptr[id] = mcbsp;
894
895 spin_lock_init(&mcbsp->lock);
896 mcbsp->id = id + 1;
897 mcbsp->free = 1;
898 mcbsp->dma_tx_lch = -1;
899 mcbsp->dma_rx_lch = -1;
900
901 mcbsp->phys_base = pdata->phys_base;
902 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
903 if (!mcbsp->io_base) {
904 ret = -ENOMEM;
905 goto err_ioremap;
906 }
832 907
833 mcbsp[id].phys_base = pdata->phys_base;
834 mcbsp[id].io_base = pdata->virt_base;
835 /* Default I/O is IRQ based */ 908 /* Default I/O is IRQ based */
836 mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO; 909 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
837 mcbsp[id].tx_irq = pdata->tx_irq; 910 mcbsp->tx_irq = pdata->tx_irq;
838 mcbsp[id].rx_irq = pdata->rx_irq; 911 mcbsp->rx_irq = pdata->rx_irq;
839 mcbsp[id].dma_rx_sync = pdata->dma_rx_sync; 912 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
840 mcbsp[id].dma_tx_sync = pdata->dma_tx_sync; 913 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
841 914
842 if (pdata->clk_name) 915 if (pdata->clk_name)
843 mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name); 916 mcbsp->clk = clk_get(&pdev->dev, pdata->clk_name);
844 if (IS_ERR(mcbsp[id].clk)) { 917 if (IS_ERR(mcbsp->clk)) {
845 mcbsp[id].free = 0;
846 dev_err(&pdev->dev, 918 dev_err(&pdev->dev,
847 "Invalid clock configuration for McBSP%d.\n", 919 "Invalid clock configuration for McBSP%d.\n",
848 mcbsp[id].id); 920 mcbsp->id);
849 ret = -EINVAL; 921 ret = PTR_ERR(mcbsp->clk);
850 goto exit; 922 goto err_clk;
851 } 923 }
852 924
853 mcbsp[id].pdata = pdata; 925 mcbsp->pdata = pdata;
854 mcbsp[id].dev = &pdev->dev; 926 mcbsp->dev = &pdev->dev;
855 platform_set_drvdata(pdev, &mcbsp[id]); 927 platform_set_drvdata(pdev, mcbsp);
928 return 0;
856 929
930err_clk:
931 iounmap(mcbsp->io_base);
932err_ioremap:
933 mcbsp->free = 0;
857exit: 934exit:
858 return ret; 935 return ret;
859} 936}
860 937
861static int omap_mcbsp_remove(struct platform_device *pdev) 938static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
862{ 939{
863 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 940 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
864 941
@@ -872,6 +949,8 @@ static int omap_mcbsp_remove(struct platform_device *pdev)
872 clk_disable(mcbsp->clk); 949 clk_disable(mcbsp->clk);
873 clk_put(mcbsp->clk); 950 clk_put(mcbsp->clk);
874 951
952 iounmap(mcbsp->io_base);
953
875 mcbsp->clk = NULL; 954 mcbsp->clk = NULL;
876 mcbsp->free = 0; 955 mcbsp->free = 0;
877 mcbsp->dev = NULL; 956 mcbsp->dev = NULL;
@@ -882,7 +961,7 @@ static int omap_mcbsp_remove(struct platform_device *pdev)
882 961
883static struct platform_driver omap_mcbsp_driver = { 962static struct platform_driver omap_mcbsp_driver = {
884 .probe = omap_mcbsp_probe, 963 .probe = omap_mcbsp_probe,
885 .remove = omap_mcbsp_remove, 964 .remove = __devexit_p(omap_mcbsp_remove),
886 .driver = { 965 .driver = {
887 .name = "omap-mcbsp", 966 .name = "omap-mcbsp",
888 }, 967 },
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e0003e0746e7..9f9a921829c0 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -271,7 +271,7 @@ int __init omap1_sram_init(void)
271#define omap1_sram_init() do {} while (0) 271#define omap1_sram_init() do {} while (0)
272#endif 272#endif
273 273
274#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 274#if defined(CONFIG_ARCH_OMAP2)
275 275
276static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 276static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
277 u32 base_cs, u32 force_unlock); 277 u32 base_cs, u32 force_unlock);
@@ -352,23 +352,19 @@ static inline int omap243x_sram_init(void)
352 352
353#ifdef CONFIG_ARCH_OMAP3 353#ifdef CONFIG_ARCH_OMAP3
354 354
355static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level); 355static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
356u32 omap2_sram_reprogram_gpmc(u32 perf_level) 356 u32 sdrc_actim_ctrla,
357{ 357 u32 sdrc_actim_ctrlb,
358 if (!_omap2_sram_reprogram_gpmc) 358 u32 m2);
359 omap_sram_error(); 359u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
360 360 u32 sdrc_actim_ctrlb, u32 m2)
361 return _omap2_sram_reprogram_gpmc(perf_level);
362}
363
364static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
365 u32 freqsel, u32 m2);
366u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
367{ 361{
368 if (!_omap2_sram_configure_core_dpll) 362 if (!_omap3_sram_configure_core_dpll)
369 omap_sram_error(); 363 omap_sram_error();
370 364
371 return _omap2_sram_configure_core_dpll(m, n, freqsel, m2); 365 return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
366 sdrc_actim_ctrla,
367 sdrc_actim_ctrlb, m2);
372} 368}
373 369
374/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ 370/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
@@ -376,31 +372,16 @@ void restore_sram_functions(void)
376{ 372{
377 omap_sram_ceil = omap_sram_base + omap_sram_size; 373 omap_sram_ceil = omap_sram_base + omap_sram_size;
378 374
379 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc, 375 _omap3_sram_configure_core_dpll =
380 omap34xx_sram_reprogram_gpmc_sz); 376 omap_sram_push(omap3_sram_configure_core_dpll,
381 377 omap3_sram_configure_core_dpll_sz);
382 _omap2_sram_configure_core_dpll =
383 omap_sram_push(omap34xx_sram_configure_core_dpll,
384 omap34xx_sram_configure_core_dpll_sz);
385} 378}
386 379
387int __init omap34xx_sram_init(void) 380int __init omap34xx_sram_init(void)
388{ 381{
389 _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init, 382 _omap3_sram_configure_core_dpll =
390 omap34xx_sram_ddr_init_sz); 383 omap_sram_push(omap3_sram_configure_core_dpll,
391 384 omap3_sram_configure_core_dpll_sz);
392 _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
393 omap34xx_sram_reprogram_sdrc_sz);
394
395 _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
396 omap34xx_sram_set_prcm_sz);
397
398 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
399 omap34xx_sram_reprogram_gpmc_sz);
400
401 _omap2_sram_configure_core_dpll =
402 omap_sram_push(omap34xx_sram_configure_core_dpll,
403 omap34xx_sram_configure_core_dpll_sz);
404 385
405 return 0; 386 return 0;
406} 387}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-03 14:23:45 -0400