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-rw-r--r--arch/arm/plat-omap/cpu-omap.c32
-rw-r--r--arch/arm/plat-omap/devices.c63
-rw-r--r--arch/arm/plat-omap/dma.c14
-rw-r--r--arch/arm/plat-omap/dmtimer.c2
-rw-r--r--arch/arm/plat-omap/gpio.c65
5 files changed, 56 insertions, 120 deletions
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index c0d63b0c61c9..d719c15daa55 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -33,43 +33,33 @@
33#define MPU_CLK "virt_prcm_set" 33#define MPU_CLK "virt_prcm_set"
34#endif 34#endif
35 35
36static struct clk *mpu_clk;
37
36/* TODO: Add support for SDRAM timing changes */ 38/* TODO: Add support for SDRAM timing changes */
37 39
38int omap_verify_speed(struct cpufreq_policy *policy) 40int omap_verify_speed(struct cpufreq_policy *policy)
39{ 41{
40 struct clk * mpu_clk;
41
42 if (policy->cpu) 42 if (policy->cpu)
43 return -EINVAL; 43 return -EINVAL;
44 44
45 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, 45 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
46 policy->cpuinfo.max_freq); 46 policy->cpuinfo.max_freq);
47 mpu_clk = clk_get(NULL, MPU_CLK); 47
48 if (IS_ERR(mpu_clk))
49 return PTR_ERR(mpu_clk);
50 policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000; 48 policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000;
51 policy->max = clk_round_rate(mpu_clk, policy->max * 1000) / 1000; 49 policy->max = clk_round_rate(mpu_clk, policy->max * 1000) / 1000;
52 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, 50 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
53 policy->cpuinfo.max_freq); 51 policy->cpuinfo.max_freq);
54 clk_put(mpu_clk);
55
56 return 0; 52 return 0;
57} 53}
58 54
59unsigned int omap_getspeed(unsigned int cpu) 55unsigned int omap_getspeed(unsigned int cpu)
60{ 56{
61 struct clk * mpu_clk;
62 unsigned long rate; 57 unsigned long rate;
63 58
64 if (cpu) 59 if (cpu)
65 return 0; 60 return 0;
66 61
67 mpu_clk = clk_get(NULL, MPU_CLK);
68 if (IS_ERR(mpu_clk))
69 return 0;
70 rate = clk_get_rate(mpu_clk) / 1000; 62 rate = clk_get_rate(mpu_clk) / 1000;
71 clk_put(mpu_clk);
72
73 return rate; 63 return rate;
74} 64}
75 65
@@ -77,14 +67,9 @@ static int omap_target(struct cpufreq_policy *policy,
77 unsigned int target_freq, 67 unsigned int target_freq,
78 unsigned int relation) 68 unsigned int relation)
79{ 69{
80 struct clk * mpu_clk;
81 struct cpufreq_freqs freqs; 70 struct cpufreq_freqs freqs;
82 int ret = 0; 71 int ret = 0;
83 72
84 mpu_clk = clk_get(NULL, MPU_CLK);
85 if (IS_ERR(mpu_clk))
86 return PTR_ERR(mpu_clk);
87
88 freqs.old = omap_getspeed(0); 73 freqs.old = omap_getspeed(0);
89 freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000; 74 freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
90 freqs.cpu = 0; 75 freqs.cpu = 0;
@@ -92,15 +77,12 @@ static int omap_target(struct cpufreq_policy *policy,
92 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 77 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
93 ret = clk_set_rate(mpu_clk, target_freq * 1000); 78 ret = clk_set_rate(mpu_clk, target_freq * 1000);
94 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 79 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
95 clk_put(mpu_clk);
96 80
97 return ret; 81 return ret;
98} 82}
99 83
100static int __init omap_cpu_init(struct cpufreq_policy *policy) 84static int __init omap_cpu_init(struct cpufreq_policy *policy)
101{ 85{
102 struct clk * mpu_clk;
103
104 mpu_clk = clk_get(NULL, MPU_CLK); 86 mpu_clk = clk_get(NULL, MPU_CLK);
105 if (IS_ERR(mpu_clk)) 87 if (IS_ERR(mpu_clk))
106 return PTR_ERR(mpu_clk); 88 return PTR_ERR(mpu_clk);
@@ -111,17 +93,23 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy)
111 policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000; 93 policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000;
112 policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / 1000; 94 policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / 1000;
113 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 95 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
114 clk_put(mpu_clk);
115 96
116 return 0; 97 return 0;
117} 98}
118 99
100static int omap_cpu_exit(struct cpufreq_policy *policy)
101{
102 clk_put(mpu_clk);
103 return 0;
104}
105
119static struct cpufreq_driver omap_driver = { 106static struct cpufreq_driver omap_driver = {
120 .flags = CPUFREQ_STICKY, 107 .flags = CPUFREQ_STICKY,
121 .verify = omap_verify_speed, 108 .verify = omap_verify_speed,
122 .target = omap_target, 109 .target = omap_target,
123 .get = omap_getspeed, 110 .get = omap_getspeed,
124 .init = omap_cpu_init, 111 .init = omap_cpu_init,
112 .exit = omap_cpu_exit,
125 .name = "omap", 113 .name = "omap",
126}; 114};
127 115
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index c5dab1d6417e..4a53f9ba6c43 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -89,68 +89,6 @@ static inline void omap_init_dsp(void) { }
89#endif /* CONFIG_OMAP_DSP */ 89#endif /* CONFIG_OMAP_DSP */
90 90
91/*-------------------------------------------------------------------------*/ 91/*-------------------------------------------------------------------------*/
92#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
93
94#define OMAP1_I2C_BASE 0xfffb3800
95#define OMAP2_I2C_BASE1 0x48070000
96#define OMAP_I2C_SIZE 0x3f
97#define OMAP1_I2C_INT INT_I2C
98#define OMAP2_I2C_INT1 56
99
100static struct resource i2c_resources1[] = {
101 {
102 .start = 0,
103 .end = 0,
104 .flags = IORESOURCE_MEM,
105 },
106 {
107 .start = 0,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112/* DMA not used; works around erratum writing to non-empty i2c fifo */
113
114static struct platform_device omap_i2c_device1 = {
115 .name = "i2c_omap",
116 .id = 1,
117 .num_resources = ARRAY_SIZE(i2c_resources1),
118 .resource = i2c_resources1,
119};
120
121/* See also arch/arm/mach-omap2/devices.c for second I2C on 24xx */
122static void omap_init_i2c(void)
123{
124 if (cpu_is_omap24xx()) {
125 i2c_resources1[0].start = OMAP2_I2C_BASE1;
126 i2c_resources1[0].end = OMAP2_I2C_BASE1 + OMAP_I2C_SIZE;
127 i2c_resources1[1].start = OMAP2_I2C_INT1;
128 } else {
129 i2c_resources1[0].start = OMAP1_I2C_BASE;
130 i2c_resources1[0].end = OMAP1_I2C_BASE + OMAP_I2C_SIZE;
131 i2c_resources1[1].start = OMAP1_I2C_INT;
132 }
133
134 /* FIXME define and use a boot tag, in case of boards that
135 * either don't wire up I2C, or chips that mux it differently...
136 * it can include clocking and address info, maybe more.
137 */
138 if (cpu_is_omap24xx()) {
139 omap_cfg_reg(M19_24XX_I2C1_SCL);
140 omap_cfg_reg(L15_24XX_I2C1_SDA);
141 } else {
142 omap_cfg_reg(I2C_SCL);
143 omap_cfg_reg(I2C_SDA);
144 }
145
146 (void) platform_device_register(&omap_i2c_device1);
147}
148
149#else
150static inline void omap_init_i2c(void) {}
151#endif
152
153/*-------------------------------------------------------------------------*/
154#if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE) 92#if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
155 93
156static void omap_init_kp(void) 94static void omap_init_kp(void)
@@ -501,7 +439,6 @@ static int __init omap_init_devices(void)
501 * in alphabetical order so they're easier to sort through. 439 * in alphabetical order so they're easier to sort through.
502 */ 440 */
503 omap_init_dsp(); 441 omap_init_dsp();
504 omap_init_i2c();
505 omap_init_kp(); 442 omap_init_kp();
506 omap_init_mmc(); 443 omap_init_mmc();
507 omap_init_uwire(); 444 omap_init_uwire();
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index a46676db8113..91004a3c4794 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -137,7 +137,7 @@ static void omap_disable_channel_irq(int lch);
137static inline void omap_enable_channel_irq(int lch); 137static inline void omap_enable_channel_irq(int lch);
138 138
139#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ 139#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
140 __FUNCTION__); 140 __func__);
141 141
142#ifdef CONFIG_ARCH_OMAP15XX 142#ifdef CONFIG_ARCH_OMAP15XX
143/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ 143/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
@@ -699,7 +699,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
699 u32 reg; 699 u32 reg;
700 700
701 if (!cpu_class_is_omap2()) { 701 if (!cpu_class_is_omap2()) {
702 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __FUNCTION__); 702 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
703 return; 703 return;
704 } 704 }
705 705
@@ -1705,14 +1705,8 @@ static int omap2_dma_handle_ch(int ch)
1705 status = OMAP_DMA_CSR_REG(ch); 1705 status = OMAP_DMA_CSR_REG(ch);
1706 } 1706 }
1707 1707
1708 if (likely(dma_chan[ch].callback != NULL)) { 1708 if (likely(dma_chan[ch].callback != NULL))
1709 if (dma_chan[ch].chain_id != -1) 1709 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1710 dma_chan[ch].callback(dma_chan[ch].chain_id, status,
1711 dma_chan[ch].data);
1712 else
1713 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1714
1715 }
1716 1710
1717 OMAP_DMA_CSR_REG(ch) = status; 1711 OMAP_DMA_CSR_REG(ch) = status;
1718 1712
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index e719d0eeb5c8..302ad8dff2cb 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -268,7 +268,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
268 if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) { 268 if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
269 spin_unlock_irqrestore(&dm_timer_lock, flags); 269 spin_unlock_irqrestore(&dm_timer_lock, flags);
270 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n", 270 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
271 __FILE__, __LINE__, __FUNCTION__, id); 271 __FILE__, __LINE__, __func__, id);
272 dump_stack(); 272 dump_stack();
273 return NULL; 273 return NULL;
274 } 274 }
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 56f4d1394d56..66a1455595f4 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -333,13 +333,14 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
333void omap_set_gpio_direction(int gpio, int is_input) 333void omap_set_gpio_direction(int gpio, int is_input)
334{ 334{
335 struct gpio_bank *bank; 335 struct gpio_bank *bank;
336 unsigned long flags;
336 337
337 if (check_gpio(gpio) < 0) 338 if (check_gpio(gpio) < 0)
338 return; 339 return;
339 bank = get_gpio_bank(gpio); 340 bank = get_gpio_bank(gpio);
340 spin_lock(&bank->lock); 341 spin_lock_irqsave(&bank->lock, flags);
341 _set_gpio_direction(bank, get_gpio_index(gpio), is_input); 342 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
342 spin_unlock(&bank->lock); 343 spin_unlock_irqrestore(&bank->lock, flags);
343} 344}
344 345
345static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) 346static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
@@ -406,13 +407,14 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
406void omap_set_gpio_dataout(int gpio, int enable) 407void omap_set_gpio_dataout(int gpio, int enable)
407{ 408{
408 struct gpio_bank *bank; 409 struct gpio_bank *bank;
410 unsigned long flags;
409 411
410 if (check_gpio(gpio) < 0) 412 if (check_gpio(gpio) < 0)
411 return; 413 return;
412 bank = get_gpio_bank(gpio); 414 bank = get_gpio_bank(gpio);
413 spin_lock(&bank->lock); 415 spin_lock_irqsave(&bank->lock, flags);
414 _set_gpio_dataout(bank, get_gpio_index(gpio), enable); 416 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
415 spin_unlock(&bank->lock); 417 spin_unlock_irqrestore(&bank->lock, flags);
416} 418}
417 419
418int omap_get_gpio_datain(int gpio) 420int omap_get_gpio_datain(int gpio)
@@ -624,6 +626,7 @@ static int gpio_irq_type(unsigned irq, unsigned type)
624 struct gpio_bank *bank; 626 struct gpio_bank *bank;
625 unsigned gpio; 627 unsigned gpio;
626 int retval; 628 int retval;
629 unsigned long flags;
627 630
628 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) 631 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
629 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 632 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
@@ -642,13 +645,13 @@ static int gpio_irq_type(unsigned irq, unsigned type)
642 return -EINVAL; 645 return -EINVAL;
643 646
644 bank = get_irq_chip_data(irq); 647 bank = get_irq_chip_data(irq);
645 spin_lock(&bank->lock); 648 spin_lock_irqsave(&bank->lock, flags);
646 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); 649 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
647 if (retval == 0) { 650 if (retval == 0) {
648 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; 651 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
649 irq_desc[irq].status |= type; 652 irq_desc[irq].status |= type;
650 } 653 }
651 spin_unlock(&bank->lock); 654 spin_unlock_irqrestore(&bank->lock, flags);
652 return retval; 655 return retval;
653} 656}
654 657
@@ -830,11 +833,13 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena
830 */ 833 */
831static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) 834static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
832{ 835{
836 unsigned long flags;
837
833 switch (bank->method) { 838 switch (bank->method) {
834#ifdef CONFIG_ARCH_OMAP16XX 839#ifdef CONFIG_ARCH_OMAP16XX
835 case METHOD_MPUIO: 840 case METHOD_MPUIO:
836 case METHOD_GPIO_1610: 841 case METHOD_GPIO_1610:
837 spin_lock(&bank->lock); 842 spin_lock_irqsave(&bank->lock, flags);
838 if (enable) { 843 if (enable) {
839 bank->suspend_wakeup |= (1 << gpio); 844 bank->suspend_wakeup |= (1 << gpio);
840 enable_irq_wake(bank->irq); 845 enable_irq_wake(bank->irq);
@@ -842,7 +847,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
842 disable_irq_wake(bank->irq); 847 disable_irq_wake(bank->irq);
843 bank->suspend_wakeup &= ~(1 << gpio); 848 bank->suspend_wakeup &= ~(1 << gpio);
844 } 849 }
845 spin_unlock(&bank->lock); 850 spin_unlock_irqrestore(&bank->lock, flags);
846 return 0; 851 return 0;
847#endif 852#endif
848#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 853#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -853,7 +858,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
853 (bank - gpio_bank) * 32 + gpio); 858 (bank - gpio_bank) * 32 + gpio);
854 return -EINVAL; 859 return -EINVAL;
855 } 860 }
856 spin_lock(&bank->lock); 861 spin_lock_irqsave(&bank->lock, flags);
857 if (enable) { 862 if (enable) {
858 bank->suspend_wakeup |= (1 << gpio); 863 bank->suspend_wakeup |= (1 << gpio);
859 enable_irq_wake(bank->irq); 864 enable_irq_wake(bank->irq);
@@ -861,7 +866,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
861 disable_irq_wake(bank->irq); 866 disable_irq_wake(bank->irq);
862 bank->suspend_wakeup &= ~(1 << gpio); 867 bank->suspend_wakeup &= ~(1 << gpio);
863 } 868 }
864 spin_unlock(&bank->lock); 869 spin_unlock_irqrestore(&bank->lock, flags);
865 return 0; 870 return 0;
866#endif 871#endif
867 default: 872 default:
@@ -897,16 +902,17 @@ static int gpio_wake_enable(unsigned int irq, unsigned int enable)
897int omap_request_gpio(int gpio) 902int omap_request_gpio(int gpio)
898{ 903{
899 struct gpio_bank *bank; 904 struct gpio_bank *bank;
905 unsigned long flags;
900 906
901 if (check_gpio(gpio) < 0) 907 if (check_gpio(gpio) < 0)
902 return -EINVAL; 908 return -EINVAL;
903 909
904 bank = get_gpio_bank(gpio); 910 bank = get_gpio_bank(gpio);
905 spin_lock(&bank->lock); 911 spin_lock_irqsave(&bank->lock, flags);
906 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) { 912 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
907 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio); 913 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
908 dump_stack(); 914 dump_stack();
909 spin_unlock(&bank->lock); 915 spin_unlock_irqrestore(&bank->lock, flags);
910 return -1; 916 return -1;
911 } 917 }
912 bank->reserved_map |= (1 << get_gpio_index(gpio)); 918 bank->reserved_map |= (1 << get_gpio_index(gpio));
@@ -925,7 +931,7 @@ int omap_request_gpio(int gpio)
925 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); 931 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
926 } 932 }
927#endif 933#endif
928 spin_unlock(&bank->lock); 934 spin_unlock_irqrestore(&bank->lock, flags);
929 935
930 return 0; 936 return 0;
931} 937}
@@ -933,15 +939,16 @@ int omap_request_gpio(int gpio)
933void omap_free_gpio(int gpio) 939void omap_free_gpio(int gpio)
934{ 940{
935 struct gpio_bank *bank; 941 struct gpio_bank *bank;
942 unsigned long flags;
936 943
937 if (check_gpio(gpio) < 0) 944 if (check_gpio(gpio) < 0)
938 return; 945 return;
939 bank = get_gpio_bank(gpio); 946 bank = get_gpio_bank(gpio);
940 spin_lock(&bank->lock); 947 spin_lock_irqsave(&bank->lock, flags);
941 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) { 948 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
942 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); 949 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
943 dump_stack(); 950 dump_stack();
944 spin_unlock(&bank->lock); 951 spin_unlock_irqrestore(&bank->lock, flags);
945 return; 952 return;
946 } 953 }
947#ifdef CONFIG_ARCH_OMAP16XX 954#ifdef CONFIG_ARCH_OMAP16XX
@@ -960,7 +967,7 @@ void omap_free_gpio(int gpio)
960#endif 967#endif
961 bank->reserved_map &= ~(1 << get_gpio_index(gpio)); 968 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
962 _reset_gpio(bank, gpio); 969 _reset_gpio(bank, gpio);
963 spin_unlock(&bank->lock); 970 spin_unlock_irqrestore(&bank->lock, flags);
964} 971}
965 972
966/* 973/*
@@ -1194,11 +1201,12 @@ static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t me
1194{ 1201{
1195 struct gpio_bank *bank = platform_get_drvdata(pdev); 1202 struct gpio_bank *bank = platform_get_drvdata(pdev);
1196 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1203 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1204 unsigned long flags;
1197 1205
1198 spin_lock(&bank->lock); 1206 spin_lock_irqsave(&bank->lock, flags);
1199 bank->saved_wakeup = __raw_readl(mask_reg); 1207 bank->saved_wakeup = __raw_readl(mask_reg);
1200 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); 1208 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1201 spin_unlock(&bank->lock); 1209 spin_unlock_irqrestore(&bank->lock, flags);
1202 1210
1203 return 0; 1211 return 0;
1204} 1212}
@@ -1207,10 +1215,11 @@ static int omap_mpuio_resume_early(struct platform_device *pdev)
1207{ 1215{
1208 struct gpio_bank *bank = platform_get_drvdata(pdev); 1216 struct gpio_bank *bank = platform_get_drvdata(pdev);
1209 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1217 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1218 unsigned long flags;
1210 1219
1211 spin_lock(&bank->lock); 1220 spin_lock_irqsave(&bank->lock, flags);
1212 __raw_writel(bank->saved_wakeup, mask_reg); 1221 __raw_writel(bank->saved_wakeup, mask_reg);
1213 spin_unlock(&bank->lock); 1222 spin_unlock_irqrestore(&bank->lock, flags);
1214 1223
1215 return 0; 1224 return 0;
1216} 1225}
@@ -1277,6 +1286,11 @@ static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1277static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; 1286static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1278#endif 1287#endif
1279 1288
1289/* This lock class tells lockdep that GPIO irqs are in a different
1290 * category than their parents, so it won't report false recursion.
1291 */
1292static struct lock_class_key gpio_lock_class;
1293
1280static int __init _omap_gpio_init(void) 1294static int __init _omap_gpio_init(void)
1281{ 1295{
1282 int i; 1296 int i;
@@ -1450,6 +1464,7 @@ static int __init _omap_gpio_init(void)
1450#endif 1464#endif
1451 for (j = bank->virtual_irq_start; 1465 for (j = bank->virtual_irq_start;
1452 j < bank->virtual_irq_start + gpio_count; j++) { 1466 j < bank->virtual_irq_start + gpio_count; j++) {
1467 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1453 set_irq_chip_data(j, bank); 1468 set_irq_chip_data(j, bank);
1454 if (bank_is_mpuio(bank)) 1469 if (bank_is_mpuio(bank))
1455 set_irq_chip(j, &mpuio_irq_chip); 1470 set_irq_chip(j, &mpuio_irq_chip);
@@ -1489,6 +1504,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1489 void __iomem *wake_status; 1504 void __iomem *wake_status;
1490 void __iomem *wake_clear; 1505 void __iomem *wake_clear;
1491 void __iomem *wake_set; 1506 void __iomem *wake_set;
1507 unsigned long flags;
1492 1508
1493 switch (bank->method) { 1509 switch (bank->method) {
1494#ifdef CONFIG_ARCH_OMAP16XX 1510#ifdef CONFIG_ARCH_OMAP16XX
@@ -1509,11 +1525,11 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1509 continue; 1525 continue;
1510 } 1526 }
1511 1527
1512 spin_lock(&bank->lock); 1528 spin_lock_irqsave(&bank->lock, flags);
1513 bank->saved_wakeup = __raw_readl(wake_status); 1529 bank->saved_wakeup = __raw_readl(wake_status);
1514 __raw_writel(0xffffffff, wake_clear); 1530 __raw_writel(0xffffffff, wake_clear);
1515 __raw_writel(bank->suspend_wakeup, wake_set); 1531 __raw_writel(bank->suspend_wakeup, wake_set);
1516 spin_unlock(&bank->lock); 1532 spin_unlock_irqrestore(&bank->lock, flags);
1517 } 1533 }
1518 1534
1519 return 0; 1535 return 0;
@@ -1530,6 +1546,7 @@ static int omap_gpio_resume(struct sys_device *dev)
1530 struct gpio_bank *bank = &gpio_bank[i]; 1546 struct gpio_bank *bank = &gpio_bank[i];
1531 void __iomem *wake_clear; 1547 void __iomem *wake_clear;
1532 void __iomem *wake_set; 1548 void __iomem *wake_set;
1549 unsigned long flags;
1533 1550
1534 switch (bank->method) { 1551 switch (bank->method) {
1535#ifdef CONFIG_ARCH_OMAP16XX 1552#ifdef CONFIG_ARCH_OMAP16XX
@@ -1548,10 +1565,10 @@ static int omap_gpio_resume(struct sys_device *dev)
1548 continue; 1565 continue;
1549 } 1566 }
1550 1567
1551 spin_lock(&bank->lock); 1568 spin_lock_irqsave(&bank->lock, flags);
1552 __raw_writel(0xffffffff, wake_clear); 1569 __raw_writel(0xffffffff, wake_clear);
1553 __raw_writel(bank->saved_wakeup, wake_set); 1570 __raw_writel(bank->saved_wakeup, wake_set);
1554 spin_unlock(&bank->lock); 1571 spin_unlock_irqrestore(&bank->lock, flags);
1555 } 1572 }
1556 1573
1557 return 0; 1574 return 0;