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-rw-r--r--arch/arm/plat-omap/Makefile1
-rw-r--r--arch/arm/plat-omap/dma.c844
-rw-r--r--arch/arm/plat-omap/dmtimer.c118
-rw-r--r--arch/arm/plat-omap/gpio.c256
-rw-r--r--arch/arm/plat-omap/i2c.c148
-rw-r--r--arch/arm/plat-omap/mcbsp.c11
6 files changed, 1237 insertions, 141 deletions
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 2549129aabc6..ce17df31b845 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
19obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 19obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
20obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o 20obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
21obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o 21obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
22obj-$(CONFIG_I2C_OMAP) += i2c.o
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index dcbba07cf98a..a46676db8113 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -6,7 +6,7 @@
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations 7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com> 8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc. 9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> 10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 * 12 *
@@ -33,12 +33,14 @@
33 33
34#include <asm/arch/tc.h> 34#include <asm/arch/tc.h>
35 35
36#define DEBUG_PRINTS 36#undef DEBUG
37#undef DEBUG_PRINTS 37
38#ifdef DEBUG_PRINTS 38#ifndef CONFIG_ARCH_OMAP1
39#define debug_printk(x) printk x 39enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40#else 40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
41#define debug_printk(x) 41};
42
43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
42#endif 44#endif
43 45
44#define OMAP_DMA_ACTIVE 0x01 46#define OMAP_DMA_ACTIVE 0x01
@@ -57,9 +59,66 @@ struct omap_dma_lch {
57 const char *dev_name; 59 const char *dev_name;
58 void (* callback)(int lch, u16 ch_status, void *data); 60 void (* callback)(int lch, u16 ch_status, void *data);
59 void *data; 61 void *data;
62
63#ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
65 int prev_linked_ch;
66 int next_linked_ch;
67 int state;
68 int chain_id;
69
70 int status;
71#endif
60 long flags; 72 long flags;
61}; 73};
62 74
75#ifndef CONFIG_ARCH_OMAP1
76struct dma_link_info {
77 int *linked_dmach_q;
78 int no_of_lchs_linked;
79
80 int q_count;
81 int q_tail;
82 int q_head;
83
84 int chain_state;
85 int chain_mode;
86
87};
88
89static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
90
91/* Chain handling macros */
92#define OMAP_DMA_CHAIN_QINIT(chain_id) \
93 do { \
94 dma_linked_lch[chain_id].q_head = \
95 dma_linked_lch[chain_id].q_tail = \
96 dma_linked_lch[chain_id].q_count = 0; \
97 } while (0)
98#define OMAP_DMA_CHAIN_QFULL(chain_id) \
99 (dma_linked_lch[chain_id].no_of_lchs_linked == \
100 dma_linked_lch[chain_id].q_count)
101#define OMAP_DMA_CHAIN_QLAST(chain_id) \
102 do { \
103 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
104 dma_linked_lch[chain_id].q_count) \
105 } while (0)
106#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
107 (0 == dma_linked_lch[chain_id].q_count)
108#define __OMAP_DMA_CHAIN_INCQ(end) \
109 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
110#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
111 do { \
112 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
113 dma_linked_lch[chain_id].q_count--; \
114 } while (0)
115
116#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
117 do { \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
119 dma_linked_lch[chain_id].q_count++; \
120 } while (0)
121#endif
63static int dma_chan_count; 122static int dma_chan_count;
64 123
65static spinlock_t dma_chan_lock; 124static spinlock_t dma_chan_lock;
@@ -73,6 +132,10 @@ static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
73 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD 132 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
74}; 133};
75 134
135static inline void disable_lnk(int lch);
136static void omap_disable_channel_irq(int lch);
137static inline void omap_enable_channel_irq(int lch);
138
76#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ 139#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
77 __FUNCTION__); 140 __FUNCTION__);
78 141
@@ -148,7 +211,7 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
148 omap_writel(l, reg); 211 omap_writel(l, reg);
149 } 212 }
150 213
151 if (cpu_is_omap24xx()) { 214 if (cpu_class_is_omap2()) {
152 if (priority) 215 if (priority)
153 OMAP_DMA_CCR_REG(lch) |= (1 << 6); 216 OMAP_DMA_CCR_REG(lch) |= (1 << 6);
154 else 217 else
@@ -173,7 +236,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
173 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2; 236 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
174 } 237 }
175 238
176 if (cpu_is_omap24xx() && dma_trigger) { 239 if (cpu_class_is_omap2() && dma_trigger) {
177 u32 val = OMAP_DMA_CCR_REG(lch); 240 u32 val = OMAP_DMA_CCR_REG(lch);
178 241
179 val &= ~(3 << 19); 242 val &= ~(3 << 19);
@@ -213,7 +276,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
213 276
214 BUG_ON(omap_dma_in_1510_mode()); 277 BUG_ON(omap_dma_in_1510_mode());
215 278
216 if (cpu_is_omap24xx()) { 279 if (cpu_class_is_omap2()) {
217 REVISIT_24XX(); 280 REVISIT_24XX();
218 return; 281 return;
219 } 282 }
@@ -245,7 +308,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
245 308
246void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) 309void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
247{ 310{
248 if (cpu_is_omap24xx()) { 311 if (cpu_class_is_omap2()) {
249 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16); 312 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
250 OMAP_DMA_CSDP_REG(lch) |= (mode << 16); 313 OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
251 } 314 }
@@ -269,7 +332,7 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
269 OMAP1_DMA_CSSA_L_REG(lch) = src_start; 332 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
270 } 333 }
271 334
272 if (cpu_is_omap24xx()) 335 if (cpu_class_is_omap2())
273 OMAP2_DMA_CSSA_REG(lch) = src_start; 336 OMAP2_DMA_CSSA_REG(lch) = src_start;
274 337
275 OMAP_DMA_CSEI_REG(lch) = src_ei; 338 OMAP_DMA_CSEI_REG(lch) = src_ei;
@@ -289,11 +352,14 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
289 omap_set_dma_dest_params(lch, params->dst_port, 352 omap_set_dma_dest_params(lch, params->dst_port,
290 params->dst_amode, params->dst_start, 353 params->dst_amode, params->dst_start,
291 params->dst_ei, params->dst_fi); 354 params->dst_ei, params->dst_fi);
355 if (params->read_prio || params->write_prio)
356 omap_dma_set_prio_lch(lch, params->read_prio,
357 params->write_prio);
292} 358}
293 359
294void omap_set_dma_src_index(int lch, int eidx, int fidx) 360void omap_set_dma_src_index(int lch, int eidx, int fidx)
295{ 361{
296 if (cpu_is_omap24xx()) { 362 if (cpu_class_is_omap2()) {
297 REVISIT_24XX(); 363 REVISIT_24XX();
298 return; 364 return;
299 } 365 }
@@ -317,13 +383,13 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
317 case OMAP_DMA_DATA_BURST_DIS: 383 case OMAP_DMA_DATA_BURST_DIS:
318 break; 384 break;
319 case OMAP_DMA_DATA_BURST_4: 385 case OMAP_DMA_DATA_BURST_4:
320 if (cpu_is_omap24xx()) 386 if (cpu_class_is_omap2())
321 burst = 0x1; 387 burst = 0x1;
322 else 388 else
323 burst = 0x2; 389 burst = 0x2;
324 break; 390 break;
325 case OMAP_DMA_DATA_BURST_8: 391 case OMAP_DMA_DATA_BURST_8:
326 if (cpu_is_omap24xx()) { 392 if (cpu_class_is_omap2()) {
327 burst = 0x2; 393 burst = 0x2;
328 break; 394 break;
329 } 395 }
@@ -332,7 +398,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
332 * fall through 398 * fall through
333 */ 399 */
334 case OMAP_DMA_DATA_BURST_16: 400 case OMAP_DMA_DATA_BURST_16:
335 if (cpu_is_omap24xx()) { 401 if (cpu_class_is_omap2()) {
336 burst = 0x3; 402 burst = 0x3;
337 break; 403 break;
338 } 404 }
@@ -363,7 +429,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
363 OMAP1_DMA_CDSA_L_REG(lch) = dest_start; 429 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
364 } 430 }
365 431
366 if (cpu_is_omap24xx()) 432 if (cpu_class_is_omap2())
367 OMAP2_DMA_CDSA_REG(lch) = dest_start; 433 OMAP2_DMA_CDSA_REG(lch) = dest_start;
368 434
369 OMAP_DMA_CDEI_REG(lch) = dst_ei; 435 OMAP_DMA_CDEI_REG(lch) = dst_ei;
@@ -372,7 +438,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
372 438
373void omap_set_dma_dest_index(int lch, int eidx, int fidx) 439void omap_set_dma_dest_index(int lch, int eidx, int fidx)
374{ 440{
375 if (cpu_is_omap24xx()) { 441 if (cpu_class_is_omap2()) {
376 REVISIT_24XX(); 442 REVISIT_24XX();
377 return; 443 return;
378 } 444 }
@@ -396,19 +462,19 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
396 case OMAP_DMA_DATA_BURST_DIS: 462 case OMAP_DMA_DATA_BURST_DIS:
397 break; 463 break;
398 case OMAP_DMA_DATA_BURST_4: 464 case OMAP_DMA_DATA_BURST_4:
399 if (cpu_is_omap24xx()) 465 if (cpu_class_is_omap2())
400 burst = 0x1; 466 burst = 0x1;
401 else 467 else
402 burst = 0x2; 468 burst = 0x2;
403 break; 469 break;
404 case OMAP_DMA_DATA_BURST_8: 470 case OMAP_DMA_DATA_BURST_8:
405 if (cpu_is_omap24xx()) 471 if (cpu_class_is_omap2())
406 burst = 0x2; 472 burst = 0x2;
407 else 473 else
408 burst = 0x3; 474 burst = 0x3;
409 break; 475 break;
410 case OMAP_DMA_DATA_BURST_16: 476 case OMAP_DMA_DATA_BURST_16:
411 if (cpu_is_omap24xx()) { 477 if (cpu_class_is_omap2()) {
412 burst = 0x3; 478 burst = 0x3;
413 break; 479 break;
414 } 480 }
@@ -430,7 +496,7 @@ static inline void omap_enable_channel_irq(int lch)
430 /* Clear CSR */ 496 /* Clear CSR */
431 if (cpu_class_is_omap1()) 497 if (cpu_class_is_omap1())
432 status = OMAP_DMA_CSR_REG(lch); 498 status = OMAP_DMA_CSR_REG(lch);
433 else if (cpu_is_omap24xx()) 499 else if (cpu_class_is_omap2())
434 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; 500 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
435 501
436 /* Enable some nice interrupts. */ 502 /* Enable some nice interrupts. */
@@ -441,7 +507,7 @@ static inline void omap_enable_channel_irq(int lch)
441 507
442static void omap_disable_channel_irq(int lch) 508static void omap_disable_channel_irq(int lch)
443{ 509{
444 if (cpu_is_omap24xx()) 510 if (cpu_class_is_omap2())
445 OMAP_DMA_CICR_REG(lch) = 0; 511 OMAP_DMA_CICR_REG(lch) = 0;
446} 512}
447 513
@@ -464,6 +530,12 @@ static inline void enable_lnk(int lch)
464 if (dma_chan[lch].next_lch != -1) 530 if (dma_chan[lch].next_lch != -1)
465 OMAP_DMA_CLNK_CTRL_REG(lch) = 531 OMAP_DMA_CLNK_CTRL_REG(lch) =
466 dma_chan[lch].next_lch | (1 << 15); 532 dma_chan[lch].next_lch | (1 << 15);
533
534#ifndef CONFIG_ARCH_OMAP1
535 if (dma_chan[lch].next_linked_ch != -1)
536 OMAP_DMA_CLNK_CTRL_REG(lch) =
537 dma_chan[lch].next_linked_ch | (1 << 15);
538#endif
467} 539}
468 540
469static inline void disable_lnk(int lch) 541static inline void disable_lnk(int lch)
@@ -475,7 +547,7 @@ static inline void disable_lnk(int lch)
475 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14; 547 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
476 } 548 }
477 549
478 if (cpu_is_omap24xx()) { 550 if (cpu_class_is_omap2()) {
479 omap_disable_channel_irq(lch); 551 omap_disable_channel_irq(lch);
480 /* Clear the ENABLE_LNK bit */ 552 /* Clear the ENABLE_LNK bit */
481 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15); 553 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
@@ -488,7 +560,7 @@ static inline void omap2_enable_irq_lch(int lch)
488{ 560{
489 u32 val; 561 u32 val;
490 562
491 if (!cpu_is_omap24xx()) 563 if (!cpu_class_is_omap2())
492 return; 564 return;
493 565
494 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); 566 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
@@ -522,7 +594,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
522 if (cpu_class_is_omap1()) 594 if (cpu_class_is_omap1())
523 clear_lch_regs(free_ch); 595 clear_lch_regs(free_ch);
524 596
525 if (cpu_is_omap24xx()) 597 if (cpu_class_is_omap2())
526 omap_clear_dma(free_ch); 598 omap_clear_dma(free_ch);
527 599
528 spin_unlock_irqrestore(&dma_chan_lock, flags); 600 spin_unlock_irqrestore(&dma_chan_lock, flags);
@@ -530,11 +602,14 @@ int omap_request_dma(int dev_id, const char *dev_name,
530 chan->dev_name = dev_name; 602 chan->dev_name = dev_name;
531 chan->callback = callback; 603 chan->callback = callback;
532 chan->data = data; 604 chan->data = data;
605#ifndef CONFIG_ARCH_OMAP1
606 chan->chain_id = -1;
607#endif
533 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; 608 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
534 609
535 if (cpu_class_is_omap1()) 610 if (cpu_class_is_omap1())
536 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; 611 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
537 else if (cpu_is_omap24xx()) 612 else if (cpu_class_is_omap2())
538 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | 613 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
539 OMAP2_DMA_TRANS_ERR_IRQ; 614 OMAP2_DMA_TRANS_ERR_IRQ;
540 615
@@ -551,7 +626,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
551 OMAP_DMA_CCR_REG(free_ch) = dev_id; 626 OMAP_DMA_CCR_REG(free_ch) = dev_id;
552 } 627 }
553 628
554 if (cpu_is_omap24xx()) { 629 if (cpu_class_is_omap2()) {
555 omap2_enable_irq_lch(free_ch); 630 omap2_enable_irq_lch(free_ch);
556 631
557 omap_enable_channel_irq(free_ch); 632 omap_enable_channel_irq(free_ch);
@@ -588,7 +663,7 @@ void omap_free_dma(int lch)
588 OMAP_DMA_CCR_REG(lch) = 0; 663 OMAP_DMA_CCR_REG(lch) = 0;
589 } 664 }
590 665
591 if (cpu_is_omap24xx()) { 666 if (cpu_class_is_omap2()) {
592 u32 val; 667 u32 val;
593 /* Disable interrupts */ 668 /* Disable interrupts */
594 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); 669 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
@@ -608,6 +683,67 @@ void omap_free_dma(int lch)
608 } 683 }
609} 684}
610 685
686/**
687 * @brief omap_dma_set_global_params : Set global priority settings for dma
688 *
689 * @param arb_rate
690 * @param max_fifo_depth
691 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
692 * DMA_THREAD_RESERVE_ONET
693 * DMA_THREAD_RESERVE_TWOT
694 * DMA_THREAD_RESERVE_THREET
695 */
696void
697omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
698{
699 u32 reg;
700
701 if (!cpu_class_is_omap2()) {
702 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __FUNCTION__);
703 return;
704 }
705
706 if (arb_rate == 0)
707 arb_rate = 1;
708
709 reg = (arb_rate & 0xff) << 16;
710 reg |= (0xff & max_fifo_depth);
711
712 omap_writel(reg, OMAP_DMA4_GCR_REG);
713}
714EXPORT_SYMBOL(omap_dma_set_global_params);
715
716/**
717 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
718 *
719 * @param lch
720 * @param read_prio - Read priority
721 * @param write_prio - Write priority
722 * Both of the above can be set with one of the following values :
723 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
724 */
725int
726omap_dma_set_prio_lch(int lch, unsigned char read_prio,
727 unsigned char write_prio)
728{
729 u32 w;
730
731 if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) {
732 printk(KERN_ERR "Invalid channel id\n");
733 return -EINVAL;
734 }
735 w = OMAP_DMA_CCR_REG(lch);
736 w &= ~((1 << 6) | (1 << 26));
737 if (cpu_is_omap2430() || cpu_is_omap34xx())
738 w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
739 else
740 w |= ((read_prio & 0x1) << 6);
741
742 OMAP_DMA_CCR_REG(lch) = w;
743 return 0;
744}
745EXPORT_SYMBOL(omap_dma_set_prio_lch);
746
611/* 747/*
612 * Clears any DMA state so the DMA engine is ready to restart with new buffers 748 * Clears any DMA state so the DMA engine is ready to restart with new buffers
613 * through omap_start_dma(). Any buffers in flight are discarded. 749 * through omap_start_dma(). Any buffers in flight are discarded.
@@ -626,9 +762,9 @@ void omap_clear_dma(int lch)
626 status = OMAP_DMA_CSR_REG(lch); 762 status = OMAP_DMA_CSR_REG(lch);
627 } 763 }
628 764
629 if (cpu_is_omap24xx()) { 765 if (cpu_class_is_omap2()) {
630 int i; 766 int i;
631 u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80; 767 u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80;
632 for (i = 0; i < 0x44; i += 4) 768 for (i = 0; i < 0x44; i += 4)
633 omap_writel(0, lch_base + i); 769 omap_writel(0, lch_base + i);
634 } 770 }
@@ -662,7 +798,7 @@ void omap_start_dma(int lch)
662 798
663 cur_lch = next_lch; 799 cur_lch = next_lch;
664 } while (next_lch != -1); 800 } while (next_lch != -1);
665 } else if (cpu_is_omap24xx()) { 801 } else if (cpu_class_is_omap2()) {
666 /* Errata: Need to write lch even if not using chaining */ 802 /* Errata: Need to write lch even if not using chaining */
667 OMAP_DMA_CLNK_CTRL_REG(lch) = lch; 803 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
668 } 804 }
@@ -753,7 +889,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
753 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) | 889 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
754 (OMAP1_DMA_CSSA_U_REG(lch) << 16)); 890 (OMAP1_DMA_CSSA_U_REG(lch) << 16));
755 891
756 if (cpu_is_omap24xx()) 892 if (cpu_class_is_omap2())
757 offset = OMAP_DMA_CSAC_REG(lch); 893 offset = OMAP_DMA_CSAC_REG(lch);
758 894
759 return offset; 895 return offset;
@@ -775,8 +911,8 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
775 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) | 911 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
776 (OMAP1_DMA_CDSA_U_REG(lch) << 16)); 912 (OMAP1_DMA_CDSA_U_REG(lch) << 16));
777 913
778 if (cpu_is_omap24xx()) 914 if (cpu_class_is_omap2())
779 offset = OMAP2_DMA_CDSA_REG(lch); 915 offset = OMAP_DMA_CDAC_REG(lch);
780 916
781 return offset; 917 return offset;
782} 918}
@@ -859,6 +995,605 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
859 dma_chan[lch_head].next_lch = -1; 995 dma_chan[lch_head].next_lch = -1;
860} 996}
861 997
998#ifndef CONFIG_ARCH_OMAP1
999/* Create chain of DMA channesls */
1000static void create_dma_lch_chain(int lch_head, int lch_queue)
1001{
1002 u32 w;
1003
1004 /* Check if this is the first link in chain */
1005 if (dma_chan[lch_head].next_linked_ch == -1) {
1006 dma_chan[lch_head].next_linked_ch = lch_queue;
1007 dma_chan[lch_head].prev_linked_ch = lch_queue;
1008 dma_chan[lch_queue].next_linked_ch = lch_head;
1009 dma_chan[lch_queue].prev_linked_ch = lch_head;
1010 }
1011
1012 /* a link exists, link the new channel in circular chain */
1013 else {
1014 dma_chan[lch_queue].next_linked_ch =
1015 dma_chan[lch_head].next_linked_ch;
1016 dma_chan[lch_queue].prev_linked_ch = lch_head;
1017 dma_chan[lch_head].next_linked_ch = lch_queue;
1018 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1019 lch_queue;
1020 }
1021
1022 w = OMAP_DMA_CLNK_CTRL_REG(lch_head);
1023 w &= ~(0x0f);
1024 w |= lch_queue;
1025 OMAP_DMA_CLNK_CTRL_REG(lch_head) = w;
1026
1027 w = OMAP_DMA_CLNK_CTRL_REG(lch_queue);
1028 w &= ~(0x0f);
1029 w |= (dma_chan[lch_queue].next_linked_ch);
1030 OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w;
1031}
1032
1033/**
1034 * @brief omap_request_dma_chain : Request a chain of DMA channels
1035 *
1036 * @param dev_id - Device id using the dma channel
1037 * @param dev_name - Device name
1038 * @param callback - Call back function
1039 * @chain_id -
1040 * @no_of_chans - Number of channels requested
1041 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1042 * OMAP_DMA_DYNAMIC_CHAIN
1043 * @params - Channel parameters
1044 *
1045 * @return - Succes : 0
1046 * Failure: -EINVAL/-ENOMEM
1047 */
1048int omap_request_dma_chain(int dev_id, const char *dev_name,
1049 void (*callback) (int chain_id, u16 ch_status,
1050 void *data),
1051 int *chain_id, int no_of_chans, int chain_mode,
1052 struct omap_dma_channel_params params)
1053{
1054 int *channels;
1055 int i, err;
1056
1057 /* Is the chain mode valid ? */
1058 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1059 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1060 printk(KERN_ERR "Invalid chain mode requested\n");
1061 return -EINVAL;
1062 }
1063
1064 if (unlikely((no_of_chans < 1
1065 || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) {
1066 printk(KERN_ERR "Invalid Number of channels requested\n");
1067 return -EINVAL;
1068 }
1069
1070 /* Allocate a queue to maintain the status of the channels
1071 * in the chain */
1072 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1073 if (channels == NULL) {
1074 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1075 return -ENOMEM;
1076 }
1077
1078 /* request and reserve DMA channels for the chain */
1079 for (i = 0; i < no_of_chans; i++) {
1080 err = omap_request_dma(dev_id, dev_name,
1081 callback, 0, &channels[i]);
1082 if (err < 0) {
1083 int j;
1084 for (j = 0; j < i; j++)
1085 omap_free_dma(channels[j]);
1086 kfree(channels);
1087 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1088 return err;
1089 }
1090 dma_chan[channels[i]].next_linked_ch = -1;
1091 dma_chan[channels[i]].prev_linked_ch = -1;
1092 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1093
1094 /*
1095 * Allowing client drivers to set common parameters now,
1096 * so that later only relevant (src_start, dest_start
1097 * and element count) can be set
1098 */
1099 omap_set_dma_params(channels[i], &params);
1100 }
1101
1102 *chain_id = channels[0];
1103 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1104 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1105 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1106 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1107
1108 for (i = 0; i < no_of_chans; i++)
1109 dma_chan[channels[i]].chain_id = *chain_id;
1110
1111 /* Reset the Queue pointers */
1112 OMAP_DMA_CHAIN_QINIT(*chain_id);
1113
1114 /* Set up the chain */
1115 if (no_of_chans == 1)
1116 create_dma_lch_chain(channels[0], channels[0]);
1117 else {
1118 for (i = 0; i < (no_of_chans - 1); i++)
1119 create_dma_lch_chain(channels[i], channels[i + 1]);
1120 }
1121 return 0;
1122}
1123EXPORT_SYMBOL(omap_request_dma_chain);
1124
1125/**
1126 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1127 * params after setting it. Dont do this while dma is running!!
1128 *
1129 * @param chain_id - Chained logical channel id.
1130 * @param params
1131 *
1132 * @return - Success : 0
1133 * Failure : -EINVAL
1134 */
1135int omap_modify_dma_chain_params(int chain_id,
1136 struct omap_dma_channel_params params)
1137{
1138 int *channels;
1139 u32 i;
1140
1141 /* Check for input params */
1142 if (unlikely((chain_id < 0
1143 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1144 printk(KERN_ERR "Invalid chain id\n");
1145 return -EINVAL;
1146 }
1147
1148 /* Check if the chain exists */
1149 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1150 printk(KERN_ERR "Chain doesn't exists\n");
1151 return -EINVAL;
1152 }
1153 channels = dma_linked_lch[chain_id].linked_dmach_q;
1154
1155 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1156 /*
1157 * Allowing client drivers to set common parameters now,
1158 * so that later only relevant (src_start, dest_start
1159 * and element count) can be set
1160 */
1161 omap_set_dma_params(channels[i], &params);
1162 }
1163 return 0;
1164}
1165EXPORT_SYMBOL(omap_modify_dma_chain_params);
1166
1167/**
1168 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1169 *
1170 * @param chain_id
1171 *
1172 * @return - Success : 0
1173 * Failure : -EINVAL
1174 */
1175int omap_free_dma_chain(int chain_id)
1176{
1177 int *channels;
1178 u32 i;
1179
1180 /* Check for input params */
1181 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1182 printk(KERN_ERR "Invalid chain id\n");
1183 return -EINVAL;
1184 }
1185
1186 /* Check if the chain exists */
1187 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1188 printk(KERN_ERR "Chain doesn't exists\n");
1189 return -EINVAL;
1190 }
1191
1192 channels = dma_linked_lch[chain_id].linked_dmach_q;
1193 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1194 dma_chan[channels[i]].next_linked_ch = -1;
1195 dma_chan[channels[i]].prev_linked_ch = -1;
1196 dma_chan[channels[i]].chain_id = -1;
1197 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1198 omap_free_dma(channels[i]);
1199 }
1200
1201 kfree(channels);
1202
1203 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1204 dma_linked_lch[chain_id].chain_mode = -1;
1205 dma_linked_lch[chain_id].chain_state = -1;
1206 return (0);
1207}
1208EXPORT_SYMBOL(omap_free_dma_chain);
1209
1210/**
1211 * @brief omap_dma_chain_status - Check if the chain is in
1212 * active / inactive state.
1213 * @param chain_id
1214 *
1215 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1216 * Failure : -EINVAL
1217 */
1218int omap_dma_chain_status(int chain_id)
1219{
1220 /* Check for input params */
1221 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1222 printk(KERN_ERR "Invalid chain id\n");
1223 return -EINVAL;
1224 }
1225
1226 /* Check if the chain exists */
1227 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1228 printk(KERN_ERR "Chain doesn't exists\n");
1229 return -EINVAL;
1230 }
1231 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1232 dma_linked_lch[chain_id].q_count);
1233
1234 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1235 return OMAP_DMA_CHAIN_INACTIVE;
1236 return OMAP_DMA_CHAIN_ACTIVE;
1237}
1238EXPORT_SYMBOL(omap_dma_chain_status);
1239
1240/**
1241 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1242 * set the params and start the transfer.
1243 *
1244 * @param chain_id
1245 * @param src_start - buffer start address
1246 * @param dest_start - Dest address
1247 * @param elem_count
1248 * @param frame_count
1249 * @param callbk_data - channel callback parameter data.
1250 *
1251 * @return - Success : start_dma status
1252 * Failure: -EINVAL/-EBUSY
1253 */
1254int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1255 int elem_count, int frame_count, void *callbk_data)
1256{
1257 int *channels;
1258 u32 w, lch;
1259 int start_dma = 0;
1260
1261 /* if buffer size is less than 1 then there is
1262 * no use of starting the chain */
1263 if (elem_count < 1) {
1264 printk(KERN_ERR "Invalid buffer size\n");
1265 return -EINVAL;
1266 }
1267
1268 /* Check for input params */
1269 if (unlikely((chain_id < 0
1270 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1271 printk(KERN_ERR "Invalid chain id\n");
1272 return -EINVAL;
1273 }
1274
1275 /* Check if the chain exists */
1276 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1277 printk(KERN_ERR "Chain doesn't exist\n");
1278 return -EINVAL;
1279 }
1280
1281 /* Check if all the channels in chain are in use */
1282 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1283 return -EBUSY;
1284
1285 /* Frame count may be negative in case of indexed transfers */
1286 channels = dma_linked_lch[chain_id].linked_dmach_q;
1287
1288 /* Get a free channel */
1289 lch = channels[dma_linked_lch[chain_id].q_tail];
1290
1291 /* Store the callback data */
1292 dma_chan[lch].data = callbk_data;
1293
1294 /* Increment the q_tail */
1295 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1296
1297 /* Set the params to the free channel */
1298 if (src_start != 0)
1299 OMAP2_DMA_CSSA_REG(lch) = src_start;
1300 if (dest_start != 0)
1301 OMAP2_DMA_CDSA_REG(lch) = dest_start;
1302
1303 /* Write the buffer size */
1304 OMAP_DMA_CEN_REG(lch) = elem_count;
1305 OMAP_DMA_CFN_REG(lch) = frame_count;
1306
1307 /* If the chain is dynamically linked,
1308 * then we may have to start the chain if its not active */
1309 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1310
1311 /* In Dynamic chain, if the chain is not started,
1312 * queue the channel */
1313 if (dma_linked_lch[chain_id].chain_state ==
1314 DMA_CHAIN_NOTSTARTED) {
1315 /* Enable the link in previous channel */
1316 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1317 DMA_CH_QUEUED)
1318 enable_lnk(dma_chan[lch].prev_linked_ch);
1319 dma_chan[lch].state = DMA_CH_QUEUED;
1320 }
1321
1322 /* Chain is already started, make sure its active,
1323 * if not then start the chain */
1324 else {
1325 start_dma = 1;
1326
1327 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1328 DMA_CH_STARTED) {
1329 enable_lnk(dma_chan[lch].prev_linked_ch);
1330 dma_chan[lch].state = DMA_CH_QUEUED;
1331 start_dma = 0;
1332 if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG
1333 (dma_chan[lch].prev_linked_ch)))) {
1334 disable_lnk(dma_chan[lch].
1335 prev_linked_ch);
1336 pr_debug("\n prev ch is stopped\n");
1337 start_dma = 1;
1338 }
1339 }
1340
1341 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1342 == DMA_CH_QUEUED) {
1343 enable_lnk(dma_chan[lch].prev_linked_ch);
1344 dma_chan[lch].state = DMA_CH_QUEUED;
1345 start_dma = 0;
1346 }
1347 omap_enable_channel_irq(lch);
1348
1349 w = OMAP_DMA_CCR_REG(lch);
1350
1351 if ((0 == (w & (1 << 24))))
1352 w &= ~(1 << 25);
1353 else
1354 w |= (1 << 25);
1355 if (start_dma == 1) {
1356 if (0 == (w & (1 << 7))) {
1357 w |= (1 << 7);
1358 dma_chan[lch].state = DMA_CH_STARTED;
1359 pr_debug("starting %d\n", lch);
1360 OMAP_DMA_CCR_REG(lch) = w;
1361 } else
1362 start_dma = 0;
1363 } else {
1364 if (0 == (w & (1 << 7)))
1365 OMAP_DMA_CCR_REG(lch) = w;
1366 }
1367 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1368 }
1369 }
1370 return start_dma;
1371}
1372EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1373
1374/**
1375 * @brief omap_start_dma_chain_transfers - Start the chain
1376 *
1377 * @param chain_id
1378 *
1379 * @return - Success : 0
1380 * Failure : -EINVAL/-EBUSY
1381 */
1382int omap_start_dma_chain_transfers(int chain_id)
1383{
1384 int *channels;
1385 u32 w, i;
1386
1387 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1388 printk(KERN_ERR "Invalid chain id\n");
1389 return -EINVAL;
1390 }
1391
1392 channels = dma_linked_lch[chain_id].linked_dmach_q;
1393
1394 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1395 printk(KERN_ERR "Chain is already started\n");
1396 return -EBUSY;
1397 }
1398
1399 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1400 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1401 i++) {
1402 enable_lnk(channels[i]);
1403 omap_enable_channel_irq(channels[i]);
1404 }
1405 } else {
1406 omap_enable_channel_irq(channels[0]);
1407 }
1408
1409 w = OMAP_DMA_CCR_REG(channels[0]);
1410 w |= (1 << 7);
1411 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1412 dma_chan[channels[0]].state = DMA_CH_STARTED;
1413
1414 if ((0 == (w & (1 << 24))))
1415 w &= ~(1 << 25);
1416 else
1417 w |= (1 << 25);
1418 OMAP_DMA_CCR_REG(channels[0]) = w;
1419
1420 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1421 return 0;
1422}
1423EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1424
1425/**
1426 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1427 *
1428 * @param chain_id
1429 *
1430 * @return - Success : 0
1431 * Failure : EINVAL
1432 */
1433int omap_stop_dma_chain_transfers(int chain_id)
1434{
1435 int *channels;
1436 u32 w, i;
1437 u32 sys_cf;
1438
1439 /* Check for input params */
1440 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1441 printk(KERN_ERR "Invalid chain id\n");
1442 return -EINVAL;
1443 }
1444
1445 /* Check if the chain exists */
1446 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1447 printk(KERN_ERR "Chain doesn't exists\n");
1448 return -EINVAL;
1449 }
1450 channels = dma_linked_lch[chain_id].linked_dmach_q;
1451
1452 /* DMA Errata:
1453 * Special programming model needed to disable DMA before end of block
1454 */
1455 sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG);
1456 w = sys_cf;
1457 /* Middle mode reg set no Standby */
1458 w &= ~((1 << 12)|(1 << 13));
1459 omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG);
1460
1461 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1462
1463 /* Stop the Channel transmission */
1464 w = OMAP_DMA_CCR_REG(channels[i]);
1465 w &= ~(1 << 7);
1466 OMAP_DMA_CCR_REG(channels[i]) = w;
1467
1468 /* Disable the link in all the channels */
1469 disable_lnk(channels[i]);
1470 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1471
1472 }
1473 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1474
1475 /* Reset the Queue pointers */
1476 OMAP_DMA_CHAIN_QINIT(chain_id);
1477
1478 /* Errata - put in the old value */
1479 omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG);
1480 return 0;
1481}
1482EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1483
1484/* Get the index of the ongoing DMA in chain */
1485/**
1486 * @brief omap_get_dma_chain_index - Get the element and frame index
1487 * of the ongoing DMA in chain
1488 *
1489 * @param chain_id
1490 * @param ei - Element index
1491 * @param fi - Frame index
1492 *
1493 * @return - Success : 0
1494 * Failure : -EINVAL
1495 */
1496int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1497{
1498 int lch;
1499 int *channels;
1500
1501 /* Check for input params */
1502 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1503 printk(KERN_ERR "Invalid chain id\n");
1504 return -EINVAL;
1505 }
1506
1507 /* Check if the chain exists */
1508 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1509 printk(KERN_ERR "Chain doesn't exists\n");
1510 return -EINVAL;
1511 }
1512 if ((!ei) || (!fi))
1513 return -EINVAL;
1514
1515 channels = dma_linked_lch[chain_id].linked_dmach_q;
1516
1517 /* Get the current channel */
1518 lch = channels[dma_linked_lch[chain_id].q_head];
1519
1520 *ei = OMAP2_DMA_CCEN_REG(lch);
1521 *fi = OMAP2_DMA_CCFN_REG(lch);
1522
1523 return 0;
1524}
1525EXPORT_SYMBOL(omap_get_dma_chain_index);
1526
1527/**
1528 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1529 * ongoing DMA in chain
1530 *
1531 * @param chain_id
1532 *
1533 * @return - Success : Destination position
1534 * Failure : -EINVAL
1535 */
1536int omap_get_dma_chain_dst_pos(int chain_id)
1537{
1538 int lch;
1539 int *channels;
1540
1541 /* Check for input params */
1542 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1543 printk(KERN_ERR "Invalid chain id\n");
1544 return -EINVAL;
1545 }
1546
1547 /* Check if the chain exists */
1548 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1549 printk(KERN_ERR "Chain doesn't exists\n");
1550 return -EINVAL;
1551 }
1552
1553 channels = dma_linked_lch[chain_id].linked_dmach_q;
1554
1555 /* Get the current channel */
1556 lch = channels[dma_linked_lch[chain_id].q_head];
1557
1558 return (OMAP_DMA_CDAC_REG(lch));
1559}
1560EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1561
1562/**
1563 * @brief omap_get_dma_chain_src_pos - Get the source position
1564 * of the ongoing DMA in chain
1565 * @param chain_id
1566 *
1567 * @return - Success : Destination position
1568 * Failure : -EINVAL
1569 */
1570int omap_get_dma_chain_src_pos(int chain_id)
1571{
1572 int lch;
1573 int *channels;
1574
1575 /* Check for input params */
1576 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1577 printk(KERN_ERR "Invalid chain id\n");
1578 return -EINVAL;
1579 }
1580
1581 /* Check if the chain exists */
1582 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1583 printk(KERN_ERR "Chain doesn't exists\n");
1584 return -EINVAL;
1585 }
1586
1587 channels = dma_linked_lch[chain_id].linked_dmach_q;
1588
1589 /* Get the current channel */
1590 lch = channels[dma_linked_lch[chain_id].q_head];
1591
1592 return (OMAP_DMA_CSAC_REG(lch));
1593}
1594EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1595#endif
1596
862/*----------------------------------------------------------------------------*/ 1597/*----------------------------------------------------------------------------*/
863 1598
864#ifdef CONFIG_ARCH_OMAP1 1599#ifdef CONFIG_ARCH_OMAP1
@@ -919,7 +1654,7 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
919#define omap1_dma_irq_handler NULL 1654#define omap1_dma_irq_handler NULL
920#endif 1655#endif
921 1656
922#ifdef CONFIG_ARCH_OMAP2 1657#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
923 1658
924static int omap2_dma_handle_ch(int ch) 1659static int omap2_dma_handle_ch(int ch)
925{ 1660{
@@ -953,8 +1688,33 @@ static int omap2_dma_handle_ch(int ch)
953 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK; 1688 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
954 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); 1689 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
955 1690
956 if (likely(dma_chan[ch].callback != NULL)) 1691 /* If the ch is not chained then chain_id will be -1 */
957 dma_chan[ch].callback(ch, status, dma_chan[ch].data); 1692 if (dma_chan[ch].chain_id != -1) {
1693 int chain_id = dma_chan[ch].chain_id;
1694 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1695 if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15))
1696 dma_chan[dma_chan[ch].next_linked_ch].state =
1697 DMA_CH_STARTED;
1698 if (dma_linked_lch[chain_id].chain_mode ==
1699 OMAP_DMA_DYNAMIC_CHAIN)
1700 disable_lnk(ch);
1701
1702 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1703 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1704
1705 status = OMAP_DMA_CSR_REG(ch);
1706 }
1707
1708 if (likely(dma_chan[ch].callback != NULL)) {
1709 if (dma_chan[ch].chain_id != -1)
1710 dma_chan[ch].callback(dma_chan[ch].chain_id, status,
1711 dma_chan[ch].data);
1712 else
1713 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1714
1715 }
1716
1717 OMAP_DMA_CSR_REG(ch) = status;
958 1718
959 return 0; 1719 return 0;
960} 1720}
@@ -1385,7 +2145,7 @@ static int __init omap_init_dma(void)
1385 w &= ~(1 << 8); 2145 w &= ~(1 << 8);
1386 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 2146 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1387 } 2147 }
1388 } else if (cpu_is_omap24xx()) { 2148 } else if (cpu_class_is_omap2()) {
1389 u8 revision = omap_readb(OMAP_DMA4_REVISION); 2149 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1390 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 2150 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
1391 revision >> 4, revision & 0xf); 2151 revision >> 4, revision & 0xf);
@@ -1428,7 +2188,11 @@ static int __init omap_init_dma(void)
1428 } 2188 }
1429 } 2189 }
1430 2190
1431 if (cpu_is_omap24xx()) 2191 if (cpu_is_omap2430() || cpu_is_omap34xx())
2192 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2193 DMA_DEFAULT_FIFO_DEPTH, 0);
2194
2195 if (cpu_class_is_omap2())
1432 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq); 2196 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
1433 2197
1434 /* FIXME: Update LCD DMA to work on 24xx */ 2198 /* FIXME: Update LCD DMA to work on 24xx */
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 3856f5aedfc1..e719d0eeb5c8 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -48,7 +48,7 @@
48#define OMAP_TIMER_COUNTER_REG 0x28 48#define OMAP_TIMER_COUNTER_REG 0x28
49#define OMAP_TIMER_LOAD_REG 0x2c 49#define OMAP_TIMER_LOAD_REG 0x2c
50#define OMAP_TIMER_TRIGGER_REG 0x30 50#define OMAP_TIMER_TRIGGER_REG 0x30
51#define OMAP_TIMER_WRITE_PEND_REG 0x34 51#define OMAP_TIMER_WRITE_PEND_REG 0x34
52#define OMAP_TIMER_MATCH_REG 0x38 52#define OMAP_TIMER_MATCH_REG 0x38
53#define OMAP_TIMER_CAPTURE_REG 0x3c 53#define OMAP_TIMER_CAPTURE_REG 0x3c
54#define OMAP_TIMER_IF_CTRL_REG 0x40 54#define OMAP_TIMER_IF_CTRL_REG 0x40
@@ -70,7 +70,7 @@
70struct omap_dm_timer { 70struct omap_dm_timer {
71 unsigned long phys_base; 71 unsigned long phys_base;
72 int irq; 72 int irq;
73#ifdef CONFIG_ARCH_OMAP2 73#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
74 struct clk *iclk, *fclk; 74 struct clk *iclk, *fclk;
75#endif 75#endif
76 void __iomem *io_base; 76 void __iomem *io_base;
@@ -82,8 +82,14 @@ struct omap_dm_timer {
82 82
83#define omap_dm_clk_enable(x) 83#define omap_dm_clk_enable(x)
84#define omap_dm_clk_disable(x) 84#define omap_dm_clk_disable(x)
85 85#define omap2_dm_timers NULL
86static struct omap_dm_timer dm_timers[] = { 86#define omap2_dm_source_names NULL
87#define omap2_dm_source_clocks NULL
88#define omap3_dm_timers NULL
89#define omap3_dm_source_names NULL
90#define omap3_dm_source_clocks NULL
91
92static struct omap_dm_timer omap1_dm_timers[] = {
87 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, 93 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
88 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, 94 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
89 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 }, 95 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
@@ -94,12 +100,18 @@ static struct omap_dm_timer dm_timers[] = {
94 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, 100 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
95}; 101};
96 102
103static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
104
97#elif defined(CONFIG_ARCH_OMAP2) 105#elif defined(CONFIG_ARCH_OMAP2)
98 106
99#define omap_dm_clk_enable(x) clk_enable(x) 107#define omap_dm_clk_enable(x) clk_enable(x)
100#define omap_dm_clk_disable(x) clk_disable(x) 108#define omap_dm_clk_disable(x) clk_disable(x)
109#define omap1_dm_timers NULL
110#define omap3_dm_timers NULL
111#define omap3_dm_source_names NULL
112#define omap3_dm_source_clocks NULL
101 113
102static struct omap_dm_timer dm_timers[] = { 114static struct omap_dm_timer omap2_dm_timers[] = {
103 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, 115 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
104 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, 116 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
105 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 }, 117 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
@@ -114,13 +126,48 @@ static struct omap_dm_timer dm_timers[] = {
114 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 }, 126 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
115}; 127};
116 128
117static const char *dm_source_names[] = { 129static const char *omap2_dm_source_names[] __initdata = {
118 "sys_ck", 130 "sys_ck",
119 "func_32k_ck", 131 "func_32k_ck",
120 "alt_ck" 132 "alt_ck",
133 NULL
134};
135
136static struct clk **omap2_dm_source_clocks[3];
137static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
138
139#elif defined(CONFIG_ARCH_OMAP3)
140
141#define omap_dm_clk_enable(x) clk_enable(x)
142#define omap_dm_clk_disable(x) clk_disable(x)
143#define omap1_dm_timers NULL
144#define omap2_dm_timers NULL
145#define omap2_dm_source_names NULL
146#define omap2_dm_source_clocks NULL
147
148static struct omap_dm_timer omap3_dm_timers[] = {
149 { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
150 { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
151 { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
152 { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
153 { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
154 { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
155 { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
156 { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
157 { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
158 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
159 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
160 { .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 },
161};
162
163static const char *omap3_dm_source_names[] __initdata = {
164 "sys_ck",
165 "omap_32k_fck",
166 NULL
121}; 167};
122 168
123static struct clk *dm_source_clocks[3]; 169static struct clk **omap3_dm_source_clocks[2];
170static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
124 171
125#else 172#else
126 173
@@ -128,7 +175,10 @@ static struct clk *dm_source_clocks[3];
128 175
129#endif 176#endif
130 177
131static const int dm_timer_count = ARRAY_SIZE(dm_timers); 178static struct omap_dm_timer *dm_timers;
179static char **dm_source_names;
180static struct clk **dm_source_clocks;
181
132static spinlock_t dm_timer_lock; 182static spinlock_t dm_timer_lock;
133 183
134static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) 184static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
@@ -299,7 +349,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
299 return inputmask; 349 return inputmask;
300} 350}
301 351
302#elif defined(CONFIG_ARCH_OMAP2) 352#elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
303 353
304struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 354struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
305{ 355{
@@ -486,36 +536,46 @@ int omap_dm_timers_active(void)
486 return 0; 536 return 0;
487} 537}
488 538
489int omap_dm_timer_init(void) 539int __init omap_dm_timer_init(void)
490{ 540{
491 struct omap_dm_timer *timer; 541 struct omap_dm_timer *timer;
492 int i; 542 int i;
493 543
494 if (!(cpu_is_omap16xx() || cpu_is_omap24xx())) 544 if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
495 return -ENODEV; 545 return -ENODEV;
496 546
497 spin_lock_init(&dm_timer_lock); 547 spin_lock_init(&dm_timer_lock);
498#ifdef CONFIG_ARCH_OMAP2 548
499 for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) { 549 if (cpu_class_is_omap1())
500 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); 550 dm_timers = omap1_dm_timers;
501 BUG_ON(dm_source_clocks[i] == NULL); 551 else if (cpu_is_omap24xx()) {
552 dm_timers = omap2_dm_timers;
553 dm_source_names = (char **)omap2_dm_source_names;
554 dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
555 } else if (cpu_is_omap34xx()) {
556 dm_timers = omap3_dm_timers;
557 dm_source_names = (char **)omap3_dm_source_names;
558 dm_source_clocks = (struct clk **)omap3_dm_source_clocks;
502 } 559 }
503#endif 560
561 if (cpu_class_is_omap2())
562 for (i = 0; dm_source_names[i] != NULL; i++)
563 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
564
504 if (cpu_is_omap243x()) 565 if (cpu_is_omap243x())
505 dm_timers[0].phys_base = 0x49018000; 566 dm_timers[0].phys_base = 0x49018000;
506 567
507 for (i = 0; i < dm_timer_count; i++) { 568 for (i = 0; i < dm_timer_count; i++) {
508#ifdef CONFIG_ARCH_OMAP2
509 char clk_name[16];
510#endif
511
512 timer = &dm_timers[i]; 569 timer = &dm_timers[i];
513 timer->io_base = (void __iomem *) io_p2v(timer->phys_base); 570 timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
514#ifdef CONFIG_ARCH_OMAP2 571#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
515 sprintf(clk_name, "gpt%d_ick", i + 1); 572 if (cpu_class_is_omap2()) {
516 timer->iclk = clk_get(NULL, clk_name); 573 char clk_name[16];
517 sprintf(clk_name, "gpt%d_fck", i + 1); 574 sprintf(clk_name, "gpt%d_ick", i + 1);
518 timer->fclk = clk_get(NULL, clk_name); 575 timer->iclk = clk_get(NULL, clk_name);
576 sprintf(clk_name, "gpt%d_fck", i + 1);
577 timer->fclk = clk_get(NULL, clk_name);
578 }
519#endif 579#endif
520 } 580 }
521 581
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index b2a87b8ef673..56f4d1394d56 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -110,6 +110,8 @@
110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111#define OMAP24XX_GPIO_RISINGDETECT 0x0048 111#define OMAP24XX_GPIO_RISINGDETECT 0x0048
112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c 112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
113#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 115#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
114#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 116#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
115#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 117#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
@@ -117,17 +119,29 @@
117#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 119#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
118#define OMAP24XX_GPIO_SETDATAOUT 0x0094 120#define OMAP24XX_GPIO_SETDATAOUT 0x0094
119 121
122/*
123 * omap34xx specific GPIO registers
124 */
125
126#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
132
133
120struct gpio_bank { 134struct gpio_bank {
121 void __iomem *base; 135 void __iomem *base;
122 u16 irq; 136 u16 irq;
123 u16 virtual_irq_start; 137 u16 virtual_irq_start;
124 int method; 138 int method;
125 u32 reserved_map; 139 u32 reserved_map;
126#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) 140#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
127 u32 suspend_wakeup; 141 u32 suspend_wakeup;
128 u32 saved_wakeup; 142 u32 saved_wakeup;
129#endif 143#endif
130#ifdef CONFIG_ARCH_OMAP24XX 144#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
131 u32 non_wakeup_gpios; 145 u32 non_wakeup_gpios;
132 u32 enabled_non_wakeup_gpios; 146 u32 enabled_non_wakeup_gpios;
133 147
@@ -192,48 +206,52 @@ static struct gpio_bank gpio_bank_243x[5] = {
192 206
193#endif 207#endif
194 208
209#ifdef CONFIG_ARCH_OMAP34XX
210static struct gpio_bank gpio_bank_34xx[6] = {
211 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
217};
218
219#endif
220
195static struct gpio_bank *gpio_bank; 221static struct gpio_bank *gpio_bank;
196static int gpio_bank_count; 222static int gpio_bank_count;
197 223
198static inline struct gpio_bank *get_gpio_bank(int gpio) 224static inline struct gpio_bank *get_gpio_bank(int gpio)
199{ 225{
200#ifdef CONFIG_ARCH_OMAP15XX
201 if (cpu_is_omap15xx()) { 226 if (cpu_is_omap15xx()) {
202 if (OMAP_GPIO_IS_MPUIO(gpio)) 227 if (OMAP_GPIO_IS_MPUIO(gpio))
203 return &gpio_bank[0]; 228 return &gpio_bank[0];
204 return &gpio_bank[1]; 229 return &gpio_bank[1];
205 } 230 }
206#endif
207#if defined(CONFIG_ARCH_OMAP16XX)
208 if (cpu_is_omap16xx()) { 231 if (cpu_is_omap16xx()) {
209 if (OMAP_GPIO_IS_MPUIO(gpio)) 232 if (OMAP_GPIO_IS_MPUIO(gpio))
210 return &gpio_bank[0]; 233 return &gpio_bank[0];
211 return &gpio_bank[1 + (gpio >> 4)]; 234 return &gpio_bank[1 + (gpio >> 4)];
212 } 235 }
213#endif
214#ifdef CONFIG_ARCH_OMAP730
215 if (cpu_is_omap730()) { 236 if (cpu_is_omap730()) {
216 if (OMAP_GPIO_IS_MPUIO(gpio)) 237 if (OMAP_GPIO_IS_MPUIO(gpio))
217 return &gpio_bank[0]; 238 return &gpio_bank[0];
218 return &gpio_bank[1 + (gpio >> 5)]; 239 return &gpio_bank[1 + (gpio >> 5)];
219 } 240 }
220#endif
221#ifdef CONFIG_ARCH_OMAP24XX
222 if (cpu_is_omap24xx()) 241 if (cpu_is_omap24xx())
223 return &gpio_bank[gpio >> 5]; 242 return &gpio_bank[gpio >> 5];
224#endif 243 if (cpu_is_omap34xx())
244 return &gpio_bank[gpio >> 5];
225} 245}
226 246
227static inline int get_gpio_index(int gpio) 247static inline int get_gpio_index(int gpio)
228{ 248{
229#ifdef CONFIG_ARCH_OMAP730
230 if (cpu_is_omap730()) 249 if (cpu_is_omap730())
231 return gpio & 0x1f; 250 return gpio & 0x1f;
232#endif
233#ifdef CONFIG_ARCH_OMAP24XX
234 if (cpu_is_omap24xx()) 251 if (cpu_is_omap24xx())
235 return gpio & 0x1f; 252 return gpio & 0x1f;
236#endif 253 if (cpu_is_omap34xx())
254 return gpio & 0x1f;
237 return gpio & 0x0f; 255 return gpio & 0x0f;
238} 256}
239 257
@@ -241,29 +259,21 @@ static inline int gpio_valid(int gpio)
241{ 259{
242 if (gpio < 0) 260 if (gpio < 0)
243 return -1; 261 return -1;
244#ifndef CONFIG_ARCH_OMAP24XX 262 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
245 if (OMAP_GPIO_IS_MPUIO(gpio)) {
246 if (gpio >= OMAP_MAX_GPIO_LINES + 16) 263 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
247 return -1; 264 return -1;
248 return 0; 265 return 0;
249 } 266 }
250#endif
251#ifdef CONFIG_ARCH_OMAP15XX
252 if (cpu_is_omap15xx() && gpio < 16) 267 if (cpu_is_omap15xx() && gpio < 16)
253 return 0; 268 return 0;
254#endif
255#if defined(CONFIG_ARCH_OMAP16XX)
256 if ((cpu_is_omap16xx()) && gpio < 64) 269 if ((cpu_is_omap16xx()) && gpio < 64)
257 return 0; 270 return 0;
258#endif
259#ifdef CONFIG_ARCH_OMAP730
260 if (cpu_is_omap730() && gpio < 192) 271 if (cpu_is_omap730() && gpio < 192)
261 return 0; 272 return 0;
262#endif
263#ifdef CONFIG_ARCH_OMAP24XX
264 if (cpu_is_omap24xx() && gpio < 128) 273 if (cpu_is_omap24xx() && gpio < 128)
265 return 0; 274 return 0;
266#endif 275 if (cpu_is_omap34xx() && gpio < 160)
276 return 0;
267 return -1; 277 return -1;
268} 278}
269 279
@@ -303,7 +313,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
303 reg += OMAP730_GPIO_DIR_CONTROL; 313 reg += OMAP730_GPIO_DIR_CONTROL;
304 break; 314 break;
305#endif 315#endif
306#ifdef CONFIG_ARCH_OMAP24XX 316#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
307 case METHOD_GPIO_24XX: 317 case METHOD_GPIO_24XX:
308 reg += OMAP24XX_GPIO_OE; 318 reg += OMAP24XX_GPIO_OE;
309 break; 319 break;
@@ -377,7 +387,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
377 l &= ~(1 << gpio); 387 l &= ~(1 << gpio);
378 break; 388 break;
379#endif 389#endif
380#ifdef CONFIG_ARCH_OMAP24XX 390#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
381 case METHOD_GPIO_24XX: 391 case METHOD_GPIO_24XX:
382 if (enable) 392 if (enable)
383 reg += OMAP24XX_GPIO_SETDATAOUT; 393 reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -435,7 +445,7 @@ int omap_get_gpio_datain(int gpio)
435 reg += OMAP730_GPIO_DATA_INPUT; 445 reg += OMAP730_GPIO_DATA_INPUT;
436 break; 446 break;
437#endif 447#endif
438#ifdef CONFIG_ARCH_OMAP24XX 448#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
439 case METHOD_GPIO_24XX: 449 case METHOD_GPIO_24XX:
440 reg += OMAP24XX_GPIO_DATAIN; 450 reg += OMAP24XX_GPIO_DATAIN;
441 break; 451 break;
@@ -455,8 +465,50 @@ do { \
455 __raw_writel(l, base + reg); \ 465 __raw_writel(l, base + reg); \
456} while(0) 466} while(0)
457 467
458#ifdef CONFIG_ARCH_OMAP24XX 468void omap_set_gpio_debounce(int gpio, int enable)
459static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 469{
470 struct gpio_bank *bank;
471 void __iomem *reg;
472 u32 val, l = 1 << get_gpio_index(gpio);
473
474 if (cpu_class_is_omap1())
475 return;
476
477 bank = get_gpio_bank(gpio);
478 reg = bank->base;
479
480 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
481 val = __raw_readl(reg);
482
483 if (enable)
484 val |= l;
485 else
486 val &= ~l;
487
488 __raw_writel(val, reg);
489}
490EXPORT_SYMBOL(omap_set_gpio_debounce);
491
492void omap_set_gpio_debounce_time(int gpio, int enc_time)
493{
494 struct gpio_bank *bank;
495 void __iomem *reg;
496
497 if (cpu_class_is_omap1())
498 return;
499
500 bank = get_gpio_bank(gpio);
501 reg = bank->base;
502
503 enc_time &= 0xff;
504 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
505 __raw_writel(enc_time, reg);
506}
507EXPORT_SYMBOL(omap_set_gpio_debounce_time);
508
509#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
510static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
511 int trigger)
460{ 512{
461 void __iomem *base = bank->base; 513 void __iomem *base = bank->base;
462 u32 gpio_bit = 1 << gpio; 514 u32 gpio_bit = 1 << gpio;
@@ -469,19 +521,25 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, in
469 trigger & __IRQT_RISEDGE); 521 trigger & __IRQT_RISEDGE);
470 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 522 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
471 trigger & __IRQT_FALEDGE); 523 trigger & __IRQT_FALEDGE);
524
472 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 525 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
473 if (trigger != 0) 526 if (trigger != 0)
474 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA); 527 __raw_writel(1 << gpio, bank->base
528 + OMAP24XX_GPIO_SETWKUENA);
475 else 529 else
476 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA); 530 __raw_writel(1 << gpio, bank->base
531 + OMAP24XX_GPIO_CLEARWKUENA);
477 } else { 532 } else {
478 if (trigger != 0) 533 if (trigger != 0)
479 bank->enabled_non_wakeup_gpios |= gpio_bit; 534 bank->enabled_non_wakeup_gpios |= gpio_bit;
480 else 535 else
481 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 536 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
482 } 537 }
483 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level 538
484 * triggering requested. */ 539 /*
540 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
541 * level triggering requested.
542 */
485} 543}
486#endif 544#endif
487 545
@@ -547,7 +605,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
547 goto bad; 605 goto bad;
548 break; 606 break;
549#endif 607#endif
550#ifdef CONFIG_ARCH_OMAP24XX 608#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
551 case METHOD_GPIO_24XX: 609 case METHOD_GPIO_24XX:
552 set_24xx_gpio_triggering(bank, gpio, trigger); 610 set_24xx_gpio_triggering(bank, gpio, trigger);
553 break; 611 break;
@@ -567,7 +625,7 @@ static int gpio_irq_type(unsigned irq, unsigned type)
567 unsigned gpio; 625 unsigned gpio;
568 int retval; 626 int retval;
569 627
570 if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE) 628 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
571 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 629 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
572 else 630 else
573 gpio = irq - IH_GPIO_BASE; 631 gpio = irq - IH_GPIO_BASE;
@@ -579,7 +637,7 @@ static int gpio_irq_type(unsigned irq, unsigned type)
579 return -EINVAL; 637 return -EINVAL;
580 638
581 /* OMAP1 allows only only edge triggering */ 639 /* OMAP1 allows only only edge triggering */
582 if (!cpu_is_omap24xx() 640 if (!cpu_class_is_omap2()
583 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 641 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
584 return -EINVAL; 642 return -EINVAL;
585 643
@@ -620,7 +678,7 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
620 reg += OMAP730_GPIO_INT_STATUS; 678 reg += OMAP730_GPIO_INT_STATUS;
621 break; 679 break;
622#endif 680#endif
623#ifdef CONFIG_ARCH_OMAP24XX 681#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
624 case METHOD_GPIO_24XX: 682 case METHOD_GPIO_24XX:
625 reg += OMAP24XX_GPIO_IRQSTATUS1; 683 reg += OMAP24XX_GPIO_IRQSTATUS1;
626 break; 684 break;
@@ -632,8 +690,10 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
632 __raw_writel(gpio_mask, reg); 690 __raw_writel(gpio_mask, reg);
633 691
634 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 692 /* Workaround for clearing DSP GPIO interrupts to allow retention */
635 if (cpu_is_omap2420()) 693#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
694 if (cpu_is_omap24xx() || cpu_is_omap34xx())
636 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); 695 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
696#endif
637} 697}
638 698
639static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 699static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -676,7 +736,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
676 inv = 1; 736 inv = 1;
677 break; 737 break;
678#endif 738#endif
679#ifdef CONFIG_ARCH_OMAP24XX 739#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
680 case METHOD_GPIO_24XX: 740 case METHOD_GPIO_24XX:
681 reg += OMAP24XX_GPIO_IRQENABLE1; 741 reg += OMAP24XX_GPIO_IRQENABLE1;
682 mask = 0xffffffff; 742 mask = 0xffffffff;
@@ -739,7 +799,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
739 l |= gpio_mask; 799 l |= gpio_mask;
740 break; 800 break;
741#endif 801#endif
742#ifdef CONFIG_ARCH_OMAP24XX 802#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
743 case METHOD_GPIO_24XX: 803 case METHOD_GPIO_24XX:
744 if (enable) 804 if (enable)
745 reg += OMAP24XX_GPIO_SETIRQENABLE1; 805 reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -785,7 +845,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
785 spin_unlock(&bank->lock); 845 spin_unlock(&bank->lock);
786 return 0; 846 return 0;
787#endif 847#endif
788#ifdef CONFIG_ARCH_OMAP24XX 848#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
789 case METHOD_GPIO_24XX: 849 case METHOD_GPIO_24XX:
790 if (bank->non_wakeup_gpios & (1 << gpio)) { 850 if (bank->non_wakeup_gpios & (1 << gpio)) {
791 printk(KERN_ERR "Unable to modify wakeup on " 851 printk(KERN_ERR "Unable to modify wakeup on "
@@ -891,7 +951,7 @@ void omap_free_gpio(int gpio)
891 __raw_writel(1 << get_gpio_index(gpio), reg); 951 __raw_writel(1 << get_gpio_index(gpio), reg);
892 } 952 }
893#endif 953#endif
894#ifdef CONFIG_ARCH_OMAP24XX 954#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
895 if (bank->method == METHOD_GPIO_24XX) { 955 if (bank->method == METHOD_GPIO_24XX) {
896 /* Disable wake-up during idle for dynamic tick */ 956 /* Disable wake-up during idle for dynamic tick */
897 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 957 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
@@ -940,7 +1000,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
940 if (bank->method == METHOD_GPIO_730) 1000 if (bank->method == METHOD_GPIO_730)
941 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; 1001 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
942#endif 1002#endif
943#ifdef CONFIG_ARCH_OMAP24XX 1003#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
944 if (bank->method == METHOD_GPIO_24XX) 1004 if (bank->method == METHOD_GPIO_24XX)
945 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; 1005 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
946#endif 1006#endif
@@ -954,7 +1014,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
954 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) 1014 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
955 isr &= 0x0000ffff; 1015 isr &= 0x0000ffff;
956 1016
957 if (cpu_is_omap24xx()) { 1017 if (cpu_class_is_omap2()) {
958 level_mask = 1018 level_mask =
959 __raw_readl(bank->base + 1019 __raw_readl(bank->base +
960 OMAP24XX_GPIO_LEVELDETECT0) | 1020 OMAP24XX_GPIO_LEVELDETECT0) |
@@ -1023,7 +1083,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1023 } 1083 }
1024 } 1084 }
1025 1085
1026 if (cpu_is_omap24xx()) { 1086 if (cpu_class_is_omap2()) {
1027 /* clear level sensitive interrupts after handler(s) */ 1087 /* clear level sensitive interrupts after handler(s) */
1028 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0); 1088 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1029 _clear_gpio_irqbank(bank, isr_saved & level_mask); 1089 _clear_gpio_irqbank(bank, isr_saved & level_mask);
@@ -1199,21 +1259,35 @@ static inline void mpuio_init(void) {}
1199/*---------------------------------------------------------------------*/ 1259/*---------------------------------------------------------------------*/
1200 1260
1201static int initialized; 1261static int initialized;
1262#if !defined(CONFIG_ARCH_OMAP3)
1202static struct clk * gpio_ick; 1263static struct clk * gpio_ick;
1264#endif
1265
1266#if defined(CONFIG_ARCH_OMAP2)
1203static struct clk * gpio_fck; 1267static struct clk * gpio_fck;
1268#endif
1204 1269
1205#ifdef CONFIG_ARCH_OMAP2430 1270#if defined(CONFIG_ARCH_OMAP2430)
1206static struct clk * gpio5_ick; 1271static struct clk * gpio5_ick;
1207static struct clk * gpio5_fck; 1272static struct clk * gpio5_fck;
1208#endif 1273#endif
1209 1274
1275#if defined(CONFIG_ARCH_OMAP3)
1276static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1277static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1278#endif
1279
1210static int __init _omap_gpio_init(void) 1280static int __init _omap_gpio_init(void)
1211{ 1281{
1212 int i; 1282 int i;
1213 struct gpio_bank *bank; 1283 struct gpio_bank *bank;
1284#if defined(CONFIG_ARCH_OMAP3)
1285 char clk_name[11];
1286#endif
1214 1287
1215 initialized = 1; 1288 initialized = 1;
1216 1289
1290#if defined(CONFIG_ARCH_OMAP1)
1217 if (cpu_is_omap15xx()) { 1291 if (cpu_is_omap15xx()) {
1218 gpio_ick = clk_get(NULL, "arm_gpio_ck"); 1292 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1219 if (IS_ERR(gpio_ick)) 1293 if (IS_ERR(gpio_ick))
@@ -1221,7 +1295,9 @@ static int __init _omap_gpio_init(void)
1221 else 1295 else
1222 clk_enable(gpio_ick); 1296 clk_enable(gpio_ick);
1223 } 1297 }
1224 if (cpu_is_omap24xx()) { 1298#endif
1299#if defined(CONFIG_ARCH_OMAP2)
1300 if (cpu_class_is_omap2()) {
1225 gpio_ick = clk_get(NULL, "gpios_ick"); 1301 gpio_ick = clk_get(NULL, "gpios_ick");
1226 if (IS_ERR(gpio_ick)) 1302 if (IS_ERR(gpio_ick))
1227 printk("Could not get gpios_ick\n"); 1303 printk("Could not get gpios_ick\n");
@@ -1234,9 +1310,9 @@ static int __init _omap_gpio_init(void)
1234 clk_enable(gpio_fck); 1310 clk_enable(gpio_fck);
1235 1311
1236 /* 1312 /*
1237 * On 2430 GPIO 5 uses CORE L4 ICLK 1313 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1238 */ 1314 */
1239#ifdef CONFIG_ARCH_OMAP2430 1315#if defined(CONFIG_ARCH_OMAP2430)
1240 if (cpu_is_omap2430()) { 1316 if (cpu_is_omap2430()) {
1241 gpio5_ick = clk_get(NULL, "gpio5_ick"); 1317 gpio5_ick = clk_get(NULL, "gpio5_ick");
1242 if (IS_ERR(gpio5_ick)) 1318 if (IS_ERR(gpio5_ick))
@@ -1250,7 +1326,28 @@ static int __init _omap_gpio_init(void)
1250 clk_enable(gpio5_fck); 1326 clk_enable(gpio5_fck);
1251 } 1327 }
1252#endif 1328#endif
1253} 1329 }
1330#endif
1331
1332#if defined(CONFIG_ARCH_OMAP3)
1333 if (cpu_is_omap34xx()) {
1334 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1335 sprintf(clk_name, "gpio%d_ick", i + 1);
1336 gpio_iclks[i] = clk_get(NULL, clk_name);
1337 if (IS_ERR(gpio_iclks[i]))
1338 printk(KERN_ERR "Could not get %s\n", clk_name);
1339 else
1340 clk_enable(gpio_iclks[i]);
1341 sprintf(clk_name, "gpio%d_fck", i + 1);
1342 gpio_fclks[i] = clk_get(NULL, clk_name);
1343 if (IS_ERR(gpio_fclks[i]))
1344 printk(KERN_ERR "Could not get %s\n", clk_name);
1345 else
1346 clk_enable(gpio_fclks[i]);
1347 }
1348 }
1349#endif
1350
1254 1351
1255#ifdef CONFIG_ARCH_OMAP15XX 1352#ifdef CONFIG_ARCH_OMAP15XX
1256 if (cpu_is_omap15xx()) { 1353 if (cpu_is_omap15xx()) {
@@ -1298,6 +1395,17 @@ static int __init _omap_gpio_init(void)
1298 (rev >> 4) & 0x0f, rev & 0x0f); 1395 (rev >> 4) & 0x0f, rev & 0x0f);
1299 } 1396 }
1300#endif 1397#endif
1398#ifdef CONFIG_ARCH_OMAP34XX
1399 if (cpu_is_omap34xx()) {
1400 int rev;
1401
1402 gpio_bank_count = OMAP34XX_NR_GPIOS;
1403 gpio_bank = gpio_bank_34xx;
1404 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1405 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1406 (rev >> 4) & 0x0f, rev & 0x0f);
1407 }
1408#endif
1301 for (i = 0; i < gpio_bank_count; i++) { 1409 for (i = 0; i < gpio_bank_count; i++) {
1302 int j, gpio_count = 16; 1410 int j, gpio_count = 16;
1303 1411
@@ -1307,28 +1415,23 @@ static int __init _omap_gpio_init(void)
1307 spin_lock_init(&bank->lock); 1415 spin_lock_init(&bank->lock);
1308 if (bank_is_mpuio(bank)) 1416 if (bank_is_mpuio(bank))
1309 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); 1417 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1310#ifdef CONFIG_ARCH_OMAP15XX 1418 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1311 if (bank->method == METHOD_GPIO_1510) {
1312 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); 1419 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1313 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); 1420 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1314 } 1421 }
1315#endif 1422 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1316#if defined(CONFIG_ARCH_OMAP16XX)
1317 if (bank->method == METHOD_GPIO_1610) {
1318 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); 1423 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1319 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); 1424 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1320 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); 1425 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1321 } 1426 }
1322#endif 1427 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1323#ifdef CONFIG_ARCH_OMAP730
1324 if (bank->method == METHOD_GPIO_730) {
1325 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); 1428 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1326 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); 1429 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1327 1430
1328 gpio_count = 32; /* 730 has 32-bit GPIOs */ 1431 gpio_count = 32; /* 730 has 32-bit GPIOs */
1329 } 1432 }
1330#endif 1433
1331#ifdef CONFIG_ARCH_OMAP24XX 1434#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1332 if (bank->method == METHOD_GPIO_24XX) { 1435 if (bank->method == METHOD_GPIO_24XX) {
1333 static const u32 non_wakeup_gpios[] = { 1436 static const u32 non_wakeup_gpios[] = {
1334 0xe203ffc0, 0x08700040 1437 0xe203ffc0, 0x08700040
@@ -1364,21 +1467,21 @@ static int __init _omap_gpio_init(void)
1364 if (cpu_is_omap16xx()) 1467 if (cpu_is_omap16xx())
1365 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); 1468 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1366 1469
1367#ifdef CONFIG_ARCH_OMAP24XX
1368 /* Enable autoidle for the OCP interface */ 1470 /* Enable autoidle for the OCP interface */
1369 if (cpu_is_omap24xx()) 1471 if (cpu_is_omap24xx())
1370 omap_writel(1 << 0, 0x48019010); 1472 omap_writel(1 << 0, 0x48019010);
1371#endif 1473 if (cpu_is_omap34xx())
1474 omap_writel(1 << 0, 0x48306814);
1372 1475
1373 return 0; 1476 return 0;
1374} 1477}
1375 1478
1376#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) 1479#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1377static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) 1480static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1378{ 1481{
1379 int i; 1482 int i;
1380 1483
1381 if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) 1484 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1382 return 0; 1485 return 0;
1383 1486
1384 for (i = 0; i < gpio_bank_count; i++) { 1487 for (i = 0; i < gpio_bank_count; i++) {
@@ -1395,7 +1498,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1395 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1498 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1396 break; 1499 break;
1397#endif 1500#endif
1398#ifdef CONFIG_ARCH_OMAP24XX 1501#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1399 case METHOD_GPIO_24XX: 1502 case METHOD_GPIO_24XX:
1400 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; 1503 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1401 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1504 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
@@ -1435,7 +1538,7 @@ static int omap_gpio_resume(struct sys_device *dev)
1435 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1538 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1436 break; 1539 break;
1437#endif 1540#endif
1438#ifdef CONFIG_ARCH_OMAP24XX 1541#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1439 case METHOD_GPIO_24XX: 1542 case METHOD_GPIO_24XX:
1440 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1543 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1441 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1544 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
@@ -1467,7 +1570,7 @@ static struct sys_device omap_gpio_device = {
1467 1570
1468#endif 1571#endif
1469 1572
1470#ifdef CONFIG_ARCH_OMAP24XX 1573#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1471 1574
1472static int workaround_enabled; 1575static int workaround_enabled;
1473 1576
@@ -1483,15 +1586,19 @@ void omap2_gpio_prepare_for_retention(void)
1483 1586
1484 if (!(bank->enabled_non_wakeup_gpios)) 1587 if (!(bank->enabled_non_wakeup_gpios))
1485 continue; 1588 continue;
1589#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1486 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1590 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1487 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1591 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1488 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); 1592 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1593#endif
1489 bank->saved_fallingdetect = l1; 1594 bank->saved_fallingdetect = l1;
1490 bank->saved_risingdetect = l2; 1595 bank->saved_risingdetect = l2;
1491 l1 &= ~bank->enabled_non_wakeup_gpios; 1596 l1 &= ~bank->enabled_non_wakeup_gpios;
1492 l2 &= ~bank->enabled_non_wakeup_gpios; 1597 l2 &= ~bank->enabled_non_wakeup_gpios;
1598#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1493 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1599 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1494 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); 1600 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1601#endif
1495 c++; 1602 c++;
1496 } 1603 }
1497 if (!c) { 1604 if (!c) {
@@ -1513,26 +1620,31 @@ void omap2_gpio_resume_after_retention(void)
1513 1620
1514 if (!(bank->enabled_non_wakeup_gpios)) 1621 if (!(bank->enabled_non_wakeup_gpios))
1515 continue; 1622 continue;
1623#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1516 __raw_writel(bank->saved_fallingdetect, 1624 __raw_writel(bank->saved_fallingdetect,
1517 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1625 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1518 __raw_writel(bank->saved_risingdetect, 1626 __raw_writel(bank->saved_risingdetect,
1519 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1627 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1628#endif
1520 /* Check if any of the non-wakeup interrupt GPIOs have changed 1629 /* Check if any of the non-wakeup interrupt GPIOs have changed
1521 * state. If so, generate an IRQ by software. This is 1630 * state. If so, generate an IRQ by software. This is
1522 * horribly racy, but it's the best we can do to work around 1631 * horribly racy, but it's the best we can do to work around
1523 * this silicon bug. */ 1632 * this silicon bug. */
1633#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1524 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1634 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1635#endif
1525 l ^= bank->saved_datain; 1636 l ^= bank->saved_datain;
1526 l &= bank->non_wakeup_gpios; 1637 l &= bank->non_wakeup_gpios;
1527 if (l) { 1638 if (l) {
1528 u32 old0, old1; 1639 u32 old0, old1;
1529 1640#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1530 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1641 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1531 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1642 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1532 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1643 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1533 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1644 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1534 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1645 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1535 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1646 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1647#endif
1536 } 1648 }
1537 } 1649 }
1538 1650
@@ -1561,8 +1673,8 @@ static int __init omap_gpio_sysinit(void)
1561 1673
1562 mpuio_init(); 1674 mpuio_init();
1563 1675
1564#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) 1676#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1565 if (cpu_is_omap16xx() || cpu_is_omap24xx()) { 1677 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1566 if (ret == 0) { 1678 if (ret == 0) {
1567 ret = sysdev_class_register(&omap_gpio_sysclass); 1679 ret = sysdev_class_register(&omap_gpio_sysclass);
1568 if (ret == 0) 1680 if (ret == 0)
@@ -1624,7 +1736,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
1624 1736
1625 if (bank_is_mpuio(bank)) 1737 if (bank_is_mpuio(bank))
1626 gpio = OMAP_MPUIO(0); 1738 gpio = OMAP_MPUIO(0);
1627 else if (cpu_is_omap24xx() || cpu_is_omap730()) 1739 else if (cpu_class_is_omap2() || cpu_is_omap730())
1628 bankwidth = 32; 1740 bankwidth = 32;
1629 1741
1630 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { 1742 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
new file mode 100644
index 000000000000..7990ab185bb1
--- /dev/null
+++ b/arch/arm/plat-omap/i2c.c
@@ -0,0 +1,148 @@
1/*
2 * linux/arch/arm/plat-omap/i2c.c
3 *
4 * Helper module for board specific I2C bus registration
5 *
6 * Copyright (C) 2007 Nokia Corporation.
7 *
8 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * 02110-1301 USA
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/platform_device.h>
28#include <linux/i2c.h>
29#include <asm/mach-types.h>
30#include <asm/arch/mux.h>
31
32#define OMAP_I2C_SIZE 0x3f
33#define OMAP1_I2C_BASE 0xfffb3800
34#define OMAP2_I2C_BASE1 0x48070000
35#define OMAP2_I2C_BASE2 0x48072000
36#define OMAP2_I2C_BASE3 0x48060000
37
38static const char name[] = "i2c_omap";
39
40#define I2C_RESOURCE_BUILDER(base, irq) \
41 { \
42 .start = (base), \
43 .end = (base) + OMAP_I2C_SIZE, \
44 .flags = IORESOURCE_MEM, \
45 }, \
46 { \
47 .start = (irq), \
48 .flags = IORESOURCE_IRQ, \
49 },
50
51static struct resource i2c_resources[][2] = {
52 { I2C_RESOURCE_BUILDER(0, 0) },
53#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
54 { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) },
55#endif
56#if defined(CONFIG_ARCH_OMAP34XX)
57 { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) },
58#endif
59};
60
61#define I2C_DEV_BUILDER(bus_id, res, data) \
62 { \
63 .id = (bus_id), \
64 .name = name, \
65 .num_resources = ARRAY_SIZE(res), \
66 .resource = (res), \
67 .dev = { \
68 .platform_data = (data), \
69 }, \
70 }
71
72static u32 i2c_rate[ARRAY_SIZE(i2c_resources)];
73static struct platform_device omap_i2c_devices[] = {
74 I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]),
75#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
76 I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]),
77#endif
78#if defined(CONFIG_ARCH_OMAP34XX)
79 I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]),
80#endif
81};
82
83static void __init omap_i2c_mux_pins(int bus_id)
84{
85 /* TODO: Muxing for OMAP3 */
86 switch (bus_id) {
87 case 1:
88 if (cpu_class_is_omap1()) {
89 omap_cfg_reg(I2C_SCL);
90 omap_cfg_reg(I2C_SDA);
91 } else if (cpu_is_omap24xx()) {
92 omap_cfg_reg(M19_24XX_I2C1_SCL);
93 omap_cfg_reg(L15_24XX_I2C1_SDA);
94 }
95 break;
96 case 2:
97 if (cpu_is_omap24xx()) {
98 omap_cfg_reg(J15_24XX_I2C2_SCL);
99 omap_cfg_reg(H19_24XX_I2C2_SDA);
100 }
101 break;
102 }
103}
104
105int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
106 struct i2c_board_info const *info,
107 unsigned len)
108{
109 int ports, err;
110 struct platform_device *pdev;
111 struct resource *res;
112 resource_size_t base, irq;
113
114 if (cpu_class_is_omap1())
115 ports = 1;
116 else if (cpu_is_omap24xx())
117 ports = 2;
118 else if (cpu_is_omap34xx())
119 ports = 3;
120
121 BUG_ON(bus_id < 1 || bus_id > ports);
122
123 if (info) {
124 err = i2c_register_board_info(bus_id, info, len);
125 if (err)
126 return err;
127 }
128
129 pdev = &omap_i2c_devices[bus_id - 1];
130 *(u32 *)pdev->dev.platform_data = clkrate;
131
132 if (bus_id == 1) {
133 res = pdev->resource;
134 if (cpu_class_is_omap1()) {
135 base = OMAP1_I2C_BASE;
136 irq = INT_I2C;
137 } else {
138 base = OMAP2_I2C_BASE1;
139 irq = INT_24XX_I2C1_IRQ;
140 }
141 res[0].start = base;
142 res[0].end = base + OMAP_I2C_SIZE;
143 res[1].start = irq;
144 }
145
146 omap_i2c_mux_pins(bus_id);
147 return platform_device_register(pdev);
148}
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 2af5bd5a1344..9cf83c4da9fa 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -201,6 +201,14 @@ static int omap_mcbsp_check(unsigned int id)
201static void omap_mcbsp_dsp_request(void) 201static void omap_mcbsp_dsp_request(void)
202{ 202{
203 if (cpu_is_omap15xx() || cpu_is_omap16xx()) { 203 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
204 int ret;
205
206 ret = omap_dsp_request_mem();
207 if (ret < 0) {
208 printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
209 return;
210 }
211
204 clk_enable(mcbsp_dsp_ck); 212 clk_enable(mcbsp_dsp_ck);
205 clk_enable(mcbsp_api_ck); 213 clk_enable(mcbsp_api_ck);
206 214
@@ -219,6 +227,7 @@ static void omap_mcbsp_dsp_request(void)
219static void omap_mcbsp_dsp_free(void) 227static void omap_mcbsp_dsp_free(void)
220{ 228{
221 if (cpu_is_omap15xx() || cpu_is_omap16xx()) { 229 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
230 omap_dsp_release_mem();
222 clk_disable(mcbsp_dspxor_ck); 231 clk_disable(mcbsp_dspxor_ck);
223 clk_disable(mcbsp_dsp_ck); 232 clk_disable(mcbsp_dsp_ck);
224 clk_disable(mcbsp_api_ck); 233 clk_disable(mcbsp_api_ck);
@@ -1024,6 +1033,8 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type);
1024EXPORT_SYMBOL(omap_mcbsp_free); 1033EXPORT_SYMBOL(omap_mcbsp_free);
1025EXPORT_SYMBOL(omap_mcbsp_start); 1034EXPORT_SYMBOL(omap_mcbsp_start);
1026EXPORT_SYMBOL(omap_mcbsp_stop); 1035EXPORT_SYMBOL(omap_mcbsp_stop);
1036EXPORT_SYMBOL(omap_mcbsp_pollread);
1037EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1027EXPORT_SYMBOL(omap_mcbsp_xmit_word); 1038EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1028EXPORT_SYMBOL(omap_mcbsp_recv_word); 1039EXPORT_SYMBOL(omap_mcbsp_recv_word);
1029EXPORT_SYMBOL(omap_mcbsp_xmit_buffer); 1040EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-07 23:05:18 -0500