aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/Kconfig1
-rw-r--r--arch/arm/plat-omap/common.c50
-rw-r--r--arch/arm/plat-omap/devices.c6
-rw-r--r--arch/arm/plat-omap/dmtimer.c2
-rw-r--r--arch/arm/plat-omap/gpio.c612
-rw-r--r--arch/arm/plat-omap/mcbsp.c15
-rw-r--r--arch/arm/plat-omap/timer32k.c139
7 files changed, 651 insertions, 174 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index f2dc363de66b..9e8d21eca4ec 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -11,6 +11,7 @@ choice
11 11
12config ARCH_OMAP1 12config ARCH_OMAP1
13 bool "TI OMAP1" 13 bool "TI OMAP1"
14 select GENERIC_CLOCKEVENTS
14 15
15config ARCH_OMAP2 16config ARCH_OMAP2
16 bool "TI OMAP2" 17 bool "TI OMAP2"
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 57b7b93674a4..fecd3d625995 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -156,3 +156,53 @@ static int __init omap_add_serial_console(void)
156 return add_preferred_console("ttyS", line, opt); 156 return add_preferred_console("ttyS", line, opt);
157} 157}
158console_initcall(omap_add_serial_console); 158console_initcall(omap_add_serial_console);
159
160
161/*
162 * 32KHz clocksource ... always available, on pretty most chips except
163 * OMAP 730 and 1510. Other timers could be used as clocksources, with
164 * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
165 * but systems won't necessarily want to spend resources that way.
166 */
167
168#if defined(CONFIG_ARCH_OMAP16XX)
169#define TIMER_32K_SYNCHRONIZED 0xfffbc410
170#elif defined(CONFIG_ARCH_OMAP24XX)
171#define TIMER_32K_SYNCHRONIZED 0x48004010
172#endif
173
174#ifdef TIMER_32K_SYNCHRONIZED
175
176#include <linux/clocksource.h>
177
178static cycle_t omap_32k_read(void)
179{
180 return omap_readl(TIMER_32K_SYNCHRONIZED);
181}
182
183static struct clocksource clocksource_32k = {
184 .name = "32k_counter",
185 .rating = 250,
186 .read = omap_32k_read,
187 .mask = CLOCKSOURCE_MASK(32),
188 .shift = 10,
189 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
190};
191
192static int __init omap_init_clocksource_32k(void)
193{
194 static char err[] __initdata = KERN_ERR
195 "%s: can't register clocksource!\n";
196
197 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
198 clocksource_32k.mult = clocksource_hz2mult(32768,
199 clocksource_32k.shift);
200
201 if (clocksource_register(&clocksource_32k))
202 printk(err, clocksource_32k.name);
203 }
204 return 0;
205}
206arch_initcall(omap_init_clocksource_32k);
207
208#endif /* TIMER_32K_SYNCHRONIZED */
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index dbc3f44e07a6..eeb33fed6f7c 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -429,6 +429,10 @@ static inline void omap_init_rng(void) {}
429 */ 429 */
430static int __init omap_init_devices(void) 430static int __init omap_init_devices(void)
431{ 431{
432/*
433 * Need to enable relevant once for 2430 SDP
434 */
435#ifndef CONFIG_MACH_OMAP_2430SDP
432 /* please keep these calls, and their implementations above, 436 /* please keep these calls, and their implementations above,
433 * in alphabetical order so they're easier to sort through. 437 * in alphabetical order so they're easier to sort through.
434 */ 438 */
@@ -438,7 +442,7 @@ static int __init omap_init_devices(void)
438 omap_init_uwire(); 442 omap_init_uwire();
439 omap_init_wdt(); 443 omap_init_wdt();
440 omap_init_rng(); 444 omap_init_rng();
441 445#endif
442 return 0; 446 return 0;
443} 447}
444arch_initcall(omap_init_devices); 448arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 45f0439bffba..659619f235ca 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -506,6 +506,8 @@ int omap_dm_timer_init(void)
506 BUG_ON(dm_source_clocks[i] == NULL); 506 BUG_ON(dm_source_clocks[i] == NULL);
507 } 507 }
508#endif 508#endif
509 if (cpu_is_omap243x())
510 dm_timers[0].phys_base = 0x49018000;
509 511
510 for (i = 0; i < dm_timer_count; i++) { 512 for (i = 0; i < dm_timer_count; i++) {
511#ifdef CONFIG_ARCH_OMAP2 513#ifdef CONFIG_ARCH_OMAP2
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 8bedc8f9b6e5..9dc6d3617bdb 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -85,10 +85,17 @@
85/* 85/*
86 * omap24xx specific GPIO registers 86 * omap24xx specific GPIO registers
87 */ 87 */
88#define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000 88#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
89#define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000 89#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
90#define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000 90#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
91#define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000 91#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
92
93#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
94#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
95#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
96#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
97#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
98
92#define OMAP24XX_GPIO_REVISION 0x0000 99#define OMAP24XX_GPIO_REVISION 0x0000
93#define OMAP24XX_GPIO_SYSCONFIG 0x0010 100#define OMAP24XX_GPIO_SYSCONFIG 0x0010
94#define OMAP24XX_GPIO_SYSSTATUS 0x0014 101#define OMAP24XX_GPIO_SYSSTATUS 0x0014
@@ -117,8 +124,18 @@ struct gpio_bank {
117 u16 virtual_irq_start; 124 u16 virtual_irq_start;
118 int method; 125 int method;
119 u32 reserved_map; 126 u32 reserved_map;
127#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
120 u32 suspend_wakeup; 128 u32 suspend_wakeup;
121 u32 saved_wakeup; 129 u32 saved_wakeup;
130#endif
131#ifdef CONFIG_ARCH_OMAP24XX
132 u32 non_wakeup_gpios;
133 u32 enabled_non_wakeup_gpios;
134
135 u32 saved_datain;
136 u32 saved_fallingdetect;
137 u32 saved_risingdetect;
138#endif
122 spinlock_t lock; 139 spinlock_t lock;
123}; 140};
124 141
@@ -158,12 +175,22 @@ static struct gpio_bank gpio_bank_730[7] = {
158#endif 175#endif
159 176
160#ifdef CONFIG_ARCH_OMAP24XX 177#ifdef CONFIG_ARCH_OMAP24XX
161static struct gpio_bank gpio_bank_24xx[4] = { 178
162 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, 179static struct gpio_bank gpio_bank_242x[4] = {
163 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, 180 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
164 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, 181 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
165 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, 182 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
183 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
184};
185
186static struct gpio_bank gpio_bank_243x[5] = {
187 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
188 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
189 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
190 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
191 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
166}; 192};
193
167#endif 194#endif
168 195
169static struct gpio_bank *gpio_bank; 196static struct gpio_bank *gpio_bank;
@@ -257,21 +284,34 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
257 u32 l; 284 u32 l;
258 285
259 switch (bank->method) { 286 switch (bank->method) {
287#ifdef CONFIG_ARCH_OMAP1
260 case METHOD_MPUIO: 288 case METHOD_MPUIO:
261 reg += OMAP_MPUIO_IO_CNTL; 289 reg += OMAP_MPUIO_IO_CNTL;
262 break; 290 break;
291#endif
292#ifdef CONFIG_ARCH_OMAP15XX
263 case METHOD_GPIO_1510: 293 case METHOD_GPIO_1510:
264 reg += OMAP1510_GPIO_DIR_CONTROL; 294 reg += OMAP1510_GPIO_DIR_CONTROL;
265 break; 295 break;
296#endif
297#ifdef CONFIG_ARCH_OMAP16XX
266 case METHOD_GPIO_1610: 298 case METHOD_GPIO_1610:
267 reg += OMAP1610_GPIO_DIRECTION; 299 reg += OMAP1610_GPIO_DIRECTION;
268 break; 300 break;
301#endif
302#ifdef CONFIG_ARCH_OMAP730
269 case METHOD_GPIO_730: 303 case METHOD_GPIO_730:
270 reg += OMAP730_GPIO_DIR_CONTROL; 304 reg += OMAP730_GPIO_DIR_CONTROL;
271 break; 305 break;
306#endif
307#ifdef CONFIG_ARCH_OMAP24XX
272 case METHOD_GPIO_24XX: 308 case METHOD_GPIO_24XX:
273 reg += OMAP24XX_GPIO_OE; 309 reg += OMAP24XX_GPIO_OE;
274 break; 310 break;
311#endif
312 default:
313 WARN_ON(1);
314 return;
275 } 315 }
276 l = __raw_readl(reg); 316 l = __raw_readl(reg);
277 if (is_input) 317 if (is_input)
@@ -299,6 +339,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
299 u32 l = 0; 339 u32 l = 0;
300 340
301 switch (bank->method) { 341 switch (bank->method) {
342#ifdef CONFIG_ARCH_OMAP1
302 case METHOD_MPUIO: 343 case METHOD_MPUIO:
303 reg += OMAP_MPUIO_OUTPUT; 344 reg += OMAP_MPUIO_OUTPUT;
304 l = __raw_readl(reg); 345 l = __raw_readl(reg);
@@ -307,6 +348,8 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
307 else 348 else
308 l &= ~(1 << gpio); 349 l &= ~(1 << gpio);
309 break; 350 break;
351#endif
352#ifdef CONFIG_ARCH_OMAP15XX
310 case METHOD_GPIO_1510: 353 case METHOD_GPIO_1510:
311 reg += OMAP1510_GPIO_DATA_OUTPUT; 354 reg += OMAP1510_GPIO_DATA_OUTPUT;
312 l = __raw_readl(reg); 355 l = __raw_readl(reg);
@@ -315,6 +358,8 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
315 else 358 else
316 l &= ~(1 << gpio); 359 l &= ~(1 << gpio);
317 break; 360 break;
361#endif
362#ifdef CONFIG_ARCH_OMAP16XX
318 case METHOD_GPIO_1610: 363 case METHOD_GPIO_1610:
319 if (enable) 364 if (enable)
320 reg += OMAP1610_GPIO_SET_DATAOUT; 365 reg += OMAP1610_GPIO_SET_DATAOUT;
@@ -322,6 +367,8 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
322 reg += OMAP1610_GPIO_CLEAR_DATAOUT; 367 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
323 l = 1 << gpio; 368 l = 1 << gpio;
324 break; 369 break;
370#endif
371#ifdef CONFIG_ARCH_OMAP730
325 case METHOD_GPIO_730: 372 case METHOD_GPIO_730:
326 reg += OMAP730_GPIO_DATA_OUTPUT; 373 reg += OMAP730_GPIO_DATA_OUTPUT;
327 l = __raw_readl(reg); 374 l = __raw_readl(reg);
@@ -330,6 +377,8 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
330 else 377 else
331 l &= ~(1 << gpio); 378 l &= ~(1 << gpio);
332 break; 379 break;
380#endif
381#ifdef CONFIG_ARCH_OMAP24XX
333 case METHOD_GPIO_24XX: 382 case METHOD_GPIO_24XX:
334 if (enable) 383 if (enable)
335 reg += OMAP24XX_GPIO_SETDATAOUT; 384 reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -337,8 +386,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
337 reg += OMAP24XX_GPIO_CLEARDATAOUT; 386 reg += OMAP24XX_GPIO_CLEARDATAOUT;
338 l = 1 << gpio; 387 l = 1 << gpio;
339 break; 388 break;
389#endif
340 default: 390 default:
341 BUG(); 391 WARN_ON(1);
342 return; 392 return;
343 } 393 }
344 __raw_writel(l, reg); 394 __raw_writel(l, reg);
@@ -362,28 +412,37 @@ int omap_get_gpio_datain(int gpio)
362 void __iomem *reg; 412 void __iomem *reg;
363 413
364 if (check_gpio(gpio) < 0) 414 if (check_gpio(gpio) < 0)
365 return -1; 415 return -EINVAL;
366 bank = get_gpio_bank(gpio); 416 bank = get_gpio_bank(gpio);
367 reg = bank->base; 417 reg = bank->base;
368 switch (bank->method) { 418 switch (bank->method) {
419#ifdef CONFIG_ARCH_OMAP1
369 case METHOD_MPUIO: 420 case METHOD_MPUIO:
370 reg += OMAP_MPUIO_INPUT_LATCH; 421 reg += OMAP_MPUIO_INPUT_LATCH;
371 break; 422 break;
423#endif
424#ifdef CONFIG_ARCH_OMAP15XX
372 case METHOD_GPIO_1510: 425 case METHOD_GPIO_1510:
373 reg += OMAP1510_GPIO_DATA_INPUT; 426 reg += OMAP1510_GPIO_DATA_INPUT;
374 break; 427 break;
428#endif
429#ifdef CONFIG_ARCH_OMAP16XX
375 case METHOD_GPIO_1610: 430 case METHOD_GPIO_1610:
376 reg += OMAP1610_GPIO_DATAIN; 431 reg += OMAP1610_GPIO_DATAIN;
377 break; 432 break;
433#endif
434#ifdef CONFIG_ARCH_OMAP730
378 case METHOD_GPIO_730: 435 case METHOD_GPIO_730:
379 reg += OMAP730_GPIO_DATA_INPUT; 436 reg += OMAP730_GPIO_DATA_INPUT;
380 break; 437 break;
438#endif
439#ifdef CONFIG_ARCH_OMAP24XX
381 case METHOD_GPIO_24XX: 440 case METHOD_GPIO_24XX:
382 reg += OMAP24XX_GPIO_DATAIN; 441 reg += OMAP24XX_GPIO_DATAIN;
383 break; 442 break;
443#endif
384 default: 444 default:
385 BUG(); 445 return -EINVAL;
386 return -1;
387 } 446 }
388 return (__raw_readl(reg) 447 return (__raw_readl(reg)
389 & (1 << get_gpio_index(gpio))) != 0; 448 & (1 << get_gpio_index(gpio))) != 0;
@@ -397,8 +456,10 @@ do { \
397 __raw_writel(l, base + reg); \ 456 __raw_writel(l, base + reg); \
398} while(0) 457} while(0)
399 458
400static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger) 459#ifdef CONFIG_ARCH_OMAP24XX
460static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
401{ 461{
462 void __iomem *base = bank->base;
402 u32 gpio_bit = 1 << gpio; 463 u32 gpio_bit = 1 << gpio;
403 464
404 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, 465 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
@@ -409,9 +470,21 @@ static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int tr
409 trigger & __IRQT_RISEDGE); 470 trigger & __IRQT_RISEDGE);
410 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 471 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
411 trigger & __IRQT_FALEDGE); 472 trigger & __IRQT_FALEDGE);
473 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
474 if (trigger != 0)
475 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
476 else
477 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
478 } else {
479 if (trigger != 0)
480 bank->enabled_non_wakeup_gpios |= gpio_bit;
481 else
482 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
483 }
412 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level 484 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
413 * triggering requested. */ 485 * triggering requested. */
414} 486}
487#endif
415 488
416static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 489static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
417{ 490{
@@ -419,6 +492,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
419 u32 l = 0; 492 u32 l = 0;
420 493
421 switch (bank->method) { 494 switch (bank->method) {
495#ifdef CONFIG_ARCH_OMAP1
422 case METHOD_MPUIO: 496 case METHOD_MPUIO:
423 reg += OMAP_MPUIO_GPIO_INT_EDGE; 497 reg += OMAP_MPUIO_GPIO_INT_EDGE;
424 l = __raw_readl(reg); 498 l = __raw_readl(reg);
@@ -429,6 +503,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
429 else 503 else
430 goto bad; 504 goto bad;
431 break; 505 break;
506#endif
507#ifdef CONFIG_ARCH_OMAP15XX
432 case METHOD_GPIO_1510: 508 case METHOD_GPIO_1510:
433 reg += OMAP1510_GPIO_INT_CONTROL; 509 reg += OMAP1510_GPIO_INT_CONTROL;
434 l = __raw_readl(reg); 510 l = __raw_readl(reg);
@@ -439,22 +515,28 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
439 else 515 else
440 goto bad; 516 goto bad;
441 break; 517 break;
518#endif
519#ifdef CONFIG_ARCH_OMAP16XX
442 case METHOD_GPIO_1610: 520 case METHOD_GPIO_1610:
443 if (gpio & 0x08) 521 if (gpio & 0x08)
444 reg += OMAP1610_GPIO_EDGE_CTRL2; 522 reg += OMAP1610_GPIO_EDGE_CTRL2;
445 else 523 else
446 reg += OMAP1610_GPIO_EDGE_CTRL1; 524 reg += OMAP1610_GPIO_EDGE_CTRL1;
447 gpio &= 0x07; 525 gpio &= 0x07;
448 /* We allow only edge triggering, i.e. two lowest bits */
449 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
450 BUG();
451 l = __raw_readl(reg); 526 l = __raw_readl(reg);
452 l &= ~(3 << (gpio << 1)); 527 l &= ~(3 << (gpio << 1));
453 if (trigger & __IRQT_RISEDGE) 528 if (trigger & __IRQT_RISEDGE)
454 l |= 2 << (gpio << 1); 529 l |= 2 << (gpio << 1);
455 if (trigger & __IRQT_FALEDGE) 530 if (trigger & __IRQT_FALEDGE)
456 l |= 1 << (gpio << 1); 531 l |= 1 << (gpio << 1);
532 if (trigger)
533 /* Enable wake-up during idle for dynamic tick */
534 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
535 else
536 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
457 break; 537 break;
538#endif
539#ifdef CONFIG_ARCH_OMAP730
458 case METHOD_GPIO_730: 540 case METHOD_GPIO_730:
459 reg += OMAP730_GPIO_INT_CONTROL; 541 reg += OMAP730_GPIO_INT_CONTROL;
460 l = __raw_readl(reg); 542 l = __raw_readl(reg);
@@ -465,11 +547,13 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
465 else 547 else
466 goto bad; 548 goto bad;
467 break; 549 break;
550#endif
551#ifdef CONFIG_ARCH_OMAP24XX
468 case METHOD_GPIO_24XX: 552 case METHOD_GPIO_24XX:
469 set_24xx_gpio_triggering(reg, gpio, trigger); 553 set_24xx_gpio_triggering(bank, gpio, trigger);
470 break; 554 break;
555#endif
471 default: 556 default:
472 BUG();
473 goto bad; 557 goto bad;
474 } 558 }
475 __raw_writel(l, reg); 559 __raw_writel(l, reg);
@@ -484,7 +568,7 @@ static int gpio_irq_type(unsigned irq, unsigned type)
484 unsigned gpio; 568 unsigned gpio;
485 int retval; 569 int retval;
486 570
487 if (irq > IH_MPUIO_BASE) 571 if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE)
488 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 572 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
489 else 573 else
490 gpio = irq - IH_GPIO_BASE; 574 gpio = irq - IH_GPIO_BASE;
@@ -492,14 +576,21 @@ static int gpio_irq_type(unsigned irq, unsigned type)
492 if (check_gpio(gpio) < 0) 576 if (check_gpio(gpio) < 0)
493 return -EINVAL; 577 return -EINVAL;
494 578
495 if (type & IRQT_PROBE) 579 if (type & ~IRQ_TYPE_SENSE_MASK)
496 return -EINVAL; 580 return -EINVAL;
497 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL))) 581
582 /* OMAP1 allows only only edge triggering */
583 if (!cpu_is_omap24xx()
584 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
498 return -EINVAL; 585 return -EINVAL;
499 586
500 bank = get_gpio_bank(gpio); 587 bank = get_irq_chip_data(irq);
501 spin_lock(&bank->lock); 588 spin_lock(&bank->lock);
502 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); 589 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
590 if (retval == 0) {
591 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
592 irq_desc[irq].status |= type;
593 }
503 spin_unlock(&bank->lock); 594 spin_unlock(&bank->lock);
504 return retval; 595 return retval;
505} 596}
@@ -509,24 +600,34 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
509 void __iomem *reg = bank->base; 600 void __iomem *reg = bank->base;
510 601
511 switch (bank->method) { 602 switch (bank->method) {
603#ifdef CONFIG_ARCH_OMAP1
512 case METHOD_MPUIO: 604 case METHOD_MPUIO:
513 /* MPUIO irqstatus is reset by reading the status register, 605 /* MPUIO irqstatus is reset by reading the status register,
514 * so do nothing here */ 606 * so do nothing here */
515 return; 607 return;
608#endif
609#ifdef CONFIG_ARCH_OMAP15XX
516 case METHOD_GPIO_1510: 610 case METHOD_GPIO_1510:
517 reg += OMAP1510_GPIO_INT_STATUS; 611 reg += OMAP1510_GPIO_INT_STATUS;
518 break; 612 break;
613#endif
614#ifdef CONFIG_ARCH_OMAP16XX
519 case METHOD_GPIO_1610: 615 case METHOD_GPIO_1610:
520 reg += OMAP1610_GPIO_IRQSTATUS1; 616 reg += OMAP1610_GPIO_IRQSTATUS1;
521 break; 617 break;
618#endif
619#ifdef CONFIG_ARCH_OMAP730
522 case METHOD_GPIO_730: 620 case METHOD_GPIO_730:
523 reg += OMAP730_GPIO_INT_STATUS; 621 reg += OMAP730_GPIO_INT_STATUS;
524 break; 622 break;
623#endif
624#ifdef CONFIG_ARCH_OMAP24XX
525 case METHOD_GPIO_24XX: 625 case METHOD_GPIO_24XX:
526 reg += OMAP24XX_GPIO_IRQSTATUS1; 626 reg += OMAP24XX_GPIO_IRQSTATUS1;
527 break; 627 break;
628#endif
528 default: 629 default:
529 BUG(); 630 WARN_ON(1);
530 return; 631 return;
531 } 632 }
532 __raw_writel(gpio_mask, reg); 633 __raw_writel(gpio_mask, reg);
@@ -549,31 +650,41 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
549 u32 mask; 650 u32 mask;
550 651
551 switch (bank->method) { 652 switch (bank->method) {
653#ifdef CONFIG_ARCH_OMAP1
552 case METHOD_MPUIO: 654 case METHOD_MPUIO:
553 reg += OMAP_MPUIO_GPIO_MASKIT; 655 reg += OMAP_MPUIO_GPIO_MASKIT;
554 mask = 0xffff; 656 mask = 0xffff;
555 inv = 1; 657 inv = 1;
556 break; 658 break;
659#endif
660#ifdef CONFIG_ARCH_OMAP15XX
557 case METHOD_GPIO_1510: 661 case METHOD_GPIO_1510:
558 reg += OMAP1510_GPIO_INT_MASK; 662 reg += OMAP1510_GPIO_INT_MASK;
559 mask = 0xffff; 663 mask = 0xffff;
560 inv = 1; 664 inv = 1;
561 break; 665 break;
666#endif
667#ifdef CONFIG_ARCH_OMAP16XX
562 case METHOD_GPIO_1610: 668 case METHOD_GPIO_1610:
563 reg += OMAP1610_GPIO_IRQENABLE1; 669 reg += OMAP1610_GPIO_IRQENABLE1;
564 mask = 0xffff; 670 mask = 0xffff;
565 break; 671 break;
672#endif
673#ifdef CONFIG_ARCH_OMAP730
566 case METHOD_GPIO_730: 674 case METHOD_GPIO_730:
567 reg += OMAP730_GPIO_INT_MASK; 675 reg += OMAP730_GPIO_INT_MASK;
568 mask = 0xffffffff; 676 mask = 0xffffffff;
569 inv = 1; 677 inv = 1;
570 break; 678 break;
679#endif
680#ifdef CONFIG_ARCH_OMAP24XX
571 case METHOD_GPIO_24XX: 681 case METHOD_GPIO_24XX:
572 reg += OMAP24XX_GPIO_IRQENABLE1; 682 reg += OMAP24XX_GPIO_IRQENABLE1;
573 mask = 0xffffffff; 683 mask = 0xffffffff;
574 break; 684 break;
685#endif
575 default: 686 default:
576 BUG(); 687 WARN_ON(1);
577 return 0; 688 return 0;
578 } 689 }
579 690
@@ -590,6 +701,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
590 u32 l; 701 u32 l;
591 702
592 switch (bank->method) { 703 switch (bank->method) {
704#ifdef CONFIG_ARCH_OMAP1
593 case METHOD_MPUIO: 705 case METHOD_MPUIO:
594 reg += OMAP_MPUIO_GPIO_MASKIT; 706 reg += OMAP_MPUIO_GPIO_MASKIT;
595 l = __raw_readl(reg); 707 l = __raw_readl(reg);
@@ -598,6 +710,8 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
598 else 710 else
599 l |= gpio_mask; 711 l |= gpio_mask;
600 break; 712 break;
713#endif
714#ifdef CONFIG_ARCH_OMAP15XX
601 case METHOD_GPIO_1510: 715 case METHOD_GPIO_1510:
602 reg += OMAP1510_GPIO_INT_MASK; 716 reg += OMAP1510_GPIO_INT_MASK;
603 l = __raw_readl(reg); 717 l = __raw_readl(reg);
@@ -606,6 +720,8 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
606 else 720 else
607 l |= gpio_mask; 721 l |= gpio_mask;
608 break; 722 break;
723#endif
724#ifdef CONFIG_ARCH_OMAP16XX
609 case METHOD_GPIO_1610: 725 case METHOD_GPIO_1610:
610 if (enable) 726 if (enable)
611 reg += OMAP1610_GPIO_SET_IRQENABLE1; 727 reg += OMAP1610_GPIO_SET_IRQENABLE1;
@@ -613,6 +729,8 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
613 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; 729 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
614 l = gpio_mask; 730 l = gpio_mask;
615 break; 731 break;
732#endif
733#ifdef CONFIG_ARCH_OMAP730
616 case METHOD_GPIO_730: 734 case METHOD_GPIO_730:
617 reg += OMAP730_GPIO_INT_MASK; 735 reg += OMAP730_GPIO_INT_MASK;
618 l = __raw_readl(reg); 736 l = __raw_readl(reg);
@@ -621,6 +739,8 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
621 else 739 else
622 l |= gpio_mask; 740 l |= gpio_mask;
623 break; 741 break;
742#endif
743#ifdef CONFIG_ARCH_OMAP24XX
624 case METHOD_GPIO_24XX: 744 case METHOD_GPIO_24XX:
625 if (enable) 745 if (enable)
626 reg += OMAP24XX_GPIO_SETIRQENABLE1; 746 reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -628,8 +748,9 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
628 reg += OMAP24XX_GPIO_CLEARIRQENABLE1; 748 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
629 l = gpio_mask; 749 l = gpio_mask;
630 break; 750 break;
751#endif
631 default: 752 default:
632 BUG(); 753 WARN_ON(1);
633 return; 754 return;
634 } 755 }
635 __raw_writel(l, reg); 756 __raw_writel(l, reg);
@@ -651,15 +772,39 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena
651static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) 772static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
652{ 773{
653 switch (bank->method) { 774 switch (bank->method) {
775#ifdef CONFIG_ARCH_OMAP16XX
776 case METHOD_MPUIO:
654 case METHOD_GPIO_1610: 777 case METHOD_GPIO_1610:
778 spin_lock(&bank->lock);
779 if (enable) {
780 bank->suspend_wakeup |= (1 << gpio);
781 enable_irq_wake(bank->irq);
782 } else {
783 disable_irq_wake(bank->irq);
784 bank->suspend_wakeup &= ~(1 << gpio);
785 }
786 spin_unlock(&bank->lock);
787 return 0;
788#endif
789#ifdef CONFIG_ARCH_OMAP24XX
655 case METHOD_GPIO_24XX: 790 case METHOD_GPIO_24XX:
791 if (bank->non_wakeup_gpios & (1 << gpio)) {
792 printk(KERN_ERR "Unable to modify wakeup on "
793 "non-wakeup GPIO%d\n",
794 (bank - gpio_bank) * 32 + gpio);
795 return -EINVAL;
796 }
656 spin_lock(&bank->lock); 797 spin_lock(&bank->lock);
657 if (enable) 798 if (enable) {
658 bank->suspend_wakeup |= (1 << gpio); 799 bank->suspend_wakeup |= (1 << gpio);
659 else 800 enable_irq_wake(bank->irq);
801 } else {
802 disable_irq_wake(bank->irq);
660 bank->suspend_wakeup &= ~(1 << gpio); 803 bank->suspend_wakeup &= ~(1 << gpio);
804 }
661 spin_unlock(&bank->lock); 805 spin_unlock(&bank->lock);
662 return 0; 806 return 0;
807#endif
663 default: 808 default:
664 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", 809 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
665 bank->method); 810 bank->method);
@@ -684,7 +829,7 @@ static int gpio_wake_enable(unsigned int irq, unsigned int enable)
684 829
685 if (check_gpio(gpio) < 0) 830 if (check_gpio(gpio) < 0)
686 return -ENODEV; 831 return -ENODEV;
687 bank = get_gpio_bank(gpio); 832 bank = get_irq_chip_data(irq);
688 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); 833 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
689 834
690 return retval; 835 return retval;
@@ -721,20 +866,6 @@ int omap_request_gpio(int gpio)
721 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); 866 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
722 } 867 }
723#endif 868#endif
724#ifdef CONFIG_ARCH_OMAP16XX
725 if (bank->method == METHOD_GPIO_1610) {
726 /* Enable wake-up during idle for dynamic tick */
727 void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
728 __raw_writel(1 << get_gpio_index(gpio), reg);
729 }
730#endif
731#ifdef CONFIG_ARCH_OMAP24XX
732 if (bank->method == METHOD_GPIO_24XX) {
733 /* Enable wake-up during idle for dynamic tick */
734 void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA;
735 __raw_writel(1 << get_gpio_index(gpio), reg);
736 }
737#endif
738 spin_unlock(&bank->lock); 869 spin_unlock(&bank->lock);
739 870
740 return 0; 871 return 0;
@@ -794,8 +925,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
794 desc->chip->ack(irq); 925 desc->chip->ack(irq);
795 926
796 bank = get_irq_data(irq); 927 bank = get_irq_data(irq);
928#ifdef CONFIG_ARCH_OMAP1
797 if (bank->method == METHOD_MPUIO) 929 if (bank->method == METHOD_MPUIO)
798 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; 930 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
931#endif
799#ifdef CONFIG_ARCH_OMAP15XX 932#ifdef CONFIG_ARCH_OMAP15XX
800 if (bank->method == METHOD_GPIO_1510) 933 if (bank->method == METHOD_GPIO_1510)
801 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; 934 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
@@ -911,7 +1044,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
911static void gpio_irq_shutdown(unsigned int irq) 1044static void gpio_irq_shutdown(unsigned int irq)
912{ 1045{
913 unsigned int gpio = irq - IH_GPIO_BASE; 1046 unsigned int gpio = irq - IH_GPIO_BASE;
914 struct gpio_bank *bank = get_gpio_bank(gpio); 1047 struct gpio_bank *bank = get_irq_chip_data(irq);
915 1048
916 _reset_gpio(bank, gpio); 1049 _reset_gpio(bank, gpio);
917} 1050}
@@ -919,7 +1052,7 @@ static void gpio_irq_shutdown(unsigned int irq)
919static void gpio_ack_irq(unsigned int irq) 1052static void gpio_ack_irq(unsigned int irq)
920{ 1053{
921 unsigned int gpio = irq - IH_GPIO_BASE; 1054 unsigned int gpio = irq - IH_GPIO_BASE;
922 struct gpio_bank *bank = get_gpio_bank(gpio); 1055 struct gpio_bank *bank = get_irq_chip_data(irq);
923 1056
924 _clear_gpio_irqstatus(bank, gpio); 1057 _clear_gpio_irqstatus(bank, gpio);
925} 1058}
@@ -927,7 +1060,7 @@ static void gpio_ack_irq(unsigned int irq)
927static void gpio_mask_irq(unsigned int irq) 1060static void gpio_mask_irq(unsigned int irq)
928{ 1061{
929 unsigned int gpio = irq - IH_GPIO_BASE; 1062 unsigned int gpio = irq - IH_GPIO_BASE;
930 struct gpio_bank *bank = get_gpio_bank(gpio); 1063 struct gpio_bank *bank = get_irq_chip_data(irq);
931 1064
932 _set_gpio_irqenable(bank, gpio, 0); 1065 _set_gpio_irqenable(bank, gpio, 0);
933} 1066}
@@ -936,11 +1069,27 @@ static void gpio_unmask_irq(unsigned int irq)
936{ 1069{
937 unsigned int gpio = irq - IH_GPIO_BASE; 1070 unsigned int gpio = irq - IH_GPIO_BASE;
938 unsigned int gpio_idx = get_gpio_index(gpio); 1071 unsigned int gpio_idx = get_gpio_index(gpio);
939 struct gpio_bank *bank = get_gpio_bank(gpio); 1072 struct gpio_bank *bank = get_irq_chip_data(irq);
940 1073
941 _set_gpio_irqenable(bank, gpio_idx, 1); 1074 _set_gpio_irqenable(bank, gpio_idx, 1);
942} 1075}
943 1076
1077static struct irq_chip gpio_irq_chip = {
1078 .name = "GPIO",
1079 .shutdown = gpio_irq_shutdown,
1080 .ack = gpio_ack_irq,
1081 .mask = gpio_mask_irq,
1082 .unmask = gpio_unmask_irq,
1083 .set_type = gpio_irq_type,
1084 .set_wake = gpio_wake_enable,
1085};
1086
1087/*---------------------------------------------------------------------*/
1088
1089#ifdef CONFIG_ARCH_OMAP1
1090
1091/* MPUIO uses the always-on 32k clock */
1092
944static void mpuio_ack_irq(unsigned int irq) 1093static void mpuio_ack_irq(unsigned int irq)
945{ 1094{
946 /* The ISR is reset automatically, so do nothing here. */ 1095 /* The ISR is reset automatically, so do nothing here. */
@@ -949,7 +1098,7 @@ static void mpuio_ack_irq(unsigned int irq)
949static void mpuio_mask_irq(unsigned int irq) 1098static void mpuio_mask_irq(unsigned int irq)
950{ 1099{
951 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 1100 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
952 struct gpio_bank *bank = get_gpio_bank(gpio); 1101 struct gpio_bank *bank = get_irq_chip_data(irq);
953 1102
954 _set_gpio_irqenable(bank, gpio, 0); 1103 _set_gpio_irqenable(bank, gpio, 0);
955} 1104}
@@ -957,33 +1106,108 @@ static void mpuio_mask_irq(unsigned int irq)
957static void mpuio_unmask_irq(unsigned int irq) 1106static void mpuio_unmask_irq(unsigned int irq)
958{ 1107{
959 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 1108 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
960 struct gpio_bank *bank = get_gpio_bank(gpio); 1109 struct gpio_bank *bank = get_irq_chip_data(irq);
961 1110
962 _set_gpio_irqenable(bank, gpio, 1); 1111 _set_gpio_irqenable(bank, gpio, 1);
963} 1112}
964 1113
965static struct irq_chip gpio_irq_chip = { 1114static struct irq_chip mpuio_irq_chip = {
966 .name = "GPIO", 1115 .name = "MPUIO",
967 .shutdown = gpio_irq_shutdown, 1116 .ack = mpuio_ack_irq,
968 .ack = gpio_ack_irq, 1117 .mask = mpuio_mask_irq,
969 .mask = gpio_mask_irq, 1118 .unmask = mpuio_unmask_irq,
970 .unmask = gpio_unmask_irq,
971 .set_type = gpio_irq_type, 1119 .set_type = gpio_irq_type,
1120#ifdef CONFIG_ARCH_OMAP16XX
1121 /* REVISIT: assuming only 16xx supports MPUIO wake events */
972 .set_wake = gpio_wake_enable, 1122 .set_wake = gpio_wake_enable,
1123#endif
973}; 1124};
974 1125
975static struct irq_chip mpuio_irq_chip = { 1126
976 .name = "MPUIO", 1127#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
977 .ack = mpuio_ack_irq, 1128
978 .mask = mpuio_mask_irq, 1129
979 .unmask = mpuio_unmask_irq, 1130#ifdef CONFIG_ARCH_OMAP16XX
980 .set_type = gpio_irq_type, 1131
1132#include <linux/platform_device.h>
1133
1134static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1135{
1136 struct gpio_bank *bank = platform_get_drvdata(pdev);
1137 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1138
1139 spin_lock(&bank->lock);
1140 bank->saved_wakeup = __raw_readl(mask_reg);
1141 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1142 spin_unlock(&bank->lock);
1143
1144 return 0;
1145}
1146
1147static int omap_mpuio_resume_early(struct platform_device *pdev)
1148{
1149 struct gpio_bank *bank = platform_get_drvdata(pdev);
1150 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1151
1152 spin_lock(&bank->lock);
1153 __raw_writel(bank->saved_wakeup, mask_reg);
1154 spin_unlock(&bank->lock);
1155
1156 return 0;
1157}
1158
1159/* use platform_driver for this, now that there's no longer any
1160 * point to sys_device (other than not disturbing old code).
1161 */
1162static struct platform_driver omap_mpuio_driver = {
1163 .suspend_late = omap_mpuio_suspend_late,
1164 .resume_early = omap_mpuio_resume_early,
1165 .driver = {
1166 .name = "mpuio",
1167 },
1168};
1169
1170static struct platform_device omap_mpuio_device = {
1171 .name = "mpuio",
1172 .id = -1,
1173 .dev = {
1174 .driver = &omap_mpuio_driver.driver,
1175 }
1176 /* could list the /proc/iomem resources */
981}; 1177};
982 1178
1179static inline void mpuio_init(void)
1180{
1181 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1182
1183 if (platform_driver_register(&omap_mpuio_driver) == 0)
1184 (void) platform_device_register(&omap_mpuio_device);
1185}
1186
1187#else
1188static inline void mpuio_init(void) {}
1189#endif /* 16xx */
1190
1191#else
1192
1193extern struct irq_chip mpuio_irq_chip;
1194
1195#define bank_is_mpuio(bank) 0
1196static inline void mpuio_init(void) {}
1197
1198#endif
1199
1200/*---------------------------------------------------------------------*/
1201
983static int initialized; 1202static int initialized;
984static struct clk * gpio_ick; 1203static struct clk * gpio_ick;
985static struct clk * gpio_fck; 1204static struct clk * gpio_fck;
986 1205
1206#ifdef CONFIG_ARCH_OMAP2430
1207static struct clk * gpio5_ick;
1208static struct clk * gpio5_fck;
1209#endif
1210
987static int __init _omap_gpio_init(void) 1211static int __init _omap_gpio_init(void)
988{ 1212{
989 int i; 1213 int i;
@@ -1009,7 +1233,25 @@ static int __init _omap_gpio_init(void)
1009 printk("Could not get gpios_fck\n"); 1233 printk("Could not get gpios_fck\n");
1010 else 1234 else
1011 clk_enable(gpio_fck); 1235 clk_enable(gpio_fck);
1012 } 1236
1237 /*
1238 * On 2430 GPIO 5 uses CORE L4 ICLK
1239 */
1240#ifdef CONFIG_ARCH_OMAP2430
1241 if (cpu_is_omap2430()) {
1242 gpio5_ick = clk_get(NULL, "gpio5_ick");
1243 if (IS_ERR(gpio5_ick))
1244 printk("Could not get gpio5_ick\n");
1245 else
1246 clk_enable(gpio5_ick);
1247 gpio5_fck = clk_get(NULL, "gpio5_fck");
1248 if (IS_ERR(gpio5_fck))
1249 printk("Could not get gpio5_fck\n");
1250 else
1251 clk_enable(gpio5_fck);
1252 }
1253#endif
1254}
1013 1255
1014#ifdef CONFIG_ARCH_OMAP15XX 1256#ifdef CONFIG_ARCH_OMAP15XX
1015 if (cpu_is_omap15xx()) { 1257 if (cpu_is_omap15xx()) {
@@ -1036,14 +1278,24 @@ static int __init _omap_gpio_init(void)
1036 gpio_bank = gpio_bank_730; 1278 gpio_bank = gpio_bank_730;
1037 } 1279 }
1038#endif 1280#endif
1281
1039#ifdef CONFIG_ARCH_OMAP24XX 1282#ifdef CONFIG_ARCH_OMAP24XX
1040 if (cpu_is_omap24xx()) { 1283 if (cpu_is_omap242x()) {
1041 int rev; 1284 int rev;
1042 1285
1043 gpio_bank_count = 4; 1286 gpio_bank_count = 4;
1044 gpio_bank = gpio_bank_24xx; 1287 gpio_bank = gpio_bank_242x;
1288 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1289 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1290 (rev >> 4) & 0x0f, rev & 0x0f);
1291 }
1292 if (cpu_is_omap243x()) {
1293 int rev;
1294
1295 gpio_bank_count = 5;
1296 gpio_bank = gpio_bank_243x;
1045 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1297 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1046 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n", 1298 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1047 (rev >> 4) & 0x0f, rev & 0x0f); 1299 (rev >> 4) & 0x0f, rev & 0x0f);
1048 } 1300 }
1049#endif 1301#endif
@@ -1054,9 +1306,8 @@ static int __init _omap_gpio_init(void)
1054 bank->reserved_map = 0; 1306 bank->reserved_map = 0;
1055 bank->base = IO_ADDRESS(bank->base); 1307 bank->base = IO_ADDRESS(bank->base);
1056 spin_lock_init(&bank->lock); 1308 spin_lock_init(&bank->lock);
1057 if (bank->method == METHOD_MPUIO) { 1309 if (bank_is_mpuio(bank))
1058 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); 1310 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1059 }
1060#ifdef CONFIG_ARCH_OMAP15XX 1311#ifdef CONFIG_ARCH_OMAP15XX
1061 if (bank->method == METHOD_GPIO_1510) { 1312 if (bank->method == METHOD_GPIO_1510) {
1062 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); 1313 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
@@ -1080,15 +1331,25 @@ static int __init _omap_gpio_init(void)
1080#endif 1331#endif
1081#ifdef CONFIG_ARCH_OMAP24XX 1332#ifdef CONFIG_ARCH_OMAP24XX
1082 if (bank->method == METHOD_GPIO_24XX) { 1333 if (bank->method == METHOD_GPIO_24XX) {
1334 static const u32 non_wakeup_gpios[] = {
1335 0xe203ffc0, 0x08700040
1336 };
1337
1083 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); 1338 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1084 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); 1339 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1340 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1085 1341
1342 /* Initialize interface clock ungated, module enabled */
1343 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1344 if (i < ARRAY_SIZE(non_wakeup_gpios))
1345 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1086 gpio_count = 32; 1346 gpio_count = 32;
1087 } 1347 }
1088#endif 1348#endif
1089 for (j = bank->virtual_irq_start; 1349 for (j = bank->virtual_irq_start;
1090 j < bank->virtual_irq_start + gpio_count; j++) { 1350 j < bank->virtual_irq_start + gpio_count; j++) {
1091 if (bank->method == METHOD_MPUIO) 1351 set_irq_chip_data(j, bank);
1352 if (bank_is_mpuio(bank))
1092 set_irq_chip(j, &mpuio_irq_chip); 1353 set_irq_chip(j, &mpuio_irq_chip);
1093 else 1354 else
1094 set_irq_chip(j, &gpio_irq_chip); 1355 set_irq_chip(j, &gpio_irq_chip);
@@ -1104,6 +1365,12 @@ static int __init _omap_gpio_init(void)
1104 if (cpu_is_omap16xx()) 1365 if (cpu_is_omap16xx())
1105 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); 1366 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1106 1367
1368#ifdef CONFIG_ARCH_OMAP24XX
1369 /* Enable autoidle for the OCP interface */
1370 if (cpu_is_omap24xx())
1371 omap_writel(1 << 0, 0x48019010);
1372#endif
1373
1107 return 0; 1374 return 0;
1108} 1375}
1109 1376
@@ -1122,16 +1389,20 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1122 void __iomem *wake_set; 1389 void __iomem *wake_set;
1123 1390
1124 switch (bank->method) { 1391 switch (bank->method) {
1392#ifdef CONFIG_ARCH_OMAP16XX
1125 case METHOD_GPIO_1610: 1393 case METHOD_GPIO_1610:
1126 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; 1394 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1127 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 1395 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1128 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1396 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1129 break; 1397 break;
1398#endif
1399#ifdef CONFIG_ARCH_OMAP24XX
1130 case METHOD_GPIO_24XX: 1400 case METHOD_GPIO_24XX:
1131 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; 1401 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1132 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1402 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1133 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1403 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1134 break; 1404 break;
1405#endif
1135 default: 1406 default:
1136 continue; 1407 continue;
1137 } 1408 }
@@ -1159,14 +1430,18 @@ static int omap_gpio_resume(struct sys_device *dev)
1159 void __iomem *wake_set; 1430 void __iomem *wake_set;
1160 1431
1161 switch (bank->method) { 1432 switch (bank->method) {
1433#ifdef CONFIG_ARCH_OMAP16XX
1162 case METHOD_GPIO_1610: 1434 case METHOD_GPIO_1610:
1163 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 1435 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1164 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1436 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1165 break; 1437 break;
1438#endif
1439#ifdef CONFIG_ARCH_OMAP24XX
1166 case METHOD_GPIO_24XX: 1440 case METHOD_GPIO_24XX:
1167 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1441 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1168 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1442 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1169 break; 1443 break;
1444#endif
1170 default: 1445 default:
1171 continue; 1446 continue;
1172 } 1447 }
@@ -1190,6 +1465,80 @@ static struct sys_device omap_gpio_device = {
1190 .id = 0, 1465 .id = 0,
1191 .cls = &omap_gpio_sysclass, 1466 .cls = &omap_gpio_sysclass,
1192}; 1467};
1468
1469#endif
1470
1471#ifdef CONFIG_ARCH_OMAP24XX
1472
1473static int workaround_enabled;
1474
1475void omap2_gpio_prepare_for_retention(void)
1476{
1477 int i, c = 0;
1478
1479 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1480 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1481 for (i = 0; i < gpio_bank_count; i++) {
1482 struct gpio_bank *bank = &gpio_bank[i];
1483 u32 l1, l2;
1484
1485 if (!(bank->enabled_non_wakeup_gpios))
1486 continue;
1487 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1488 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1489 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1490 bank->saved_fallingdetect = l1;
1491 bank->saved_risingdetect = l2;
1492 l1 &= ~bank->enabled_non_wakeup_gpios;
1493 l2 &= ~bank->enabled_non_wakeup_gpios;
1494 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1495 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1496 c++;
1497 }
1498 if (!c) {
1499 workaround_enabled = 0;
1500 return;
1501 }
1502 workaround_enabled = 1;
1503}
1504
1505void omap2_gpio_resume_after_retention(void)
1506{
1507 int i;
1508
1509 if (!workaround_enabled)
1510 return;
1511 for (i = 0; i < gpio_bank_count; i++) {
1512 struct gpio_bank *bank = &gpio_bank[i];
1513 u32 l;
1514
1515 if (!(bank->enabled_non_wakeup_gpios))
1516 continue;
1517 __raw_writel(bank->saved_fallingdetect,
1518 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1519 __raw_writel(bank->saved_risingdetect,
1520 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1521 /* Check if any of the non-wakeup interrupt GPIOs have changed
1522 * state. If so, generate an IRQ by software. This is
1523 * horribly racy, but it's the best we can do to work around
1524 * this silicon bug. */
1525 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1526 l ^= bank->saved_datain;
1527 l &= bank->non_wakeup_gpios;
1528 if (l) {
1529 u32 old0, old1;
1530
1531 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1532 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1533 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1534 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1535 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1536 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1537 }
1538 }
1539
1540}
1541
1193#endif 1542#endif
1194 1543
1195/* 1544/*
@@ -1211,6 +1560,8 @@ static int __init omap_gpio_sysinit(void)
1211 if (!initialized) 1560 if (!initialized)
1212 ret = _omap_gpio_init(); 1561 ret = _omap_gpio_init();
1213 1562
1563 mpuio_init();
1564
1214#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) 1565#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1215 if (cpu_is_omap16xx() || cpu_is_omap24xx()) { 1566 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1216 if (ret == 0) { 1567 if (ret == 0) {
@@ -1231,3 +1582,128 @@ EXPORT_SYMBOL(omap_set_gpio_dataout);
1231EXPORT_SYMBOL(omap_get_gpio_datain); 1582EXPORT_SYMBOL(omap_get_gpio_datain);
1232 1583
1233arch_initcall(omap_gpio_sysinit); 1584arch_initcall(omap_gpio_sysinit);
1585
1586
1587#ifdef CONFIG_DEBUG_FS
1588
1589#include <linux/debugfs.h>
1590#include <linux/seq_file.h>
1591
1592static int gpio_is_input(struct gpio_bank *bank, int mask)
1593{
1594 void __iomem *reg = bank->base;
1595
1596 switch (bank->method) {
1597 case METHOD_MPUIO:
1598 reg += OMAP_MPUIO_IO_CNTL;
1599 break;
1600 case METHOD_GPIO_1510:
1601 reg += OMAP1510_GPIO_DIR_CONTROL;
1602 break;
1603 case METHOD_GPIO_1610:
1604 reg += OMAP1610_GPIO_DIRECTION;
1605 break;
1606 case METHOD_GPIO_730:
1607 reg += OMAP730_GPIO_DIR_CONTROL;
1608 break;
1609 case METHOD_GPIO_24XX:
1610 reg += OMAP24XX_GPIO_OE;
1611 break;
1612 }
1613 return __raw_readl(reg) & mask;
1614}
1615
1616
1617static int dbg_gpio_show(struct seq_file *s, void *unused)
1618{
1619 unsigned i, j, gpio;
1620
1621 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1622 struct gpio_bank *bank = gpio_bank + i;
1623 unsigned bankwidth = 16;
1624 u32 mask = 1;
1625
1626 if (bank_is_mpuio(bank))
1627 gpio = OMAP_MPUIO(0);
1628 else if (cpu_is_omap24xx() || cpu_is_omap730())
1629 bankwidth = 32;
1630
1631 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1632 unsigned irq, value, is_in, irqstat;
1633
1634 if (!(bank->reserved_map & mask))
1635 continue;
1636
1637 irq = bank->virtual_irq_start + j;
1638 value = omap_get_gpio_datain(gpio);
1639 is_in = gpio_is_input(bank, mask);
1640
1641 if (bank_is_mpuio(bank))
1642 seq_printf(s, "MPUIO %2d: ", j);
1643 else
1644 seq_printf(s, "GPIO %3d: ", gpio);
1645 seq_printf(s, "%s %s",
1646 is_in ? "in " : "out",
1647 value ? "hi" : "lo");
1648
1649 irqstat = irq_desc[irq].status;
1650 if (is_in && ((bank->suspend_wakeup & mask)
1651 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1652 char *trigger = NULL;
1653
1654 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1655 case IRQ_TYPE_EDGE_FALLING:
1656 trigger = "falling";
1657 break;
1658 case IRQ_TYPE_EDGE_RISING:
1659 trigger = "rising";
1660 break;
1661 case IRQ_TYPE_EDGE_BOTH:
1662 trigger = "bothedge";
1663 break;
1664 case IRQ_TYPE_LEVEL_LOW:
1665 trigger = "low";
1666 break;
1667 case IRQ_TYPE_LEVEL_HIGH:
1668 trigger = "high";
1669 break;
1670 case IRQ_TYPE_NONE:
1671 trigger = "(unspecified)";
1672 break;
1673 }
1674 seq_printf(s, ", irq-%d %s%s",
1675 irq, trigger,
1676 (bank->suspend_wakeup & mask)
1677 ? " wakeup" : "");
1678 }
1679 seq_printf(s, "\n");
1680 }
1681
1682 if (bank_is_mpuio(bank)) {
1683 seq_printf(s, "\n");
1684 gpio = 0;
1685 }
1686 }
1687 return 0;
1688}
1689
1690static int dbg_gpio_open(struct inode *inode, struct file *file)
1691{
1692 return single_open(file, dbg_gpio_show, &inode->i_private);
1693}
1694
1695static const struct file_operations debug_fops = {
1696 .open = dbg_gpio_open,
1697 .read = seq_read,
1698 .llseek = seq_lseek,
1699 .release = single_release,
1700};
1701
1702static int __init omap_gpio_debuginit(void)
1703{
1704 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1705 NULL, NULL, &debug_fops);
1706 return 0;
1707}
1708late_initcall(omap_gpio_debuginit);
1709#endif
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index b8d6f17ff58f..f7b9ccdaacbc 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -225,11 +225,16 @@ static void omap_mcbsp_dsp_free(void)
225#ifdef CONFIG_ARCH_OMAP2 225#ifdef CONFIG_ARCH_OMAP2
226static void omap2_mcbsp2_mux_setup(void) 226static void omap2_mcbsp2_mux_setup(void)
227{ 227{
228 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); 228 if (cpu_is_omap2420()) {
229 omap_cfg_reg(R14_24XX_MCBSP2_FSX); 229 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
230 omap_cfg_reg(W15_24XX_MCBSP2_DR); 230 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
231 omap_cfg_reg(V15_24XX_MCBSP2_DX); 231 omap_cfg_reg(W15_24XX_MCBSP2_DR);
232 omap_cfg_reg(V14_24XX_GPIO117); 232 omap_cfg_reg(V15_24XX_MCBSP2_DX);
233 omap_cfg_reg(V14_24XX_GPIO117);
234 }
235 /*
236 * Need to add MUX settings for OMAP 2430 SDP
237 */
233} 238}
234#endif 239#endif
235 240
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c
index 265310601161..114f87151d60 100644
--- a/arch/arm/plat-omap/timer32k.c
+++ b/arch/arm/plat-omap/timer32k.c
@@ -42,6 +42,8 @@
42#include <linux/spinlock.h> 42#include <linux/spinlock.h>
43#include <linux/err.h> 43#include <linux/err.h>
44#include <linux/clk.h> 44#include <linux/clk.h>
45#include <linux/clocksource.h>
46#include <linux/clockchips.h>
45 47
46#include <asm/system.h> 48#include <asm/system.h>
47#include <asm/hardware.h> 49#include <asm/hardware.h>
@@ -80,13 +82,13 @@ struct sys_timer omap_timer;
80#define OMAP1_32K_TIMER_TVR 0x00 82#define OMAP1_32K_TIMER_TVR 0x00
81#define OMAP1_32K_TIMER_TCR 0x04 83#define OMAP1_32K_TIMER_TCR 0x04
82 84
83#define OMAP_32K_TICKS_PER_HZ (32768 / HZ) 85#define OMAP_32K_TICKS_PER_SEC (32768)
84 86
85/* 87/*
86 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1 88 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
87 * so with HZ = 128, TVR = 255. 89 * so with HZ = 128, TVR = 255.
88 */ 90 */
89#define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1) 91#define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
90 92
91#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ 93#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
92 (((nr_jiffies) * (clock_rate)) / HZ) 94 (((nr_jiffies) * (clock_rate)) / HZ)
@@ -142,6 +144,28 @@ static inline void omap_32k_timer_ack_irq(void)
142 144
143#endif 145#endif
144 146
147static void omap_32k_timer_set_mode(enum clock_event_mode mode,
148 struct clock_event_device *evt)
149{
150 switch (mode) {
151 case CLOCK_EVT_MODE_ONESHOT:
152 case CLOCK_EVT_MODE_PERIODIC:
153 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
154 break;
155 case CLOCK_EVT_MODE_UNUSED:
156 case CLOCK_EVT_MODE_SHUTDOWN:
157 omap_32k_timer_stop();
158 break;
159 }
160}
161
162static struct clock_event_device clockevent_32k_timer = {
163 .name = "32k-timer",
164 .features = CLOCK_EVT_FEAT_PERIODIC,
165 .shift = 32,
166 .set_mode = omap_32k_timer_set_mode,
167};
168
145/* 169/*
146 * The 32KHz synchronized timer is an additional timer on 16xx. 170 * The 32KHz synchronized timer is an additional timer on 16xx.
147 * It is always running. 171 * It is always running.
@@ -171,15 +195,6 @@ omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
171static unsigned long omap_32k_last_tick = 0; 195static unsigned long omap_32k_last_tick = 0;
172 196
173/* 197/*
174 * Returns elapsed usecs since last 32k timer interrupt
175 */
176static unsigned long omap_32k_timer_gettimeoffset(void)
177{
178 unsigned long now = omap_32k_sync_timer_read();
179 return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
180}
181
182/*
183 * Returns current time from boot in nsecs. It's OK for this to wrap 198 * Returns current time from boot in nsecs. It's OK for this to wrap
184 * around for now, as it's just a relative time stamp. 199 * around for now, as it's just a relative time stamp.
185 */ 200 */
@@ -188,95 +203,16 @@ unsigned long long sched_clock(void)
188 return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read()); 203 return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
189} 204}
190 205
191/*
192 * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
193 * function is also called from other interrupts to remove latency
194 * issues with dynamic tick. In the dynamic tick case, we need to lock
195 * with irqsave.
196 */
197static inline irqreturn_t _omap_32k_timer_interrupt(int irq, void *dev_id)
198{
199 unsigned long now;
200
201 omap_32k_timer_ack_irq();
202 now = omap_32k_sync_timer_read();
203
204 while ((signed long)(now - omap_32k_last_tick)
205 >= OMAP_32K_TICKS_PER_HZ) {
206 omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
207 timer_tick();
208 }
209
210 /* Restart timer so we don't drift off due to modulo or dynamic tick.
211 * By default we program the next timer to be continuous to avoid
212 * latencies during high system load. During dynamic tick operation the
213 * continuous timer can be overridden from pm_idle to be longer.
214 */
215 omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
216
217 return IRQ_HANDLED;
218}
219
220static irqreturn_t omap_32k_timer_handler(int irq, void *dev_id)
221{
222 return _omap_32k_timer_interrupt(irq, dev_id);
223}
224
225static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id) 206static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
226{ 207{
227 unsigned long flags; 208 struct clock_event_device *evt = &clockevent_32k_timer;
209 omap_32k_timer_ack_irq();
228 210
229 write_seqlock_irqsave(&xtime_lock, flags); 211 evt->event_handler(evt);
230 _omap_32k_timer_interrupt(irq, dev_id);
231 write_sequnlock_irqrestore(&xtime_lock, flags);
232 212
233 return IRQ_HANDLED; 213 return IRQ_HANDLED;
234} 214}
235 215
236#ifdef CONFIG_NO_IDLE_HZ
237/*
238 * Programs the next timer interrupt needed. Called when dynamic tick is
239 * enabled, and to reprogram the ticks to skip from pm_idle. Note that
240 * we can keep the timer continuous, and don't need to set it to run in
241 * one-shot mode. This is because the timer will get reprogrammed again
242 * after next interrupt.
243 */
244void omap_32k_timer_reprogram(unsigned long next_tick)
245{
246 unsigned long ticks = JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1;
247 unsigned long now = omap_32k_sync_timer_read();
248 unsigned long idled = now - omap_32k_last_tick;
249
250 if (idled + 1 < ticks)
251 ticks -= idled;
252 else
253 ticks = 1;
254 omap_32k_timer_start(ticks);
255}
256
257static struct irqaction omap_32k_timer_irq;
258extern struct timer_update_handler timer_update;
259
260static int omap_32k_timer_enable_dyn_tick(void)
261{
262 /* No need to reprogram timer, just use the next interrupt */
263 return 0;
264}
265
266static int omap_32k_timer_disable_dyn_tick(void)
267{
268 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
269 return 0;
270}
271
272static struct dyn_tick_timer omap_dyn_tick_timer = {
273 .enable = omap_32k_timer_enable_dyn_tick,
274 .disable = omap_32k_timer_disable_dyn_tick,
275 .reprogram = omap_32k_timer_reprogram,
276 .handler = omap_32k_timer_handler,
277};
278#endif /* CONFIG_NO_IDLE_HZ */
279
280static struct irqaction omap_32k_timer_irq = { 216static struct irqaction omap_32k_timer_irq = {
281 .name = "32KHz timer", 217 .name = "32KHz timer",
282 .flags = IRQF_DISABLED | IRQF_TIMER, 218 .flags = IRQF_DISABLED | IRQF_TIMER,
@@ -285,13 +221,8 @@ static struct irqaction omap_32k_timer_irq = {
285 221
286static __init void omap_init_32k_timer(void) 222static __init void omap_init_32k_timer(void)
287{ 223{
288#ifdef CONFIG_NO_IDLE_HZ
289 omap_timer.dyn_tick = &omap_dyn_tick_timer;
290#endif
291
292 if (cpu_class_is_omap1()) 224 if (cpu_class_is_omap1())
293 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); 225 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
294 omap_timer.offset = omap_32k_timer_gettimeoffset;
295 omap_32k_last_tick = omap_32k_sync_timer_read(); 226 omap_32k_last_tick = omap_32k_sync_timer_read();
296 227
297#ifdef CONFIG_ARCH_OMAP2 228#ifdef CONFIG_ARCH_OMAP2
@@ -308,7 +239,16 @@ static __init void omap_init_32k_timer(void)
308 } 239 }
309#endif 240#endif
310 241
311 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD); 242 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
243 NSEC_PER_SEC,
244 clockevent_32k_timer.shift);
245 clockevent_32k_timer.max_delta_ns =
246 clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
247 clockevent_32k_timer.min_delta_ns =
248 clockevent_delta2ns(1, &clockevent_32k_timer);
249
250 clockevent_32k_timer.cpumask = cpumask_of_cpu(0);
251 clockevents_register_device(&clockevent_32k_timer);
312} 252}
313 253
314/* 254/*
@@ -326,5 +266,4 @@ static void __init omap_timer_init(void)
326 266
327struct sys_timer omap_timer = { 267struct sys_timer omap_timer = {
328 .init = omap_timer_init, 268 .init = omap_timer_init,
329 .offset = NULL, /* Initialized later */
330}; 269};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 18:23:22 -0500