92 files changed, 1241 insertions, 1323 deletions

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 64b3f52bd9b2..f348ddfb0492 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -165,7 +165,7 @@ config OMAP_DM_TIMER
 choice
         prompt "Low-level debug console UART"
         depends on ARCH_OMAP
-        default OMAP_LL_DEBUG_UART1
+        default OMAP_LL_DEBUG_NONE
 
 config OMAP_LL_DEBUG_UART1
         bool "UART1"
@@ -176,6 +176,9 @@ config OMAP_LL_DEBUG_UART2
 config OMAP_LL_DEBUG_UART3
         bool "UART3"
 
+config OMAP_LL_DEBUG_NONE
+        bool "None"
+
 endchoice
 
 config OMAP_SERIAL_WAKE
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index bf880e966d3b..681bfc37ebb2 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -24,7 +24,7 @@
 #include <linux/debugfs.h>
 #include <linux/io.h>
 
-#include <mach/clock.h>
+#include <plat/clock.h>
 
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 3a4768d55895..cc050b3313bd 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -29,13 +29,13 @@
 #include <asm/mach/map.h>
 #include <asm/setup.h>
 
-#include <mach/common.h>
-#include <mach/board.h>
-#include <mach/control.h>
-#include <mach/mux.h>
-#include <mach/fpga.h>
+#include <plat/common.h>
+#include <plat/board.h>
+#include <plat/control.h>
+#include <plat/mux.h>
+#include <plat/fpga.h>
 
-#include <mach/clock.h>
+#include <plat/clock.h>
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 # include "../mach-omap2/sdrc.h"
@@ -49,6 +49,9 @@ int omap_bootloader_tag_len;
 struct omap_board_config_kernel *omap_board_config;
 int omap_board_config_size;
 
+/* used by omap-smp.c and board-4430sdp.c */
+void __iomem *gic_cpu_base_addr;
+
 static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
 {
         struct omap_board_config_kernel *kinfo = NULL;
@@ -224,12 +227,12 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
 
 static struct omap_globals omap242x_globals = {
         .class  = OMAP242X_CLASS,
-        .tap    = OMAP2_IO_ADDRESS(0x48014000),
-        .sdrc   = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
-        .sms    = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
-        .ctrl   = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
-        .prm    = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
-        .cm     = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
+        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
+        .sms    = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
+        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE),
+        .prm    = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
+        .cm     = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
 };
 
 void __init omap2_set_globals_242x(void)
@@ -242,12 +245,12 @@ void __init omap2_set_globals_242x(void)
 
 static struct omap_globals omap243x_globals = {
         .class  = OMAP243X_CLASS,
-        .tap    = OMAP2_IO_ADDRESS(0x4900a000),
-        .sdrc   = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
-        .sms    = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
-        .ctrl   = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
-        .prm    = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
-        .cm     = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
+        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
+        .sms    = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
+        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
+        .prm    = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
+        .cm     = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
 };
 
 void __init omap2_set_globals_243x(void)
@@ -260,12 +263,12 @@ void __init omap2_set_globals_243x(void)
 
 static struct omap_globals omap343x_globals = {
         .class  = OMAP343X_CLASS,
-        .tap    = OMAP2_IO_ADDRESS(0x4830A000),
-        .sdrc   = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
-        .sms    = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
-        .ctrl   = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
-        .prm    = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
-        .cm     = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
+        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
+        .sms    = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
+        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
+        .prm    = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
+        .cm     = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
 };
 
 void __init omap2_set_globals_343x(void)
@@ -277,10 +280,10 @@ void __init omap2_set_globals_343x(void)
 #if defined(CONFIG_ARCH_OMAP4)
 static struct omap_globals omap4_globals = {
         .class  = OMAP443X_CLASS,
-        .tap    = OMAP2_IO_ADDRESS(0x4830a000),
-        .ctrl   = OMAP2_IO_ADDRESS(OMAP443X_CTRL_BASE),
-        .prm    = OMAP2_IO_ADDRESS(OMAP4430_PRM_BASE),
-        .cm     = OMAP2_IO_ADDRESS(OMAP4430_CM_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4830a000),
+        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
+        .prm    = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
+        .cm     = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
 };
 
 void __init omap2_set_globals_443x(void)
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 341235c278ac..f8ddbdd8b076 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -23,7 +23,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <mach/clock.h>
+#include <plat/clock.h>
 #include <asm/system.h>
 
 #define VERY_HI_RATE    900000000
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index f6684832ca8f..09c1107637f6 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -16,7 +16,7 @@
 
 #include <mach/hardware.h>
 
-#include <mach/board.h>
+#include <plat/board.h>
 #include <mach/gpio.h>
 
 
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 9395898dd49a..6c768b71ad64 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -18,7 +18,7 @@
 #include <asm/system.h>
 #include <asm/mach-types.h>
 
-#include <mach/fpga.h>
+#include <plat/fpga.h>
 #include <mach/gpio.h>
 
 
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index a64b692a1bfe..f86617869b38 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -19,15 +19,15 @@
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
-#include <mach/tc.h>
-#include <mach/control.h>
-#include <mach/board.h>
-#include <mach/mmc.h>
-#include <mach/mux.h>
+#include <plat/tc.h>
+#include <plat/control.h>
+#include <plat/board.h>
+#include <plat/mmc.h>
+#include <plat/mux.h>
 #include <mach/gpio.h>
-#include <mach/menelaus.h>
-#include <mach/mcbsp.h>
-#include <mach/dsp_common.h>
+#include <plat/menelaus.h>
+#include <plat/mcbsp.h>
+#include <plat/dsp_common.h>
 
 #if     defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
 
@@ -113,17 +113,17 @@ static void omap_init_kp(void)
                 omap_cfg_reg(E19_1610_KBR4);
                 omap_cfg_reg(N19_1610_KBR5);
         } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
-                omap_cfg_reg(E2_730_KBR0);
-                omap_cfg_reg(J7_730_KBR1);
-                omap_cfg_reg(E1_730_KBR2);
-                omap_cfg_reg(F3_730_KBR3);
-                omap_cfg_reg(D2_730_KBR4);
-
-                omap_cfg_reg(C2_730_KBC0);
-                omap_cfg_reg(D3_730_KBC1);
-                omap_cfg_reg(E4_730_KBC2);
-                omap_cfg_reg(F4_730_KBC3);
-                omap_cfg_reg(E3_730_KBC4);
+                omap_cfg_reg(E2_7XX_KBR0);
+                omap_cfg_reg(J7_7XX_KBR1);
+                omap_cfg_reg(E1_7XX_KBR2);
+                omap_cfg_reg(F3_7XX_KBR3);
+                omap_cfg_reg(D2_7XX_KBR4);
+
+                omap_cfg_reg(C2_7XX_KBC0);
+                omap_cfg_reg(D3_7XX_KBC1);
+                omap_cfg_reg(E4_7XX_KBC2);
+                omap_cfg_reg(F4_7XX_KBC3);
+                omap_cfg_reg(E3_7XX_KBC4);
         } else if (machine_is_omap_h4()) {
                 omap_cfg_reg(T19_24XX_KBR0);
                 omap_cfg_reg(R19_24XX_KBR1);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 68eaae324b6a..be4ce070fb4c 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -32,9 +32,9 @@
 
 #include <asm/system.h>
 #include <mach/hardware.h>
-#include <mach/dma.h>
+#include <plat/dma.h>
 
-#include <mach/tc.h>
+#include <plat/tc.h>
 
 #undef DEBUG
 
@@ -54,6 +54,12 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 
 static int enable_1510_mode;
 
+static struct omap_dma_global_context_registers {
+        u32 dma_irqenable_l0;
+        u32 dma_ocp_sysconfig;
+        u32 dma_gcr;
+} omap_dma_global_context;
+
 struct omap_dma_lch {
         int next_lch;
         int dev_id;
@@ -2355,44 +2361,83 @@ void omap_stop_lcd_dma(void)
 }
 EXPORT_SYMBOL(omap_stop_lcd_dma);
 
+void omap_dma_global_context_save(void)
+{
+        omap_dma_global_context.dma_irqenable_l0 =
+                dma_read(IRQENABLE_L0);
+        omap_dma_global_context.dma_ocp_sysconfig =
+                dma_read(OCP_SYSCONFIG);
+        omap_dma_global_context.dma_gcr = dma_read(GCR);
+}
+
+void omap_dma_global_context_restore(void)
+{
+        int ch;
+
+        dma_write(omap_dma_global_context.dma_gcr, GCR);
+        dma_write(omap_dma_global_context.dma_ocp_sysconfig,
+                OCP_SYSCONFIG);
+        dma_write(omap_dma_global_context.dma_irqenable_l0,
+                IRQENABLE_L0);
+
+        /*
+         * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+         * after secure sram context save and restore. Hence we need to
+         * manually clear those IRQs to avoid spurious interrupts. This
+         * affects only secure devices.
+         */
+        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+                dma_write(0x3 , IRQSTATUS_L0);
+
+        for (ch = 0; ch < dma_chan_count; ch++)
+                if (dma_chan[ch].dev_id != -1)
+                        omap_clear_dma(ch);
+}
+
 /*----------------------------------------------------------------------------*/
 
 static int __init omap_init_dma(void)
 {
+        unsigned long base;
         int ch, r;
 
         if (cpu_class_is_omap1()) {
-                omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
+                base = OMAP1_DMA_BASE;
                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
         } else if (cpu_is_omap24xx()) {
-                omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
+                base = OMAP24XX_DMA4_BASE;
                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else if (cpu_is_omap34xx()) {
-                omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
+                base = OMAP34XX_DMA4_BASE;
                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else if (cpu_is_omap44xx()) {
-                omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
+                base = OMAP44XX_DMA4_BASE;
                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else {
                 pr_err("DMA init failed for unsupported omap\n");
                 return -ENODEV;
         }
 
+        omap_dma_base = ioremap(base, SZ_4K);
+        BUG_ON(!omap_dma_base);
+
         if (cpu_class_is_omap2() && omap_dma_reserve_channels
                         && (omap_dma_reserve_channels <= dma_lch_count))
                 dma_lch_count = omap_dma_reserve_channels;
 
         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
                                 GFP_KERNEL);
-        if (!dma_chan)
-                return -ENOMEM;
+        if (!dma_chan) {
+                r = -ENOMEM;
+                goto out_unmap;
+        }
 
         if (cpu_class_is_omap2()) {
                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
                                                 dma_lch_count, GFP_KERNEL);
                 if (!dma_linked_lch) {
-                        kfree(dma_chan);
-                        return -ENOMEM;
+                        r = -ENOMEM;
+                        goto out_free;
                 }
         }
 
@@ -2466,7 +2511,7 @@ static int __init omap_init_dma(void)
                                 for (i = 0; i < ch; i++)
                                         free_irq(omap1_dma_irq[i],
                                                  (void *) (i + 1));
-                                return r;
+                                goto out_free;
                         }
                 }
         }
@@ -2484,8 +2529,8 @@ static int __init omap_init_dma(void)
                 setup_irq(irq, &omap24xx_dma_irq);
         }
 
-        /* Enable smartidle idlemodes and autoidle */
         if (cpu_is_omap34xx()) {
+                /* Enable smartidle idlemodes and autoidle */
                 u32 v = dma_read(OCP_SYSCONFIG);
                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
                                 DMA_SYSCONFIG_SIDLEMODE_MASK |
@@ -2494,6 +2539,13 @@ static int __init omap_init_dma(void)
                         DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
                         DMA_SYSCONFIG_AUTOIDLE);
                 dma_write(v , OCP_SYSCONFIG);
+                /* reserve dma channels 0 and 1 in high security devices */
+                if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+                        printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
+                                        "HS ROM code\n");
+                        dma_chan[0].dev_id = 0;
+                        dma_chan[1].dev_id = 1;
+                }
         }
 
 
@@ -2508,11 +2560,19 @@ static int __init omap_init_dma(void)
                                "(error %d)\n", r);
                         for (i = 0; i < dma_chan_count; i++)
                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
-                        return r;
+                        goto out_free;
                 }
         }
 
         return 0;
+
+out_free:
+        kfree(dma_chan);
+
+out_unmap:
+        iounmap(omap_dma_base);
+
+        return r;
 }
 
 arch_initcall(omap_init_dma);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index d325b54daeb5..64f407ee0f4e 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -38,7 +38,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <mach/hardware.h>
-#include <mach/dmtimer.h>
+#include <plat/dmtimer.h>
 #include <mach/irqs.h>
 
 /* register offsets */
@@ -742,16 +742,17 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active);
 int __init omap_dm_timer_init(void)
 {
         struct omap_dm_timer *timer;
-        int i;
+        int i, map_size = SZ_8K;        /* Module 4KB + L4 4KB except on omap1 */
 
         if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
                 return -ENODEV;
 
         spin_lock_init(&dm_timer_lock);
 
-        if (cpu_class_is_omap1())
+        if (cpu_class_is_omap1()) {
                 dm_timers = omap1_dm_timers;
-        else if (cpu_is_omap24xx()) {
+                map_size = SZ_2K;
+        } else if (cpu_is_omap24xx()) {
                 dm_timers = omap2_dm_timers;
                 dm_source_names = omap2_dm_source_names;
                 dm_source_clocks = omap2_dm_source_clocks;
@@ -774,10 +775,11 @@ int __init omap_dm_timer_init(void)
 
         for (i = 0; i < dm_timer_count; i++) {
                 timer = &dm_timers[i];
-                if (cpu_class_is_omap1())
-                        timer->io_base = OMAP1_IO_ADDRESS(timer->phys_base);
-                else
-                        timer->io_base = OMAP2_IO_ADDRESS(timer->phys_base);
+
+                /* Static mapping, never released */
+                timer->io_base = ioremap(timer->phys_base, map_size);
+                BUG_ON(!timer->io_base);
+
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
                                         defined(CONFIG_ARCH_OMAP4)
                 if (cpu_class_is_omap2()) {
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index 3746222bed10..78a4ce538dbd 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -32,9 +32,9 @@
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 
-#include <mach/board.h>
-#include <mach/sram.h>
-#include <mach/omapfb.h>
+#include <plat/board.h>
+#include <plat/sram.h>
+#include <plat/omapfb.h>
 
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 7c345b757df1..055160e0620e 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -31,7 +31,7 @@
 /*
  * OMAP1510 GPIO registers
  */
-#define OMAP1510_GPIO_BASE              OMAP1_IO_ADDRESS(0xfffce000)
+#define OMAP1510_GPIO_BASE              0xfffce000
 #define OMAP1510_GPIO_DATA_INPUT        0x00
 #define OMAP1510_GPIO_DATA_OUTPUT       0x04
 #define OMAP1510_GPIO_DIR_CONTROL       0x08
@@ -45,10 +45,10 @@
 /*
  * OMAP1610 specific GPIO registers
  */
-#define OMAP1610_GPIO1_BASE             OMAP1_IO_ADDRESS(0xfffbe400)
-#define OMAP1610_GPIO2_BASE             OMAP1_IO_ADDRESS(0xfffbec00)
-#define OMAP1610_GPIO3_BASE             OMAP1_IO_ADDRESS(0xfffbb400)
-#define OMAP1610_GPIO4_BASE             OMAP1_IO_ADDRESS(0xfffbbc00)
+#define OMAP1610_GPIO1_BASE             0xfffbe400
+#define OMAP1610_GPIO2_BASE             0xfffbec00
+#define OMAP1610_GPIO3_BASE             0xfffbb400
+#define OMAP1610_GPIO4_BASE             0xfffbbc00
 #define OMAP1610_GPIO_REVISION          0x0000
 #define OMAP1610_GPIO_SYSCONFIG         0x0010
 #define OMAP1610_GPIO_SYSSTATUS         0x0014
@@ -68,52 +68,36 @@
 #define OMAP1610_GPIO_SET_DATAOUT       0x00f0
 
 /*
- * OMAP730 specific GPIO registers
+ * OMAP7XX specific GPIO registers
  */
-#define OMAP730_GPIO1_BASE              OMAP1_IO_ADDRESS(0xfffbc000)
-#define OMAP730_GPIO2_BASE              OMAP1_IO_ADDRESS(0xfffbc800)
-#define OMAP730_GPIO3_BASE              OMAP1_IO_ADDRESS(0xfffbd000)
-#define OMAP730_GPIO4_BASE              OMAP1_IO_ADDRESS(0xfffbd800)
-#define OMAP730_GPIO5_BASE              OMAP1_IO_ADDRESS(0xfffbe000)
-#define OMAP730_GPIO6_BASE              OMAP1_IO_ADDRESS(0xfffbe800)
-#define OMAP730_GPIO_DATA_INPUT         0x00
-#define OMAP730_GPIO_DATA_OUTPUT        0x04
-#define OMAP730_GPIO_DIR_CONTROL        0x08
-#define OMAP730_GPIO_INT_CONTROL        0x0c
-#define OMAP730_GPIO_INT_MASK           0x10
-#define OMAP730_GPIO_INT_STATUS         0x14
-
-/*
- * OMAP850 specific GPIO registers
- */
-#define OMAP850_GPIO1_BASE              OMAP1_IO_ADDRESS(0xfffbc000)
-#define OMAP850_GPIO2_BASE              OMAP1_IO_ADDRESS(0xfffbc800)
-#define OMAP850_GPIO3_BASE              OMAP1_IO_ADDRESS(0xfffbd000)
-#define OMAP850_GPIO4_BASE              OMAP1_IO_ADDRESS(0xfffbd800)
-#define OMAP850_GPIO5_BASE              OMAP1_IO_ADDRESS(0xfffbe000)
-#define OMAP850_GPIO6_BASE              OMAP1_IO_ADDRESS(0xfffbe800)
-#define OMAP850_GPIO_DATA_INPUT         0x00
-#define OMAP850_GPIO_DATA_OUTPUT        0x04
-#define OMAP850_GPIO_DIR_CONTROL        0x08
-#define OMAP850_GPIO_INT_CONTROL        0x0c
-#define OMAP850_GPIO_INT_MASK           0x10
-#define OMAP850_GPIO_INT_STATUS         0x14
-
-#define OMAP1_MPUIO_VBASE               OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
+#define OMAP7XX_GPIO1_BASE              0xfffbc000
+#define OMAP7XX_GPIO2_BASE              0xfffbc800
+#define OMAP7XX_GPIO3_BASE              0xfffbd000
+#define OMAP7XX_GPIO4_BASE              0xfffbd800
+#define OMAP7XX_GPIO5_BASE              0xfffbe000
+#define OMAP7XX_GPIO6_BASE              0xfffbe800
+#define OMAP7XX_GPIO_DATA_INPUT         0x00
+#define OMAP7XX_GPIO_DATA_OUTPUT        0x04
+#define OMAP7XX_GPIO_DIR_CONTROL        0x08
+#define OMAP7XX_GPIO_INT_CONTROL        0x0c
+#define OMAP7XX_GPIO_INT_MASK           0x10
+#define OMAP7XX_GPIO_INT_STATUS         0x14
+
+#define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
 
 /*
  * omap24xx specific GPIO registers
  */
-#define OMAP242X_GPIO1_BASE             OMAP2_IO_ADDRESS(0x48018000)
-#define OMAP242X_GPIO2_BASE             OMAP2_IO_ADDRESS(0x4801a000)
-#define OMAP242X_GPIO3_BASE             OMAP2_IO_ADDRESS(0x4801c000)
-#define OMAP242X_GPIO4_BASE             OMAP2_IO_ADDRESS(0x4801e000)
+#define OMAP242X_GPIO1_BASE             0x48018000
+#define OMAP242X_GPIO2_BASE             0x4801a000
+#define OMAP242X_GPIO3_BASE             0x4801c000
+#define OMAP242X_GPIO4_BASE             0x4801e000
 
-#define OMAP243X_GPIO1_BASE             OMAP2_IO_ADDRESS(0x4900C000)
-#define OMAP243X_GPIO2_BASE             OMAP2_IO_ADDRESS(0x4900E000)
-#define OMAP243X_GPIO3_BASE             OMAP2_IO_ADDRESS(0x49010000)
-#define OMAP243X_GPIO4_BASE             OMAP2_IO_ADDRESS(0x49012000)
-#define OMAP243X_GPIO5_BASE             OMAP2_IO_ADDRESS(0x480B6000)
+#define OMAP243X_GPIO1_BASE             0x4900C000
+#define OMAP243X_GPIO2_BASE             0x4900E000
+#define OMAP243X_GPIO3_BASE             0x49010000
+#define OMAP243X_GPIO4_BASE             0x49012000
+#define OMAP243X_GPIO5_BASE             0x480B6000
 
 #define OMAP24XX_GPIO_REVISION          0x0000
 #define OMAP24XX_GPIO_SYSCONFIG         0x0010
@@ -170,24 +154,25 @@
  * omap34xx specific GPIO registers
  */
 
-#define OMAP34XX_GPIO1_BASE             OMAP2_IO_ADDRESS(0x48310000)
-#define OMAP34XX_GPIO2_BASE             OMAP2_IO_ADDRESS(0x49050000)
-#define OMAP34XX_GPIO3_BASE             OMAP2_IO_ADDRESS(0x49052000)
-#define OMAP34XX_GPIO4_BASE             OMAP2_IO_ADDRESS(0x49054000)
-#define OMAP34XX_GPIO5_BASE             OMAP2_IO_ADDRESS(0x49056000)
-#define OMAP34XX_GPIO6_BASE             OMAP2_IO_ADDRESS(0x49058000)
+#define OMAP34XX_GPIO1_BASE             0x48310000
+#define OMAP34XX_GPIO2_BASE             0x49050000
+#define OMAP34XX_GPIO3_BASE             0x49052000
+#define OMAP34XX_GPIO4_BASE             0x49054000
+#define OMAP34XX_GPIO5_BASE             0x49056000
+#define OMAP34XX_GPIO6_BASE             0x49058000
 
 /*
  * OMAP44XX  specific GPIO registers
  */
-#define OMAP44XX_GPIO1_BASE             OMAP2_IO_ADDRESS(0x4a310000)
-#define OMAP44XX_GPIO2_BASE             OMAP2_IO_ADDRESS(0x48055000)
-#define OMAP44XX_GPIO3_BASE             OMAP2_IO_ADDRESS(0x48057000)
-#define OMAP44XX_GPIO4_BASE             OMAP2_IO_ADDRESS(0x48059000)
-#define OMAP44XX_GPIO5_BASE             OMAP2_IO_ADDRESS(0x4805B000)
-#define OMAP44XX_GPIO6_BASE             OMAP2_IO_ADDRESS(0x4805D000)
+#define OMAP44XX_GPIO1_BASE             0x4a310000
+#define OMAP44XX_GPIO2_BASE             0x48055000
+#define OMAP44XX_GPIO3_BASE             0x48057000
+#define OMAP44XX_GPIO4_BASE             0x48059000
+#define OMAP44XX_GPIO5_BASE             0x4805B000
+#define OMAP44XX_GPIO6_BASE             0x4805D000
 
 struct gpio_bank {
+        unsigned long pbase;
         void __iomem *base;
         u16 irq;
         u16 virtual_irq_start;
@@ -210,101 +195,134 @@ struct gpio_bank {
         spinlock_t lock;
         struct gpio_chip chip;
         struct clk *dbck;
+        u32 mod_usage;
 };
 
 #define METHOD_MPUIO            0
 #define METHOD_GPIO_1510        1
 #define METHOD_GPIO_1610        2
-#define METHOD_GPIO_730         3
-#define METHOD_GPIO_850         4
+#define METHOD_GPIO_7XX         3
 #define METHOD_GPIO_24XX        5
 
 #ifdef CONFIG_ARCH_OMAP16XX
 static struct gpio_bank gpio_bank_1610[5] = {
-        { OMAP1_MPUIO_VBASE,    INT_MPUIO,          IH_MPUIO_BASE,     METHOD_MPUIO},
-        { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      METHOD_GPIO_1610 },
-        { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
-        { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
-        { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
+        { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
+                METHOD_MPUIO },
+        { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_1610 },
+        { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
+                METHOD_GPIO_1610 },
+        { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
+                METHOD_GPIO_1610 },
+        { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
+                METHOD_GPIO_1610 },
 };
 #endif
 
 #ifdef CONFIG_ARCH_OMAP15XX
 static struct gpio_bank gpio_bank_1510[2] = {
-        { OMAP1_MPUIO_VBASE,   INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
-        { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP730
-static struct gpio_bank gpio_bank_730[7] = {
-        { OMAP1_MPUIO_VBASE,    INT_730_MPUIO,      IH_MPUIO_BASE,      METHOD_MPUIO },
-        { OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_730 },
-        { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_730 },
-        { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_730 },
-        { OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_730 },
-        { OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_730 },
-        { OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_730 },
+        { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
+                METHOD_MPUIO },
+        { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_1510 }
 };
 #endif
 
-#ifdef CONFIG_ARCH_OMAP850
-static struct gpio_bank gpio_bank_850[7] = {
-        { OMAP1_MPUIO_VBASE,     INT_850_MPUIO,     IH_MPUIO_BASE,      METHOD_MPUIO },
-        { OMAP850_GPIO1_BASE,  INT_850_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_850 },
-        { OMAP850_GPIO2_BASE,  INT_850_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_850 },
-        { OMAP850_GPIO3_BASE,  INT_850_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_850 },
-        { OMAP850_GPIO4_BASE,  INT_850_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_850 },
-        { OMAP850_GPIO5_BASE,  INT_850_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_850 },
-        { OMAP850_GPIO6_BASE,  INT_850_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_850 },
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+static struct gpio_bank gpio_bank_7xx[7] = {
+        { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
+                METHOD_MPUIO },
+        { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_7XX },
+        { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
+                METHOD_GPIO_7XX },
+        { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
+                METHOD_GPIO_7XX },
+        { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4,  IH_GPIO_BASE + 96,
+                METHOD_GPIO_7XX },
+        { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5,  IH_GPIO_BASE + 128,
+                METHOD_GPIO_7XX },
+        { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6,  IH_GPIO_BASE + 160,
+                METHOD_GPIO_7XX },
 };
 #endif
 
-
 #ifdef CONFIG_ARCH_OMAP24XX
 
 static struct gpio_bank gpio_bank_242x[4] = {
-        { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
-        { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
-        { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
-        { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
+        { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_24XX },
+        { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
+                METHOD_GPIO_24XX },
+        { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
+                METHOD_GPIO_24XX },
+        { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
+                METHOD_GPIO_24XX },
 };
 
 static struct gpio_bank gpio_bank_243x[5] = {
-        { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
-        { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
-        { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
-        { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
-        { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
+        { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_24XX },
+        { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
+                METHOD_GPIO_24XX },
+        { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
+                METHOD_GPIO_24XX },
+        { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
+                METHOD_GPIO_24XX },
+        { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
+                METHOD_GPIO_24XX },
 };
 
 #endif
 
 #ifdef CONFIG_ARCH_OMAP34XX
 static struct gpio_bank gpio_bank_34xx[6] = {
-        { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
+        { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
+                METHOD_GPIO_24XX },
+        { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
+                METHOD_GPIO_24XX },
+        { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
+                METHOD_GPIO_24XX },
+        { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
+                METHOD_GPIO_24XX },
+        { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
+                METHOD_GPIO_24XX },
+        { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
+                METHOD_GPIO_24XX },
 };
 
+struct omap3_gpio_regs {
+        u32 sysconfig;
+        u32 irqenable1;
+        u32 irqenable2;
+        u32 wake_en;
+        u32 ctrl;
+        u32 oe;
+        u32 leveldetect0;
+        u32 leveldetect1;
+        u32 risingdetect;
+        u32 fallingdetect;
+        u32 dataout;
+        u32 setwkuena;
+        u32 setdataout;
+};
+
+static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
 static struct gpio_bank gpio_bank_44xx[6] = {
-        { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,       \
+        { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
                 METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,  \
+        { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
                 METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,  \
+        { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
                 METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,  \
+        { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
                 METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
+        { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
                 METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
+        { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
                 METHOD_GPIO_24XX },
 };
 
@@ -402,14 +420,9 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
                 reg += OMAP1610_GPIO_DIRECTION;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DIR_CONTROL;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DIR_CONTROL;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_DIR_CONTROL;
                 break;
 #endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -469,19 +482,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                 l = 1 << gpio;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DATA_OUTPUT;
-                l = __raw_readl(reg);
-                if (enable)
-                        l |= 1 << gpio;
-                else
-                        l &= ~(1 << gpio);
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DATA_OUTPUT;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_DATA_OUTPUT;
                 l = __raw_readl(reg);
                 if (enable)
                         l |= 1 << gpio;
@@ -537,14 +540,9 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
                 reg += OMAP1610_GPIO_DATAIN;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DATA_INPUT;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DATA_INPUT;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_DATA_INPUT;
                 break;
 #endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -588,14 +586,9 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
                 reg += OMAP1610_GPIO_DATAOUT;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DATA_OUTPUT;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DATA_OUTPUT;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_DATA_OUTPUT;
                 break;
 #endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
@@ -636,6 +629,10 @@ void omap_set_gpio_debounce(int gpio, int enable)
 #else
         reg += OMAP24XX_GPIO_DEBOUNCE_EN;
 #endif
+        if (!(bank->mod_usage & l)) {
+                printk(KERN_ERR "GPIO %d not requested\n", gpio);
+                return;
+        }
 
         spin_lock_irqsave(&bank->lock, flags);
         val = __raw_readl(reg);
@@ -671,6 +668,11 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
         bank = get_gpio_bank(gpio);
         reg = bank->base;
 
+        if (!bank->mod_usage) {
+                printk(KERN_ERR "GPIO not requested\n");
+                return;
+        }
+
         enc_time &= 0xff;
 #ifdef CONFIG_ARCH_OMAP4
         reg += OMAP4_GPIO_DEBOUNCINGTIME;
@@ -797,21 +799,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
                         __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_INT_CONTROL;
-                l = __raw_readl(reg);
-                if (trigger & IRQ_TYPE_EDGE_RISING)
-                        l |= 1 << gpio;
-                else if (trigger & IRQ_TYPE_EDGE_FALLING)
-                        l &= ~(1 << gpio);
-                else
-                        goto bad;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_INT_CONTROL;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_CONTROL;
                 l = __raw_readl(reg);
                 if (trigger & IRQ_TYPE_EDGE_RISING)
                         l |= 1 << gpio;
@@ -897,14 +887,9 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
                 reg += OMAP1610_GPIO_IRQSTATUS1;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_INT_STATUS;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_INT_STATUS;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_STATUS;
                 break;
 #endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -971,16 +956,9 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
                 mask = 0xffff;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_INT_MASK;
-                mask = 0xffffffff;
-                inv = 1;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_INT_MASK;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_MASK;
                 mask = 0xffffffff;
                 inv = 1;
                 break;
@@ -1044,19 +1022,9 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                 l = gpio_mask;
                 break;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_INT_MASK;
-                l = __raw_readl(reg);
-                if (enable)
-                        l &= ~(gpio_mask);
-                else
-                        l |= gpio_mask;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_INT_MASK;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_MASK;
                 l = __raw_readl(reg);
                 if (enable)
                         l &= ~(gpio_mask);
@@ -1186,6 +1154,16 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
                 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
         }
 #endif
+        if (!cpu_class_is_omap1()) {
+                if (!bank->mod_usage) {
+                        u32 ctrl;
+                        ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+                        ctrl &= 0xFFFFFFFE;
+                        /* Module is enabled, clocks are not gated */
+                        __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
+                }
+                bank->mod_usage |= 1 << offset;
+        }
         spin_unlock_irqrestore(&bank->lock, flags);
 
         return 0;
@@ -1212,6 +1190,16 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
                 __raw_writel(1 << offset, reg);
         }
 #endif
+        if (!cpu_class_is_omap1()) {
+                bank->mod_usage &= ~(1 << offset);
+                if (!bank->mod_usage) {
+                        u32 ctrl;
+                        ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+                        /* Module is disabled, clocks are gated */
+                        ctrl |= 1;
+                        __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
+                }
+        }
         _reset_gpio(bank, bank->chip.base + offset);
         spin_unlock_irqrestore(&bank->lock, flags);
 }
@@ -1249,13 +1237,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         if (bank->method == METHOD_GPIO_1610)
                 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        if (bank->method == METHOD_GPIO_730)
-                isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        if (bank->method == METHOD_GPIO_850)
-                isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        if (bank->method == METHOD_GPIO_7XX)
+                isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
 #endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         if (bank->method == METHOD_GPIO_24XX)
@@ -1524,11 +1508,8 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
         case METHOD_GPIO_1610:
                 reg += OMAP1610_GPIO_DIRECTION;
                 break;
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DIR_CONTROL;
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_DIR_CONTROL;
                 break;
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_OE;
@@ -1607,6 +1588,23 @@ static struct clk * gpio5_fck;
 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
 #endif
 
+static void __init omap_gpio_show_rev(void)
+{
+        u32 rev;
+
+        if (cpu_is_omap16xx())
+                rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
+        else if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+        else if (cpu_is_omap44xx())
+                rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
+        else
+                return;
+
+        printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
+                (rev >> 4) & 0x0f, rev & 0x0f);
+}
+
 /* This lock class tells lockdep that GPIO irqs are in a different
  * category than their parents, so it won't report false recursion.
  */
@@ -1617,6 +1615,7 @@ static int __init _omap_gpio_init(void)
         int i;
         int gpio = 0;
         struct gpio_bank *bank;
+        int bank_size = SZ_8K;  /* Module 4KB + L4 4KB except on omap1 */
         char clk_name[11];
 
         initialized = 1;
@@ -1679,77 +1678,45 @@ static int __init _omap_gpio_init(void)
 
 #ifdef CONFIG_ARCH_OMAP15XX
         if (cpu_is_omap15xx()) {
-                printk(KERN_INFO "OMAP1510 GPIO hardware\n");
                 gpio_bank_count = 2;
                 gpio_bank = gpio_bank_1510;
+                bank_size = SZ_2K;
         }
 #endif
 #if defined(CONFIG_ARCH_OMAP16XX)
         if (cpu_is_omap16xx()) {
-                u32 rev;
-
                 gpio_bank_count = 5;
                 gpio_bank = gpio_bank_1610;
-                rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
-                printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
-                       (rev >> 4) & 0x0f, rev & 0x0f);
+                bank_size = SZ_2K;
         }
 #endif
-#ifdef CONFIG_ARCH_OMAP730
-        if (cpu_is_omap730()) {
-                printk(KERN_INFO "OMAP730 GPIO hardware\n");
-                gpio_bank_count = 7;
-                gpio_bank = gpio_bank_730;
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-        if (cpu_is_omap850()) {
-                printk(KERN_INFO "OMAP850 GPIO hardware\n");
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        if (cpu_is_omap7xx()) {
                 gpio_bank_count = 7;
-                gpio_bank = gpio_bank_850;
+                gpio_bank = gpio_bank_7xx;
+                bank_size = SZ_2K;
         }
 #endif
-
 #ifdef CONFIG_ARCH_OMAP24XX
         if (cpu_is_omap242x()) {
-                int rev;
-
                 gpio_bank_count = 4;
                 gpio_bank = gpio_bank_242x;
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
-                printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
-                        (rev >> 4) & 0x0f, rev & 0x0f);
         }
         if (cpu_is_omap243x()) {
-                int rev;
-
                 gpio_bank_count = 5;
                 gpio_bank = gpio_bank_243x;
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
-                printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
-                        (rev >> 4) & 0x0f, rev & 0x0f);
         }
 #endif
 #ifdef CONFIG_ARCH_OMAP34XX
         if (cpu_is_omap34xx()) {
-                int rev;
-
                 gpio_bank_count = OMAP34XX_NR_GPIOS;
                 gpio_bank = gpio_bank_34xx;
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
-                printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
-                        (rev >> 4) & 0x0f, rev & 0x0f);
         }
 #endif
 #ifdef CONFIG_ARCH_OMAP4
         if (cpu_is_omap44xx()) {
-                int rev;
-
                 gpio_bank_count = OMAP34XX_NR_GPIOS;
                 gpio_bank = gpio_bank_44xx;
-                rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
-                printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
-                        (rev >> 4) & 0x0f, rev & 0x0f);
         }
 #endif
         for (i = 0; i < gpio_bank_count; i++) {
@@ -1757,6 +1724,14 @@ static int __init _omap_gpio_init(void)
 
                 bank = &gpio_bank[i];
                 spin_lock_init(&bank->lock);
+
+                /* Static mapping, never released */
+                bank->base = ioremap(bank->pbase, bank_size);
+                if (!bank->base) {
+                        printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
+                        continue;
+                }
+
                 if (bank_is_mpuio(bank))
                         __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
                 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
@@ -1768,11 +1743,11 @@ static int __init _omap_gpio_init(void)
                         __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
                         __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
                 }
-                if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
-                        __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
-                        __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
+                if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
+                        __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
+                        __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
 
-                        gpio_count = 32; /* 730 has 32-bit GPIOs */
+                        gpio_count = 32; /* 7xx has 32-bit GPIOs */
                 }
 
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
@@ -1804,6 +1779,8 @@ static int __init _omap_gpio_init(void)
                         gpio_count = 32;
                 }
 #endif
+
+                bank->mod_usage = 0;
                 /* REVISIT eventually switch from OMAP-specific gpio structs
                  * over to the generic ones
                  */
@@ -1862,6 +1839,8 @@ static int __init _omap_gpio_init(void)
         if (cpu_is_omap34xx())
                 omap_writel(1 << 0, 0x48306814);
 
+        omap_gpio_show_rev();
+
         return 0;
 }
 
@@ -2106,6 +2085,81 @@ void omap2_gpio_resume_after_retention(void)
 
 #endif
 
+#ifdef CONFIG_ARCH_OMAP34XX
+/* save the registers of bank 2-6 */
+void omap_gpio_save_context(void)
+{
+        int i;
+
+        /* saving banks from 2-6 only since GPIO1 is in WKUP */
+        for (i = 1; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                gpio_context[i].sysconfig =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
+                gpio_context[i].irqenable1 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
+                gpio_context[i].irqenable2 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
+                gpio_context[i].wake_en =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
+                gpio_context[i].ctrl =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+                gpio_context[i].oe =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_OE);
+                gpio_context[i].leveldetect0 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+                gpio_context[i].leveldetect1 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+                gpio_context[i].risingdetect =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
+                gpio_context[i].fallingdetect =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+                gpio_context[i].dataout =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
+                gpio_context[i].setwkuena =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
+                gpio_context[i].setdataout =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
+        }
+}
+
+/* restore the required registers of bank 2-6 */
+void omap_gpio_restore_context(void)
+{
+        int i;
+
+        for (i = 1; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                __raw_writel(gpio_context[i].sysconfig,
+                                bank->base + OMAP24XX_GPIO_SYSCONFIG);
+                __raw_writel(gpio_context[i].irqenable1,
+                                bank->base + OMAP24XX_GPIO_IRQENABLE1);
+                __raw_writel(gpio_context[i].irqenable2,
+                                bank->base + OMAP24XX_GPIO_IRQENABLE2);
+                __raw_writel(gpio_context[i].wake_en,
+                                bank->base + OMAP24XX_GPIO_WAKE_EN);
+                __raw_writel(gpio_context[i].ctrl,
+                                bank->base + OMAP24XX_GPIO_CTRL);
+                __raw_writel(gpio_context[i].oe,
+                                bank->base + OMAP24XX_GPIO_OE);
+                __raw_writel(gpio_context[i].leveldetect0,
+                                bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+                __raw_writel(gpio_context[i].leveldetect1,
+                                bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+                __raw_writel(gpio_context[i].risingdetect,
+                                bank->base + OMAP24XX_GPIO_RISINGDETECT);
+                __raw_writel(gpio_context[i].fallingdetect,
+                                bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+                __raw_writel(gpio_context[i].dataout,
+                                bank->base + OMAP24XX_GPIO_DATAOUT);
+                __raw_writel(gpio_context[i].setwkuena,
+                                bank->base + OMAP24XX_GPIO_SETWKUENA);
+                __raw_writel(gpio_context[i].setdataout,
+                                bank->base + OMAP24XX_GPIO_SETDATAOUT);
+        }
+}
+#endif
+
 /*
  * This may get called early from board specific init
  * for boards that have interrupts routed via FPGA.
@@ -2160,8 +2214,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
 
                 if (bank_is_mpuio(bank))
                         gpio = OMAP_MPUIO(0);
-                else if (cpu_class_is_omap2() || cpu_is_omap730() ||
-                                cpu_is_omap850())
+                else if (cpu_class_is_omap2() || cpu_is_omap7xx())
                         bankwidth = 32;
 
                 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 8b848391f0c8..c08362dbb8ed 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -27,7 +27,7 @@
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <mach/irqs.h>
-#include <mach/mux.h>
+#include <plat/mux.h>
 
 #define OMAP_I2C_SIZE           0x3f
 #define OMAP1_I2C_BASE          0xfffb3800
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
deleted file mode 100644
index ac24050e3416..000000000000
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/* arch/arm/plat-omap/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-#ifdef CONFIG_ARCH_OMAP1
-                moveq   \rx, #0xff000000        @ physical base address
-                movne   \rx, #0xfe000000        @ virtual base
-                orr     \rx, \rx, #0x00fb0000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                orr     \rx, \rx, #0x00009000   @ UART 3
-#endif
-#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
-                orr     \rx, \rx, #0x00000800   @ UART 2 & 3
-#endif
-
-#elif  CONFIG_ARCH_OMAP2
-                moveq   \rx, #0x48000000        @ physical base address
-                movne   \rx, #0xd8000000        @ virtual base
-                orr     \rx, \rx, #0x0006a000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART2
-                add     \rx, \rx, #0x00002000   @ UART 2
-#endif
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                add     \rx, \rx, #0x00004000   @ UART 3
-#endif
-
-#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-                moveq   \rx, #0x48000000        @ physical base address
-                movne   \rx, #0xd8000000        @ virtual base
-                orr     \rx, \rx, #0x0006a000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART2
-                add     \rx, \rx, #0x00002000   @ UART 2
-#endif
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                add     \rx, \rx, #0x00fb0000   @ UART 3
-                add     \rx, \rx, #0x00006000
-#endif
-#endif
-                .endm
-
-                .macro  senduart,rd,rx
-                strb    \rd, [\rx]
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldrb    \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
-                and     \rd, \rd, #0x60
-                teq     \rd, #0x60
-                beq     1002f
-                ldrb    \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
-                and     \rd, \rd, #0x60
-                teq     \rd, #0x60
-                bne     1001b
-1002:
-                .endm
-
-                .macro  waituart,rd,rx
-                .endm
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
deleted file mode 100644
index a5592991634d..000000000000
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for OMAP-based platforms
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-#include <asm/hardware/gic.h>
-
-#if defined(CONFIG_ARCH_OMAP1)
-
-#if defined(CONFIG_ARCH_OMAP730) && \
-        (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
-#error "FIXME: OMAP730 doesn't support multiple-OMAP"
-#elif defined(CONFIG_ARCH_OMAP730)
-#define INT_IH2_IRQ             INT_730_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP15XX)
-#define INT_IH2_IRQ             INT_1510_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#define INT_IH2_IRQ             INT_1610_IH2_IRQ
-#else
-#warning "IH2 IRQ defaulted"
-#define INT_IH2_IRQ             INT_1510_IH2_IRQ
-#endif
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
-                ldr     \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
-                ldr     \tmp, [\base, #IRQ_MIR_REG_OFFSET]
-                mov     \irqstat, #0xffffffff
-                bic     \tmp, \irqstat, \tmp
-                tst     \irqnr, \tmp
-                beq     1510f
-
-                ldr     \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
-                cmp     \irqnr, #0
-                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-                cmpeq   \irqnr, #INT_IH2_IRQ
-                ldreq   \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
-                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-                addeqs  \irqnr, \irqnr, #32
-1510:
-                .endm
-
-#endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
-
-#include <mach/omap24xx.h>
-#include <mach/omap34xx.h>
-
-/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
-#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
-#define OMAP2_VA_IC_BASE                OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
-#elif defined(CONFIG_ARCH_OMAP34XX)
-#define OMAP2_VA_IC_BASE                OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-#include <mach/omap44xx.h>
-#endif
-#define INTCPS_SIR_IRQ_OFFSET   0x0040          /* Active interrupt offset */
-#define ACTIVEIRQ_MASK          0x7f            /* Active interrupt bits */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-#ifndef CONFIG_ARCH_OMAP4
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =OMAP2_VA_IC_BASE
-                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-                cmp     \irqnr, #0x0
-                bne     2222f
-                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-                cmp     \irqnr, #0x0
-                bne     2222f
-                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-                cmp     \irqnr, #0x0
-2222:
-                ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-                and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-
-                .endm
-#else
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an
-                 * interrupt if it's between 30 and 1020.  The test_for_ipi
-                 * routine below will pick up on IPIs.
-                 * A simple read from the controller will tell us the number
-                 * of the highest priority enabled interrupt.
-                 * We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =OMAP44XX_VA_GIC_CPU_BASE
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-
-                ldr     \tmp, =1021
-
-                bic     \irqnr, \irqstat, #0x1c00
-
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt
-                 * on the controller, since this requires the original irqstat
-                 * value which we won't easily be able to recreate later.
-                 */
-
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                it      cc
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                it      cs
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* As above, this assumes that irqstat and base are preserved */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                itt     eq
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
-#endif
-
-                .macro  irq_prio_table
-                .endm
-
-#endif
diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/plat-omap/include/mach/mtd-xip.h
deleted file mode 100644
index f82a8dcaad94..000000000000
--- a/arch/arm/plat-omap/include/mach/mtd-xip.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * MTD primitives for XIP support. Architecture specific functions.
- *
- * Do not include this file directly. It's included from linux/mtd/xip.h
- *
- * Author: Vladimir Barinov <vbarinov@embeddedalley.com>
- *
- * (c) 2005 MontaVista Software, Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2.  This program is
- * licensed "as is" without any warranty of any kind, whether express or
- * implied.
- */
-
-#ifndef __ARCH_OMAP_MTD_XIP_H__
-#define __ARCH_OMAP_MTD_XIP_H__
-
-#include <mach/hardware.h>
-#define OMAP_MPU_TIMER_BASE     (0xfffec500)
-#define OMAP_MPU_TIMER_OFFSET   0x100
-
-typedef struct {
-        u32 cntl;                       /* CNTL_TIMER, R/W */
-        u32 load_tim;                   /* LOAD_TIM,   W */
-        u32 read_tim;                   /* READ_TIM,   R */
-} xip_omap_mpu_timer_regs_t;
-
-#define xip_omap_mpu_timer_base(n)                                      \
-((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +    \
-        (n)*OMAP_MPU_TIMER_OFFSET))
-
-static inline unsigned long xip_omap_mpu_timer_read(int nr)
-{
-        volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr);
-        return timer->read_tim;
-}
-
-#define xip_irqpending()        \
-        (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR))
-#define xip_currtime()          (~xip_omap_mpu_timer_read(0))
-
-/*
- * It's permitted to do approxmation for xip_elapsed_since macro
- * (see linux/mtd/xip.h)
- */
-
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7)
-#else
-#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
-#endif
-
-/*
- * xip_cpu_idle() is used when waiting for a delay equal or larger than
- * the system timer tick period.  This should put the CPU into idle mode
- * to save power and to be woken up only when some interrupts are pending.
- * As above, this should not rely upon standard kernel code.
- */
-
-#define xip_cpu_idle()  asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
-
-#endif /* __ARCH_OMAP_MTD_XIP_H__ */
diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h
deleted file mode 100644
index b97dfafeebda..000000000000
--- a/arch/arm/plat-omap/include/mach/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x18000000)
-
diff --git a/arch/arm/plat-omap/include/mach/blizzard.h b/arch/arm/plat-omap/include/plat/blizzard.h
index 8d160f171372..8d160f171372 100644
--- a/arch/arm/plat-omap/include/mach/blizzard.h
+++ b/arch/arm/plat-omap/include/plat/blizzard.h
diff --git a/arch/arm/plat-omap/include/mach/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
index 51b102dc906b..51b102dc906b 100644
--- a/arch/arm/plat-omap/include/mach/board-ams-delta.h
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
diff --git a/arch/arm/plat-omap/include/mach/board-sx1.h b/arch/arm/plat-omap/include/plat/board-sx1.h
index 355adbdaae33..355adbdaae33 100644
--- a/arch/arm/plat-omap/include/mach/board-sx1.h
+++ b/arch/arm/plat-omap/include/plat/board-sx1.h
diff --git a/arch/arm/plat-omap/include/mach/board-voiceblue.h b/arch/arm/plat-omap/include/plat/board-voiceblue.h
index 27916b210f57..27916b210f57 100644
--- a/arch/arm/plat-omap/include/mach/board-voiceblue.h
+++ b/arch/arm/plat-omap/include/plat/board-voiceblue.h
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/plat/board.h
index 8e913c322810..abb17b604f82 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -12,7 +12,19 @@
 
 #include <linux/types.h>
 
-#include <mach/gpio-switch.h>
+#include <plat/gpio-switch.h>
+
+/*
+ * OMAP35x EVM revision
+ * Run time detection of EVM revision is done by reading Ethernet
+ * PHY ID -
+ *      GEN_1   = 0x01150000
+ *      GEN_2   = 0x92200000
+ */
+enum {
+        OMAP3EVM_BOARD_GEN_1 = 0,       /* EVM Rev between  A - D */
+        OMAP3EVM_BOARD_GEN_2,           /* EVM Rev >= Rev E */
+};
 
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK          0x4f01
@@ -157,4 +169,10 @@ extern int omap_board_config_size;
 /* for TI reference platforms sharing the same debug card */
 extern int debug_card_init(u32 addr, unsigned gpio);
 
+/* OMAP3EVM revision */
+#if defined(CONFIG_MACH_OMAP3EVM)
+u8 get_omap3_evm_rev(void);
+#else
+#define get_omap3_evm_rev() (-EINVAL)
+#endif
 #endif
diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/plat/clkdev.h
index 730c49d1ebd8..730c49d1ebd8 100644
--- a/arch/arm/plat-omap/include/mach/clkdev.h
+++ b/arch/arm/plat-omap/include/plat/clkdev.h
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 4b8b0d65cbf2..4b8b0d65cbf2 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h
index 99ebd886f134..eb734826e64e 100644
--- a/arch/arm/plat-omap/include/mach/clockdomain.h
+++ b/arch/arm/plat-omap/include/plat/clockdomain.h
@@ -16,9 +16,9 @@
 #ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
 #define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
 
-#include <mach/powerdomain.h>
-#include <mach/clock.h>
-#include <mach/cpu.h>
+#include <plat/powerdomain.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
 
 /* Clockdomain capability flags */
 #define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/plat/common.h
index fdeab421b4dc..064f1730f43b 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -31,6 +31,9 @@
 
 struct sys_timer;
 
+/* used by omap-smp.c and board-4430sdp.c */
+extern void __iomem *gic_cpu_base_addr;
+
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
 #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/plat/control.h
index 826d317cdbec..2ae884378638 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -20,15 +20,18 @@
 
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
-        OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
 #define OMAP243X_CTRL_REGADDR(reg)                                      \
-        OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                      \
-        OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
 #else
-#define OMAP242X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
-#define OMAP343X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define OMAP242X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -109,6 +112,8 @@
 #define OMAP24XX_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e0)
 #define OMAP24XX_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00e4)
 
+#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
+
 /* 34xx-only CONTROL_GENERAL register offsets */
 #define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
 #define OMAP343X_CONTROL_MEM_DFTRW0     (OMAP2_CONTROL_GENERAL + 0x0008)
@@ -141,8 +146,51 @@
 #define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
 #define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
-#define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02b0)
-#define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02b4)
+#define OMAP343X_CONTROL_DEBOBS(i)      (OMAP2_CONTROL_GENERAL + 0x01B0 \
+                                        + ((i) >> 1) * 4 + (!(i) & 1) * 2)
+#define OMAP343X_CONTROL_PROG_IO0       (OMAP2_CONTROL_GENERAL + 0x01D4)
+#define OMAP343X_CONTROL_PROG_IO1       (OMAP2_CONTROL_GENERAL + 0x01D8)
+#define OMAP343X_CONTROL_DSS_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E0)
+#define OMAP343X_CONTROL_CORE_DPLL_SPREADING    (OMAP2_CONTROL_GENERAL + 0x01E4)
+#define OMAP343X_CONTROL_PER_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E8)
+#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
+#define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02B0)
+#define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02B4)
+#define OMAP343X_CONTROL_SRAMLDO4       (OMAP2_CONTROL_GENERAL + 0x02B8)
+#define OMAP343X_CONTROL_SRAMLDO5       (OMAP2_CONTROL_GENERAL + 0x02C0)
+#define OMAP343X_CONTROL_CSI            (OMAP2_CONTROL_GENERAL + 0x02C4)
+
+
+/* 34xx PADCONF register offsets */
+#define OMAP343X_PADCONF_ETK(i)         (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
+                                                (i)*2)
+#define OMAP343X_PADCONF_ETK_CLK        OMAP343X_PADCONF_ETK(0)
+#define OMAP343X_PADCONF_ETK_CTL        OMAP343X_PADCONF_ETK(1)
+#define OMAP343X_PADCONF_ETK_D0         OMAP343X_PADCONF_ETK(2)
+#define OMAP343X_PADCONF_ETK_D1         OMAP343X_PADCONF_ETK(3)
+#define OMAP343X_PADCONF_ETK_D2         OMAP343X_PADCONF_ETK(4)
+#define OMAP343X_PADCONF_ETK_D3         OMAP343X_PADCONF_ETK(5)
+#define OMAP343X_PADCONF_ETK_D4         OMAP343X_PADCONF_ETK(6)
+#define OMAP343X_PADCONF_ETK_D5         OMAP343X_PADCONF_ETK(7)
+#define OMAP343X_PADCONF_ETK_D6         OMAP343X_PADCONF_ETK(8)
+#define OMAP343X_PADCONF_ETK_D7         OMAP343X_PADCONF_ETK(9)
+#define OMAP343X_PADCONF_ETK_D8         OMAP343X_PADCONF_ETK(10)
+#define OMAP343X_PADCONF_ETK_D9         OMAP343X_PADCONF_ETK(11)
+#define OMAP343X_PADCONF_ETK_D10        OMAP343X_PADCONF_ETK(12)
+#define OMAP343X_PADCONF_ETK_D11        OMAP343X_PADCONF_ETK(13)
+#define OMAP343X_PADCONF_ETK_D12        OMAP343X_PADCONF_ETK(14)
+#define OMAP343X_PADCONF_ETK_D13        OMAP343X_PADCONF_ETK(15)
+#define OMAP343X_PADCONF_ETK_D14        OMAP343X_PADCONF_ETK(16)
+#define OMAP343X_PADCONF_ETK_D15        OMAP343X_PADCONF_ETK(17)
+
+/* 34xx GENERAL_WKUP regist offsets */
+#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
+                                                0x008 + (i))
+#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
+#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
+#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
+#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
+#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
 
 /* 34xx D2D idle-related pins, handled by PM core */
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
@@ -193,6 +241,9 @@
 #define OMAP2_PBIASLITEPWRDNZ0          (1 << 1)
 #define OMAP2_PBIASLITEVMODE0           (1 << 0)
 
+/* CONTROL_PROG_IO1 bits */
+#define OMAP3630_PRG_SDMMC1_SPEEDCTRL   (1 << 20)
+
 /* CONTROL_IVA2_BOOTMOD bits */
 #define OMAP3_IVA2_BOOTMOD_SHIFT        0
 #define OMAP3_IVA2_BOOTMOD_MASK         (0xf << 0)
@@ -202,6 +253,44 @@
 #define OMAP3_PADCONF_WAKEUPEVENT0      (1 << 15)
 #define OMAP3_PADCONF_WAKEUPENABLE0     (1 << 14)
 
+#define OMAP343X_SCRATCHPAD_ROM         (OMAP343X_CTRL_BASE + 0x860)
+#define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
+#define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
+
+/*
+ * CONTROL OMAP STATUS register to identify OMAP3 features
+ */
+#define OMAP3_CONTROL_OMAP_STATUS       0x044c
+
+#define OMAP3_SGX_SHIFT                 13
+#define OMAP3_SGX_MASK                  (3 << OMAP3_SGX_SHIFT)
+#define         FEAT_SGX_FULL           0
+#define         FEAT_SGX_HALF           1
+#define         FEAT_SGX_NONE           2
+
+#define OMAP3_IVA_SHIFT                 12
+#define OMAP3_IVA_MASK                  (1 << OMAP3_SGX_SHIFT)
+#define         FEAT_IVA                0
+#define         FEAT_IVA_NONE           1
+
+#define OMAP3_L2CACHE_SHIFT             10
+#define OMAP3_L2CACHE_MASK              (3 << OMAP3_L2CACHE_SHIFT)
+#define         FEAT_L2CACHE_NONE       0
+#define         FEAT_L2CACHE_64KB       1
+#define         FEAT_L2CACHE_128KB      2
+#define         FEAT_L2CACHE_256KB      3
+
+#define OMAP3_ISP_SHIFT                 5
+#define OMAP3_ISP_MASK                  (1<< OMAP3_ISP_SHIFT)
+#define         FEAT_ISP                0
+#define         FEAT_ISP_NONE           1
+
+#define OMAP3_NEON_SHIFT                4
+#define OMAP3_NEON_MASK                 (1<< OMAP3_NEON_SHIFT)
+#define         FEAT_NEON               0
+#define         FEAT_NEON_NONE          1
+
+
 #ifndef __ASSEMBLY__
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
                 defined(CONFIG_ARCH_OMAP4)
@@ -212,6 +301,15 @@ extern u32 omap_ctrl_readl(u16 offset);
 extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
+
+extern void omap3_save_scratchpad_contents(void);
+extern void omap3_clear_scratchpad_contents(void);
+extern u32 *get_restore_pointer(void);
+extern u32 *get_es3_restore_pointer(void);
+extern u32 omap3_arm_context[128];
+extern void omap3_control_save_context(void);
+extern void omap3_control_restore_context(void);
+
 #else
 #define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index f129efb3075e..2e1789001dfe 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -30,6 +30,8 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
 
+#include <linux/bitops.h>
+
 /*
  * Omap device type i.e. EMU/HS/TST/GP/BAD
  */
@@ -57,6 +59,23 @@ struct omap_chip_id {
 unsigned int omap_rev(void);
 
 /*
+ * Define CPU revision bits
+ *
+ * Verbose meaning of the revision bits may be different for a silicon
+ * family. This difference can be handled separately.
+ */
+#define OMAP_REVBITS_00         0x00
+#define OMAP_REVBITS_10         0x10
+#define OMAP_REVBITS_20         0x20
+#define OMAP_REVBITS_30         0x30
+#define OMAP_REVBITS_40         0x40
+
+/*
+ * Get the CPU revision for OMAP devices
+ */
+#define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
+
+/*
  * Test if multicore OMAP support is needed
  */
 #undef MULTI_OMAP1
@@ -161,6 +180,7 @@ IS_OMAP_CLASS(34xx, 0x34)
 IS_OMAP_SUBCLASS(242x, 0x242)
 IS_OMAP_SUBCLASS(243x, 0x243)
 IS_OMAP_SUBCLASS(343x, 0x343)
+IS_OMAP_SUBCLASS(363x, 0x363)
 
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
@@ -264,6 +284,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
  * cpu_is_omap2423():   True for OMAP2423
  * cpu_is_omap2430():   True for OMAP2430
  * cpu_is_omap3430():   True for OMAP3430
+ * cpu_is_omap3505():   True for OMAP3505
+ * cpu_is_omap3517():   True for OMAP3517
  */
 #define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
 
@@ -287,6 +309,8 @@ IS_OMAP_TYPE(2422, 0x2422)
 IS_OMAP_TYPE(2423, 0x2423)
 IS_OMAP_TYPE(2430, 0x2430)
 IS_OMAP_TYPE(3430, 0x3430)
+IS_OMAP_TYPE(3505, 0x3505)
+IS_OMAP_TYPE(3517, 0x3517)
 
 #define cpu_is_omap310()                0
 #define cpu_is_omap730()                0
@@ -301,7 +325,14 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_is_omap2422()               0
 #define cpu_is_omap2423()               0
 #define cpu_is_omap2430()               0
+#define cpu_is_omap3503()               0
+#define cpu_is_omap3515()               0
+#define cpu_is_omap3525()               0
+#define cpu_is_omap3530()               0
+#define cpu_is_omap3505()               0
+#define cpu_is_omap3517()               0
 #define cpu_is_omap3430()               0
+#define cpu_is_omap3630()               0
 
 /*
  * Whether we have MULTI_OMAP1 or not, we still need to distinguish
@@ -351,7 +382,27 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 #if defined(CONFIG_ARCH_OMAP34XX)
 # undef cpu_is_omap3430
+# undef cpu_is_omap3503
+# undef cpu_is_omap3515
+# undef cpu_is_omap3525
+# undef cpu_is_omap3530
+# undef cpu_is_omap3505
+# undef cpu_is_omap3517
 # define cpu_is_omap3430()              is_omap3430()
+# define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
+                                                (!omap3_has_iva()) &&   \
+                                                (!omap3_has_sgx()))
+# define cpu_is_omap3515()              (cpu_is_omap3430() &&           \
+                                                (omap3_has_iva()) &&    \
+                                                (!omap3_has_sgx()))
+# define cpu_is_omap3525()              (cpu_is_omap3430() &&           \
+                                                (omap3_has_sgx()) &&    \
+                                                (!omap3_has_iva()))
+# define cpu_is_omap3530()              (cpu_is_omap3430())
+# define cpu_is_omap3505()              is_omap3505()
+# define cpu_is_omap3517()              is_omap3517()
+# undef cpu_is_omap3630
+# define cpu_is_omap3630()              is_omap363x()
 #endif
 
 # if defined(CONFIG_ARCH_OMAP4)
@@ -382,6 +433,16 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP3430_REV_ES3_0      0x34303034
 #define OMAP3430_REV_ES3_1      0x34304034
 
+#define OMAP3630_REV_ES1_0      0x36300034
+
+#define OMAP35XX_CLASS          0x35000034
+#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12))
+#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12))
+#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12))
+#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12))
+#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 12))
+#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 12))
+
 #define OMAP443X_CLASS          0x44300034
 
 /*
@@ -405,6 +466,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define CHIP_IS_OMAP3430ES2             (1 << 4)
 #define CHIP_IS_OMAP3430ES3_0           (1 << 5)
 #define CHIP_IS_OMAP3430ES3_1           (1 << 6)
+#define CHIP_IS_OMAP3630ES1             (1 << 7)
 
 #define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
@@ -416,11 +478,36 @@ IS_OMAP_TYPE(3430, 0x3430)
  */
 #define CHIP_GE_OMAP3430ES2             (CHIP_IS_OMAP3430ES2 | \
                                          CHIP_IS_OMAP3430ES3_0 | \
-                                         CHIP_IS_OMAP3430ES3_1)
-#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1)
+                                         CHIP_IS_OMAP3430ES3_1 | \
+                                         CHIP_IS_OMAP3630ES1)
+#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1 | \
+                                         CHIP_IS_OMAP3630ES1)
 
 
 int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
 
+/*
+ * Runtime detection of OMAP3 features
+ */
+extern u32 omap3_features;
+
+#define OMAP3_HAS_L2CACHE               BIT(0)
+#define OMAP3_HAS_IVA                   BIT(1)
+#define OMAP3_HAS_SGX                   BIT(2)
+#define OMAP3_HAS_NEON                  BIT(3)
+#define OMAP3_HAS_ISP                   BIT(4)
+
+#define OMAP3_HAS_FEATURE(feat,flag)                    \
+static inline unsigned int omap3_has_ ##feat(void)      \
+{                                                       \
+        return (omap3_features & OMAP3_HAS_ ##flag);    \
+}                                                       \
+
+OMAP3_HAS_FEATURE(l2cache, L2CACHE)
+OMAP3_HAS_FEATURE(sgx, SGX)
+OMAP3_HAS_FEATURE(iva, IVA)
+OMAP3_HAS_FEATURE(neon, NEON)
+OMAP3_HAS_FEATURE(isp, ISP)
+
 #endif
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 72f680b7180d..1c017b29b7e9 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -633,6 +633,11 @@ extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
 extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
 extern int omap_get_dma_index(int lch, int *ei, int *fi);
 
+void omap_dma_global_context_save(void);
+void omap_dma_global_context_restore(void);
+
+extern void omap_dma_disable_irq(int lch);
+
 /* Chaining APIs */
 #ifndef CONFIG_ARCH_OMAP1
 extern int omap_request_dma_chain(int dev_id, const char *dev_name,
diff --git a/arch/arm/plat-omap/include/mach/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 20f1054c0a80..20f1054c0a80 100644
--- a/arch/arm/plat-omap/include/mach/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
diff --git a/arch/arm/plat-omap/include/mach/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h
index da97736f3efa..da97736f3efa 100644
--- a/arch/arm/plat-omap/include/mach/dsp_common.h
+++ b/arch/arm/plat-omap/include/plat/dsp_common.h
diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
index f1864a652f7a..f1864a652f7a 100644
--- a/arch/arm/plat-omap/include/mach/fpga.h
+++ b/arch/arm/plat-omap/include/plat/fpga.h
diff --git a/arch/arm/plat-omap/include/mach/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
index 10da0e07c0cf..10da0e07c0cf 100644
--- a/arch/arm/plat-omap/include/mach/gpio-switch.h
+++ b/arch/arm/plat-omap/include/plat/gpio-switch.h
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 633ff688b928..de7c54731cbe 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -76,7 +76,8 @@ extern void omap2_gpio_prepare_for_retention(void);
 extern void omap2_gpio_resume_after_retention(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
-
+extern void omap_gpio_save_context(void);
+extern void omap_gpio_restore_context(void);
 /*-------------------------------------------------------------------------*/
 
 /* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
index b64fbee4d567..b64fbee4d567 100644
--- a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
+++ b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 9c99cda77ba6..696e0ca051b7 100644
--- a/arch/arm/plat-omap/include/mach/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -52,6 +52,7 @@
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
+#define GPMC_CONFIG7_CSVALID            (1 << 6)
 
 /*
  * Note that all values in this struct are in nanoseconds, while
@@ -107,6 +108,8 @@ extern int gpmc_prefetch_enable(int cs, int dma_mode,
                                         unsigned int u32_count, int is_write);
 extern void gpmc_prefetch_reset(void);
 extern int gpmc_prefetch_status(void);
+extern void omap3_gpmc_save_context(void);
+extern void omap3_gpmc_restore_context(void);
 extern void __init gpmc_init(void);
 
 #endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index 26c1fbff08aa..d5b26adfb890 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -39,9 +39,9 @@
 #include <asm/sizes.h>
 #ifndef __ASSEMBLER__
 #include <asm/types.h>
-#include <mach/cpu.h>
+#include <plat/cpu.h>
 #endif
-#include <mach/serial.h>
+#include <plat/serial.h>
 
 /*
  * ---------------------------------------------------------------------------
@@ -280,11 +280,11 @@
  * ---------------------------------------------------------------------------
  */
 
-#include "omap730.h"
-#include "omap1510.h"
-#include "omap16xx.h"
-#include "omap24xx.h"
-#include "omap34xx.h"
-#include "omap44xx.h"
+#include <plat/omap7xx.h>
+#include <plat/omap1510.h>
+#include <plat/omap16xx.h>
+#include <plat/omap24xx.h>
+#include <plat/omap34xx.h>
+#include <plat/omap44xx.h>
 
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/plat/hwa742.h
index 886248d32b49..886248d32b49 100644
--- a/arch/arm/plat-omap/include/mach/hwa742.h
+++ b/arch/arm/plat-omap/include/plat/hwa742.h
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/plat/io.h
index 8d32df32b0b1..7e5319f907d1 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -63,8 +63,24 @@
 #define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
 #define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
 
-#define OMAP2_IO_OFFSET         0x90000000
-#define OMAP2_IO_ADDRESS(pa)    IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */
+#define OMAP2_L3_IO_OFFSET      0x90000000
+#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
+
+
+#define OMAP2_L4_IO_OFFSET      0xb2000000
+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
+
+#define OMAP4_L3_IO_OFFSET      0xb4000000
+#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
+
+#define OMAP4_L3_PER_IO_OFFSET  0xb1100000
+#define OMAP4_L3_PER_IO_ADDRESS(pa)     IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
+
+#define OMAP4_GPMC_IO_OFFSET            0xa9000000
+#define OMAP4_GPMC_IO_ADDRESS(pa)       IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
+
+#define OMAP2_EMU_IO_OFFSET             0xaa800000      /* Emulation */
+#define OMAP2_EMU_IO_ADDRESS(pa)        IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
 
 /*
  * ----------------------------------------------------------------------------
@@ -83,24 +99,27 @@
  */
 
 /* We map both L3 and L4 on OMAP2 */
-#define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 */
-#define L3_24XX_VIRT    0xf8000000
+#define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 --> 0xf8000000*/
+#define L3_24XX_VIRT    (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
 #define L3_24XX_SIZE    SZ_1M           /* 44kB of 128MB used, want 1MB sect */
-#define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 */
-#define L4_24XX_VIRT    0xd8000000
+#define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 --> 0xfa000000 */
+#define L4_24XX_VIRT    (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_24XX_SIZE    SZ_1M           /* 1MB of 128MB used, want 1MB sect */
 
-#define L4_WK_243X_PHYS         L4_WK_243X_BASE         /* 0x49000000 */
-#define L4_WK_243X_VIRT         0xd9000000
+#define L4_WK_243X_PHYS         L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
+#define L4_WK_243X_VIRT         (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_WK_243X_SIZE         SZ_1M
-#define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE      /* 0x49000000 */
-#define OMAP243X_GPMC_VIRT      0xFE000000
+#define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE
+#define OMAP243X_GPMC_VIRT      (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
+                                                /* 0x6e000000 --> 0xfe000000 */
 #define OMAP243X_GPMC_SIZE      SZ_1M
 #define OMAP243X_SDRC_PHYS      OMAP243X_SDRC_BASE
-#define OMAP243X_SDRC_VIRT      0xFD000000
+                                                /* 0x6D000000 --> 0xfd000000 */
+#define OMAP243X_SDRC_VIRT      (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP243X_SDRC_SIZE      SZ_1M
 #define OMAP243X_SMS_PHYS       OMAP243X_SMS_BASE
-#define OMAP243X_SMS_VIRT       0xFC000000
+                                                /* 0x6c000000 --> 0xfc000000 */
+#define OMAP243X_SMS_VIRT       (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP243X_SMS_SIZE       SZ_1M
 
 /* DSP */
@@ -121,12 +140,12 @@
  */
 
 /* We map both L3 and L4 on OMAP3 */
-#define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 */
-#define L3_34XX_VIRT            0xf8000000
+#define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 --> 0xf8000000 */
+#define L3_34XX_VIRT            (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
 #define L3_34XX_SIZE            SZ_1M   /* 44kB of 128MB used, want 1MB sect */
 
-#define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 */
-#define L4_34XX_VIRT            0xd8000000
+#define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 --> 0xfa000000 */
+#define L4_34XX_VIRT            (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 
 /*
@@ -134,28 +153,33 @@
  * VPOM3430 was not working for Int controller
  */
 
-#define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 */
-#define L4_WK_34XX_VIRT         0xd8300000
+#define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
+#define L4_WK_34XX_VIRT         (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_WK_34XX_SIZE         SZ_1M
 
-#define L4_PER_34XX_PHYS        L4_PER_34XX_BASE /* 0x49000000 */
-#define L4_PER_34XX_VIRT        0xd9000000
+#define L4_PER_34XX_PHYS        L4_PER_34XX_BASE
+                                                /* 0x49000000 --> 0xfb000000 */
+#define L4_PER_34XX_VIRT        (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_PER_34XX_SIZE        SZ_1M
 
-#define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE /* 0x54000000 */
-#define L4_EMU_34XX_VIRT        0xe4000000
-#define L4_EMU_34XX_SIZE        SZ_64M
+#define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE
+                                                /* 0x54000000 --> 0xfe800000 */
+#define L4_EMU_34XX_VIRT        (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
+#define L4_EMU_34XX_SIZE        SZ_8M
 
-#define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE /* 0x6E000000 */
-#define OMAP34XX_GPMC_VIRT      0xFE000000
+#define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE
+                                                /* 0x6e000000 --> 0xfe000000 */
+#define OMAP34XX_GPMC_VIRT      (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP34XX_GPMC_SIZE      SZ_1M
 
-#define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE /* 0x6C000000 */
-#define OMAP343X_SMS_VIRT       0xFC000000
+#define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE
+                                                /* 0x6c000000 --> 0xfc000000 */
+#define OMAP343X_SMS_VIRT       (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP343X_SMS_SIZE       SZ_1M
 
-#define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE /* 0x6D000000 */
-#define OMAP343X_SDRC_VIRT      0xFD000000
+#define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE
+                                                /* 0x6D000000 --> 0xfd000000 */
+#define OMAP343X_SDRC_VIRT      (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP343X_SDRC_SIZE      SZ_1M
 
 /* DSP */
@@ -176,32 +200,54 @@
  */
 
 /* We map both L3 and L4 on OMAP4 */
-#define L3_44XX_PHYS            L3_44XX_BASE
-#define L3_44XX_VIRT            0xd4000000
+#define L3_44XX_PHYS            L3_44XX_BASE    /* 0x44000000 --> 0xf8000000 */
+#define L3_44XX_VIRT            (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
 #define L3_44XX_SIZE            SZ_1M
 
-#define L4_44XX_PHYS            L4_44XX_BASE
-#define L4_44XX_VIRT            0xda000000
+#define L4_44XX_PHYS            L4_44XX_BASE    /* 0x4a000000 --> 0xfc000000 */
+#define L4_44XX_VIRT            (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_44XX_SIZE            SZ_4M
 
 
-#define L4_WK_44XX_PHYS         L4_WK_44XX_BASE
-#define L4_WK_44XX_VIRT         0xda300000
+#define L4_WK_44XX_PHYS         L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
+#define L4_WK_44XX_VIRT         (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_WK_44XX_SIZE         SZ_1M
 
 #define L4_PER_44XX_PHYS        L4_PER_44XX_BASE
-#define L4_PER_44XX_VIRT        0xd8000000
+                                                /* 0x48000000 --> 0xfa000000 */
+#define L4_PER_44XX_VIRT        (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_PER_44XX_SIZE        SZ_4M
 
+#define L4_ABE_44XX_PHYS        L4_ABE_44XX_BASE
+                                                /* 0x49000000 --> 0xfb000000 */
+#define L4_ABE_44XX_VIRT        (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_ABE_44XX_SIZE        SZ_1M
+
 #define L4_EMU_44XX_PHYS        L4_EMU_44XX_BASE
-#define L4_EMU_44XX_VIRT        0xe4000000
-#define L4_EMU_44XX_SIZE        SZ_64M
+                                                /* 0x54000000 --> 0xfe800000 */
+#define L4_EMU_44XX_VIRT        (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
+#define L4_EMU_44XX_SIZE        SZ_8M
 
 #define OMAP44XX_GPMC_PHYS      OMAP44XX_GPMC_BASE
-#define OMAP44XX_GPMC_VIRT      0xe0000000
+                                                /* 0x50000000 --> 0xf9000000 */
+#define OMAP44XX_GPMC_VIRT      (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
 #define OMAP44XX_GPMC_SIZE      SZ_1M
 
 
+#define OMAP44XX_EMIF1_PHYS     OMAP44XX_EMIF1_BASE
+                                                /* 0x4c000000 --> 0xfd100000 */
+#define OMAP44XX_EMIF1_VIRT     (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
+#define OMAP44XX_EMIF1_SIZE     SZ_1M
+
+#define OMAP44XX_EMIF2_PHYS     OMAP44XX_EMIF2_BASE
+                                                /* 0x4d000000 --> 0xfd200000 */
+#define OMAP44XX_EMIF2_VIRT     (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
+#define OMAP44XX_EMIF2_SIZE     SZ_1M
+
+#define OMAP44XX_DMM_PHYS       OMAP44XX_DMM_BASE
+                                                /* 0x4e000000 --> 0xfd300000 */
+#define OMAP44XX_DMM_VIRT       (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
+#define OMAP44XX_DMM_SIZE       SZ_1M
 /*
  * ----------------------------------------------------------------------------
  * Omap specific register access
diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 46d41ac83dbf..0752af9d099e 100644
--- a/arch/arm/plat-omap/include/mach/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -107,7 +107,7 @@ struct iommu_platform_data {
 #if defined(CONFIG_ARCH_OMAP1)
 #error "iommu for this processor not implemented yet"
 #else
-#include <mach/iommu2.h>
+#include <plat/iommu2.h>
 #endif
 
 /*
diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/plat/iommu2.h
index 10ad05f410e9..10ad05f410e9 100644
--- a/arch/arm/plat-omap/include/mach/iommu2.h
+++ b/arch/arm/plat-omap/include/plat/iommu2.h
diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
index bdc7ce5d7a4a..bdc7ce5d7a4a 100644
--- a/arch/arm/plat-omap/include/mach/iovmm.h
+++ b/arch/arm/plat-omap/include/plat/iovmm.h
diff --git a/arch/arm/plat-omap/include/mach/irda.h b/arch/arm/plat-omap/include/plat/irda.h
index 40f60339d1c6..40f60339d1c6 100644
--- a/arch/arm/plat-omap/include/mach/irda.h
+++ b/arch/arm/plat-omap/include/plat/irda.h
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 28a165058b61..ce5dd2d1dc21 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -86,49 +86,26 @@
 #define INT_1610_SSR_FIFO_0     29
 
 /*
- * OMAP-730 specific IRQ numbers for interrupt handler 1
+ * OMAP-7xx specific IRQ numbers for interrupt handler 1
  */
-#define INT_730_IH2_FIQ         0
-#define INT_730_IH2_IRQ         1
-#define INT_730_USB_NON_ISO     2
-#define INT_730_USB_ISO         3
-#define INT_730_ICR             4
-#define INT_730_EAC             5
-#define INT_730_GPIO_BANK1      6
-#define INT_730_GPIO_BANK2      7
-#define INT_730_GPIO_BANK3      8
-#define INT_730_McBSP2TX        10
-#define INT_730_McBSP2RX        11
-#define INT_730_McBSP2RX_OVF    12
-#define INT_730_LCD_LINE        14
-#define INT_730_GSM_PROTECT     15
-#define INT_730_TIMER3          16
-#define INT_730_GPIO_BANK5      17
-#define INT_730_GPIO_BANK6      18
-#define INT_730_SPGIO_WR        29
-
-/*
- * OMAP-850 specific IRQ numbers for interrupt handler 1
- */
-#define INT_850_IH2_FIQ         0
-#define INT_850_IH2_IRQ         1
-#define INT_850_USB_NON_ISO     2
-#define INT_850_USB_ISO         3
-#define INT_850_ICR             4
-#define INT_850_EAC             5
-#define INT_850_GPIO_BANK1      6
-#define INT_850_GPIO_BANK2      7
-#define INT_850_GPIO_BANK3      8
-#define INT_850_McBSP2TX        10
-#define INT_850_McBSP2RX        11
-#define INT_850_McBSP2RX_OVF    12
-#define INT_850_LCD_LINE        14
-#define INT_850_GSM_PROTECT     15
-#define INT_850_TIMER3          16
-#define INT_850_GPIO_BANK5      17
-#define INT_850_GPIO_BANK6      18
-#define INT_850_SPGIO_WR        29
-
+#define INT_7XX_IH2_FIQ         0
+#define INT_7XX_IH2_IRQ         1
+#define INT_7XX_USB_NON_ISO     2
+#define INT_7XX_USB_ISO         3
+#define INT_7XX_ICR             4
+#define INT_7XX_EAC             5
+#define INT_7XX_GPIO_BANK1      6
+#define INT_7XX_GPIO_BANK2      7
+#define INT_7XX_GPIO_BANK3      8
+#define INT_7XX_McBSP2TX        10
+#define INT_7XX_McBSP2RX        11
+#define INT_7XX_McBSP2RX_OVF    12
+#define INT_7XX_LCD_LINE        14
+#define INT_7XX_GSM_PROTECT     15
+#define INT_7XX_TIMER3          16
+#define INT_7XX_GPIO_BANK5      17
+#define INT_7XX_GPIO_BANK6      18
+#define INT_7XX_SPGIO_WR        29
 
 /*
  * IRQ numbers for interrupt handler 2
@@ -206,120 +183,62 @@
 #define INT_1610_SHA1MD5        (91 + IH2_BASE)
 
 /*
- * OMAP-730 specific IRQ numbers for interrupt handler 2
+ * OMAP-7xx specific IRQ numbers for interrupt handler 2
  */
-#define INT_730_HW_ERRORS       (0 + IH2_BASE)
-#define INT_730_NFIQ_PWR_FAIL   (1 + IH2_BASE)
-#define INT_730_CFCD            (2 + IH2_BASE)
-#define INT_730_CFIREQ          (3 + IH2_BASE)
-#define INT_730_I2C             (4 + IH2_BASE)
-#define INT_730_PCC             (5 + IH2_BASE)
-#define INT_730_MPU_EXT_NIRQ    (6 + IH2_BASE)
-#define INT_730_SPI_100K_1      (7 + IH2_BASE)
-#define INT_730_SYREN_SPI       (8 + IH2_BASE)
-#define INT_730_VLYNQ           (9 + IH2_BASE)
-#define INT_730_GPIO_BANK4      (10 + IH2_BASE)
-#define INT_730_McBSP1TX        (11 + IH2_BASE)
-#define INT_730_McBSP1RX        (12 + IH2_BASE)
-#define INT_730_McBSP1RX_OF     (13 + IH2_BASE)
-#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_730_UART_MODEM_1    (15 + IH2_BASE)
-#define INT_730_MCSI            (16 + IH2_BASE)
-#define INT_730_uWireTX         (17 + IH2_BASE)
-#define INT_730_uWireRX         (18 + IH2_BASE)
-#define INT_730_SMC_CD          (19 + IH2_BASE)
-#define INT_730_SMC_IREQ        (20 + IH2_BASE)
-#define INT_730_HDQ_1WIRE       (21 + IH2_BASE)
-#define INT_730_TIMER32K        (22 + IH2_BASE)
-#define INT_730_MMC_SDIO        (23 + IH2_BASE)
-#define INT_730_UPLD            (24 + IH2_BASE)
-#define INT_730_USB_HHC_1       (27 + IH2_BASE)
-#define INT_730_USB_HHC_2       (28 + IH2_BASE)
-#define INT_730_USB_GENI        (29 + IH2_BASE)
-#define INT_730_USB_OTG         (30 + IH2_BASE)
-#define INT_730_CAMERA_IF       (31 + IH2_BASE)
-#define INT_730_RNG             (32 + IH2_BASE)
-#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_730_DBB_RF_EN       (34 + IH2_BASE)
-#define INT_730_MPUIO_KEYPAD    (35 + IH2_BASE)
-#define INT_730_SHA1_MD5        (36 + IH2_BASE)
-#define INT_730_SPI_100K_2      (37 + IH2_BASE)
-#define INT_730_RNG_IDLE        (38 + IH2_BASE)
-#define INT_730_MPUIO           (39 + IH2_BASE)
-#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
-#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_730_LLPC_OE_RISING  (42 + IH2_BASE)
-#define INT_730_LLPC_VSYNC      (43 + IH2_BASE)
-#define INT_730_WAKE_UP_REQ     (46 + IH2_BASE)
-#define INT_730_DMA_CH6         (53 + IH2_BASE)
-#define INT_730_DMA_CH7         (54 + IH2_BASE)
-#define INT_730_DMA_CH8         (55 + IH2_BASE)
-#define INT_730_DMA_CH9         (56 + IH2_BASE)
-#define INT_730_DMA_CH10        (57 + IH2_BASE)
-#define INT_730_DMA_CH11        (58 + IH2_BASE)
-#define INT_730_DMA_CH12        (59 + IH2_BASE)
-#define INT_730_DMA_CH13        (60 + IH2_BASE)
-#define INT_730_DMA_CH14        (61 + IH2_BASE)
-#define INT_730_DMA_CH15        (62 + IH2_BASE)
-#define INT_730_NAND            (63 + IH2_BASE)
-
-/*
- * OMAP-850 specific IRQ numbers for interrupt handler 2
- */
-#define INT_850_HW_ERRORS       (0 + IH2_BASE)
-#define INT_850_NFIQ_PWR_FAIL   (1 + IH2_BASE)
-#define INT_850_CFCD            (2 + IH2_BASE)
-#define INT_850_CFIREQ          (3 + IH2_BASE)
-#define INT_850_I2C             (4 + IH2_BASE)
-#define INT_850_PCC             (5 + IH2_BASE)
-#define INT_850_MPU_EXT_NIRQ    (6 + IH2_BASE)
-#define INT_850_SPI_100K_1      (7 + IH2_BASE)
-#define INT_850_SYREN_SPI       (8 + IH2_BASE)
-#define INT_850_VLYNQ           (9 + IH2_BASE)
-#define INT_850_GPIO_BANK4      (10 + IH2_BASE)
-#define INT_850_McBSP1TX        (11 + IH2_BASE)
-#define INT_850_McBSP1RX        (12 + IH2_BASE)
-#define INT_850_McBSP1RX_OF     (13 + IH2_BASE)
-#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_850_UART_MODEM_1    (15 + IH2_BASE)
-#define INT_850_MCSI            (16 + IH2_BASE)
-#define INT_850_uWireTX         (17 + IH2_BASE)
-#define INT_850_uWireRX         (18 + IH2_BASE)
-#define INT_850_SMC_CD          (19 + IH2_BASE)
-#define INT_850_SMC_IREQ        (20 + IH2_BASE)
-#define INT_850_HDQ_1WIRE       (21 + IH2_BASE)
-#define INT_850_TIMER32K        (22 + IH2_BASE)
-#define INT_850_MMC_SDIO        (23 + IH2_BASE)
-#define INT_850_UPLD            (24 + IH2_BASE)
-#define INT_850_USB_HHC_1       (27 + IH2_BASE)
-#define INT_850_USB_HHC_2       (28 + IH2_BASE)
-#define INT_850_USB_GENI        (29 + IH2_BASE)
-#define INT_850_USB_OTG         (30 + IH2_BASE)
-#define INT_850_CAMERA_IF       (31 + IH2_BASE)
-#define INT_850_RNG             (32 + IH2_BASE)
-#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_850_DBB_RF_EN       (34 + IH2_BASE)
-#define INT_850_MPUIO_KEYPAD    (35 + IH2_BASE)
-#define INT_850_SHA1_MD5        (36 + IH2_BASE)
-#define INT_850_SPI_100K_2      (37 + IH2_BASE)
-#define INT_850_RNG_IDLE        (38 + IH2_BASE)
-#define INT_850_MPUIO           (39 + IH2_BASE)
-#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
-#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_850_LLPC_OE_RISING  (42 + IH2_BASE)
-#define INT_850_LLPC_VSYNC      (43 + IH2_BASE)
-#define INT_850_WAKE_UP_REQ     (46 + IH2_BASE)
-#define INT_850_DMA_CH6         (53 + IH2_BASE)
-#define INT_850_DMA_CH7         (54 + IH2_BASE)
-#define INT_850_DMA_CH8         (55 + IH2_BASE)
-#define INT_850_DMA_CH9         (56 + IH2_BASE)
-#define INT_850_DMA_CH10        (57 + IH2_BASE)
-#define INT_850_DMA_CH11        (58 + IH2_BASE)
-#define INT_850_DMA_CH12        (59 + IH2_BASE)
-#define INT_850_DMA_CH13        (60 + IH2_BASE)
-#define INT_850_DMA_CH14        (61 + IH2_BASE)
-#define INT_850_DMA_CH15        (62 + IH2_BASE)
-#define INT_850_NAND            (63 + IH2_BASE)
+#define INT_7XX_HW_ERRORS       (0 + IH2_BASE)
+#define INT_7XX_NFIQ_PWR_FAIL   (1 + IH2_BASE)
+#define INT_7XX_CFCD            (2 + IH2_BASE)
+#define INT_7XX_CFIREQ          (3 + IH2_BASE)
+#define INT_7XX_I2C             (4 + IH2_BASE)
+#define INT_7XX_PCC             (5 + IH2_BASE)
+#define INT_7XX_MPU_EXT_NIRQ    (6 + IH2_BASE)
+#define INT_7XX_SPI_100K_1      (7 + IH2_BASE)
+#define INT_7XX_SYREN_SPI       (8 + IH2_BASE)
+#define INT_7XX_VLYNQ           (9 + IH2_BASE)
+#define INT_7XX_GPIO_BANK4      (10 + IH2_BASE)
+#define INT_7XX_McBSP1TX        (11 + IH2_BASE)
+#define INT_7XX_McBSP1RX        (12 + IH2_BASE)
+#define INT_7XX_McBSP1RX_OF     (13 + IH2_BASE)
+#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_7XX_UART_MODEM_1    (15 + IH2_BASE)
+#define INT_7XX_MCSI            (16 + IH2_BASE)
+#define INT_7XX_uWireTX         (17 + IH2_BASE)
+#define INT_7XX_uWireRX         (18 + IH2_BASE)
+#define INT_7XX_SMC_CD          (19 + IH2_BASE)
+#define INT_7XX_SMC_IREQ        (20 + IH2_BASE)
+#define INT_7XX_HDQ_1WIRE       (21 + IH2_BASE)
+#define INT_7XX_TIMER32K        (22 + IH2_BASE)
+#define INT_7XX_MMC_SDIO        (23 + IH2_BASE)
+#define INT_7XX_UPLD            (24 + IH2_BASE)
+#define INT_7XX_USB_HHC_1       (27 + IH2_BASE)
+#define INT_7XX_USB_HHC_2       (28 + IH2_BASE)
+#define INT_7XX_USB_GENI        (29 + IH2_BASE)
+#define INT_7XX_USB_OTG         (30 + IH2_BASE)
+#define INT_7XX_CAMERA_IF       (31 + IH2_BASE)
+#define INT_7XX_RNG             (32 + IH2_BASE)
+#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_7XX_DBB_RF_EN       (34 + IH2_BASE)
+#define INT_7XX_MPUIO_KEYPAD    (35 + IH2_BASE)
+#define INT_7XX_SHA1_MD5        (36 + IH2_BASE)
+#define INT_7XX_SPI_100K_2      (37 + IH2_BASE)
+#define INT_7XX_RNG_IDLE        (38 + IH2_BASE)
+#define INT_7XX_MPUIO           (39 + IH2_BASE)
+#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
+#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_7XX_LLPC_OE_RISING  (42 + IH2_BASE)
+#define INT_7XX_LLPC_VSYNC      (43 + IH2_BASE)
+#define INT_7XX_WAKE_UP_REQ     (46 + IH2_BASE)
+#define INT_7XX_DMA_CH6         (53 + IH2_BASE)
+#define INT_7XX_DMA_CH7         (54 + IH2_BASE)
+#define INT_7XX_DMA_CH8         (55 + IH2_BASE)
+#define INT_7XX_DMA_CH9         (56 + IH2_BASE)
+#define INT_7XX_DMA_CH10        (57 + IH2_BASE)
+#define INT_7XX_DMA_CH11        (58 + IH2_BASE)
+#define INT_7XX_DMA_CH12        (59 + IH2_BASE)
+#define INT_7XX_DMA_CH13        (60 + IH2_BASE)
+#define INT_7XX_DMA_CH14        (61 + IH2_BASE)
+#define INT_7XX_DMA_CH15        (62 + IH2_BASE)
+#define INT_7XX_NAND            (63 + IH2_BASE)
 
 #define INT_24XX_SYS_NIRQ       7
 #define INT_24XX_SDMA_IRQ0      12
@@ -558,9 +477,14 @@
 
 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
 
+#define INTCPS_NR_MIR_REGS      3
+#define INTCPS_NR_IRQS          96
+
 #ifndef __ASSEMBLY__
 extern void omap_init_irq(void);
 extern int omap_irq_pending(void);
+void omap_intc_save_context(void);
+void omap_intc_restore_context(void);
 #endif
 
 #include <mach/hardware.h>
diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 3ae52ccc793c..3ae52ccc793c 100644
--- a/arch/arm/plat-omap/include/mach/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
diff --git a/arch/arm/plat-omap/include/mach/lcd_mipid.h b/arch/arm/plat-omap/include/plat/lcd_mipid.h
index 8e52c6572281..8e52c6572281 100644
--- a/arch/arm/plat-omap/include/mach/lcd_mipid.h
+++ b/arch/arm/plat-omap/include/plat/lcd_mipid.h
diff --git a/arch/arm/plat-omap/include/mach/led.h b/arch/arm/plat-omap/include/plat/led.h
index 25e451e7e2fd..25e451e7e2fd 100644
--- a/arch/arm/plat-omap/include/mach/led.h
+++ b/arch/arm/plat-omap/include/plat/led.h
diff --git a/arch/arm/plat-omap/include/mach/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index b7a6991814ec..729166b76a7c 100644
--- a/arch/arm/plat-omap/include/mach/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -6,9 +6,9 @@
 #include <linux/wait.h>
 #include <linux/workqueue.h>
 #include <linux/blkdev.h>
+#include <linux/interrupt.h>
 
 typedef u32 mbox_msg_t;
-typedef void (mbox_receiver_t)(mbox_msg_t msg);
 struct omap_mbox;
 
 typedef int __bitwise omap_mbox_irq_t;
@@ -29,8 +29,10 @@ struct omap_mbox_ops {
         int             (*fifo_empty)(struct omap_mbox *mbox);
         int             (*fifo_full)(struct omap_mbox *mbox);
         /* irq */
-        void            (*enable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
-        void            (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+        void            (*enable_irq)(struct omap_mbox *mbox,
+                                                omap_mbox_irq_t irq);
+        void            (*disable_irq)(struct omap_mbox *mbox,
+                                                omap_mbox_irq_t irq);
         void            (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
         int             (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
         /* ctx */
@@ -42,6 +44,7 @@ struct omap_mbox_queue {
         spinlock_t              lock;
         struct request_queue    *queue;
         struct work_struct      work;
+        struct tasklet_struct   tasklet;
         int     (*callback)(void *);
         struct omap_mbox        *mbox;
 };
@@ -64,7 +67,7 @@ struct omap_mbox {
         void                    (*err_notify)(void);
 };
 
-int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *);
+int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
 void omap_mbox_init_seq(struct omap_mbox *);
 
 struct omap_mbox *omap_mbox_get(const char *);
@@ -93,4 +96,16 @@ static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
         mbox->ops->restore_ctx(mbox);
 }
 
+static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
+                                        omap_mbox_irq_t irq)
+{
+        mbox->ops->enable_irq(mbox, irq);
+}
+
+static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
+                                         omap_mbox_irq_t irq)
+{
+        mbox->ops->disable_irq(mbox, irq);
+}
+
 #endif /* MAILBOX_H */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index e0d6eca222cc..4f22e5bb7ff7 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -28,10 +28,10 @@
 #include <linux/spinlock.h>
 
 #include <mach/hardware.h>
-#include <mach/clock.h>
+#include <plat/clock.h>
 
-#define OMAP730_MCBSP1_BASE     0xfffb1000
-#define OMAP730_MCBSP2_BASE     0xfffb1800
+#define OMAP7XX_MCBSP1_BASE     0xfffb1000
+#define OMAP7XX_MCBSP2_BASE     0xfffb1800
 
 #define OMAP1510_MCBSP1_BASE    0xe1011800
 #define OMAP1510_MCBSP2_BASE    0xfffb1000
@@ -58,7 +58,7 @@
 #define OMAP44XX_MCBSP3_BASE    0x49026000
 #define OMAP44XX_MCBSP4_BASE    0x48074000
 
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x02
diff --git a/arch/arm/plat-omap/include/mach/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 1254e4945b6f..1254e4945b6f 100644
--- a/arch/arm/plat-omap/include/mach/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/plat/memory.h
index 3325f7b49eaa..3325f7b49eaa 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/plat/memory.h
diff --git a/arch/arm/plat-omap/include/mach/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h
index 3122bf68c7ce..3122bf68c7ce 100644
--- a/arch/arm/plat-omap/include/mach/menelaus.h
+++ b/arch/arm/plat-omap/include/plat/menelaus.h
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 7229b9593301..29937137bf3e 100644
--- a/arch/arm/plat-omap/include/mach/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -15,7 +15,7 @@
 #include <linux/device.h>
 #include <linux/mmc/host.h>
 
-#include <mach/board.h>
+#include <plat/board.h>
 
 #define OMAP15XX_NR_MMC         1
 #define OMAP16XX_NR_MMC         2
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index 0f49d2d563d9..ba77de601501 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -51,23 +51,13 @@
                                         .pu_pd_reg = PU_PD_SEL_##reg, \
                                         .pu_pd_val = status,
 
-#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
-                                        .mux_reg = OMAP730_IO_CONF_##reg, \
+#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
+                                        .mux_reg = OMAP7XX_IO_CONF_##reg, \
                                         .mask_offset = mode_offset, \
                                         .mask = mode,
 
-#define PULL_REG_730(reg, bit, status)  .pull_name = "OMAP730_IO_CONF_"#reg, \
-                                        .pull_reg = OMAP730_IO_CONF_##reg, \
-                                        .pull_bit = bit, \
-                                        .pull_val = status,
-
-#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
-                                        .mux_reg = OMAP850_IO_CONF_##reg, \
-                                        .mask_offset = mode_offset, \
-                                        .mask = mode,
-
-#define PULL_REG_850(reg, bit, status)  .pull_name = "OMAP850_IO_CONF_"#reg, \
-                                        .pull_reg = OMAP850_IO_CONF_##reg, \
+#define PULL_REG_7XX(reg, bit, status)  .pull_name = "OMAP7XX_IO_CONF_"#reg, \
+                                        .pull_reg = OMAP7XX_IO_CONF_##reg, \
                                         .pull_bit = bit, \
                                         .pull_val = status,
 
@@ -84,21 +74,12 @@
 #define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
                                         .pu_pd_val = status,
 
-#define MUX_REG_730(reg, mode_offset, mode) \
-                                        .mux_reg = OMAP730_IO_CONF_##reg, \
+#define MUX_REG_7XX(reg, mode_offset, mode) \
+                                        .mux_reg = OMAP7XX_IO_CONF_##reg, \
                                         .mask_offset = mode_offset, \
                                         .mask = mode,
 
-#define PULL_REG_730(reg, bit, status)  .pull_reg = OMAP730_IO_CONF_##reg, \
-                                        .pull_bit = bit, \
-                                        .pull_val = status,
-
-#define MUX_REG_850(reg, mode_offset, mode) \
-                                        .mux_reg = OMAP850_IO_CONF_##reg, \
-                                        .mask_offset = mode_offset, \
-                                        .mask = mode,
-
-#define PULL_REG_850(reg, bit, status)  .pull_reg = OMAP850_IO_CONF_##reg, \
+#define PULL_REG_7XX(reg, bit, status)  .pull_reg = OMAP7XX_IO_CONF_##reg, \
                                         .pull_bit = bit, \
                                         .pull_val = status,
 
@@ -118,32 +99,21 @@
 
 /*
  * OMAP730/850 has a slightly different config for the pin mux.
- * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
+ * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
  *   not the FUNC_MUX_CTRL_x regs from hardware.h
  * - for pull-up/down, only has one enable bit which is is in the same register
  *   as mux config
  */
-#define MUX_CFG_730(desc, mux_reg, mode_offset, mode,   \
-                   pull_bit, pull_status, debug_status)\
-{                                                       \
-        .name =  desc,                                  \
-        .debug = debug_status,                          \
-        MUX_REG_730(mux_reg, mode_offset, mode)         \
-        PULL_REG_730(mux_reg, pull_bit, pull_status)    \
-        PU_PD_REG(NA, 0)                \
-},
-
-#define MUX_CFG_850(desc, mux_reg, mode_offset, mode,   \
+#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,   \
                    pull_bit, pull_status, debug_status)\
 {                                                       \
         .name =  desc,                                  \
         .debug = debug_status,                          \
-        MUX_REG_850(mux_reg, mode_offset, mode)         \
-        PULL_REG_850(mux_reg, pull_bit, pull_status)    \
+        MUX_REG_7XX(mux_reg, mode_offset, mode)         \
+        PULL_REG_7XX(mux_reg, pull_bit, pull_status)    \
         PU_PD_REG(NA, 0)                \
 },
 
-
 #define MUX_CFG_24XX(desc, reg_offset, mode,                    \
                                 pull_en, pull_mode, dbg)        \
 {                                                               \
@@ -232,45 +202,30 @@ struct pin_config {
 
 };
 
-enum omap730_index {
+enum omap7xx_index {
         /* OMAP 730 keyboard */
-        E2_730_KBR0,
-        J7_730_KBR1,
-        E1_730_KBR2,
-        F3_730_KBR3,
-        D2_730_KBR4,
-        C2_730_KBC0,
-        D3_730_KBC1,
-        E4_730_KBC2,
-        F4_730_KBC3,
-        E3_730_KBC4,
+        E2_7XX_KBR0,
+        J7_7XX_KBR1,
+        E1_7XX_KBR2,
+        F3_7XX_KBR3,
+        D2_7XX_KBR4,
+        C2_7XX_KBC0,
+        D3_7XX_KBC1,
+        E4_7XX_KBC2,
+        F4_7XX_KBC3,
+        E3_7XX_KBC4,
 
         /* USB */
-        AA17_730_USB_DM,
-        W16_730_USB_PU_EN,
-        W17_730_USB_VBUSI,
+        AA17_7XX_USB_DM,
+        W16_7XX_USB_PU_EN,
+        W17_7XX_USB_VBUSI,
+
+        /* MMC */
+        MMC_7XX_CMD,
+        MMC_7XX_CLK,
+        MMC_7XX_DAT0,
 };
 
-enum omap850_index {
-        /* OMAP 850 keyboard */
-        E2_850_KBR0,
-        J7_850_KBR1,
-        E1_850_KBR2,
-        F3_850_KBR3,
-        D2_850_KBR4,
-        C2_850_KBC0,
-        D3_850_KBC1,
-        E4_850_KBC2,
-        F4_850_KBC3,
-        E3_850_KBC4,
-
-        /* USB */
-        AA17_850_USB_DM,
-        W16_850_USB_PU_EN,
-        W17_850_USB_VBUSI,
-};
-
-
 enum omap1xxx_index {
         /* UART1 (BT_UART_GATING)*/
         UART1_TX = 0,
@@ -879,6 +834,10 @@ enum omap34xx_index {
         AH4_3430_MMC2_DAT1,
         AG4_3430_MMC2_DAT2,
         AF4_3430_MMC2_DAT3,
+        AE4_3430_MMC2_DAT4,
+        AH3_3430_MMC2_DAT5,
+        AF3_3430_MMC2_DAT6,
+        AE3_3430_MMC2_DAT7,
 
         /* MMC3 */
         AF10_3430_MMC3_CLK,
@@ -890,6 +849,11 @@ enum omap34xx_index {
 
         /* SYS_NIRQ T2 INT1 */
         AF26_34XX_SYS_NIRQ,
+
+        /* EHCI GPIO's for OMAP3EVM (Rev >= E) */
+        AH14_34XX_GPIO21,
+        AF9_34XX_GPIO22,
+        U3_34XX_GPIO61,
 };
 
 struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 631a7bed1eef..631a7bed1eef 100644
--- a/arch/arm/plat-omap/include/mach/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
diff --git a/arch/arm/plat-omap/include/mach/omap-alsa.h b/arch/arm/plat-omap/include/plat/omap-alsa.h
index bdf30a0f87f2..b53055b390d0 100644
--- a/arch/arm/plat-omap/include/mach/omap-alsa.h
+++ b/arch/arm/plat-omap/include/plat/omap-alsa.h
@@ -40,10 +40,10 @@
 #ifndef __OMAP_ALSA_H
 #define __OMAP_ALSA_H
 
-#include <mach/dma.h>
+#include <plat/dma.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
-#include <mach/mcbsp.h>
+#include <plat/mcbsp.h>
 #include <linux/platform_device.h>
 
 #define DMA_BUF_SIZE    (1024 * 8)
diff --git a/arch/arm/plat-omap/include/mach/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index 3ee41d711492..3ee41d711492 100644
--- a/arch/arm/plat-omap/include/mach/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/plat/omap1510.h
index d24004668138..d24004668138 100644
--- a/arch/arm/plat-omap/include/mach/omap1510.h
+++ b/arch/arm/plat-omap/include/plat/omap1510.h
diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h
index 0e69b504c25f..0e69b504c25f 100644
--- a/arch/arm/plat-omap/include/mach/omap16xx.h
+++ b/arch/arm/plat-omap/include/plat/omap16xx.h
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
index 696edfc145a6..696edfc145a6 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index f8d186a73712..077f05979f86 100644
--- a/arch/arm/plat-omap/include/mach/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -72,16 +72,15 @@
 #define OMAP3430_ISP_CSI2A_END          (OMAP3430_ISP_CSI2A_BASE   + 0x16F)
 #define OMAP3430_ISP_CSI2PHY_END        (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
 
-#define OMAP34XX_IVA_INTC_BASE  0x40000000
 #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
-#define OMAP34XX_HSUSB_HOST_BASE        (L4_34XX_BASE + 0x64000)
 #define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
+#define OMAP34XX_UHH_CONFIG_BASE        (L4_34XX_BASE + 0x64000)
+#define OMAP34XX_OHCI_BASE      (L4_34XX_BASE + 0x64400)
+#define OMAP34XX_EHCI_BASE      (L4_34XX_BASE + 0x64800)
+#define OMAP34XX_SR1_BASE       0x480C9000
+#define OMAP34XX_SR2_BASE       0x480CB000
 
 #define OMAP34XX_MAILBOX_BASE           (L4_34XX_BASE + 0x94000)
 
-#define OMAP34XX_DSP_BASE       0x58000000
-#define OMAP34XX_DSP_MEM_BASE   (OMAP34XX_DSP_BASE + 0x0)
-#define OMAP34XX_DSP_IPI_BASE   (OMAP34XX_DSP_BASE + 0x1000000)
-#define OMAP34XX_DSP_MMU_BASE   (OMAP34XX_DSP_BASE + 0x2000000)
 #endif /* __ASM_ARCH_OMAP34XX_H */
 
diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index b3ba5ac7b4a4..e52902a15c1a 100644
--- a/arch/arm/plat-omap/include/mach/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -22,6 +22,9 @@
 #define L4_PER_44XX_BASE                0x48000000
 #define L4_EMU_44XX_BASE                0x54000000
 #define L3_44XX_BASE                    0x44000000
+#define OMAP44XX_EMIF1_BASE             0x4c000000
+#define OMAP44XX_EMIF2_BASE             0x4d000000
+#define OMAP44XX_DMM_BASE               0x4e000000
 #define OMAP4430_32KSYNCT_BASE          0x4a304000
 #define OMAP4430_CM_BASE                0x4a004000
 #define OMAP4430_PRM_BASE               0x48306000
@@ -33,14 +36,11 @@
 #define IRQ_SIR_IRQ                     0x0040
 #define OMAP44XX_GIC_DIST_BASE          0x48241000
 #define OMAP44XX_GIC_CPU_BASE           0x48240100
-#define OMAP44XX_VA_GIC_CPU_BASE        OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
 #define OMAP44XX_SCU_BASE               0x48240000
-#define OMAP44XX_VA_SCU_BASE            OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE)
 #define OMAP44XX_LOCAL_TWD_BASE         0x48240600
-#define OMAP44XX_VA_LOCAL_TWD_BASE      OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
-#define OMAP44XX_LOCAL_TWD_SIZE         0x00000100
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
-#define OMAP44XX_VA_WKUPGEN_BASE        OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
+
+#define OMAP44XX_MAILBOX_BASE           (L4_44XX_BASE + 0xF4000)
 
 #endif /* __ASM_ARCH_OMAP44XX_H */
 
diff --git a/arch/arm/plat-omap/include/mach/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h
index 14272bc1a6fd..14272bc1a6fd 100644
--- a/arch/arm/plat-omap/include/mach/omap730.h
+++ b/arch/arm/plat-omap/include/plat/omap730.h
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h
new file mode 100644
index 000000000000..53f52414b0e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap7xx.h
@@ -0,0 +1,104 @@
+/* arch/arm/plat-omap/include/mach/omap7xx.h
+ *
+ * Hardware definitions for TI OMAP7XX processor.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
+ * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP7XX_H
+#define __ASM_ARCH_OMAP7XX_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP7XX_DSP_BASE        0xE0000000
+#define OMAP7XX_DSP_SIZE        0x50000
+#define OMAP7XX_DSP_START       0xE0000000
+
+#define OMAP7XX_DSPREG_BASE     0xE1000000
+#define OMAP7XX_DSPREG_SIZE     SZ_128K
+#define OMAP7XX_DSPREG_START    0xE1000000
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX specific configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_CONFIG_BASE     0xfffe1000
+#define OMAP7XX_IO_CONF_0       0xfffe1070
+#define OMAP7XX_IO_CONF_1       0xfffe1074
+#define OMAP7XX_IO_CONF_2       0xfffe1078
+#define OMAP7XX_IO_CONF_3       0xfffe107c
+#define OMAP7XX_IO_CONF_4       0xfffe1080
+#define OMAP7XX_IO_CONF_5       0xfffe1084
+#define OMAP7XX_IO_CONF_6       0xfffe1088
+#define OMAP7XX_IO_CONF_7       0xfffe108c
+#define OMAP7XX_IO_CONF_8       0xfffe1090
+#define OMAP7XX_IO_CONF_9       0xfffe1094
+#define OMAP7XX_IO_CONF_10      0xfffe1098
+#define OMAP7XX_IO_CONF_11      0xfffe109c
+#define OMAP7XX_IO_CONF_12      0xfffe10a0
+#define OMAP7XX_IO_CONF_13      0xfffe10a4
+
+#define OMAP7XX_MODE_1          0xfffe1010
+#define OMAP7XX_MODE_2          0xfffe1014
+
+/* CSMI specials: in terms of base + offset */
+#define OMAP7XX_MODE2_OFFSET    0x14
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX traffic controller configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_FLASH_CFG_0     0xfffecc10
+#define OMAP7XX_FLASH_ACFG_0    0xfffecc50
+#define OMAP7XX_FLASH_CFG_1     0xfffecc14
+#define OMAP7XX_FLASH_ACFG_1    0xfffecc54
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX DSP control registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_ICR_BASE        0xfffbb800
+#define OMAP7XX_DSP_M_CTL       0xfffbb804
+#define OMAP7XX_DSP_MMU_BASE    0xfffed200
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX PCC_UPLD configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_PCC_UPLD_CTRL_BASE      (0xfffe0900)
+#define OMAP7XX_PCC_UPLD_CTRL           (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
+
+#endif /*  __ASM_ARCH_OMAP7XX_H */
+
diff --git a/arch/arm/plat-omap/include/mach/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h
index c33f67981712..c33f67981712 100644
--- a/arch/arm/plat-omap/include/mach/omap850.h
+++ b/arch/arm/plat-omap/include/plat/omap850.h
diff --git a/arch/arm/plat-omap/include/mach/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index bd0e136db337..11a9773a4e7f 100644
--- a/arch/arm/plat-omap/include/mach/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -34,7 +34,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
-#include <mach/omap_hwmod.h>
+#include <plat/omap_hwmod.h>
 
 /* omap_device._state values */
 #define OMAP_DEVICE_STATE_UNKNOWN       0
diff --git a/arch/arm/plat-omap/include/mach/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1f79c20e2929..dbdd123eca16 100644
--- a/arch/arm/plat-omap/include/mach/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -35,7 +35,7 @@
 #include <linux/kernel.h>
 #include <linux/ioport.h>
 
-#include <mach/cpu.h>
+#include <plat/cpu.h>
 
 struct omap_device;
 
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/plat/omapfb.h
index b226bdf45739..bfef7ab95f17 100644
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ b/arch/arm/plat-omap/include/plat/omapfb.h
@@ -168,7 +168,7 @@ enum omapfb_update_mode {
 #include <linux/fb.h>
 #include <linux/mutex.h>
 
-#include <mach/board.h>
+#include <plat/board.h>
 
 #define OMAP_LCDC_INV_VSYNC             0x0001
 #define OMAP_LCDC_INV_HSYNC             0x0002
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index 72f433d7d827..72f433d7d827 100644
--- a/arch/arm/plat-omap/include/mach/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
diff --git a/arch/arm/plat-omap/include/mach/param.h b/arch/arm/plat-omap/include/plat/param.h
index 1eb4dc326979..1eb4dc326979 100644
--- a/arch/arm/plat-omap/include/mach/param.h
+++ b/arch/arm/plat-omap/include/plat/param.h
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index fa6461423bd0..3d45ee1d3cf4 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -19,7 +19,7 @@
 
 #include <asm/atomic.h>
 
-#include <mach/cpu.h>
+#include <plat/cpu.h>
 
 
 /* Powerdomain basic power states */
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index cda2a70397b4..e63e94e18975 100644
--- a/arch/arm/plat-omap/include/mach/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -27,9 +27,13 @@ u32 omap_prcm_get_reset_sources(void);
 void omap_prcm_arch_reset(char mode);
 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
 
-#endif
+#define START_PADCONF_SAVE 0x2
+#define PADCONF_SAVE_DONE  0x1
 
+void omap3_prcm_save_context(void);
+void omap3_prcm_restore_context(void);
 
+#endif
 
 
 
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 1c09c78a48f2..f704030d2a70 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -44,6 +44,12 @@
 #define SDRC_RFR_CTRL_1         0x0D4
 #define SDRC_MANUAL_1           0x0D8
 
+#define SDRC_POWER_AUTOCOUNT_SHIFT      8
+#define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
+#define SDRC_POWER_CLKCTRL_SHIFT        4
+#define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
+#define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
+
 /*
  * These values represent the number of memory clock cycles between
  * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
@@ -80,11 +86,11 @@
  */
 
 #define OMAP242X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
 #define OMAP243X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
 #define OMAP343X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
 
 /* SMS register offsets - read/write with sms_{read,write}_reg() */
 
@@ -120,6 +126,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 int omap2_sdrc_get_params(unsigned long r,
                           struct omap_sdrc_params **sdrc_cs0,
                           struct omap_sdrc_params **sdrc_cs1);
+void omap2_sms_save_context(void);
+void omap2_sms_restore_context(void);
 
 #ifdef CONFIG_ARCH_OMAP2
 
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index e249186d26e2..9951345a25d6 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -20,26 +20,22 @@
 #define OMAP_UART1_BASE         0xfffb0000
 #define OMAP_UART2_BASE         0xfffb0800
 #define OMAP_UART3_BASE         0xfffb9800
-#define OMAP_MAX_NR_PORTS       3
 #elif defined(CONFIG_ARCH_OMAP2)
 /* OMAP2 serial ports */
 #define OMAP_UART1_BASE         0x4806a000
 #define OMAP_UART2_BASE         0x4806c000
 #define OMAP_UART3_BASE         0x4806e000
-#define OMAP_MAX_NR_PORTS       3
 #elif defined(CONFIG_ARCH_OMAP3)
 /* OMAP3 serial ports */
 #define OMAP_UART1_BASE         0x4806a000
 #define OMAP_UART2_BASE         0x4806c000
 #define OMAP_UART3_BASE         0x49020000
-#define OMAP_MAX_NR_PORTS       3
 #elif defined(CONFIG_ARCH_OMAP4)
 /* OMAP4 serial ports */
 #define OMAP_UART1_BASE         0x4806a000
 #define OMAP_UART2_BASE         0x4806c000
 #define OMAP_UART3_BASE         0x48020000
 #define OMAP_UART4_BASE         0x4806e000
-#define OMAP_MAX_NR_PORTS       4
 #endif
 
 #define OMAP1510_BASE_BAUD      (12000000/16)
diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index dcaa8fde7063..dcaa8fde7063 100644
--- a/arch/arm/plat-omap/include/mach/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 8974e3fc2691..16a1b458d53c 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -27,6 +27,7 @@ extern u32 omap3_configure_core_dpll(
                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+extern void omap3_sram_restore_context(void);
 
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -68,4 +69,10 @@ extern u32 omap3_sram_configure_core_dpll(
                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
+#ifdef CONFIG_PM
+extern void omap_push_sram_idle(void);
+#else
+static inline void omap_push_sram_idle(void) {}
+#endif /* CONFIG_PM */
+
 #endif
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/plat/system.h
index ed8ec7477261..c58a4ef42a45 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/plat/system.h
@@ -9,7 +9,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 
-#include <mach/prcm.h>
+#include <plat/prcm.h>
 
 #ifndef CONFIG_MACH_VOICEBLUE
 #define voiceblue_reset()               do {} while (0)
diff --git a/arch/arm/plat-omap/include/mach/tc.h b/arch/arm/plat-omap/include/plat/tc.h
index d2fcd789bb9a..d2fcd789bb9a 100644
--- a/arch/arm/plat-omap/include/mach/tc.h
+++ b/arch/arm/plat-omap/include/plat/tc.h
diff --git a/arch/arm/plat-omap/include/mach/timer-gp.h b/arch/arm/plat-omap/include/plat/timer-gp.h
index c88d346b59d9..c88d346b59d9 100644
--- a/arch/arm/plat-omap/include/mach/timer-gp.h
+++ b/arch/arm/plat-omap/include/plat/timer-gp.h
diff --git a/arch/arm/plat-omap/include/mach/timex.h b/arch/arm/plat-omap/include/plat/timex.h
index 6d35767bc48f..6d35767bc48f 100644
--- a/arch/arm/plat-omap/include/mach/timex.h
+++ b/arch/arm/plat-omap/include/plat/timex.h
diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 0814c5f210c3..13c305d62127 100644
--- a/arch/arm/plat-omap/include/mach/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -19,12 +19,13 @@
 
 #include <linux/types.h>
 #include <linux/serial_reg.h>
-#include <mach/serial.h>
+#include <plat/serial.h>
 
 unsigned int system_rev;
 
 #define UART_OMAP_MDR1          0x08    /* mode definition register */
 #define OMAP_ID_730             0x355F
+#define OMAP_ID_850             0x362C
 #define ID_MASK                 0x7fff
 #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
 #define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
@@ -43,8 +44,12 @@ static void putc(int c)
         uart = (volatile u8 *)(OMAP_UART3_BASE);
 #elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
         uart = (volatile u8 *)(OMAP_UART2_BASE);
-#else
+#elif defined(CONFIG_OMAP_LL_DEBUG_UART1)
         uart = (volatile u8 *)(OMAP_UART1_BASE);
+#elif defined(CONFIG_OMAP_LL_DEBUG_NONE)
+        return;
+#else
+        return;
 #endif
 
 #ifdef CONFIG_ARCH_OMAP1
@@ -53,7 +58,7 @@ static void putc(int c)
                 /* MMU is not on, so cpu_is_omapXXXX() won't work here */
                 unsigned int omap_id = omap_get_id();
 
-                if (omap_id == OMAP_ID_730)
+                if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
                         shift = 0;
 
                 if (check_port(uart, shift))
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index f337e1761e2c..33a500eb2f93 100644
--- a/arch/arm/plat-omap/include/mach/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -3,7 +3,22 @@
 #ifndef __ASM_ARCH_OMAP_USB_H
 #define __ASM_ARCH_OMAP_USB_H
 
-#include <mach/board.h>
+#include <plat/board.h>
+
+#define OMAP3_HS_USB_PORTS      3
+enum ehci_hcd_omap_mode {
+        EHCI_HCD_OMAP_MODE_UNKNOWN,
+        EHCI_HCD_OMAP_MODE_PHY,
+        EHCI_HCD_OMAP_MODE_TLL,
+};
+
+struct ehci_hcd_omap_platform_data {
+        enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
+        unsigned                        phy_reset:1;
+
+        /* have to be valid if phy_reset is true and portx is in phy mode */
+        int     reset_gpio_port[OMAP3_HS_USB_PORTS];
+};
 
 /*-------------------------------------------------------------------------*/
 
@@ -29,6 +44,8 @@
 
 extern void usb_musb_init(void);
 
+extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
+
 #endif
 
 void omap_usb_init(struct omap_usb_config *pdata);
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index b6defa23e77e..11f5d7961c73 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -13,12 +13,12 @@
 #include <linux/io.h>
 #include <linux/mm.h>
 
-#include <mach/omap730.h>
-#include <mach/omap1510.h>
-#include <mach/omap16xx.h>
-#include <mach/omap24xx.h>
-#include <mach/omap34xx.h>
-#include <mach/omap44xx.h>
+#include <plat/omap7xx.h>
+#include <plat/omap1510.h>
+#include <plat/omap16xx.h>
+#include <plat/omap24xx.h>
+#include <plat/omap34xx.h>
+#include <plat/omap44xx.h>
 
 #define BETWEEN(p,st,sz)        ((p) >= (st) && (p) < ((st) + (sz)))
 #define XLATE(p,pst,vst)        ((void __iomem *)((p) - (pst) + (vst)))
@@ -33,13 +33,13 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                 if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
                         return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
         }
-        if (cpu_is_omap730()) {
-                if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
-                        return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
+        if (cpu_is_omap7xx()) {
+                if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
+                        return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
 
-                if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE))
-                        return XLATE(p, OMAP730_DSPREG_BASE,
-                                        OMAP730_DSPREG_START);
+                if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
+                        return XLATE(p, OMAP7XX_DSPREG_BASE,
+                                        OMAP7XX_DSPREG_START);
         }
         if (cpu_is_omap15xx()) {
                 if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
@@ -114,6 +114,14 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                         return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
                 if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
                         return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
+                if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE))
+                        return XLATE(p, OMAP44XX_EMIF1_PHYS,            \
+                                                        OMAP44XX_EMIF1_VIRT);
+                if (BETWEEN(p, OMAP44XX_EMIF2_PHYS, OMAP44XX_EMIF2_SIZE))
+                        return XLATE(p, OMAP44XX_EMIF2_PHYS,            \
+                                                        OMAP44XX_EMIF2_VIRT);
+                if (BETWEEN(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_SIZE))
+                        return XLATE(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_VIRT);
                 if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
                         return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
                 if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
@@ -142,7 +150,7 @@ u8 omap_readb(u32 pa)
         if (cpu_class_is_omap1())
                 return __raw_readb(OMAP1_IO_ADDRESS(pa));
         else
-                return __raw_readb(OMAP2_IO_ADDRESS(pa));
+                return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_readb);
 
@@ -151,7 +159,7 @@ u16 omap_readw(u32 pa)
         if (cpu_class_is_omap1())
                 return __raw_readw(OMAP1_IO_ADDRESS(pa));
         else
-                return __raw_readw(OMAP2_IO_ADDRESS(pa));
+                return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_readw);
 
@@ -160,7 +168,7 @@ u32 omap_readl(u32 pa)
         if (cpu_class_is_omap1())
                 return __raw_readl(OMAP1_IO_ADDRESS(pa));
         else
-                return __raw_readl(OMAP2_IO_ADDRESS(pa));
+                return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_readl);
 
@@ -169,7 +177,7 @@ void omap_writeb(u8 v, u32 pa)
         if (cpu_class_is_omap1())
                 __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
         else
-                __raw_writeb(v, OMAP2_IO_ADDRESS(pa));
+                __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_writeb);
 
@@ -178,7 +186,7 @@ void omap_writew(u16 v, u32 pa)
         if (cpu_class_is_omap1())
                 __raw_writew(v, OMAP1_IO_ADDRESS(pa));
         else
-                __raw_writew(v, OMAP2_IO_ADDRESS(pa));
+                __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_writew);
 
@@ -187,6 +195,6 @@ void omap_writel(u32 v, u32 pa)
         if (cpu_class_is_omap1())
                 __raw_writel(v, OMAP1_IO_ADDRESS(pa));
         else
-                __raw_writel(v, OMAP2_IO_ADDRESS(pa));
+                __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
 }
 EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c
index c799b3b0d709..afd1c27cff7c 100644
--- a/arch/arm/plat-omap/iommu-debug.c
+++ b/arch/arm/plat-omap/iommu-debug.c
@@ -17,8 +17,8 @@
 #include <linux/platform_device.h>
 #include <linux/debugfs.h>
 
-#include <mach/iommu.h>
-#include <mach/iovmm.h>
+#include <plat/iommu.h>
+#include <plat/iovmm.h>
 
 #include "iopgtable.h"
 
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 94584f167a82..c0ff1e39d893 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -20,7 +20,7 @@
 
 #include <asm/cacheflush.h>
 
-#include <mach/iommu.h>
+#include <plat/iommu.h>
 
 #include "iopgtable.h"
 
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index dc3fac3dd0ea..936aef1971cd 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -18,8 +18,8 @@
 #include <asm/cacheflush.h>
 #include <asm/mach/map.h>
 
-#include <mach/iommu.h>
-#include <mach/iovmm.h>
+#include <plat/iommu.h>
+#include <plat/iovmm.h>
 
 #include "iopgtable.h"
 
@@ -392,7 +392,6 @@ static void sgtable_fill_vmalloc(struct sg_table *sgt, void *_va)
         }
 
         va_end = _va + PAGE_SIZE * i;
-        flush_cache_vmap((unsigned long)_va, (unsigned long)va_end);
 }
 
 static inline void sgtable_drain_vmalloc(struct sg_table *sgt)
@@ -427,8 +426,6 @@ static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
                 len -= bytes;
         }
         BUG_ON(len);
-
-        clean_dcache_area(va, len);
 }
 
 static inline void sgtable_drain_kmalloc(struct sg_table *sgt)
@@ -449,7 +446,7 @@ static int map_iovm_area(struct iommu *obj, struct iovm_struct *new,
         struct scatterlist *sg;
         u32 da = new->da_start;
 
-        if (!obj || !new || !sgt)
+        if (!obj || !sgt)
                 return -EINVAL;
 
         BUG_ON(!sgtable_ok(sgt));
@@ -617,7 +614,7 @@ u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt,
                  u32 flags)
 {
         size_t bytes;
-        void *va;
+        void *va = NULL;
 
         if (!obj || !obj->dev || !sgt)
                 return -EINVAL;
@@ -627,9 +624,11 @@ u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt,
                 return -EINVAL;
         bytes = PAGE_ALIGN(bytes);
 
-        va = vmap_sg(sgt);
-        if (IS_ERR(va))
-                return PTR_ERR(va);
+        if (flags & IOVMF_MMIO) {
+                va = vmap_sg(sgt);
+                if (IS_ERR(va))
+                        return PTR_ERR(va);
+        }
 
         flags &= IOVMF_HW_MASK;
         flags |= IOVMF_DISCONT;
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 40424edae939..8e90633e4cb9 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -26,55 +26,12 @@
 #include <linux/device.h>
 #include <linux/delay.h>
 
-#include <mach/mailbox.h>
-
-static int enable_seq_bit;
-module_param(enable_seq_bit, bool, 0);
-MODULE_PARM_DESC(enable_seq_bit, "Enable sequence bit checking.");
+#include <plat/mailbox.h>
 
 static struct omap_mbox *mboxes;
 static DEFINE_RWLOCK(mboxes_lock);
 
-/*
- * Mailbox sequence bit API
- */
-
-/* seq_rcv should be initialized with any value other than
- * 0 and 1 << 31, to allow either value for the first
- * message.  */
-static inline void mbox_seq_init(struct omap_mbox *mbox)
-{
-        if (!enable_seq_bit)
-                return;
-
-        /* any value other than 0 and 1 << 31 */
-        mbox->seq_rcv = 0xffffffff;
-}
-
-static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg)
-{
-        if (!enable_seq_bit)
-                return;
-
-        /* add seq_snd to msg */
-        *msg = (*msg & 0x7fffffff) | mbox->seq_snd;
-        /* flip seq_snd */
-        mbox->seq_snd ^= 1 << 31;
-}
-
-static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        mbox_msg_t seq;
-
-        if (!enable_seq_bit)
-                return 0;
-
-        seq = msg & (1 << 31);
-        if (seq == mbox->seq_rcv)
-                return -1;
-        mbox->seq_rcv = seq;
-        return 0;
-}
+static int mbox_configured;
 
 /* Mailbox FIFO handle functions */
 static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
@@ -95,14 +52,6 @@ static inline int mbox_fifo_full(struct omap_mbox *mbox)
 }
 
 /* Mailbox IRQ handle functions */
-static inline void enable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        mbox->ops->enable_irq(mbox, irq);
-}
-static inline void disable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        mbox->ops->disable_irq(mbox, irq);
-}
 static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
 {
         if (mbox->ops->ack_irq)
@@ -113,17 +62,10 @@ static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
         return mbox->ops->is_irq(mbox, irq);
 }
 
-/* Mailbox Sequence Bit function */
-void omap_mbox_init_seq(struct omap_mbox *mbox)
-{
-        mbox_seq_init(mbox);
-}
-EXPORT_SYMBOL(omap_mbox_init_seq);
-
 /*
  * message sender
  */
-static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg, void *arg)
+static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
 {
         int ret = 0, i = 1000;
 
@@ -134,89 +76,49 @@ static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg, void *arg)
                         return -1;
                 udelay(1);
         }
-
-        if (arg && mbox->txq->callback) {
-                ret = mbox->txq->callback(arg);
-                if (ret)
-                        goto out;
-        }
-
-        mbox_seq_toggle(mbox, &msg);
         mbox_fifo_write(mbox, msg);
- out:
         return ret;
 }
 
-struct omap_msg_tx_data {
-        mbox_msg_t      msg;
-        void            *arg;
-};
 
-static void omap_msg_tx_end_io(struct request *rq, int error)
+int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
 {
-        kfree(rq->special);
-        __blk_put_request(rq->q, rq);
-}
 
-int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg, void* arg)
-{
-        struct omap_msg_tx_data *tx_data;
         struct request *rq;
         struct request_queue *q = mbox->txq->queue;
 
-        tx_data = kmalloc(sizeof(*tx_data), GFP_ATOMIC);
-        if (unlikely(!tx_data))
-                return -ENOMEM;
-
         rq = blk_get_request(q, WRITE, GFP_ATOMIC);
-        if (unlikely(!rq)) {
-                kfree(tx_data);
+        if (unlikely(!rq))
                 return -ENOMEM;
-        }
 
-        tx_data->msg = msg;
-        tx_data->arg = arg;
-        rq->end_io = omap_msg_tx_end_io;
-        blk_insert_request(q, rq, 0, tx_data);
+        blk_insert_request(q, rq, 0, (void *) msg);
+        tasklet_schedule(&mbox->txq->tasklet);
 
-        schedule_work(&mbox->txq->work);
         return 0;
 }
 EXPORT_SYMBOL(omap_mbox_msg_send);
 
-static void mbox_tx_work(struct work_struct *work)
+static void mbox_tx_tasklet(unsigned long tx_data)
 {
         int ret;
         struct request *rq;
-        struct omap_mbox_queue *mq = container_of(work,
-                                struct omap_mbox_queue, work);
-        struct omap_mbox *mbox = mq->queue->queuedata;
+        struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
         struct request_queue *q = mbox->txq->queue;
 
         while (1) {
-                struct omap_msg_tx_data *tx_data;
 
-                spin_lock(q->queue_lock);
                 rq = blk_fetch_request(q);
-                spin_unlock(q->queue_lock);
 
                 if (!rq)
                         break;
 
-                tx_data = rq->special;
-
-                ret = __mbox_msg_send(mbox, tx_data->msg, tx_data->arg);
+                ret = __mbox_msg_send(mbox, (mbox_msg_t)rq->special);
                 if (ret) {
-                        enable_mbox_irq(mbox, IRQ_TX);
-                        spin_lock(q->queue_lock);
+                        omap_mbox_enable_irq(mbox, IRQ_TX);
                         blk_requeue_request(q, rq);
-                        spin_unlock(q->queue_lock);
                         return;
                 }
-
-                spin_lock(q->queue_lock);
-                __blk_end_request_all(rq, 0);
-                spin_unlock(q->queue_lock);
+                blk_end_request_all(rq, 0);
         }
 }
 
@@ -233,11 +135,6 @@ static void mbox_rx_work(struct work_struct *work)
         mbox_msg_t msg;
         unsigned long flags;
 
-        if (mbox->rxq->callback == NULL) {
-                sysfs_notify(&mbox->dev->kobj, NULL, "mbox");
-                return;
-        }
-
         while (1) {
                 spin_lock_irqsave(q->queue_lock, flags);
                 rq = blk_fetch_request(q);
@@ -254,19 +151,19 @@ static void mbox_rx_work(struct work_struct *work)
 /*
  * Mailbox interrupt handler
  */
-static void mbox_txq_fn(struct request_queue * q)
+static void mbox_txq_fn(struct request_queue *q)
 {
 }
 
-static void mbox_rxq_fn(struct request_queue * q)
+static void mbox_rxq_fn(struct request_queue *q)
 {
 }
 
 static void __mbox_tx_interrupt(struct omap_mbox *mbox)
 {
-        disable_mbox_irq(mbox, IRQ_TX);
+        omap_mbox_disable_irq(mbox, IRQ_TX);
         ack_mbox_irq(mbox, IRQ_TX);
-        schedule_work(&mbox->txq->work);
+        tasklet_schedule(&mbox->txq->tasklet);
 }
 
 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
@@ -275,8 +172,6 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
         mbox_msg_t msg;
         struct request_queue *q = mbox->rxq->queue;
 
-        disable_mbox_irq(mbox, IRQ_RX);
-
         while (!mbox_fifo_empty(mbox)) {
                 rq = blk_get_request(q, WRITE, GFP_ATOMIC);
                 if (unlikely(!rq))
@@ -284,11 +179,6 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 
                 msg = mbox_fifo_read(mbox);
 
-                if (unlikely(mbox_seq_test(mbox, msg))) {
-                        pr_info("mbox: Illegal seq bit!(%08x)\n", msg);
-                        if (mbox->err_notify)
-                                mbox->err_notify();
-                }
 
                 blk_insert_request(q, rq, 0, (void *)msg);
                 if (mbox->ops->type == OMAP_MBOX_TYPE1)
@@ -297,7 +187,6 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 
         /* no more messages in the fifo. clear IRQ source. */
         ack_mbox_irq(mbox, IRQ_RX);
-        enable_mbox_irq(mbox, IRQ_RX);
 nomem:
         schedule_work(&mbox->rxq->work);
 }
@@ -315,76 +204,10 @@ static irqreturn_t mbox_interrupt(int irq, void *p)
         return IRQ_HANDLED;
 }
 
-/*
- * sysfs files
- */
-static ssize_t
-omap_mbox_write(struct device *dev, struct device_attribute *attr,
-                const char * buf, size_t count)
-{
-        int ret;
-        mbox_msg_t *p = (mbox_msg_t *)buf;
-        struct omap_mbox *mbox = dev_get_drvdata(dev);
-
-        for (; count >= sizeof(mbox_msg_t); count -= sizeof(mbox_msg_t)) {
-                ret = omap_mbox_msg_send(mbox, be32_to_cpu(*p), NULL);
-                if (ret)
-                        return -EAGAIN;
-                p++;
-        }
-
-        return (size_t)((char *)p - buf);
-}
-
-static ssize_t
-omap_mbox_read(struct device *dev, struct device_attribute *attr, char *buf)
-{
-        unsigned long flags;
-        struct request *rq;
-        mbox_msg_t *p = (mbox_msg_t *) buf;
-        struct omap_mbox *mbox = dev_get_drvdata(dev);
-        struct request_queue *q = mbox->rxq->queue;
-
-        while (1) {
-                spin_lock_irqsave(q->queue_lock, flags);
-                rq = blk_fetch_request(q);
-                spin_unlock_irqrestore(q->queue_lock, flags);
-
-                if (!rq)
-                        break;
-
-                *p = (mbox_msg_t)rq->special;
-
-                blk_end_request_all(rq, 0);
-
-                if (unlikely(mbox_seq_test(mbox, *p))) {
-                        pr_info("mbox: Illegal seq bit!(%08x) ignored\n", *p);
-                        continue;
-                }
-                p++;
-        }
-
-        pr_debug("%02x %02x %02x %02x\n", buf[0], buf[1], buf[2], buf[3]);
-
-        return (size_t) ((char *)p - buf);
-}
-
-static DEVICE_ATTR(mbox, S_IRUGO | S_IWUSR, omap_mbox_read, omap_mbox_write);
-
-static ssize_t mbox_show(struct class *class, char *buf)
-{
-        return sprintf(buf, "mbox");
-}
-
-static CLASS_ATTR(mbox, S_IRUGO, mbox_show, NULL);
-
-static struct class omap_mbox_class = {
-        .name = "omap-mailbox",
-};
-
 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
-                                        request_fn_proc * proc,
-                                        void (*work) (struct work_struct *))
+                                        request_fn_proc *proc,
+                                        void (*work) (struct work_struct *),
+                                        void (*tasklet)(unsigned long))
 {
         struct request_queue *q;
         struct omap_mbox_queue *mq;
@@ -401,8 +224,11 @@ static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
         q->queuedata = mbox;
         mq->queue = q;
 
-        INIT_WORK(&mq->work, work);
+        if (work)
+                INIT_WORK(&mq->work, work);
 
+        if (tasklet)
+                tasklet_init(&mq->tasklet, tasklet, (unsigned long)mbox);
         return mq;
 error:
         kfree(mq);
@@ -415,18 +241,25 @@ static void mbox_queue_free(struct omap_mbox_queue *q)
         kfree(q);
 }
 
-static int omap_mbox_init(struct omap_mbox *mbox)
+static int omap_mbox_startup(struct omap_mbox *mbox)
 {
-        int ret;
+        int ret = 0;
         struct omap_mbox_queue *mq;
 
         if (likely(mbox->ops->startup)) {
-                ret = mbox->ops->startup(mbox);
-                if (unlikely(ret))
+                write_lock(&mboxes_lock);
+                if (!mbox_configured)
+                        ret = mbox->ops->startup(mbox);
+
+                if (unlikely(ret)) {
+                        write_unlock(&mboxes_lock);
                         return ret;
+                }
+                mbox_configured++;
+                write_unlock(&mboxes_lock);
         }
 
-        ret = request_irq(mbox->irq, mbox_interrupt, IRQF_DISABLED,
+        ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
                                 mbox->name, mbox);
         if (unlikely(ret)) {
                 printk(KERN_ERR
@@ -434,14 +267,14 @@ static int omap_mbox_init(struct omap_mbox *mbox)
                 goto fail_request_irq;
         }
 
-        mq = mbox_queue_alloc(mbox, mbox_txq_fn, mbox_tx_work);
+        mq = mbox_queue_alloc(mbox, mbox_txq_fn, NULL, mbox_tx_tasklet);
         if (!mq) {
                 ret = -ENOMEM;
                 goto fail_alloc_txq;
         }
         mbox->txq = mq;
 
-        mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work);
+        mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work, NULL);
         if (!mq) {
                 ret = -ENOMEM;
                 goto fail_alloc_rxq;
@@ -468,8 +301,14 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 
         free_irq(mbox->irq, mbox);
 
-        if (unlikely(mbox->ops->shutdown))
-                mbox->ops->shutdown(mbox);
+        if (unlikely(mbox->ops->shutdown)) {
+                write_lock(&mboxes_lock);
+                if (mbox_configured > 0)
+                        mbox_configured--;
+                if (!mbox_configured)
+                        mbox->ops->shutdown(mbox);
+                write_unlock(&mboxes_lock);
+        }
 }
 
 static struct omap_mbox **find_mboxes(const char *name)
@@ -498,7 +337,7 @@ struct omap_mbox *omap_mbox_get(const char *name)
 
         read_unlock(&mboxes_lock);
 
-        ret = omap_mbox_init(mbox);
+        ret = omap_mbox_startup(mbox);
         if (ret)
                 return ERR_PTR(-ENODEV);
 
@@ -522,15 +361,6 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
         if (mbox->next)
                 return -EBUSY;
 
-        mbox->dev = device_create(&omap_mbox_class,
-                                  parent, 0, mbox, "%s", mbox->name);
-        if (IS_ERR(mbox->dev))
-                return PTR_ERR(mbox->dev);
-
-        ret = device_create_file(mbox->dev, &dev_attr_mbox);
-        if (ret)
-                goto err_sysfs;
-
         write_lock(&mboxes_lock);
         tmp = find_mboxes(mbox->name);
         if (*tmp) {
@@ -544,9 +374,6 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
         return 0;
 
 err_find:
-        device_remove_file(mbox->dev, &dev_attr_mbox);
-err_sysfs:
-        device_unregister(mbox->dev);
         return ret;
 }
 EXPORT_SYMBOL(omap_mbox_register);
@@ -562,8 +389,6 @@ int omap_mbox_unregister(struct omap_mbox *mbox)
                         *tmp = mbox->next;
                         mbox->next = NULL;
                         write_unlock(&mboxes_lock);
-                        device_remove_file(mbox->dev, &dev_attr_mbox);
-                        device_unregister(mbox->dev);
                         return 0;
                 }
                 tmp = &(*tmp)->next;
@@ -574,23 +399,16 @@ int omap_mbox_unregister(struct omap_mbox *mbox)
 }
 EXPORT_SYMBOL(omap_mbox_unregister);
 
-static int __init omap_mbox_class_init(void)
+static int __init omap_mbox_init(void)
 {
-        int ret = class_register(&omap_mbox_class);
-        if (!ret)
-                ret = class_create_file(&omap_mbox_class, &class_attr_mbox);
-
-        return ret;
+        return 0;
 }
+module_init(omap_mbox_init);
 
-static void __exit omap_mbox_class_exit(void)
+static void __exit omap_mbox_exit(void)
 {
-        class_remove_file(&omap_mbox_class, &class_attr_mbox);
-        class_unregister(&omap_mbox_class);
 }
-
-subsys_initcall(omap_mbox_class_init);
-module_exit(omap_mbox_class_exit);
+module_exit(omap_mbox_exit);
 
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index e664b912d7bb..2cc1cc328bac 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -24,8 +24,8 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 
-#include <mach/dma.h>
-#include <mach/mcbsp.h>
+#include <plat/dma.h>
+#include <plat/mcbsp.h>
 
 struct omap_mcbsp **mcbsp_ptr;
 int omap_mcbsp_count;
@@ -298,9 +298,7 @@ int omap_mcbsp_get_dma_op_mode(unsigned int id)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
-        spin_lock_irq(&mcbsp->lock);
         dma_op_mode = mcbsp->dma_op_mode;
-        spin_unlock_irq(&mcbsp->lock);
 
         return dma_op_mode;
 }
@@ -318,7 +316,6 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 
-                spin_lock_irq(&mcbsp->lock);
                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
                                         CLOCKACTIVITY(0x02));
@@ -327,7 +324,6 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
                 } else {
                         syscon |= SIDLEMODE(0x01);
                 }
-                spin_unlock_irq(&mcbsp->lock);
 
                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
         }
@@ -1145,9 +1141,7 @@ static ssize_t dma_op_mode_show(struct device *dev,
         ssize_t len = 0;
         const char * const *s;
 
-        spin_lock_irq(&mcbsp->lock);
         dma_op_mode = mcbsp->dma_op_mode;
-        spin_unlock_irq(&mcbsp->lock);
 
         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
                 if (dma_op_mode == i)
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 8d329fb20740..05aebcad215b 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -28,7 +28,7 @@
 #include <linux/io.h>
 #include <asm/system.h>
 #include <linux/spinlock.h>
-#include <mach/mux.h>
+#include <plat/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
 
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index e98f0a2a6c26..186bca82cfab 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -22,9 +22,9 @@
 #include <linux/device.h>
 
 /* Interface documentation is in mach/omap-pm.h */
-#include <mach/omap-pm.h>
+#include <plat/omap-pm.h>
 
-#include <mach/powerdomain.h>
+#include <plat/powerdomain.h>
 
 struct omap_opp *dsp_opps;
 struct omap_opp *mpu_opps;
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 2c409fc6dd21..bb16e624a557 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -82,8 +82,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <mach/omap_device.h>
-#include <mach/omap_hwmod.h>
+#include <plat/omap_device.h>
+#include <plat/omap_hwmod.h>
 
 /* These parameters are passed to _omap_device_{de,}activate() */
 #define USE_WAKEUP_LAT                  0
@@ -103,21 +103,6 @@
 /* Private functions */
 
 /**
- * _read_32ksynct - read the OMAP 32K sync timer
- *
- * Returns the current value of the 32KiHz synchronization counter.
- * XXX this should be generalized to simply read the system clocksource.
- * XXX this should be moved to a separate synctimer32k.c file
- */
-static u32 _read_32ksynct(void)
-{
-        if (!cpu_class_is_omap2())
-                BUG();
-
-        return __raw_readl(OMAP2_IO_ADDRESS(OMAP_32KSYNCT_BASE + 0x010));
-}
-
-/**
  * _omap_device_activate - increase device readiness
  * @od: struct omap_device *
  * @ignore_lat: increase to latency target (0) or full readiness (1)?
@@ -133,13 +118,13 @@ static u32 _read_32ksynct(void)
  */
 static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
 {
-        u32 a, b;
+        struct timespec a, b, c;
 
         pr_debug("omap_device: %s: activating\n", od->pdev.name);
 
         while (od->pm_lat_level > 0) {
                 struct omap_device_pm_latency *odpl;
-                int act_lat = 0;
+                unsigned long long act_lat = 0;
 
                 od->pm_lat_level--;
 
@@ -149,20 +134,22 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
                     (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
                         break;
 
-                a = _read_32ksynct();
+                getnstimeofday(&a);
 
                 /* XXX check return code */
                 odpl->activate_func(od);
 
-                b = _read_32ksynct();
+                getnstimeofday(&b);
 
-                act_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
+                c = timespec_sub(b, a);
+                act_lat = timespec_to_ns(&c) * NSEC_PER_USEC;
 
                 pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time "
-                         "%d usec\n", od->pdev.name, od->pm_lat_level, act_lat);
+                         "%llu usec\n", od->pdev.name, od->pm_lat_level,
+                         act_lat);
 
                 WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: "
-                     "activate step %d took longer than expected (%d > %d)\n",
+                     "activate step %d took longer than expected (%llu > %d)\n",
                      od->pdev.name, od->pdev.id, od->pm_lat_level,
                      act_lat, odpl->activate_lat);
 
@@ -188,13 +175,13 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
  */
 static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
 {
-        u32 a, b;
+        struct timespec a, b, c;
 
         pr_debug("omap_device: %s: deactivating\n", od->pdev.name);
 
         while (od->pm_lat_level < od->pm_lats_cnt) {
                 struct omap_device_pm_latency *odpl;
-                int deact_lat = 0;
+                unsigned long long deact_lat = 0;
 
                 odpl = od->pm_lats + od->pm_lat_level;
 
@@ -203,23 +190,24 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
                      od->_dev_wakeup_lat_limit))
                         break;
 
-                a = _read_32ksynct();
+                getnstimeofday(&a);
 
                 /* XXX check return code */
                 odpl->deactivate_func(od);
 
-                b = _read_32ksynct();
+                getnstimeofday(&b);
 
-                deact_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
+                c = timespec_sub(b, a);
+                deact_lat = timespec_to_ns(&c) * NSEC_PER_USEC;
 
                 pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time "
-                         "%d usec\n", od->pdev.name, od->pm_lat_level,
+                         "%llu usec\n", od->pdev.name, od->pm_lat_level,
                          deact_lat);
 
                 WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: "
-                     "deactivate step %d took longer than expected (%d > %d)\n",
-                     od->pdev.name, od->pdev.id, od->pm_lat_level,
-                     deact_lat, odpl->deactivate_lat);
+                     "deactivate step %d took longer than expected "
+                     "(%llu > %d)\n", od->pdev.name, od->pdev.id,
+                     od->pm_lat_level, deact_lat, odpl->deactivate_lat);
 
                 od->dev_wakeup_lat += odpl->activate_lat;
 
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 75d1f26e5b17..3e923668778d 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -25,11 +25,11 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/sram.h>
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <plat/sram.h>
+#include <plat/board.h>
+#include <plat/cpu.h>
 
-#include <mach/control.h>
+#include <plat/control.h>
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 # include "../mach-omap2/prm.h"
@@ -41,14 +41,14 @@
 #define OMAP1_SRAM_VA           VMALLOC_END
 #define OMAP2_SRAM_PA           0x40200000
 #define OMAP2_SRAM_PUB_PA       0x4020f800
-#define OMAP2_SRAM_VA           0xe3000000
+#define OMAP2_SRAM_VA           0xfe400000
 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
 #define OMAP3_SRAM_PA           0x40200000
-#define OMAP3_SRAM_VA           0xe3000000
+#define OMAP3_SRAM_VA           0xfe400000
 #define OMAP3_SRAM_PUB_PA       0x40208000
 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
 #define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
-#define OMAP4_SRAM_VA           0xd7000000              /*0xd70f0000*/
+#define OMAP4_SRAM_VA           0xfe400000              /*0xfe4f0000*/
 
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 #define SRAM_BOOTLOADER_SZ      0x00
@@ -56,16 +56,16 @@
 #define SRAM_BOOTLOADER_SZ      0x80
 #endif
 
-#define OMAP24XX_VA_REQINFOPERM0        OMAP2_IO_ADDRESS(0x68005048)
-#define OMAP24XX_VA_READPERM0           OMAP2_IO_ADDRESS(0x68005050)
-#define OMAP24XX_VA_WRITEPERM0          OMAP2_IO_ADDRESS(0x68005058)
+#define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
+#define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
+#define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
 
-#define OMAP34XX_VA_REQINFOPERM0        OMAP2_IO_ADDRESS(0x68012848)
-#define OMAP34XX_VA_READPERM0           OMAP2_IO_ADDRESS(0x68012850)
-#define OMAP34XX_VA_WRITEPERM0          OMAP2_IO_ADDRESS(0x68012858)
-#define OMAP34XX_VA_ADDR_MATCH2         OMAP2_IO_ADDRESS(0x68012880)
-#define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_IO_ADDRESS(0x6C000048)
-#define OMAP34XX_VA_CONTROL_STAT        OMAP2_IO_ADDRESS(0x480022F0)
+#define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
+#define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
+#define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
+#define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
+#define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
+#define OMAP34XX_VA_CONTROL_STAT        OMAP2_L4_IO_ADDRESS(0x480022F0)
 
 #define GP_DEVICE               0x300
 
@@ -396,22 +396,24 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 }
 
-/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
-void restore_sram_functions(void)
+#ifdef CONFIG_PM
+void omap3_sram_restore_context(void)
 {
         omap_sram_ceil = omap_sram_base + omap_sram_size;
 
         _omap3_sram_configure_core_dpll =
                 omap_sram_push(omap3_sram_configure_core_dpll,
                                omap3_sram_configure_core_dpll_sz);
+        omap_push_sram_idle();
 }
+#endif /* CONFIG_PM */
 
 int __init omap34xx_sram_init(void)
 {
         _omap3_sram_configure_core_dpll =
                 omap_sram_push(omap3_sram_configure_core_dpll,
                                omap3_sram_configure_core_dpll_sz);
-
+        omap_push_sram_idle();
         return 0;
 }
 #else
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 509f2ed99e21..51033a4503c3 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -33,10 +33,10 @@
 #include <asm/system.h>
 #include <mach/hardware.h>
 
-#include <mach/control.h>
-#include <mach/mux.h>
-#include <mach/usb.h>
-#include <mach/board.h>
+#include <plat/control.h>
+#include <plat/mux.h>
+#include <plat/usb.h>
+#include <plat/board.h>
 
 #ifdef CONFIG_ARCH_OMAP1
 
@@ -159,11 +159,14 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
                  *  - OTG support on this port not yet written
                  */
 
-                l = omap_readl(USB_TRANSCEIVER_CTRL);
-                l &= ~(7 << 4);
-                if (!is_device)
-                        l |= (3 << 1);
-                omap_writel(l, USB_TRANSCEIVER_CTRL);
+                /* Don't do this for omap7xx -- it causes USB to not work correctly */
+                if (!cpu_is_omap7xx()) {
+                        l = omap_readl(USB_TRANSCEIVER_CTRL);
+                        l &= ~(7 << 4);
+                        if (!is_device)
+                                l |= (3 << 1);
+                        omap_writel(l, USB_TRANSCEIVER_CTRL);
+                }
 
                 return 3 << 16;
         }
@@ -603,7 +606,12 @@ omap_otg_init(struct omap_usb_config *config)
         if (config->otg || config->register_dev) {
                 syscon &= ~DEV_IDLE_EN;
                 udc_device.dev.platform_data = config;
-                /* FIXME patch IRQ numbers for omap730 */
+                /* IRQ numbers for omap7xx */
+                if(cpu_is_omap7xx()) {
+                        udc_resources[1].start = INT_7XX_USB_GENI;
+                        udc_resources[2].start = INT_7XX_USB_NON_ISO;
+                        udc_resources[3].start = INT_7XX_USB_ISO;
+                }
                 status = platform_device_register(&udc_device);
                 if (status)
                         pr_debug("can't register UDC device, %d\n", status);
@@ -614,8 +622,8 @@ omap_otg_init(struct omap_usb_config *config)
         if (config->otg || config->register_host) {
                 syscon &= ~HST_IDLE_EN;
                 ohci_device.dev.platform_data = config;
-                if (cpu_is_omap730())
-                        ohci_resources[1].start = INT_730_USB_HHC_1;
+                if (cpu_is_omap7xx())
+                        ohci_resources[1].start = INT_7XX_USB_HHC_1;
                 status = platform_device_register(&ohci_device);
                 if (status)
                         pr_debug("can't register OHCI device, %d\n", status);
@@ -626,8 +634,8 @@ omap_otg_init(struct omap_usb_config *config)
         if (config->otg) {
                 syscon &= ~OTG_IDLE_EN;
                 otg_device.dev.platform_data = config;
-                if (cpu_is_omap730())
-                        otg_resources[1].start = INT_730_USB_OTG;
+                if (cpu_is_omap7xx())
+                        otg_resources[1].start = INT_7XX_USB_OTG;
                 status = platform_device_register(&otg_device);
                 if (status)
                         pr_debug("can't register OTG device, %d\n", status);
@@ -731,7 +739,7 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
 
 void __init omap_usb_init(struct omap_usb_config *pdata)
 {
-        if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx())
+        if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
                 omap_otg_init(pdata);
         else if (cpu_is_omap15xx())
                 omap_1510_usb_init(pdata);