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-rw-r--r--arch/arm/plat-omap/Kconfig9
-rw-r--r--arch/arm/plat-omap/clock.c25
-rw-r--r--arch/arm/plat-omap/common.c3
-rw-r--r--arch/arm/plat-omap/dma.c45
-rw-r--r--arch/arm/plat-omap/dmtimer.c4
-rw-r--r--arch/arm/plat-omap/gpio.c236
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h14
-rw-r--r--arch/arm/plat-omap/include/plat/common.h3
-rw-r--r--arch/arm/plat-omap/include/plat/control.h20
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h4
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h4
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h4
-rw-r--r--arch/arm/plat-omap/include/plat/multi.h16
-rw-r--r--arch/arm/plat-omap/include/plat/omap44xx.h4
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h16
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h7
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h16
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h44
-rw-r--r--arch/arm/plat-omap/iommu.c101
-rw-r--r--arch/arm/plat-omap/iovmm.c9
-rw-r--r--arch/arm/plat-omap/omap_device.c4
-rw-r--r--arch/arm/plat-omap/sram.c16
22 files changed, 334 insertions, 270 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 6da796ef82bd..78b49a626d06 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -110,8 +110,13 @@ config OMAP_IOMMU
110 tristate 110 tristate
111 111
112config OMAP_IOMMU_DEBUG 112config OMAP_IOMMU_DEBUG
113 depends on OMAP_IOMMU 113 tristate "Export OMAP IOMMU internals in DebugFS"
114 tristate 114 depends on OMAP_IOMMU && DEBUG_FS
115 help
116 Select this to see extensive information about
117 the internal state of OMAP IOMMU in debugfs.
118
119 Say N unless you know you need this.
115 120
116choice 121choice
117 prompt "System timer" 122 prompt "System timer"
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 5261a0923691..7190cbd92620 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -12,14 +12,12 @@
12 */ 12 */
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/list.h> 15#include <linux/list.h>
17#include <linux/errno.h> 16#include <linux/errno.h>
18#include <linux/err.h> 17#include <linux/err.h>
19#include <linux/string.h> 18#include <linux/string.h>
20#include <linux/clk.h> 19#include <linux/clk.h>
21#include <linux/mutex.h> 20#include <linux/mutex.h>
22#include <linux/platform_device.h>
23#include <linux/cpufreq.h> 21#include <linux/cpufreq.h>
24#include <linux/debugfs.h> 22#include <linux/debugfs.h>
25#include <linux/io.h> 23#include <linux/io.h>
@@ -32,9 +30,9 @@ static DEFINE_SPINLOCK(clockfw_lock);
32 30
33static struct clk_functions *arch_clock; 31static struct clk_functions *arch_clock;
34 32
35/*------------------------------------------------------------------------- 33/*
36 * Standard clock functions defined in include/linux/clk.h 34 * Standard clock functions defined in include/linux/clk.h
37 *-------------------------------------------------------------------------*/ 35 */
38 36
39int clk_enable(struct clk *clk) 37int clk_enable(struct clk *clk)
40{ 38{
@@ -92,9 +90,9 @@ unsigned long clk_get_rate(struct clk *clk)
92} 90}
93EXPORT_SYMBOL(clk_get_rate); 91EXPORT_SYMBOL(clk_get_rate);
94 92
95/*------------------------------------------------------------------------- 93/*
96 * Optional clock functions defined in include/linux/clk.h 94 * Optional clock functions defined in include/linux/clk.h
97 *-------------------------------------------------------------------------*/ 95 */
98 96
99long clk_round_rate(struct clk *clk, unsigned long rate) 97long clk_round_rate(struct clk *clk, unsigned long rate)
100{ 98{
@@ -140,9 +138,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
140 unsigned long flags; 138 unsigned long flags;
141 int ret = -EINVAL; 139 int ret = -EINVAL;
142 140
143 if (cpu_is_omap44xx())
144 /* OMAP4 clk framework not supported yet */
145 return 0;
146 if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) 141 if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
147 return ret; 142 return ret;
148 143
@@ -169,9 +164,9 @@ struct clk *clk_get_parent(struct clk *clk)
169} 164}
170EXPORT_SYMBOL(clk_get_parent); 165EXPORT_SYMBOL(clk_get_parent);
171 166
172/*------------------------------------------------------------------------- 167/*
173 * OMAP specific clock functions shared between omap1 and omap2 168 * OMAP specific clock functions shared between omap1 and omap2
174 *-------------------------------------------------------------------------*/ 169 */
175 170
176int __initdata mpurate; 171int __initdata mpurate;
177 172
@@ -222,7 +217,7 @@ void clk_reparent(struct clk *child, struct clk *parent)
222} 217}
223 218
224/* Propagate rate to children */ 219/* Propagate rate to children */
225void propagate_rate(struct clk * tclk) 220void propagate_rate(struct clk *tclk)
226{ 221{
227 struct clk *clkp; 222 struct clk *clkp;
228 223
@@ -389,7 +384,9 @@ void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
389} 384}
390#endif 385#endif
391 386
392/*-------------------------------------------------------------------------*/ 387/*
388 *
389 */
393 390
394#ifdef CONFIG_OMAP_RESET_CLOCKS 391#ifdef CONFIG_OMAP_RESET_CLOCKS
395/* 392/*
@@ -404,7 +401,7 @@ static int __init clk_disable_unused(void)
404 if (ck->ops == &clkops_null) 401 if (ck->ops == &clkops_null)
405 continue; 402 continue;
406 403
407 if (ck->usecount > 0 || ck->enable_reg == 0) 404 if (ck->usecount > 0 || !ck->enable_reg)
408 continue; 405 continue;
409 406
410 spin_lock_irqsave(&clockfw_lock, flags); 407 spin_lock_irqsave(&clockfw_lock, flags);
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index f12f0e39ddf2..219c01e82bc5 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -47,9 +47,6 @@
47struct omap_board_config_kernel *omap_board_config; 47struct omap_board_config_kernel *omap_board_config;
48int omap_board_config_size; 48int omap_board_config_size;
49 49
50/* used by omap-smp.c and board-4430sdp.c */
51void __iomem *gic_cpu_base_addr;
52
53static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) 50static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
54{ 51{
55 struct omap_board_config_kernel *kinfo = NULL; 52 struct omap_board_config_kernel *kinfo = NULL;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 1d959965ff52..f7f571e7987e 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -501,7 +501,8 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
501 burst = 0x2; 501 burst = 0x2;
502 break; 502 break;
503 } 503 }
504 /* not supported by current hardware on OMAP1 504 /*
505 * not supported by current hardware on OMAP1
505 * w |= (0x03 << 7); 506 * w |= (0x03 << 7);
506 * fall through 507 * fall through
507 */ 508 */
@@ -510,7 +511,8 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
510 burst = 0x3; 511 burst = 0x3;
511 break; 512 break;
512 } 513 }
513 /* OMAP1 don't support burst 16 514 /*
515 * OMAP1 don't support burst 16
514 * fall through 516 * fall through
515 */ 517 */
516 default: 518 default:
@@ -604,7 +606,8 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
604 burst = 0x3; 606 burst = 0x3;
605 break; 607 break;
606 } 608 }
607 /* OMAP1 don't support burst 16 609 /*
610 * OMAP1 don't support burst 16
608 * fall through 611 * fall through
609 */ 612 */
610 default: 613 default:
@@ -709,6 +712,21 @@ static inline void omap2_enable_irq_lch(int lch)
709 spin_unlock_irqrestore(&dma_chan_lock, flags); 712 spin_unlock_irqrestore(&dma_chan_lock, flags);
710} 713}
711 714
715static inline void omap2_disable_irq_lch(int lch)
716{
717 u32 val;
718 unsigned long flags;
719
720 if (!cpu_class_is_omap2())
721 return;
722
723 spin_lock_irqsave(&dma_chan_lock, flags);
724 val = dma_read(IRQENABLE_L0);
725 val &= ~(1 << lch);
726 dma_write(val, IRQENABLE_L0);
727 spin_unlock_irqrestore(&dma_chan_lock, flags);
728}
729
712int omap_request_dma(int dev_id, const char *dev_name, 730int omap_request_dma(int dev_id, const char *dev_name,
713 void (*callback)(int lch, u16 ch_status, void *data), 731 void (*callback)(int lch, u16 ch_status, void *data),
714 void *data, int *dma_ch_out) 732 void *data, int *dma_ch_out)
@@ -807,14 +825,7 @@ void omap_free_dma(int lch)
807 } 825 }
808 826
809 if (cpu_class_is_omap2()) { 827 if (cpu_class_is_omap2()) {
810 u32 val; 828 omap2_disable_irq_lch(lch);
811
812 spin_lock_irqsave(&dma_chan_lock, flags);
813 /* Disable interrupts */
814 val = dma_read(IRQENABLE_L0);
815 val &= ~(1 << lch);
816 dma_write(val, IRQENABLE_L0);
817 spin_unlock_irqrestore(&dma_chan_lock, flags);
818 829
819 /* Clear the CSR register and IRQ status register */ 830 /* Clear the CSR register and IRQ status register */
820 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); 831 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
@@ -1277,8 +1288,10 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1277 return -EINVAL; 1288 return -EINVAL;
1278 } 1289 }
1279 1290
1280 /* Allocate a queue to maintain the status of the channels 1291 /*
1281 * in the chain */ 1292 * Allocate a queue to maintain the status of the channels
1293 * in the chain
1294 */
1282 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL); 1295 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1283 if (channels == NULL) { 1296 if (channels == NULL) {
1284 printk(KERN_ERR "omap_dma: No memory for channel queue\n"); 1297 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
@@ -1907,7 +1920,8 @@ static int omap2_dma_handle_ch(int ch)
1907 printk(KERN_INFO "DMA transaction error with device %d\n", 1920 printk(KERN_INFO "DMA transaction error with device %d\n",
1908 dma_chan[ch].dev_id); 1921 dma_chan[ch].dev_id);
1909 if (cpu_class_is_omap2()) { 1922 if (cpu_class_is_omap2()) {
1910 /* Errata: sDMA Channel is not disabled 1923 /*
1924 * Errata: sDMA Channel is not disabled
1911 * after a transaction error. So we explicitely 1925 * after a transaction error. So we explicitely
1912 * disable the channel 1926 * disable the channel
1913 */ 1927 */
@@ -2107,6 +2121,9 @@ static int __init omap_init_dma(void)
2107 2121
2108 for (ch = 0; ch < dma_chan_count; ch++) { 2122 for (ch = 0; ch < dma_chan_count; ch++) {
2109 omap_clear_dma(ch); 2123 omap_clear_dma(ch);
2124 if (cpu_class_is_omap2())
2125 omap2_disable_irq_lch(ch);
2126
2110 dma_chan[ch].dev_id = -1; 2127 dma_chan[ch].dev_id = -1;
2111 dma_chan[ch].next_lch = -1; 2128 dma_chan[ch].next_lch = -1;
2112 2129
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 4d99dfbc8bef..c64875f11fac 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -264,8 +264,8 @@ static struct omap_dm_timer omap4_dm_timers[] = {
264 { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 }, 264 { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
265}; 265};
266static const char *omap4_dm_source_names[] __initdata = { 266static const char *omap4_dm_source_names[] __initdata = {
267 "sys_ck", 267 "sys_clkin_ck",
268 "omap_32k_fck", 268 "sys_32k_ck",
269 NULL 269 NULL
270}; 270};
271static struct clk *omap4_dm_source_clocks[2]; 271static struct clk *omap4_dm_source_clocks[2];
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 45a225d09125..dc2ac42d6319 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -27,6 +27,7 @@
27#include <mach/irqs.h> 27#include <mach/irqs.h>
28#include <mach/gpio.h> 28#include <mach/gpio.h>
29#include <asm/mach/irq.h> 29#include <asm/mach/irq.h>
30#include <plat/powerdomain.h>
30 31
31/* 32/*
32 * OMAP1510 GPIO registers 33 * OMAP1510 GPIO registers
@@ -137,7 +138,11 @@
137#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 138#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138#define OMAP4_GPIO_IRQWAKEN0 0x0044 139#define OMAP4_GPIO_IRQWAKEN0 0x0044
139#define OMAP4_GPIO_IRQWAKEN1 0x0048 140#define OMAP4_GPIO_IRQWAKEN1 0x0048
140#define OMAP4_GPIO_SYSSTATUS 0x0104 141#define OMAP4_GPIO_SYSSTATUS 0x0114
142#define OMAP4_GPIO_IRQENABLE1 0x011c
143#define OMAP4_GPIO_WAKE_EN 0x0120
144#define OMAP4_GPIO_IRQSTATUS2 0x0128
145#define OMAP4_GPIO_IRQENABLE2 0x012c
141#define OMAP4_GPIO_CTRL 0x0130 146#define OMAP4_GPIO_CTRL 0x0130
142#define OMAP4_GPIO_OE 0x0134 147#define OMAP4_GPIO_OE 0x0134
143#define OMAP4_GPIO_DATAIN 0x0138 148#define OMAP4_GPIO_DATAIN 0x0138
@@ -148,6 +153,10 @@
148#define OMAP4_GPIO_FALLINGDETECT 0x014c 153#define OMAP4_GPIO_FALLINGDETECT 0x014c
149#define OMAP4_GPIO_DEBOUNCENABLE 0x0150 154#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 155#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
156#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
157#define OMAP4_GPIO_SETIRQENABLE1 0x0164
158#define OMAP4_GPIO_CLEARWKUENA 0x0180
159#define OMAP4_GPIO_SETWKUENA 0x0184
151#define OMAP4_GPIO_CLEARDATAOUT 0x0190 160#define OMAP4_GPIO_CLEARDATAOUT 0x0190
152#define OMAP4_GPIO_SETDATAOUT 0x0194 161#define OMAP4_GPIO_SETDATAOUT 0x0194
153/* 162/*
@@ -195,6 +204,7 @@ struct gpio_bank {
195 struct gpio_chip chip; 204 struct gpio_chip chip;
196 struct clk *dbck; 205 struct clk *dbck;
197 u32 mod_usage; 206 u32 mod_usage;
207 u32 dbck_enable_mask;
198}; 208};
199 209
200#define METHOD_MPUIO 0 210#define METHOD_MPUIO 0
@@ -303,8 +313,6 @@ struct omap3_gpio_regs {
303 u32 risingdetect; 313 u32 risingdetect;
304 u32 fallingdetect; 314 u32 fallingdetect;
305 u32 dataout; 315 u32 dataout;
306 u32 setwkuena;
307 u32 setdataout;
308}; 316};
309 317
310static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; 318static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
@@ -591,12 +599,16 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
591 reg += OMAP7XX_GPIO_DATA_OUTPUT; 599 reg += OMAP7XX_GPIO_DATA_OUTPUT;
592 break; 600 break;
593#endif 601#endif
594#ifdef CONFIG_ARCH_OMAP2PLUS 602#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
595 case METHOD_GPIO_24XX: 603 case METHOD_GPIO_24XX:
596 case METHOD_GPIO_44XX:
597 reg += OMAP24XX_GPIO_DATAOUT; 604 reg += OMAP24XX_GPIO_DATAOUT;
598 break; 605 break;
599#endif 606#endif
607#ifdef CONFIG_ARCH_OMAP4
608 case METHOD_GPIO_44XX:
609 reg += OMAP4_GPIO_DATAOUT;
610 break;
611#endif
600 default: 612 default:
601 return -EINVAL; 613 return -EINVAL;
602 } 614 }
@@ -646,6 +658,7 @@ void omap_set_gpio_debounce(int gpio, int enable)
646 goto done; 658 goto done;
647 659
648 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 660 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
661 bank->dbck_enable_mask = val;
649 if (enable) 662 if (enable)
650 clk_enable(bank->dbck); 663 clk_enable(bank->dbck);
651 else 664 else
@@ -724,15 +737,27 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
724 OMAP4_GPIO_IRQWAKEN0); 737 OMAP4_GPIO_IRQWAKEN0);
725 } 738 }
726 } else { 739 } else {
727 if (trigger != 0) 740 /*
741 * GPIO wakeup request can only be generated on edge
742 * transitions
743 */
744 if (trigger & IRQ_TYPE_EDGE_BOTH)
728 __raw_writel(1 << gpio, bank->base 745 __raw_writel(1 << gpio, bank->base
729 + OMAP24XX_GPIO_SETWKUENA); 746 + OMAP24XX_GPIO_SETWKUENA);
730 else 747 else
731 __raw_writel(1 << gpio, bank->base 748 __raw_writel(1 << gpio, bank->base
732 + OMAP24XX_GPIO_CLEARWKUENA); 749 + OMAP24XX_GPIO_CLEARWKUENA);
733 } 750 }
734 } else { 751 }
735 if (trigger != 0) 752 /* This part needs to be executed always for OMAP34xx */
753 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
754 /*
755 * Log the edge gpio and manually trigger the IRQ
756 * after resume if the input level changes
757 * to avoid irq lost during PER RET/OFF mode
758 * Applies for omap2 non-wakeup gpio and all omap3 gpios
759 */
760 if (trigger & IRQ_TYPE_EDGE_BOTH)
736 bank->enabled_non_wakeup_gpios |= gpio_bit; 761 bank->enabled_non_wakeup_gpios |= gpio_bit;
737 else 762 else
738 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 763 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
@@ -1200,11 +1225,17 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1200#endif 1225#endif
1201 if (!cpu_class_is_omap1()) { 1226 if (!cpu_class_is_omap1()) {
1202 if (!bank->mod_usage) { 1227 if (!bank->mod_usage) {
1228 void __iomem *reg = bank->base;
1203 u32 ctrl; 1229 u32 ctrl;
1204 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); 1230
1205 ctrl &= 0xFFFFFFFE; 1231 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1232 reg += OMAP24XX_GPIO_CTRL;
1233 else if (cpu_is_omap44xx())
1234 reg += OMAP4_GPIO_CTRL;
1235 ctrl = __raw_readl(reg);
1206 /* Module is enabled, clocks are not gated */ 1236 /* Module is enabled, clocks are not gated */
1207 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL); 1237 ctrl &= 0xFFFFFFFE;
1238 __raw_writel(ctrl, reg);
1208 } 1239 }
1209 bank->mod_usage |= 1 << offset; 1240 bank->mod_usage |= 1 << offset;
1210 } 1241 }
@@ -1226,22 +1257,34 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1226 __raw_writel(1 << offset, reg); 1257 __raw_writel(1 << offset, reg);
1227 } 1258 }
1228#endif 1259#endif
1229#ifdef CONFIG_ARCH_OMAP2PLUS 1260#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1230 if ((bank->method == METHOD_GPIO_24XX) || 1261 if (bank->method == METHOD_GPIO_24XX) {
1231 (bank->method == METHOD_GPIO_44XX)) {
1232 /* Disable wake-up during idle for dynamic tick */ 1262 /* Disable wake-up during idle for dynamic tick */
1233 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1263 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1234 __raw_writel(1 << offset, reg); 1264 __raw_writel(1 << offset, reg);
1235 } 1265 }
1236#endif 1266#endif
1267#ifdef CONFIG_ARCH_OMAP4
1268 if (bank->method == METHOD_GPIO_44XX) {
1269 /* Disable wake-up during idle for dynamic tick */
1270 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1271 __raw_writel(1 << offset, reg);
1272 }
1273#endif
1237 if (!cpu_class_is_omap1()) { 1274 if (!cpu_class_is_omap1()) {
1238 bank->mod_usage &= ~(1 << offset); 1275 bank->mod_usage &= ~(1 << offset);
1239 if (!bank->mod_usage) { 1276 if (!bank->mod_usage) {
1277 void __iomem *reg = bank->base;
1240 u32 ctrl; 1278 u32 ctrl;
1241 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); 1279
1280 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1281 reg += OMAP24XX_GPIO_CTRL;
1282 else if (cpu_is_omap44xx())
1283 reg += OMAP4_GPIO_CTRL;
1284 ctrl = __raw_readl(reg);
1242 /* Module is disabled, clocks are gated */ 1285 /* Module is disabled, clocks are gated */
1243 ctrl |= 1; 1286 ctrl |= 1;
1244 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL); 1287 __raw_writel(ctrl, reg);
1245 } 1288 }
1246 } 1289 }
1247 _reset_gpio(bank, bank->chip.base + offset); 1290 _reset_gpio(bank, bank->chip.base + offset);
@@ -1570,9 +1613,14 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
1570 reg += OMAP7XX_GPIO_DIR_CONTROL; 1613 reg += OMAP7XX_GPIO_DIR_CONTROL;
1571 break; 1614 break;
1572 case METHOD_GPIO_24XX: 1615 case METHOD_GPIO_24XX:
1573 case METHOD_GPIO_44XX:
1574 reg += OMAP24XX_GPIO_OE; 1616 reg += OMAP24XX_GPIO_OE;
1575 break; 1617 break;
1618 case METHOD_GPIO_44XX:
1619 reg += OMAP4_GPIO_OE;
1620 break;
1621 default:
1622 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1623 return -EINVAL;
1576 } 1624 }
1577 return __raw_readl(reg) & mask; 1625 return __raw_readl(reg) & mask;
1578} 1626}
@@ -1845,7 +1893,8 @@ static int __init _omap_gpio_init(void)
1845 __raw_writel(0, bank->base + 1893 __raw_writel(0, bank->base +
1846 OMAP24XX_GPIO_CTRL); 1894 OMAP24XX_GPIO_CTRL);
1847 } 1895 }
1848 if (i < ARRAY_SIZE(non_wakeup_gpios)) 1896 if (cpu_is_omap24xx() &&
1897 i < ARRAY_SIZE(non_wakeup_gpios))
1849 bank->non_wakeup_gpios = non_wakeup_gpios[i]; 1898 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1850 gpio_count = 32; 1899 gpio_count = 32;
1851 } 1900 }
@@ -2028,16 +2077,27 @@ static struct sys_device omap_gpio_device = {
2028 2077
2029static int workaround_enabled; 2078static int workaround_enabled;
2030 2079
2031void omap2_gpio_prepare_for_retention(void) 2080void omap2_gpio_prepare_for_idle(int power_state)
2032{ 2081{
2033 int i, c = 0; 2082 int i, c = 0;
2083 int min = 0;
2034 2084
2035 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious 2085 if (cpu_is_omap34xx())
2036 * IRQs will be generated. See OMAP2420 Errata item 1.101. */ 2086 min = 1;
2037 for (i = 0; i < gpio_bank_count; i++) { 2087
2088 for (i = min; i < gpio_bank_count; i++) {
2038 struct gpio_bank *bank = &gpio_bank[i]; 2089 struct gpio_bank *bank = &gpio_bank[i];
2039 u32 l1, l2; 2090 u32 l1, l2;
2040 2091
2092 if (bank->dbck_enable_mask)
2093 clk_disable(bank->dbck);
2094
2095 if (power_state > PWRDM_POWER_OFF)
2096 continue;
2097
2098 /* If going to OFF, remove triggering for all
2099 * non-wakeup GPIOs. Otherwise spurious IRQs will be
2100 * generated. See OMAP2420 Errata item 1.101. */
2041 if (!(bank->enabled_non_wakeup_gpios)) 2101 if (!(bank->enabled_non_wakeup_gpios))
2042 continue; 2102 continue;
2043 2103
@@ -2085,16 +2145,23 @@ void omap2_gpio_prepare_for_retention(void)
2085 workaround_enabled = 1; 2145 workaround_enabled = 1;
2086} 2146}
2087 2147
2088void omap2_gpio_resume_after_retention(void) 2148void omap2_gpio_resume_after_idle(void)
2089{ 2149{
2090 int i; 2150 int i;
2151 int min = 0;
2091 2152
2092 if (!workaround_enabled) 2153 if (cpu_is_omap34xx())
2093 return; 2154 min = 1;
2094 for (i = 0; i < gpio_bank_count; i++) { 2155 for (i = min; i < gpio_bank_count; i++) {
2095 struct gpio_bank *bank = &gpio_bank[i]; 2156 struct gpio_bank *bank = &gpio_bank[i];
2096 u32 l, gen, gen0, gen1; 2157 u32 l, gen, gen0, gen1;
2097 2158
2159 if (bank->dbck_enable_mask)
2160 clk_enable(bank->dbck);
2161
2162 if (!workaround_enabled)
2163 continue;
2164
2098 if (!(bank->enabled_non_wakeup_gpios)) 2165 if (!(bank->enabled_non_wakeup_gpios))
2099 continue; 2166 continue;
2100 2167
@@ -2119,7 +2186,7 @@ void omap2_gpio_resume_after_retention(void)
2119 * horribly racy, but it's the best we can do to work around 2186 * horribly racy, but it's the best we can do to work around
2120 * this silicon bug. */ 2187 * this silicon bug. */
2121 l ^= bank->saved_datain; 2188 l ^= bank->saved_datain;
2122 l &= bank->non_wakeup_gpios; 2189 l &= bank->enabled_non_wakeup_gpios;
2123 2190
2124 /* 2191 /*
2125 * No need to generate IRQs for the rising edge for gpio IRQs 2192 * No need to generate IRQs for the rising edge for gpio IRQs
@@ -2207,10 +2274,6 @@ void omap_gpio_save_context(void)
2207 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2274 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2208 gpio_context[i].dataout = 2275 gpio_context[i].dataout =
2209 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); 2276 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2210 gpio_context[i].setwkuena =
2211 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2212 gpio_context[i].setdataout =
2213 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2214 } 2277 }
2215} 2278}
2216 2279
@@ -2243,10 +2306,6 @@ void omap_gpio_restore_context(void)
2243 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2306 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2244 __raw_writel(gpio_context[i].dataout, 2307 __raw_writel(gpio_context[i].dataout,
2245 bank->base + OMAP24XX_GPIO_DATAOUT); 2308 bank->base + OMAP24XX_GPIO_DATAOUT);
2246 __raw_writel(gpio_context[i].setwkuena,
2247 bank->base + OMAP24XX_GPIO_SETWKUENA);
2248 __raw_writel(gpio_context[i].setdataout,
2249 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2250 } 2309 }
2251} 2310}
2252#endif 2311#endif
@@ -2286,110 +2345,3 @@ static int __init omap_gpio_sysinit(void)
2286} 2345}
2287 2346
2288arch_initcall(omap_gpio_sysinit); 2347arch_initcall(omap_gpio_sysinit);
2289
2290
2291#ifdef CONFIG_DEBUG_FS
2292
2293#include <linux/debugfs.h>
2294#include <linux/seq_file.h>
2295
2296static int dbg_gpio_show(struct seq_file *s, void *unused)
2297{
2298 unsigned i, j, gpio;
2299
2300 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2301 struct gpio_bank *bank = gpio_bank + i;
2302 unsigned bankwidth = 16;
2303 u32 mask = 1;
2304
2305 if (bank_is_mpuio(bank))
2306 gpio = OMAP_MPUIO(0);
2307 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2308 bankwidth = 32;
2309
2310 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2311 unsigned irq, value, is_in, irqstat;
2312 const char *label;
2313
2314 label = gpiochip_is_requested(&bank->chip, j);
2315 if (!label)
2316 continue;
2317
2318 irq = bank->virtual_irq_start + j;
2319 value = gpio_get_value(gpio);
2320 is_in = gpio_is_input(bank, mask);
2321
2322 if (bank_is_mpuio(bank))
2323 seq_printf(s, "MPUIO %2d ", j);
2324 else
2325 seq_printf(s, "GPIO %3d ", gpio);
2326 seq_printf(s, "(%-20.20s): %s %s",
2327 label,
2328 is_in ? "in " : "out",
2329 value ? "hi" : "lo");
2330
2331/* FIXME for at least omap2, show pullup/pulldown state */
2332
2333 irqstat = irq_desc[irq].status;
2334#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2335 if (is_in && ((bank->suspend_wakeup & mask)
2336 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2337 char *trigger = NULL;
2338
2339 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2340 case IRQ_TYPE_EDGE_FALLING:
2341 trigger = "falling";
2342 break;
2343 case IRQ_TYPE_EDGE_RISING:
2344 trigger = "rising";
2345 break;
2346 case IRQ_TYPE_EDGE_BOTH:
2347 trigger = "bothedge";
2348 break;
2349 case IRQ_TYPE_LEVEL_LOW:
2350 trigger = "low";
2351 break;
2352 case IRQ_TYPE_LEVEL_HIGH:
2353 trigger = "high";
2354 break;
2355 case IRQ_TYPE_NONE:
2356 trigger = "(?)";
2357 break;
2358 }
2359 seq_printf(s, ", irq-%d %-8s%s",
2360 irq, trigger,
2361 (bank->suspend_wakeup & mask)
2362 ? " wakeup" : "");
2363 }
2364#endif
2365 seq_printf(s, "\n");
2366 }
2367
2368 if (bank_is_mpuio(bank)) {
2369 seq_printf(s, "\n");
2370 gpio = 0;
2371 }
2372 }
2373 return 0;
2374}
2375
2376static int dbg_gpio_open(struct inode *inode, struct file *file)
2377{
2378 return single_open(file, dbg_gpio_show, &inode->i_private);
2379}
2380
2381static const struct file_operations debug_fops = {
2382 .open = dbg_gpio_open,
2383 .read = seq_read,
2384 .llseek = seq_lseek,
2385 .release = single_release,
2386};
2387
2388static int __init omap_gpio_debuginit(void)
2389{
2390 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2391 NULL, NULL, &debug_fops);
2392 return 0;
2393}
2394late_initcall(omap_gpio_debuginit);
2395#endif
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 34f7fa9ad4c0..dfc472ca0cc4 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -196,15 +196,15 @@ extern struct clk dummy_ck;
196#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 196#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
197 197
198/* Clksel_rate flags */ 198/* Clksel_rate flags */
199#define DEFAULT_RATE (1 << 0) 199#define RATE_IN_242X (1 << 0)
200#define RATE_IN_242X (1 << 1) 200#define RATE_IN_243X (1 << 1)
201#define RATE_IN_243X (1 << 2) 201#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */
202#define RATE_IN_343X (1 << 3) /* rates common to all 343X */ 202#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */
203#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ 203#define RATE_IN_36XX (1 << 4)
204#define RATE_IN_36XX (1 << 5) 204#define RATE_IN_4430 (1 << 5)
205#define RATE_IN_4430 (1 << 6)
206 205
207#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 206#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
208 207
208#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX)
209 209
210#endif 210#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 7556e271942e..d265018f5e6b 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -31,9 +31,6 @@
31 31
32struct sys_timer; 32struct sys_timer;
33 33
34/* used by omap-smp.c and board-4430sdp.c */
35extern void __iomem *gic_cpu_base_addr;
36
37extern void omap_map_common_io(void); 34extern void omap_map_common_io(void);
38extern struct sys_timer omap_timer; 35extern struct sys_timer omap_timer;
39 36
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index a56deee97676..131bf405c2f6 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -207,6 +207,9 @@
207/* 44xx control status register offset */ 207/* 44xx control status register offset */
208#define OMAP44XX_CONTROL_STATUS 0x2c4 208#define OMAP44XX_CONTROL_STATUS 0x2c4
209 209
210/* 44xx-only CONTROL_GENERAL register offsets */
211#define OMAP44XX_CONTROL_MMC1 0x628
212#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
210/* 213/*
211 * REVISIT: This list of registers is not comprehensive - there are more 214 * REVISIT: This list of registers is not comprehensive - there are more
212 * that should be added. 215 * that should be added.
@@ -252,6 +255,23 @@
252#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 255#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
253#define OMAP2_PBIASLITEVMODE0 (1 << 0) 256#define OMAP2_PBIASLITEVMODE0 (1 << 0)
254 257
258/* CONTROL_PBIAS_LITE bits for OMAP4 */
259#define OMAP4_MMC1_PWRDNZ (1 << 26)
260#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
261#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
262#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
263#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
264#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
265#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
266
267#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
268#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
269#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
270#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
271#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
272#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
273#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
274
255/* CONTROL_PROG_IO1 bits */ 275/* CONTROL_PROG_IO1 bits */
256#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) 276#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
257 277
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index de7c54731cbe..de1c604962eb 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -72,8 +72,8 @@
72 IH_GPIO_BASE + (nr)) 72 IH_GPIO_BASE + (nr))
73 73
74extern int omap_gpio_init(void); /* Call from board init only */ 74extern int omap_gpio_init(void); /* Call from board init only */
75extern void omap2_gpio_prepare_for_retention(void); 75extern void omap2_gpio_prepare_for_idle(int power_state);
76extern void omap2_gpio_resume_after_retention(void); 76extern void omap2_gpio_resume_after_idle(void);
77extern void omap_set_gpio_debounce(int gpio, int enable); 77extern void omap_set_gpio_debounce(int gpio, int enable);
78extern void omap_set_gpio_debounce_time(int gpio, int enable); 78extern void omap_set_gpio_debounce_time(int gpio, int enable);
79extern void omap_gpio_save_context(void); 79extern void omap_gpio_save_context(void);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 401701977dbb..c01d9f08a198 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -428,4 +428,8 @@ void omap3_intc_resume_idle(void);
428 428
429#include <mach/hardware.h> 429#include <mach/hardware.h>
430 430
431#ifdef CONFIG_FIQ
432#define FIQ_START 1024
433#endif
434
431#endif 435#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index a1bac07c89eb..c835f1e994c6 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -102,6 +102,10 @@ struct omap_mmc_platform_data {
102 /* Regulator off remapped to sleep */ 102 /* Regulator off remapped to sleep */
103 unsigned vcc_aux_disable_is_sleep:1; 103 unsigned vcc_aux_disable_is_sleep:1;
104 104
105 /* we can put the features above into this variable */
106#define HSMMC_HAS_PBIAS (1 << 0)
107 unsigned features;
108
105 int switch_pin; /* gpio (card detect) */ 109 int switch_pin; /* gpio (card detect) */
106 int gpio_wp; /* gpio (write protect) */ 110 int gpio_wp; /* gpio (write protect) */
107 111
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index f235d32cd942..ffd909fa5287 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -61,9 +61,9 @@
61# define OMAP_NAME omap16xx 61# define OMAP_NAME omap16xx
62# endif 62# endif
63#endif 63#endif
64#if (defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) 64#ifdef CONFIG_ARCH_OMAP2PLUS
65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) 65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
66# error "OMAP1 and OMAP2 can't be selected at the same time" 66# error "OMAP1 and OMAP2PLUS can't be selected at the same time"
67# endif 67# endif
68#endif 68#endif
69#ifdef CONFIG_ARCH_OMAP2420 69#ifdef CONFIG_ARCH_OMAP2420
@@ -82,12 +82,20 @@
82# define OMAP_NAME omap2430 82# define OMAP_NAME omap2430
83# endif 83# endif
84#endif 84#endif
85#ifdef CONFIG_ARCH_OMAP3430 85#ifdef CONFIG_ARCH_OMAP3
86# ifdef OMAP_NAME 86# ifdef OMAP_NAME
87# undef MULTI_OMAP2 87# undef MULTI_OMAP2
88# define MULTI_OMAP2 88# define MULTI_OMAP2
89# else 89# else
90# define OMAP_NAME omap3430 90# define OMAP_NAME omap3
91# endif
92#endif
93#ifdef CONFIG_ARCH_OMAP4
94# ifdef OMAP_NAME
95# undef MULTI_OMAP2
96# define MULTI_OMAP2
97# else
98# define OMAP_NAME omap4
91# endif 99# endif
92#endif 100#endif
93 101
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index b3ef1a7f53cc..8b3f12ff5cbc 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -30,6 +30,7 @@
30#define OMAP4430_CM_BASE OMAP4430_CM1_BASE 30#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
31#define OMAP4430_CM2_BASE 0x4a008000 31#define OMAP4430_CM2_BASE 0x4a008000
32#define OMAP4430_PRM_BASE 0x4a306000 32#define OMAP4430_PRM_BASE 0x4a306000
33#define OMAP4430_PRCM_MPU_BASE 0x48243000
33#define OMAP44XX_GPMC_BASE 0x50000000 34#define OMAP44XX_GPMC_BASE 0x50000000
34#define OMAP443X_SCM_BASE 0x4a002000 35#define OMAP443X_SCM_BASE 0x4a002000
35#define OMAP443X_CTRL_BASE 0x4a100000 36#define OMAP443X_CTRL_BASE 0x4a100000
@@ -48,5 +49,8 @@
48#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) 49#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
49#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000) 50#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000)
50 51
52#define OMAP4_MMU1_BASE 0x55082000
53#define OMAP4_MMU2_BASE 0x4A066000
54
51#endif /* __ASM_ARCH_OMAP44XX_H */ 55#endif /* __ASM_ARCH_OMAP44XX_H */
52 56
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 36d6ea56ab51..0eccc09ac4a9 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -176,9 +176,8 @@ struct omap_hwmod_addr_space {
176#define OCP_USER_SDMA (1 << 1) 176#define OCP_USER_SDMA (1 << 1)
177 177
178/* omap_hwmod_ocp_if.flags bits */ 178/* omap_hwmod_ocp_if.flags bits */
179#define OCPIF_HAS_IDLEST (1 << 0) 179#define OCPIF_SWSUP_IDLE (1 << 0)
180#define OCPIF_SWSUP_IDLE (1 << 1) 180#define OCPIF_CAN_BURST (1 << 1)
181#define OCPIF_CAN_BURST (1 << 2)
182 181
183/** 182/**
184 * struct omap_hwmod_ocp_if - OCP interface data 183 * struct omap_hwmod_ocp_if - OCP interface data
@@ -327,14 +326,12 @@ struct omap_hwmod_omap2_prcm {
327 326
328/** 327/**
329 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data 328 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
330 * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2 329 * @clkctrl_reg: PRCM address of the clock control register
331 * @device_offs: device register offset from @module_offs
332 * @submodule_wkdep_bit: bit shift of the WKDEP range 330 * @submodule_wkdep_bit: bit shift of the WKDEP range
333 */ 331 */
334struct omap_hwmod_omap4_prcm { 332struct omap_hwmod_omap4_prcm {
335 u32 module_offs; 333 void __iomem *clkctrl_reg;
336 u16 device_offs; 334 u8 submodule_wkdep_bit;
337 u8 submodule_wkdep_bit;
338}; 335};
339 336
340 337
@@ -353,6 +350,8 @@ struct omap_hwmod_omap4_prcm {
353 * when module is enabled, rather than the default, which is to 350 * when module is enabled, rather than the default, which is to
354 * enable autoidle 351 * enable autoidle
355 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup 352 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
353 * HWMOD_NO_IDLEST : this module does not have idle status - this is the case
354 * only for few initiator modules on OMAP2 & 3.
356 */ 355 */
357#define HWMOD_SWSUP_SIDLE (1 << 0) 356#define HWMOD_SWSUP_SIDLE (1 << 0)
358#define HWMOD_SWSUP_MSTANDBY (1 << 1) 357#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -360,6 +359,7 @@ struct omap_hwmod_omap4_prcm {
360#define HWMOD_INIT_NO_IDLE (1 << 3) 359#define HWMOD_INIT_NO_IDLE (1 << 3)
361#define HWMOD_NO_OCP_AUTOIDLE (1 << 4) 360#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
362#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) 361#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
362#define HWMOD_NO_IDLEST (1 << 6)
363 363
364/* 364/*
365 * omap_hwmod._int_flags definitions 365 * omap_hwmod._int_flags definitions
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index d82b2c00d4f1..fb6ec74fe39e 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -31,6 +31,7 @@
31#define PWRDM_MAX_PWRSTS 4 31#define PWRDM_MAX_PWRSTS 4
32 32
33/* Powerdomain allowable state bitfields */ 33/* Powerdomain allowable state bitfields */
34#define PWRSTS_ON (1 << PWRDM_POWER_ON)
34#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ 35#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
35 (1 << PWRDM_POWER_ON)) 36 (1 << PWRDM_POWER_ON))
36 37
@@ -49,6 +50,12 @@
49 * in MEM bank 1 position. This is 50 * in MEM bank 1 position. This is
50 * true for OMAP3430 51 * true for OMAP3430
51 */ 52 */
53#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
54 * support to transition from a
55 * sleep state to a lower sleep
56 * state without waking up the
57 * powerdomain
58 */
52 59
53/* 60/*
54 * Number of memory banks that are power-controllable. On OMAP4430, the 61 * Number of memory banks that are power-controllable. On OMAP4430, the
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 83dce4c4f7e6..19145f5c32ba 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -15,6 +15,20 @@
15 15
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18/*
19 * Memory entry used for the DEBUG_LL UART configuration. See also
20 * uncompress.h and debug-macro.S.
21 *
22 * Note that using a memory location for storing the UART configuration
23 * has at least two limitations:
24 *
25 * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
26 * uncompress code could then partially overwrite itself
27 * 2. We assume printascii is called at least once before paging_init,
28 * and addruart has a chance to read OMAP_UART_INFO
29 */
30#define OMAP_UART_INFO (PHYS_OFFSET + 0x3ffc)
31
18/* OMAP1 serial ports */ 32/* OMAP1 serial ports */
19#define OMAP1_UART1_BASE 0xfffb0000 33#define OMAP1_UART1_BASE 0xfffb0000
20#define OMAP1_UART2_BASE 0xfffb0800 34#define OMAP1_UART2_BASE 0xfffb0800
@@ -39,7 +53,7 @@
39 53
40/* External port on Zoom2/3 */ 54/* External port on Zoom2/3 */
41#define ZOOM_UART_BASE 0x10000000 55#define ZOOM_UART_BASE 0x10000000
42#define ZOOM_UART_VIRT 0xfb000000 56#define ZOOM_UART_VIRT 0xfa400000
43 57
44#define OMAP_PORT_SHIFT 2 58#define OMAP_PORT_SHIFT 2
45#define OMAP7XX_PORT_SHIFT 0 59#define OMAP7XX_PORT_SHIFT 0
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 81d9ec540fcf..bbedd71943f6 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -20,27 +20,21 @@
20#include <linux/types.h> 20#include <linux/types.h>
21#include <linux/serial_reg.h> 21#include <linux/serial_reg.h>
22 22
23#include <asm/memory.h>
23#include <asm/mach-types.h> 24#include <asm/mach-types.h>
24 25
25#include <plat/serial.h> 26#include <plat/serial.h>
26 27
27static volatile u8 *uart1_base;
28static int uart1_shift;
29
30static volatile u8 *uart_base; 28static volatile u8 *uart_base;
31static int uart_shift; 29static int uart_shift;
32 30
33/* 31/*
34 * Store the DEBUG_LL uart number into UART1 scratchpad register. 32 * Store the DEBUG_LL uart number into memory.
35 * See also debug-macro.S, and serial.c for related code. 33 * See also debug-macro.S, and serial.c for related code.
36 *
37 * Please note that we currently assume that:
38 * - UART1 clocks are enabled for register access
39 * - UART1 scratchpad register can be used
40 */ 34 */
41static void set_uart1_scratchpad(unsigned char port) 35static void set_omap_uart_info(unsigned char port)
42{ 36{
43 uart1_base[UART_SCR << uart1_shift] = port; 37 *(volatile u32 *)OMAP_UART_INFO = port;
44} 38}
45 39
46static void putc(int c) 40static void putc(int c)
@@ -60,42 +54,38 @@ static inline void flush(void)
60/* 54/*
61 * Macros to configure UART1 and debug UART 55 * Macros to configure UART1 and debug UART
62 */ 56 */
63#define _DEBUG_LL_ENTRY(mach, uart1_phys, uart1_shft, \ 57#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \
64 dbg_uart, dbg_shft, dbg_id) \
65 if (machine_is_##mach()) { \ 58 if (machine_is_##mach()) { \
66 uart1_base = (volatile u8 *)(uart1_phys); \
67 uart1_shift = (uart1_shft); \
68 uart_base = (volatile u8 *)(dbg_uart); \ 59 uart_base = (volatile u8 *)(dbg_uart); \
69 uart_shift = (dbg_shft); \ 60 uart_shift = (dbg_shft); \
70 port = (dbg_id); \ 61 port = (dbg_id); \
71 set_uart1_scratchpad(port); \ 62 set_omap_uart_info(port); \
72 break; \ 63 break; \
73 } 64 }
74 65
75#define DEBUG_LL_OMAP7XX(p, mach) \ 66#define DEBUG_LL_OMAP7XX(p, mach) \
76 _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP7XX_PORT_SHIFT, \ 67 _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
77 OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, OMAP1UART##p) 68 OMAP1UART##p)
78 69
79#define DEBUG_LL_OMAP1(p, mach) \ 70#define DEBUG_LL_OMAP1(p, mach) \
80 _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP_PORT_SHIFT, \ 71 _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \
81 OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP1UART##p) 72 OMAP1UART##p)
82 73
83#define DEBUG_LL_OMAP2(p, mach) \ 74#define DEBUG_LL_OMAP2(p, mach) \
84 _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ 75 _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, \
85 OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP2UART##p) 76 OMAP2UART##p)
86 77
87#define DEBUG_LL_OMAP3(p, mach) \ 78#define DEBUG_LL_OMAP3(p, mach) \
88 _DEBUG_LL_ENTRY(mach, OMAP3_UART1_BASE, OMAP_PORT_SHIFT, \ 79 _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, \
89 OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP3UART##p) 80 OMAP3UART##p)
90 81
91#define DEBUG_LL_OMAP4(p, mach) \ 82#define DEBUG_LL_OMAP4(p, mach) \
92 _DEBUG_LL_ENTRY(mach, OMAP4_UART1_BASE, OMAP_PORT_SHIFT, \ 83 _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
93 OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP4UART##p) 84 OMAP4UART##p)
94 85
95/* Zoom2/3 shift is different for UART1 and external port */ 86/* Zoom2/3 shift is different for UART1 and external port */
96#define DEBUG_LL_ZOOM(mach) \ 87#define DEBUG_LL_ZOOM(mach) \
97 _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ 88 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
98 ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
99 89
100static inline void __arch_decomp_setup(unsigned long arch_id) 90static inline void __arch_decomp_setup(unsigned long arch_id)
101{ 91{
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 0e137663349c..bc094dbacee6 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -25,6 +25,11 @@
25 25
26#include "iopgtable.h" 26#include "iopgtable.h"
27 27
28#define for_each_iotlb_cr(obj, n, __i, cr) \
29 for (__i = 0; \
30 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
31 __i++)
32
28/* accommodate the difference between omap1 and omap2/3 */ 33/* accommodate the difference between omap1 and omap2/3 */
29static const struct iommu_functions *arch_iommu; 34static const struct iommu_functions *arch_iommu;
30 35
@@ -172,15 +177,12 @@ static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l)
172 l->base = MMU_LOCK_BASE(val); 177 l->base = MMU_LOCK_BASE(val);
173 l->vict = MMU_LOCK_VICT(val); 178 l->vict = MMU_LOCK_VICT(val);
174 179
175 BUG_ON(l->base != 0); /* Currently no preservation is used */
176} 180}
177 181
178static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l) 182static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l)
179{ 183{
180 u32 val; 184 u32 val;
181 185
182 BUG_ON(l->base != 0); /* Currently no preservation is used */
183
184 val = (l->base << MMU_LOCK_BASE_SHIFT); 186 val = (l->base << MMU_LOCK_BASE_SHIFT);
185 val |= (l->vict << MMU_LOCK_VICT_SHIFT); 187 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
186 188
@@ -214,6 +216,20 @@ static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr,
214 return arch_iommu->dump_cr(obj, cr, buf); 216 return arch_iommu->dump_cr(obj, cr, buf);
215} 217}
216 218
219/* only used in iotlb iteration for-loop */
220static struct cr_regs __iotlb_read_cr(struct iommu *obj, int n)
221{
222 struct cr_regs cr;
223 struct iotlb_lock l;
224
225 iotlb_lock_get(obj, &l);
226 l.vict = n;
227 iotlb_lock_set(obj, &l);
228 iotlb_read_cr(obj, &cr);
229
230 return cr;
231}
232
217/** 233/**
218 * load_iotlb_entry - Set an iommu tlb entry 234 * load_iotlb_entry - Set an iommu tlb entry
219 * @obj: target iommu 235 * @obj: target iommu
@@ -221,7 +237,6 @@ static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr,
221 **/ 237 **/
222int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) 238int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
223{ 239{
224 int i;
225 int err = 0; 240 int err = 0;
226 struct iotlb_lock l; 241 struct iotlb_lock l;
227 struct cr_regs *cr; 242 struct cr_regs *cr;
@@ -231,21 +246,30 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
231 246
232 clk_enable(obj->clk); 247 clk_enable(obj->clk);
233 248
234 for (i = 0; i < obj->nr_tlb_entries; i++) { 249 iotlb_lock_get(obj, &l);
250 if (l.base == obj->nr_tlb_entries) {
251 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
252 err = -EBUSY;
253 goto out;
254 }
255 if (!e->prsvd) {
256 int i;
235 struct cr_regs tmp; 257 struct cr_regs tmp;
236 258
259 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
260 if (!iotlb_cr_valid(&tmp))
261 break;
262
263 if (i == obj->nr_tlb_entries) {
264 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
265 err = -EBUSY;
266 goto out;
267 }
268
237 iotlb_lock_get(obj, &l); 269 iotlb_lock_get(obj, &l);
238 l.vict = i; 270 } else {
271 l.vict = l.base;
239 iotlb_lock_set(obj, &l); 272 iotlb_lock_set(obj, &l);
240 iotlb_read_cr(obj, &tmp);
241 if (!iotlb_cr_valid(&tmp))
242 break;
243 }
244
245 if (i == obj->nr_tlb_entries) {
246 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
247 err = -EBUSY;
248 goto out;
249 } 273 }
250 274
251 cr = iotlb_alloc_cr(obj, e); 275 cr = iotlb_alloc_cr(obj, e);
@@ -257,9 +281,11 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
257 iotlb_load_cr(obj, cr); 281 iotlb_load_cr(obj, cr);
258 kfree(cr); 282 kfree(cr);
259 283
284 if (e->prsvd)
285 l.base++;
260 /* increment victim for next tlb load */ 286 /* increment victim for next tlb load */
261 if (++l.vict == obj->nr_tlb_entries) 287 if (++l.vict == obj->nr_tlb_entries)
262 l.vict = 0; 288 l.vict = l.base;
263 iotlb_lock_set(obj, &l); 289 iotlb_lock_set(obj, &l);
264out: 290out:
265 clk_disable(obj->clk); 291 clk_disable(obj->clk);
@@ -276,20 +302,15 @@ EXPORT_SYMBOL_GPL(load_iotlb_entry);
276 **/ 302 **/
277void flush_iotlb_page(struct iommu *obj, u32 da) 303void flush_iotlb_page(struct iommu *obj, u32 da)
278{ 304{
279 struct iotlb_lock l;
280 int i; 305 int i;
306 struct cr_regs cr;
281 307
282 clk_enable(obj->clk); 308 clk_enable(obj->clk);
283 309
284 for (i = 0; i < obj->nr_tlb_entries; i++) { 310 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
285 struct cr_regs cr;
286 u32 start; 311 u32 start;
287 size_t bytes; 312 size_t bytes;
288 313
289 iotlb_lock_get(obj, &l);
290 l.vict = i;
291 iotlb_lock_set(obj, &l);
292 iotlb_read_cr(obj, &cr);
293 if (!iotlb_cr_valid(&cr)) 314 if (!iotlb_cr_valid(&cr))
294 continue; 315 continue;
295 316
@@ -299,7 +320,6 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
299 if ((start <= da) && (da < start + bytes)) { 320 if ((start <= da) && (da < start + bytes)) {
300 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", 321 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
301 __func__, start, da, bytes); 322 __func__, start, da, bytes);
302 iotlb_load_cr(obj, &cr);
303 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); 323 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
304 } 324 }
305 } 325 }
@@ -370,26 +390,19 @@ EXPORT_SYMBOL_GPL(iommu_dump_ctx);
370static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num) 390static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num)
371{ 391{
372 int i; 392 int i;
373 struct iotlb_lock saved, l; 393 struct iotlb_lock saved;
394 struct cr_regs tmp;
374 struct cr_regs *p = crs; 395 struct cr_regs *p = crs;
375 396
376 clk_enable(obj->clk); 397 clk_enable(obj->clk);
377
378 iotlb_lock_get(obj, &saved); 398 iotlb_lock_get(obj, &saved);
379 memcpy(&l, &saved, sizeof(saved));
380 399
381 for (i = 0; i < num; i++) { 400 for_each_iotlb_cr(obj, num, i, tmp) {
382 struct cr_regs tmp;
383
384 iotlb_lock_get(obj, &l);
385 l.vict = i;
386 iotlb_lock_set(obj, &l);
387 iotlb_read_cr(obj, &tmp);
388 if (!iotlb_cr_valid(&tmp)) 401 if (!iotlb_cr_valid(&tmp))
389 continue; 402 continue;
390
391 *p++ = tmp; 403 *p++ = tmp;
392 } 404 }
405
393 iotlb_lock_set(obj, &saved); 406 iotlb_lock_set(obj, &saved);
394 clk_disable(obj->clk); 407 clk_disable(obj->clk);
395 408
@@ -503,6 +516,12 @@ static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot)
503{ 516{
504 u32 *iopgd = iopgd_offset(obj, da); 517 u32 *iopgd = iopgd_offset(obj, da);
505 518
519 if ((da | pa) & ~IOSECTION_MASK) {
520 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
521 __func__, da, pa, IOSECTION_SIZE);
522 return -EINVAL;
523 }
524
506 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; 525 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
507 flush_iopgd_range(iopgd, iopgd); 526 flush_iopgd_range(iopgd, iopgd);
508 return 0; 527 return 0;
@@ -513,6 +532,12 @@ static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot)
513 u32 *iopgd = iopgd_offset(obj, da); 532 u32 *iopgd = iopgd_offset(obj, da);
514 int i; 533 int i;
515 534
535 if ((da | pa) & ~IOSUPER_MASK) {
536 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
537 __func__, da, pa, IOSUPER_SIZE);
538 return -EINVAL;
539 }
540
516 for (i = 0; i < 16; i++) 541 for (i = 0; i < 16; i++)
517 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; 542 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
518 flush_iopgd_range(iopgd, iopgd + 15); 543 flush_iopgd_range(iopgd, iopgd + 15);
@@ -542,6 +567,12 @@ static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot)
542 u32 *iopte = iopte_alloc(obj, iopgd, da); 567 u32 *iopte = iopte_alloc(obj, iopgd, da);
543 int i; 568 int i;
544 569
570 if ((da | pa) & ~IOLARGE_MASK) {
571 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
572 __func__, da, pa, IOLARGE_SIZE);
573 return -EINVAL;
574 }
575
545 if (IS_ERR(iopte)) 576 if (IS_ERR(iopte))
546 return PTR_ERR(iopte); 577 return PTR_ERR(iopte);
547 578
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index 65c6d1ff7237..e43983ba59c5 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -287,16 +287,19 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
287 prev_end = 0; 287 prev_end = 0;
288 list_for_each_entry(tmp, &obj->mmap, list) { 288 list_for_each_entry(tmp, &obj->mmap, list) {
289 289
290 if ((prev_end <= start) && (start + bytes < tmp->da_start)) 290 if (prev_end >= start)
291 break;
292
293 if (start + bytes < tmp->da_start)
291 goto found; 294 goto found;
292 295
293 if (flags & IOVMF_DA_ANON) 296 if (flags & IOVMF_DA_ANON)
294 start = roundup(tmp->da_end, alignement); 297 start = roundup(tmp->da_end + 1, alignement);
295 298
296 prev_end = tmp->da_end; 299 prev_end = tmp->da_end;
297 } 300 }
298 301
299 if ((start >= prev_end) && (ULONG_MAX - start >= bytes)) 302 if ((start > prev_end) && (ULONG_MAX - start >= bytes))
300 goto found; 303 goto found;
301 304
302 dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n", 305 dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n",
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 0f5197479513..f899603051ac 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -2,10 +2,10 @@
2 * omap_device implementation 2 * omap_device implementation
3 * 3 *
4 * Copyright (C) 2009 Nokia Corporation 4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley, Kevin Hilman
6 * 6 *
7 * Developed in collaboration with (alphabetical order): Benoit 7 * Developed in collaboration with (alphabetical order): Benoit
8 * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram 8 * Cousson, Thara Gopinath, Tony Lindgren, Rajendra Nayak, Vikram
9 * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard 9 * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
10 * Woodruff 10 * Woodruff
11 * 11 *
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 51f4dfb82e2b..226b2e858d6c 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -437,6 +437,20 @@ static inline int omap34xx_sram_init(void)
437} 437}
438#endif 438#endif
439 439
440#ifdef CONFIG_ARCH_OMAP4
441int __init omap44xx_sram_init(void)
442{
443 printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
444
445 return -ENODEV;
446}
447#else
448static inline int omap44xx_sram_init(void)
449{
450 return 0;
451}
452#endif
453
440int __init omap_sram_init(void) 454int __init omap_sram_init(void)
441{ 455{
442 omap_detect_sram(); 456 omap_detect_sram();
@@ -451,7 +465,7 @@ int __init omap_sram_init(void)
451 else if (cpu_is_omap34xx()) 465 else if (cpu_is_omap34xx())
452 omap34xx_sram_init(); 466 omap34xx_sram_init();
453 else if (cpu_is_omap44xx()) 467 else if (cpu_is_omap44xx())
454 omap34xx_sram_init(); /* FIXME: */ 468 omap44xx_sram_init();
455 469
456 return 0; 470 return 0;
457} 471}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 18:44:21 -0500