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-rw-r--r--arch/arm/plat-omap/Kconfig13
-rw-r--r--arch/arm/plat-omap/clock.c369
-rw-r--r--arch/arm/plat-omap/clock.h10
-rw-r--r--arch/arm/plat-omap/dma.c44
-rw-r--r--arch/arm/plat-omap/mcbsp.c97
-rw-r--r--arch/arm/plat-omap/mux.c17
-rw-r--r--arch/arm/plat-omap/usb.c2
7 files changed, 460 insertions, 92 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index a72fe55b513b..345365852f8c 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -19,6 +19,19 @@ endchoice
19 19
20comment "OMAP Feature Selections" 20comment "OMAP Feature Selections"
21 21
22config OMAP_RESET_CLOCKS
23 bool "Reset unused clocks during boot"
24 depends on ARCH_OMAP
25 default n
26 help
27 Say Y if you want to reset unused clocks during boot.
28 This option saves power, but assumes all drivers are
29 using the clock framework. Broken drivers that do not
30 yet use clock framework may not work with this option.
31 If you are booting from another operating system, you
32 probably do not want this option enabled until your
33 device drivers work properly.
34
22config OMAP_MUX 35config OMAP_MUX
23 bool "OMAP multiplexing support" 36 bool "OMAP multiplexing support"
24 depends on ARCH_OMAP 37 depends on ARCH_OMAP
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 155157f309e0..59d91b3262ba 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -14,6 +14,7 @@
14#include <linux/errno.h> 14#include <linux/errno.h>
15#include <linux/err.h> 15#include <linux/err.h>
16 16
17#include <asm/io.h>
17#include <asm/semaphore.h> 18#include <asm/semaphore.h>
18#include <asm/hardware/clock.h> 19#include <asm/hardware/clock.h>
19#include <asm/arch/board.h> 20#include <asm/arch/board.h>
@@ -25,6 +26,8 @@ static LIST_HEAD(clocks);
25static DECLARE_MUTEX(clocks_sem); 26static DECLARE_MUTEX(clocks_sem);
26static DEFINE_SPINLOCK(clockfw_lock); 27static DEFINE_SPINLOCK(clockfw_lock);
27static void propagate_rate(struct clk * clk); 28static void propagate_rate(struct clk * clk);
29/* UART clock function */
30static int set_uart_rate(struct clk * clk, unsigned long rate);
28/* External clock (MCLK & BCLK) functions */ 31/* External clock (MCLK & BCLK) functions */
29static int set_ext_clk_rate(struct clk * clk, unsigned long rate); 32static int set_ext_clk_rate(struct clk * clk, unsigned long rate);
30static long round_ext_clk_rate(struct clk * clk, unsigned long rate); 33static long round_ext_clk_rate(struct clk * clk, unsigned long rate);
@@ -34,7 +37,7 @@ static int select_table_rate(struct clk * clk, unsigned long rate);
34static long round_to_table_rate(struct clk * clk, unsigned long rate); 37static long round_to_table_rate(struct clk * clk, unsigned long rate);
35void clk_setdpll(__u16, __u16); 38void clk_setdpll(__u16, __u16);
36 39
37struct mpu_rate rate_table[] = { 40static struct mpu_rate rate_table[] = {
38 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL 41 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
39 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv 42 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
40 */ 43 */
@@ -48,7 +51,7 @@ struct mpu_rate rate_table[] = {
48 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ 51 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
49 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ 52 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
50 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ 53 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
51 { 48000000, 12000000, 192000000, 0x0ccf, 0x2810 }, /* 4/4/4/4/8/8 */ 54 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/8/4/4/8/8 */
52 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ 55 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
53#endif 56#endif
54#if defined(CONFIG_OMAP_ARM_182MHZ) 57#if defined(CONFIG_OMAP_ARM_182MHZ)
@@ -58,7 +61,7 @@ struct mpu_rate rate_table[] = {
58 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ 61 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
59#endif 62#endif
60#if defined(CONFIG_OMAP_ARM_150MHZ) 63#if defined(CONFIG_OMAP_ARM_150MHZ)
61 { 150000000, 12000000, 150000000, 0x150a, 0x2cb0 }, /* 0/0/1/1/2/2 */ 64 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
62#endif 65#endif
63#if defined(CONFIG_OMAP_ARM_120MHZ) 66#if defined(CONFIG_OMAP_ARM_120MHZ)
64 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ 67 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
@@ -76,19 +79,11 @@ struct mpu_rate rate_table[] = {
76}; 79};
77 80
78 81
79static void ckctl_recalc(struct clk * clk) 82static void ckctl_recalc(struct clk * clk);
80{ 83int __clk_enable(struct clk *clk);
81 int dsor; 84void __clk_disable(struct clk *clk);
82 85void __clk_unuse(struct clk *clk);
83 /* Calculate divisor encoded as 2-bit exponent */ 86int __clk_use(struct clk *clk);
84 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
85 if (unlikely(clk->rate == clk->parent->rate / dsor))
86 return; /* No change, quick exit */
87 clk->rate = clk->parent->rate / dsor;
88
89 if (unlikely(clk->flags & RATE_PROPAGATES))
90 propagate_rate(clk);
91}
92 87
93 88
94static void followparent_recalc(struct clk * clk) 89static void followparent_recalc(struct clk * clk)
@@ -102,6 +97,14 @@ static void watchdog_recalc(struct clk * clk)
102 clk->rate = clk->parent->rate / 14; 97 clk->rate = clk->parent->rate / 14;
103} 98}
104 99
100static void uart_recalc(struct clk * clk)
101{
102 unsigned int val = omap_readl(clk->enable_reg);
103 if (val & clk->enable_bit)
104 clk->rate = 48000000;
105 else
106 clk->rate = 12000000;
107}
105 108
106static struct clk ck_ref = { 109static struct clk ck_ref = {
107 .name = "ck_ref", 110 .name = "ck_ref",
@@ -138,7 +141,7 @@ static struct clk arm_ck = {
138static struct clk armper_ck = { 141static struct clk armper_ck = {
139 .name = "armper_ck", 142 .name = "armper_ck",
140 .parent = &ck_dpll1, 143 .parent = &ck_dpll1,
141 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 144 .flags = CLOCK_IN_OMAP730 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
142 RATE_CKCTL, 145 RATE_CKCTL,
143 .enable_reg = ARM_IDLECT2, 146 .enable_reg = ARM_IDLECT2,
144 .enable_bit = EN_PERCK, 147 .enable_bit = EN_PERCK,
@@ -185,7 +188,7 @@ static struct clk armwdt_ck = {
185static struct clk arminth_ck16xx = { 188static struct clk arminth_ck16xx = {
186 .name = "arminth_ck", 189 .name = "arminth_ck",
187 .parent = &arm_ck, 190 .parent = &arm_ck,
188 .flags = CLOCK_IN_OMAP16XX, 191 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
189 .recalc = &followparent_recalc, 192 .recalc = &followparent_recalc,
190 /* Note: On 16xx the frequency can be divided by 2 by programming 193 /* Note: On 16xx the frequency can be divided by 2 by programming
191 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 194 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
@@ -214,6 +217,38 @@ static struct clk dspmmu_ck = {
214 .recalc = &ckctl_recalc, 217 .recalc = &ckctl_recalc,
215}; 218};
216 219
220static struct clk dspper_ck = {
221 .name = "dspper_ck",
222 .parent = &ck_dpll1,
223 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
224 RATE_CKCTL | DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
225 .enable_reg = DSP_IDLECT2,
226 .enable_bit = EN_PERCK,
227 .rate_offset = CKCTL_PERDIV_OFFSET,
228 .recalc = &followparent_recalc,
229 //.recalc = &ckctl_recalc,
230};
231
232static struct clk dspxor_ck = {
233 .name = "dspxor_ck",
234 .parent = &ck_ref,
235 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
236 DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
237 .enable_reg = DSP_IDLECT2,
238 .enable_bit = EN_XORPCK,
239 .recalc = &followparent_recalc,
240};
241
242static struct clk dsptim_ck = {
243 .name = "dsptim_ck",
244 .parent = &ck_ref,
245 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
246 DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
247 .enable_reg = DSP_IDLECT2,
248 .enable_bit = EN_DSPTIMCK,
249 .recalc = &followparent_recalc,
250};
251
217static struct clk tc_ck = { 252static struct clk tc_ck = {
218 .name = "tc_ck", 253 .name = "tc_ck",
219 .parent = &ck_dpll1, 254 .parent = &ck_dpll1,
@@ -226,7 +261,7 @@ static struct clk tc_ck = {
226static struct clk arminth_ck1510 = { 261static struct clk arminth_ck1510 = {
227 .name = "arminth_ck", 262 .name = "arminth_ck",
228 .parent = &tc_ck, 263 .parent = &tc_ck,
229 .flags = CLOCK_IN_OMAP1510, 264 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
230 .recalc = &followparent_recalc, 265 .recalc = &followparent_recalc,
231 /* Note: On 1510 the frequency follows TC_CK 266 /* Note: On 1510 the frequency follows TC_CK
232 * 267 *
@@ -237,7 +272,7 @@ static struct clk arminth_ck1510 = {
237static struct clk tipb_ck = { 272static struct clk tipb_ck = {
238 .name = "tibp_ck", 273 .name = "tibp_ck",
239 .parent = &tc_ck, 274 .parent = &tc_ck,
240 .flags = CLOCK_IN_OMAP1510, 275 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
241 .recalc = &followparent_recalc, 276 .recalc = &followparent_recalc,
242}; 277};
243 278
@@ -271,14 +306,15 @@ static struct clk tc2_ck = {
271static struct clk dma_ck = { 306static struct clk dma_ck = {
272 .name = "dma_ck", 307 .name = "dma_ck",
273 .parent = &tc_ck, 308 .parent = &tc_ck,
274 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, 309 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
310 ALWAYS_ENABLED,
275 .recalc = &followparent_recalc, 311 .recalc = &followparent_recalc,
276}; 312};
277 313
278static struct clk dma_lcdfree_ck = { 314static struct clk dma_lcdfree_ck = {
279 .name = "dma_lcdfree_ck", 315 .name = "dma_lcdfree_ck",
280 .parent = &tc_ck, 316 .parent = &tc_ck,
281 .flags = CLOCK_IN_OMAP16XX, 317 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
282 .recalc = &followparent_recalc, 318 .recalc = &followparent_recalc,
283}; 319};
284 320
@@ -303,14 +339,14 @@ static struct clk lb_ck = {
303static struct clk rhea1_ck = { 339static struct clk rhea1_ck = {
304 .name = "rhea1_ck", 340 .name = "rhea1_ck",
305 .parent = &tc_ck, 341 .parent = &tc_ck,
306 .flags = CLOCK_IN_OMAP16XX, 342 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
307 .recalc = &followparent_recalc, 343 .recalc = &followparent_recalc,
308}; 344};
309 345
310static struct clk rhea2_ck = { 346static struct clk rhea2_ck = {
311 .name = "rhea2_ck", 347 .name = "rhea2_ck",
312 .parent = &tc_ck, 348 .parent = &tc_ck,
313 .flags = CLOCK_IN_OMAP16XX, 349 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
314 .recalc = &followparent_recalc, 350 .recalc = &followparent_recalc,
315}; 351};
316 352
@@ -325,43 +361,55 @@ static struct clk lcd_ck = {
325 .recalc = &ckctl_recalc, 361 .recalc = &ckctl_recalc,
326}; 362};
327 363
328static struct clk uart1_ck = { 364static struct clk uart1_1510 = {
365 .name = "uart1_ck",
366 /* Direct from ULPD, no parent */
367 .rate = 12000000,
368 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
369 .enable_reg = MOD_CONF_CTRL_0,
370 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
371 .set_rate = &set_uart_rate,
372 .recalc = &uart_recalc,
373};
374
375static struct clk uart1_16xx = {
329 .name = "uart1_ck", 376 .name = "uart1_ck",
330 /* Direct from ULPD, no parent */ 377 /* Direct from ULPD, no parent */
331 .rate = 48000000, 378 .rate = 48000000,
332 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 379 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
333 RATE_FIXED | ENABLE_REG_32BIT,
334 .enable_reg = MOD_CONF_CTRL_0, 380 .enable_reg = MOD_CONF_CTRL_0,
335 .enable_bit = 29, 381 .enable_bit = 29,
336 /* (Only on 1510)
337 * The "enable bit" actually chooses between 48MHz and 12MHz.
338 */
339}; 382};
340 383
341static struct clk uart2_ck = { 384static struct clk uart2_ck = {
342 .name = "uart2_ck", 385 .name = "uart2_ck",
343 /* Direct from ULPD, no parent */ 386 /* Direct from ULPD, no parent */
344 .rate = 48000000, 387 .rate = 12000000,
345 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 388 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT,
346 RATE_FIXED | ENABLE_REG_32BIT,
347 .enable_reg = MOD_CONF_CTRL_0, 389 .enable_reg = MOD_CONF_CTRL_0,
348 .enable_bit = 30, 390 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
349 /* (for both 1510 and 16xx) 391 .set_rate = &set_uart_rate,
350 * The "enable bit" actually chooses between 48MHz and 12MHz/32kHz. 392 .recalc = &uart_recalc,
351 */
352}; 393};
353 394
354static struct clk uart3_ck = { 395static struct clk uart3_1510 = {
396 .name = "uart3_ck",
397 /* Direct from ULPD, no parent */
398 .rate = 12000000,
399 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
400 .enable_reg = MOD_CONF_CTRL_0,
401 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
402 .set_rate = &set_uart_rate,
403 .recalc = &uart_recalc,
404};
405
406static struct clk uart3_16xx = {
355 .name = "uart3_ck", 407 .name = "uart3_ck",
356 /* Direct from ULPD, no parent */ 408 /* Direct from ULPD, no parent */
357 .rate = 48000000, 409 .rate = 48000000,
358 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 410 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
359 RATE_FIXED | ENABLE_REG_32BIT,
360 .enable_reg = MOD_CONF_CTRL_0, 411 .enable_reg = MOD_CONF_CTRL_0,
361 .enable_bit = 31, 412 .enable_bit = 31,
362 /* (Only on 1510)
363 * The "enable bit" actually chooses between 48MHz and 12MHz.
364 */
365}; 413};
366 414
367static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ 415static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
@@ -480,6 +528,9 @@ static struct clk * onchip_clks[] = {
480 /* CK_GEN2 clocks */ 528 /* CK_GEN2 clocks */
481 &dsp_ck, 529 &dsp_ck,
482 &dspmmu_ck, 530 &dspmmu_ck,
531 &dspper_ck,
532 &dspxor_ck,
533 &dsptim_ck,
483 /* CK_GEN3 clocks */ 534 /* CK_GEN3 clocks */
484 &tc_ck, 535 &tc_ck,
485 &tipb_ck, 536 &tipb_ck,
@@ -494,9 +545,11 @@ static struct clk * onchip_clks[] = {
494 &rhea2_ck, 545 &rhea2_ck,
495 &lcd_ck, 546 &lcd_ck,
496 /* ULPD clocks */ 547 /* ULPD clocks */
497 &uart1_ck, 548 &uart1_1510,
549 &uart1_16xx,
498 &uart2_ck, 550 &uart2_ck,
499 &uart3_ck, 551 &uart3_1510,
552 &uart3_16xx,
500 &usb_clko, 553 &usb_clko,
501 &usb_hhc_ck1510, &usb_hhc_ck16xx, 554 &usb_hhc_ck1510, &usb_hhc_ck16xx,
502 &mclk_1510, &mclk_16xx, 555 &mclk_1510, &mclk_16xx,
@@ -547,14 +600,34 @@ int __clk_enable(struct clk *clk)
547 return 0; 600 return 0;
548 } 601 }
549 602
603 if (clk->flags & DSP_DOMAIN_CLOCK) {
604 __clk_use(&api_ck);
605 }
606
550 if (clk->flags & ENABLE_REG_32BIT) { 607 if (clk->flags & ENABLE_REG_32BIT) {
551 regval32 = omap_readl(clk->enable_reg); 608 if (clk->flags & VIRTUAL_IO_ADDRESS) {
552 regval32 |= (1 << clk->enable_bit); 609 regval32 = __raw_readl(clk->enable_reg);
553 omap_writel(regval32, clk->enable_reg); 610 regval32 |= (1 << clk->enable_bit);
611 __raw_writel(regval32, clk->enable_reg);
612 } else {
613 regval32 = omap_readl(clk->enable_reg);
614 regval32 |= (1 << clk->enable_bit);
615 omap_writel(regval32, clk->enable_reg);
616 }
554 } else { 617 } else {
555 regval16 = omap_readw(clk->enable_reg); 618 if (clk->flags & VIRTUAL_IO_ADDRESS) {
556 regval16 |= (1 << clk->enable_bit); 619 regval16 = __raw_readw(clk->enable_reg);
557 omap_writew(regval16, clk->enable_reg); 620 regval16 |= (1 << clk->enable_bit);
621 __raw_writew(regval16, clk->enable_reg);
622 } else {
623 regval16 = omap_readw(clk->enable_reg);
624 regval16 |= (1 << clk->enable_bit);
625 omap_writew(regval16, clk->enable_reg);
626 }
627 }
628
629 if (clk->flags & DSP_DOMAIN_CLOCK) {
630 __clk_unuse(&api_ck);
558 } 631 }
559 632
560 return 0; 633 return 0;
@@ -569,14 +642,34 @@ void __clk_disable(struct clk *clk)
569 if (clk->enable_reg == 0) 642 if (clk->enable_reg == 0)
570 return; 643 return;
571 644
645 if (clk->flags & DSP_DOMAIN_CLOCK) {
646 __clk_use(&api_ck);
647 }
648
572 if (clk->flags & ENABLE_REG_32BIT) { 649 if (clk->flags & ENABLE_REG_32BIT) {
573 regval32 = omap_readl(clk->enable_reg); 650 if (clk->flags & VIRTUAL_IO_ADDRESS) {
574 regval32 &= ~(1 << clk->enable_bit); 651 regval32 = __raw_readl(clk->enable_reg);
575 omap_writel(regval32, clk->enable_reg); 652 regval32 &= ~(1 << clk->enable_bit);
653 __raw_writel(regval32, clk->enable_reg);
654 } else {
655 regval32 = omap_readl(clk->enable_reg);
656 regval32 &= ~(1 << clk->enable_bit);
657 omap_writel(regval32, clk->enable_reg);
658 }
576 } else { 659 } else {
577 regval16 = omap_readw(clk->enable_reg); 660 if (clk->flags & VIRTUAL_IO_ADDRESS) {
578 regval16 &= ~(1 << clk->enable_bit); 661 regval16 = __raw_readw(clk->enable_reg);
579 omap_writew(regval16, clk->enable_reg); 662 regval16 &= ~(1 << clk->enable_bit);
663 __raw_writew(regval16, clk->enable_reg);
664 } else {
665 regval16 = omap_readw(clk->enable_reg);
666 regval16 &= ~(1 << clk->enable_bit);
667 omap_writew(regval16, clk->enable_reg);
668 }
669 }
670
671 if (clk->flags & DSP_DOMAIN_CLOCK) {
672 __clk_unuse(&api_ck);
580 } 673 }
581} 674}
582 675
@@ -766,6 +859,33 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
766 return dsor_exp; 859 return dsor_exp;
767} 860}
768 861
862
863static void ckctl_recalc(struct clk * clk)
864{
865 int dsor;
866
867 /* Calculate divisor encoded as 2-bit exponent */
868 if (clk->flags & DSP_DOMAIN_CLOCK) {
869 /* The clock control bits are in DSP domain,
870 * so api_ck is needed for access.
871 * Note that DSP_CKCTL virt addr = phys addr, so
872 * we must use __raw_readw() instead of omap_readw().
873 */
874 __clk_use(&api_ck);
875 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
876 __clk_unuse(&api_ck);
877 } else {
878 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
879 }
880 if (unlikely(clk->rate == clk->parent->rate / dsor))
881 return; /* No change, quick exit */
882 clk->rate = clk->parent->rate / dsor;
883
884 if (unlikely(clk->flags & RATE_PROPAGATES))
885 propagate_rate(clk);
886}
887
888
769long clk_round_rate(struct clk *clk, unsigned long rate) 889long clk_round_rate(struct clk *clk, unsigned long rate)
770{ 890{
771 int dsor_exp; 891 int dsor_exp;
@@ -826,6 +946,9 @@ static int select_table_rate(struct clk * clk, unsigned long rate)
826 if (!ptr->rate) 946 if (!ptr->rate)
827 return -EINVAL; 947 return -EINVAL;
828 948
949 if (!ptr->rate)
950 return -EINVAL;
951
829 if (unlikely(ck_dpll1.rate == 0)) { 952 if (unlikely(ck_dpll1.rate == 0)) {
830 omap_writew(ptr->dpllctl_val, DPLL_CTL); 953 omap_writew(ptr->dpllctl_val, DPLL_CTL);
831 ck_dpll1.rate = ptr->pll_rate; 954 ck_dpll1.rate = ptr->pll_rate;
@@ -921,6 +1044,23 @@ static unsigned calc_ext_dsor(unsigned long rate)
921 return dsor; 1044 return dsor;
922} 1045}
923 1046
1047/* Only needed on 1510 */
1048static int set_uart_rate(struct clk * clk, unsigned long rate)
1049{
1050 unsigned int val;
1051
1052 val = omap_readl(clk->enable_reg);
1053 if (rate == 12000000)
1054 val &= ~(1 << clk->enable_bit);
1055 else if (rate == 48000000)
1056 val |= (1 << clk->enable_bit);
1057 else
1058 return -EINVAL;
1059 omap_writel(val, clk->enable_reg);
1060 clk->rate = rate;
1061
1062 return 0;
1063}
924 1064
925static int set_ext_clk_rate(struct clk * clk, unsigned long rate) 1065static int set_ext_clk_rate(struct clk * clk, unsigned long rate)
926{ 1066{
@@ -985,7 +1125,18 @@ void clk_unregister(struct clk *clk)
985} 1125}
986EXPORT_SYMBOL(clk_unregister); 1126EXPORT_SYMBOL(clk_unregister);
987 1127
988 1128#ifdef CONFIG_OMAP_RESET_CLOCKS
1129/*
1130 * Resets some clocks that may be left on from bootloader,
1131 * but leaves serial clocks on. See also omap_late_clk_reset().
1132 */
1133static inline void omap_early_clk_reset(void)
1134{
1135 //omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
1136}
1137#else
1138#define omap_early_clk_reset() {}
1139#endif
989 1140
990int __init clk_init(void) 1141int __init clk_init(void)
991{ 1142{
@@ -993,6 +1144,8 @@ int __init clk_init(void)
993 const struct omap_clock_config *info; 1144 const struct omap_clock_config *info;
994 int crystal_type = 0; /* Default 12 MHz */ 1145 int crystal_type = 0; /* Default 12 MHz */
995 1146
1147 omap_early_clk_reset();
1148
996 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { 1149 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
997 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) { 1150 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
998 clk_register(*clkp); 1151 clk_register(*clkp);
@@ -1023,9 +1176,42 @@ int __init clk_init(void)
1023 ck_ref.rate = 19200000; 1176 ck_ref.rate = 19200000;
1024#endif 1177#endif
1025 1178
1179 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
1180 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
1181 omap_readw(ARM_CKCTL));
1182
1026 /* We want to be in syncronous scalable mode */ 1183 /* We want to be in syncronous scalable mode */
1027 omap_writew(0x1000, ARM_SYSST); 1184 omap_writew(0x1000, ARM_SYSST);
1028 1185
1186#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
1187 /* Use values set by bootloader. Determine PLL rate and recalculate
1188 * dependent clocks as if kernel had changed PLL or divisors.
1189 */
1190 {
1191 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
1192
1193 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
1194 if (pll_ctl_val & 0x10) {
1195 /* PLL enabled, apply multiplier and divisor */
1196 if (pll_ctl_val & 0xf80)
1197 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
1198 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
1199 } else {
1200 /* PLL disabled, apply bypass divisor */
1201 switch (pll_ctl_val & 0xc) {
1202 case 0:
1203 break;
1204 case 0x4:
1205 ck_dpll1.rate /= 2;
1206 break;
1207 default:
1208 ck_dpll1.rate /= 4;
1209 break;
1210 }
1211 }
1212 }
1213 propagate_rate(&ck_dpll1);
1214#else
1029 /* Find the highest supported frequency and enable it */ 1215 /* Find the highest supported frequency and enable it */
1030 if (select_table_rate(&virtual_ck_mpu, ~0)) { 1216 if (select_table_rate(&virtual_ck_mpu, ~0)) {
1031 printk(KERN_ERR "System frequencies not set. Check your config.\n"); 1217 printk(KERN_ERR "System frequencies not set. Check your config.\n");
@@ -1034,12 +1220,13 @@ int __init clk_init(void)
1034 omap_writew(0x1005, ARM_CKCTL); 1220 omap_writew(0x1005, ARM_CKCTL);
1035 ck_dpll1.rate = 60000000; 1221 ck_dpll1.rate = 60000000;
1036 propagate_rate(&ck_dpll1); 1222 propagate_rate(&ck_dpll1);
1037 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld/%ld/%ld\n",
1038 ck_ref.rate, ck_dpll1.rate, arm_ck.rate);
1039 } 1223 }
1040 1224#endif
1041 /* Cache rates for clocks connected to ck_ref (not dpll1) */ 1225 /* Cache rates for clocks connected to ck_ref (not dpll1) */
1042 propagate_rate(&ck_ref); 1226 propagate_rate(&ck_ref);
1227 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld/%ld MHz\n",
1228 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
1229 ck_dpll1.rate, arm_ck.rate);
1043 1230
1044#ifdef CONFIG_MACH_OMAP_PERSEUS2 1231#ifdef CONFIG_MACH_OMAP_PERSEUS2
1045 /* Select slicer output as OMAP input clock */ 1232 /* Select slicer output as OMAP input clock */
@@ -1074,3 +1261,63 @@ int __init clk_init(void)
1074 1261
1075 return 0; 1262 return 0;
1076} 1263}
1264
1265
1266#ifdef CONFIG_OMAP_RESET_CLOCKS
1267
1268static int __init omap_late_clk_reset(void)
1269{
1270 /* Turn off all unused clocks */
1271 struct clk *p;
1272 __u32 regval32;
1273
1274 omap_writew(0, SOFT_REQ_REG);
1275 omap_writew(0, SOFT_REQ_REG2);
1276
1277 list_for_each_entry(p, &clocks, node) {
1278 if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) ||
1279 p->enable_reg == 0)
1280 continue;
1281
1282 /* Assume no DSP clocks have been activated by bootloader */
1283 if (p->flags & DSP_DOMAIN_CLOCK)
1284 continue;
1285
1286 /* Is the clock already disabled? */
1287 if (p->flags & ENABLE_REG_32BIT) {
1288 if (p->flags & VIRTUAL_IO_ADDRESS)
1289 regval32 = __raw_readl(p->enable_reg);
1290 else
1291 regval32 = omap_readl(p->enable_reg);
1292 } else {
1293 if (p->flags & VIRTUAL_IO_ADDRESS)
1294 regval32 = __raw_readw(p->enable_reg);
1295 else
1296 regval32 = omap_readw(p->enable_reg);
1297 }
1298
1299 if ((regval32 & (1 << p->enable_bit)) == 0)
1300 continue;
1301
1302 /* FIXME: This clock seems to be necessary but no-one
1303 * has asked for its activation. */
1304 if (p == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
1305 || p == &ck_dpll1out // FIX: SoSSI, SSR
1306 || p == &arm_gpio_ck // FIX: GPIO code for 1510
1307 ) {
1308 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
1309 p->name);
1310 continue;
1311 }
1312
1313 printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name);
1314 __clk_disable(p);
1315 printk(" done\n");
1316 }
1317
1318 return 0;
1319}
1320
1321late_initcall(omap_late_clk_reset);
1322
1323#endif
diff --git a/arch/arm/plat-omap/clock.h b/arch/arm/plat-omap/clock.h
index 08b504deb1a1..a89e1e8c2519 100644
--- a/arch/arm/plat-omap/clock.h
+++ b/arch/arm/plat-omap/clock.h
@@ -52,6 +52,8 @@ struct mpu_rate {
52#define CLOCK_IN_OMAP16XX 64 52#define CLOCK_IN_OMAP16XX 64
53#define CLOCK_IN_OMAP1510 128 53#define CLOCK_IN_OMAP1510 128
54#define CLOCK_IN_OMAP730 256 54#define CLOCK_IN_OMAP730 256
55#define DSP_DOMAIN_CLOCK 512
56#define VIRTUAL_IO_ADDRESS 1024
55 57
56/* ARM_CKCTL bit shifts */ 58/* ARM_CKCTL bit shifts */
57#define CKCTL_PERDIV_OFFSET 0 59#define CKCTL_PERDIV_OFFSET 0
@@ -63,6 +65,8 @@ struct mpu_rate {
63/*#define ARM_TIMXO 12*/ 65/*#define ARM_TIMXO 12*/
64#define EN_DSPCK 13 66#define EN_DSPCK 13
65/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ 67/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
68/* DSP_CKCTL bit shifts */
69#define CKCTL_DSPPERDIV_OFFSET 0
66 70
67/* ARM_IDLECT1 bit shifts */ 71/* ARM_IDLECT1 bit shifts */
68/*#define IDLWDT_ARM 0*/ 72/*#define IDLWDT_ARM 0*/
@@ -96,6 +100,9 @@ struct mpu_rate {
96#define EN_TC1_CK 2 100#define EN_TC1_CK 2
97#define EN_TC2_CK 4 101#define EN_TC2_CK 4
98 102
103/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
104#define EN_DSPTIMCK 5
105
99/* Various register defines for clock controls scattered around OMAP chip */ 106/* Various register defines for clock controls scattered around OMAP chip */
100#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ 107#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
101#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ 108#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
@@ -103,7 +110,8 @@ struct mpu_rate {
103#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ 110#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
104#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 111#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
105#define COM_CLK_DIV_CTRL_SEL 0xfffe0878 112#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
106 113#define SOFT_REQ_REG 0xfffe0834
114#define SOFT_REQ_REG2 0xfffe0880
107 115
108int clk_register(struct clk *clk); 116int clk_register(struct clk *clk);
109void clk_unregister(struct clk *clk); 117void clk_unregister(struct clk *clk);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 015bd2cf869f..c0a5c2fa42bd 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -794,10 +794,6 @@ static void set_b1_regs(void)
794 w = omap_readw(OMAP1610_DMA_LCD_CTRL); 794 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
795 /* Always set the source port as SDRAM for now*/ 795 /* Always set the source port as SDRAM for now*/
796 w &= ~(0x03 << 6); 796 w &= ~(0x03 << 6);
797 if (lcd_dma.ext_ctrl)
798 w |= 1 << 8;
799 else
800 w &= ~(1 << 8);
801 if (lcd_dma.callback != NULL) 797 if (lcd_dma.callback != NULL)
802 w |= 1 << 1; /* Block interrupt enable */ 798 w |= 1 << 1; /* Block interrupt enable */
803 else 799 else
@@ -889,9 +885,15 @@ void omap_enable_lcd_dma(void)
889 */ 885 */
890 if (enable_1510_mode || !lcd_dma.ext_ctrl) 886 if (enable_1510_mode || !lcd_dma.ext_ctrl)
891 return; 887 return;
888
889 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
890 w |= 1 << 8;
891 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
892
892 w = omap_readw(OMAP1610_DMA_LCD_CCR); 893 w = omap_readw(OMAP1610_DMA_LCD_CCR);
893 w |= 1 << 7; 894 w |= 1 << 7;
894 omap_writew(w, OMAP1610_DMA_LCD_CCR); 895 omap_writew(w, OMAP1610_DMA_LCD_CCR);
896
895 lcd_dma.active = 1; 897 lcd_dma.active = 1;
896} 898}
897 899
@@ -922,10 +924,19 @@ void omap_setup_lcd_dma(void)
922 924
923void omap_stop_lcd_dma(void) 925void omap_stop_lcd_dma(void)
924{ 926{
927 u16 w;
928
925 lcd_dma.active = 0; 929 lcd_dma.active = 0;
926 if (!enable_1510_mode && lcd_dma.ext_ctrl) 930 if (enable_1510_mode || !lcd_dma.ext_ctrl)
927 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~(1 << 7), 931 return;
928 OMAP1610_DMA_LCD_CCR); 932
933 w = omap_readw(OMAP1610_DMA_LCD_CCR);
934 w &= ~(1 << 7);
935 omap_writew(w, OMAP1610_DMA_LCD_CCR);
936
937 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
938 w &= ~(1 << 8);
939 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
929} 940}
930 941
931/* 942/*
@@ -972,6 +983,25 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
972 (OMAP_DMA_CDSA_U(lch) << 16)); 983 (OMAP_DMA_CDSA_U(lch) << 16));
973} 984}
974 985
986int omap_dma_running(void)
987{
988 int lch;
989
990 /* Check if LCD DMA is running */
991 if (cpu_is_omap16xx())
992 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
993 return 1;
994
995 for (lch = 0; lch < dma_chan_count; lch++) {
996 u16 w;
997
998 w = omap_readw(OMAP_DMA_CCR(lch));
999 if (w & OMAP_DMA_CCR_EN)
1000 return 1;
1001 }
1002 return 0;
1003}
1004
975static int __init omap_init_dma(void) 1005static int __init omap_init_dma(void)
976{ 1006{
977 int ch, r; 1007 int ch, r;
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 10c3f22f9c6a..43567d5edddb 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -66,6 +66,7 @@ struct omap_mcbsp {
66static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT]; 66static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
67static struct clk *mcbsp_dsp_ck = 0; 67static struct clk *mcbsp_dsp_ck = 0;
68static struct clk *mcbsp_api_ck = 0; 68static struct clk *mcbsp_api_ck = 0;
69static struct clk *mcbsp_dspxor_ck = 0;
69 70
70 71
71static void omap_mcbsp_dump_reg(u8 id) 72static void omap_mcbsp_dump_reg(u8 id)
@@ -175,7 +176,7 @@ static int omap_mcbsp_check(unsigned int id)
175 return 0; 176 return 0;
176 } 177 }
177 178
178 if (cpu_is_omap1510() || cpu_is_omap1610() || cpu_is_omap1710()) { 179 if (cpu_is_omap1510() || cpu_is_omap16xx()) {
179 if (id > OMAP_MAX_MCBSP_COUNT) { 180 if (id > OMAP_MAX_MCBSP_COUNT) {
180 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1); 181 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
181 return -1; 182 return -1;
@@ -191,15 +192,12 @@ static int omap_mcbsp_check(unsigned int id)
191 192
192static void omap_mcbsp_dsp_request(void) 193static void omap_mcbsp_dsp_request(void)
193{ 194{
194 if (cpu_is_omap1510() || cpu_is_omap1610() || cpu_is_omap1710()) { 195 if (cpu_is_omap1510() || cpu_is_omap16xx()) {
195 omap_writew((omap_readw(ARM_RSTCT1) | (1 << 1) | (1 << 2)), 196 clk_use(mcbsp_dsp_ck);
196 ARM_RSTCT1); 197 clk_use(mcbsp_api_ck);
197 clk_enable(mcbsp_dsp_ck);
198 clk_enable(mcbsp_api_ck);
199 198
200 /* enable 12MHz clock to mcbsp 1 & 3 */ 199 /* enable 12MHz clock to mcbsp 1 & 3 */
201 __raw_writew(__raw_readw(DSP_IDLECT2) | (1 << EN_XORPCK), 200 clk_use(mcbsp_dspxor_ck);
202 DSP_IDLECT2);
203 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1, 201 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
204 DSP_RSTCT2); 202 DSP_RSTCT2);
205 } 203 }
@@ -207,10 +205,13 @@ static void omap_mcbsp_dsp_request(void)
207 205
208static void omap_mcbsp_dsp_free(void) 206static void omap_mcbsp_dsp_free(void)
209{ 207{
210 /* Useless for now */ 208 if (cpu_is_omap1510() || cpu_is_omap16xx()) {
209 clk_unuse(mcbsp_dspxor_ck);
210 clk_unuse(mcbsp_dsp_ck);
211 clk_unuse(mcbsp_api_ck);
212 }
211} 213}
212 214
213
214int omap_mcbsp_request(unsigned int id) 215int omap_mcbsp_request(unsigned int id)
215{ 216{
216 int err; 217 int err;
@@ -350,6 +351,73 @@ void omap_mcbsp_stop(unsigned int id)
350} 351}
351 352
352 353
354/* polled mcbsp i/o operations */
355int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
356{
357 u32 base = mcbsp[id].io_base;
358 writew(buf, base + OMAP_MCBSP_REG_DXR1);
359 /* if frame sync error - clear the error */
360 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
361 /* clear error */
362 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
363 base + OMAP_MCBSP_REG_SPCR2);
364 /* resend */
365 return -1;
366 } else {
367 /* wait for transmit confirmation */
368 int attemps = 0;
369 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
370 if (attemps++ > 1000) {
371 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
372 (~XRST),
373 base + OMAP_MCBSP_REG_SPCR2);
374 udelay(10);
375 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
376 (XRST),
377 base + OMAP_MCBSP_REG_SPCR2);
378 udelay(10);
379 printk(KERN_ERR
380 " Could not write to McBSP Register\n");
381 return -2;
382 }
383 }
384 }
385 return 0;
386}
387
388int omap_mcbsp_pollread(unsigned int id, u16 * buf)
389{
390 u32 base = mcbsp[id].io_base;
391 /* if frame sync error - clear the error */
392 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
393 /* clear error */
394 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
395 base + OMAP_MCBSP_REG_SPCR1);
396 /* resend */
397 return -1;
398 } else {
399 /* wait for recieve confirmation */
400 int attemps = 0;
401 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
402 if (attemps++ > 1000) {
403 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
404 (~RRST),
405 base + OMAP_MCBSP_REG_SPCR1);
406 udelay(10);
407 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
408 (RRST),
409 base + OMAP_MCBSP_REG_SPCR1);
410 udelay(10);
411 printk(KERN_ERR
412 " Could not read from McBSP Register\n");
413 return -2;
414 }
415 }
416 }
417 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
418 return 0;
419}
420
353/* 421/*
354 * IRQ based word transmission. 422 * IRQ based word transmission.
355 */ 423 */
@@ -625,10 +693,15 @@ static int __init omap_mcbsp_init(void)
625 return PTR_ERR(mcbsp_dsp_ck); 693 return PTR_ERR(mcbsp_dsp_ck);
626 } 694 }
627 mcbsp_api_ck = clk_get(0, "api_ck"); 695 mcbsp_api_ck = clk_get(0, "api_ck");
628 if (IS_ERR(mcbsp_dsp_ck)) { 696 if (IS_ERR(mcbsp_api_ck)) {
629 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n"); 697 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
630 return PTR_ERR(mcbsp_api_ck); 698 return PTR_ERR(mcbsp_api_ck);
631 } 699 }
700 mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
701 if (IS_ERR(mcbsp_dspxor_ck)) {
702 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
703 return PTR_ERR(mcbsp_dspxor_ck);
704 }
632 705
633#ifdef CONFIG_ARCH_OMAP730 706#ifdef CONFIG_ARCH_OMAP730
634 if (cpu_is_omap730()) { 707 if (cpu_is_omap730()) {
@@ -643,7 +716,7 @@ static int __init omap_mcbsp_init(void)
643 } 716 }
644#endif 717#endif
645#if defined(CONFIG_ARCH_OMAP16XX) 718#if defined(CONFIG_ARCH_OMAP16XX)
646 if (cpu_is_omap1610() || cpu_is_omap1710()) { 719 if (cpu_is_omap16xx()) {
647 mcbsp_info = mcbsp_1610; 720 mcbsp_info = mcbsp_1610;
648 mcbsp_count = ARRAY_SIZE(mcbsp_1610); 721 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
649 } 722 }
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index cbecd10d0b6c..ea7b955b9c81 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -53,19 +53,13 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
53 return -EINVAL; 53 return -EINVAL;
54 } 54 }
55 55
56 cfg = &reg_cfg_table[reg_cfg]; 56 cfg = (reg_cfg_set *)&reg_cfg_table[reg_cfg];
57
58 /*
59 * We do a pretty long section here with lock on, but pin muxing
60 * should only happen on driver init for each driver, so it's not time
61 * critical.
62 */
63 spin_lock_irqsave(&mux_spin_lock, flags);
64 57
65 /* Check the mux register in question */ 58 /* Check the mux register in question */
66 if (cfg->mux_reg) { 59 if (cfg->mux_reg) {
67 unsigned tmp1, tmp2; 60 unsigned tmp1, tmp2;
68 61
62 spin_lock_irqsave(&mux_spin_lock, flags);
69 reg_orig = omap_readl(cfg->mux_reg); 63 reg_orig = omap_readl(cfg->mux_reg);
70 64
71 /* The mux registers always seem to be 3 bits long */ 65 /* The mux registers always seem to be 3 bits long */
@@ -80,11 +74,13 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
80 warn = 1; 74 warn = 1;
81 75
82 omap_writel(reg, cfg->mux_reg); 76 omap_writel(reg, cfg->mux_reg);
77 spin_unlock_irqrestore(&mux_spin_lock, flags);
83 } 78 }
84 79
85 /* Check for pull up or pull down selection on 1610 */ 80 /* Check for pull up or pull down selection on 1610 */
86 if (!cpu_is_omap1510()) { 81 if (!cpu_is_omap1510()) {
87 if (cfg->pu_pd_reg && cfg->pull_val) { 82 if (cfg->pu_pd_reg && cfg->pull_val) {
83 spin_lock_irqsave(&mux_spin_lock, flags);
88 pu_pd_orig = omap_readl(cfg->pu_pd_reg); 84 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
89 mask = 1 << cfg->pull_bit; 85 mask = 1 << cfg->pull_bit;
90 86
@@ -100,11 +96,13 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
100 pu_pd = pu_pd_orig & ~mask; 96 pu_pd = pu_pd_orig & ~mask;
101 } 97 }
102 omap_writel(pu_pd, cfg->pu_pd_reg); 98 omap_writel(pu_pd, cfg->pu_pd_reg);
99 spin_unlock_irqrestore(&mux_spin_lock, flags);
103 } 100 }
104 } 101 }
105 102
106 /* Check for an associated pull down register */ 103 /* Check for an associated pull down register */
107 if (cfg->pull_reg) { 104 if (cfg->pull_reg) {
105 spin_lock_irqsave(&mux_spin_lock, flags);
108 pull_orig = omap_readl(cfg->pull_reg); 106 pull_orig = omap_readl(cfg->pull_reg);
109 mask = 1 << cfg->pull_bit; 107 mask = 1 << cfg->pull_bit;
110 108
@@ -121,6 +119,7 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
121 } 119 }
122 120
123 omap_writel(pull, cfg->pull_reg); 121 omap_writel(pull, cfg->pull_reg);
122 spin_unlock_irqrestore(&mux_spin_lock, flags);
124 } 123 }
125 124
126 if (warn) { 125 if (warn) {
@@ -149,8 +148,6 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
149 } 148 }
150#endif 149#endif
151 150
152 spin_unlock_irqrestore(&mux_spin_lock, flags);
153
154#ifdef CONFIG_OMAP_MUX_ERRORS 151#ifdef CONFIG_OMAP_MUX_ERRORS
155 return warn ? -ETXTBSY : 0; 152 return warn ? -ETXTBSY : 0;
156#else 153#else
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index ab38e4eb3130..25bc4a8dd763 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -326,7 +326,7 @@ static u64 ohci_dmamask = ~(u32)0;
326static struct resource ohci_resources[] = { 326static struct resource ohci_resources[] = {
327 { 327 {
328 .start = OMAP_OHCI_BASE, 328 .start = OMAP_OHCI_BASE,
329 .end = OMAP_OHCI_BASE + 4096, 329 .end = OMAP_OHCI_BASE + 4096 - 1,
330 .flags = IORESOURCE_MEM, 330 .flags = IORESOURCE_MEM,
331 }, 331 },
332 { 332 {