50 files changed, 2471 insertions, 1114 deletions

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index e2ea04a4c8a1..6da796ef82bd 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -7,27 +7,37 @@ config ARCH_OMAP_OTG
 
 choice
         prompt "OMAP System Type"
-        default ARCH_OMAP1
+        default ARCH_OMAP2PLUS
 
 config ARCH_OMAP1
         bool "TI OMAP1"
         select COMMON_CLKDEV
+        help
+          "Systems based on omap7xx, omap15xx or omap16xx"
+
+config ARCH_OMAP2PLUS
+        bool "TI OMAP2/3/4"
+        select COMMON_CLKDEV
+        help
+          "Systems based on omap24xx, omap34xx or omap44xx"
 
 config ARCH_OMAP2
         bool "TI OMAP2"
+        depends on ARCH_OMAP2PLUS
         select CPU_V6
-        select COMMON_CLKDEV
 
 config ARCH_OMAP3
         bool "TI OMAP3"
+        depends on ARCH_OMAP2PLUS
         select CPU_V7
-        select COMMON_CLKDEV
+        select USB_ARCH_HAS_EHCI
+        select ARM_L1_CACHE_SHIFT_6
 
 config ARCH_OMAP4
         bool "TI OMAP4"
+        depends on ARCH_OMAP2PLUS
         select CPU_V7
         select ARM_GIC
-        select COMMON_CLKDEV
 
 endchoice
 
@@ -116,7 +126,7 @@ config OMAP_MPU_TIMER
 
 config OMAP_32K_TIMER
         bool "Use 32KHz timer"
-        depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4
+        depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
         help
           Select this option if you want to enable the OMAP 32KHz timer.
           This timer saves power compared to the OMAP_MPU_TIMER, and has
@@ -126,6 +136,23 @@ config OMAP_32K_TIMER
 
 endchoice
 
+config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
+        bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
+        depends on ARCH_OMAP3 && PM
+        default n
+        help
+          Without this option, L2 Auxiliary control register contents are
+          lost during off-mode entry on HS/EMU devices. This feature
+          requires support from PPA / boot-loader in HS/EMU devices, which
+          currently does not exist by default.
+
+config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
+        int "Service ID for the support routine to set L2 AUX control"
+        depends on OMAP3_L2_AUX_SECURE_SAVE_RESTORE
+        default 43
+        help
+          PPA routine service ID for setting L2 auxiliary control register.
+
 config OMAP_32K_TIMER_HZ
         int "Kernel internal timer frequency for 32KHz timer"
         range 32 1024
@@ -137,29 +164,10 @@ config OMAP_32K_TIMER_HZ
 
 config OMAP_DM_TIMER
         bool "Use dual-mode timer"
-        depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4
+        depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
         help
          Select this option if you want to use OMAP Dual-Mode timers.
 
-choice
-        prompt "Low-level debug console UART"
-        depends on ARCH_OMAP
-        default OMAP_LL_DEBUG_NONE
-
-config OMAP_LL_DEBUG_UART1
-        bool "UART1"
-
-config OMAP_LL_DEBUG_UART2
-        bool "UART2"
-
-config OMAP_LL_DEBUG_UART3
-        bool "UART3"
-
-config OMAP_LL_DEBUG_NONE
-        bool "None"
-
-endchoice
-
 config OMAP_SERIAL_WAKE
         bool "Enable wake-up events for serial ports"
         depends on ARCH_OMAP1 && OMAP_MUX
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 89cafc937249..5261a0923691 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -36,10 +36,6 @@ static struct clk_functions *arch_clock;
  * Standard clock functions defined in include/linux/clk.h
  *-------------------------------------------------------------------------*/
 
-/* This functions is moved to arch/arm/common/clkdev.c. For OMAP4 since
- * clock framework is not up , it is defined here to avoid rework in
- * every driver. Also dummy prcm reset function is added */
-
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
@@ -177,7 +173,7 @@ EXPORT_SYMBOL(clk_get_parent);
  * OMAP specific clock functions shared between omap1 and omap2
  *-------------------------------------------------------------------------*/
 
-unsigned int __initdata mpurate;
+int __initdata mpurate;
 
 /*
  * By default we use the rate set by the bootloader.
@@ -203,6 +199,17 @@ unsigned long followparent_recalc(struct clk *clk)
         return clk->parent->rate;
 }
 
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+unsigned long omap_fixed_divisor_recalc(struct clk *clk)
+{
+        WARN_ON(!clk->fixed_div);
+
+        return clk->parent->rate / clk->fixed_div;
+}
+
 void clk_reparent(struct clk *child, struct clk *parent)
 {
         list_del_init(&child->sibling);
@@ -305,7 +312,33 @@ void clk_enable_init_clocks(void)
                         clk_enable(clkp);
         }
 }
-EXPORT_SYMBOL(clk_enable_init_clocks);
+
+/**
+ * omap_clk_get_by_name - locate OMAP struct clk by its name
+ * @name: name of the struct clk to locate
+ *
+ * Locate an OMAP struct clk by its name.  Assumes that struct clk
+ * names are unique.  Returns NULL if not found or a pointer to the
+ * struct clk if found.
+ */
+struct clk *omap_clk_get_by_name(const char *name)
+{
+        struct clk *c;
+        struct clk *ret = NULL;
+
+        mutex_lock(&clocks_mutex);
+
+        list_for_each_entry(c, &clocks, node) {
+                if (!strcmp(c->name, name)) {
+                        ret = c;
+                        break;
+                }
+        }
+
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
 
 /*
  * Low level helpers
@@ -324,6 +357,16 @@ const struct clkops clkops_null = {
         .disable        = clkll_disable_null,
 };
 
+/*
+ * Dummy clock
+ *
+ * Used for clock aliases that are needed on some OMAPs, but not others
+ */
+struct clk dummy_ck = {
+        .name   = "dummy",
+        .ops    = &clkops_null,
+};
+
 #ifdef CONFIG_CPU_FREQ
 void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 {
@@ -334,7 +377,16 @@ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
                 arch_clock->clk_init_cpufreq_table(table);
         spin_unlock_irqrestore(&clockfw_lock, flags);
 }
-EXPORT_SYMBOL(clk_init_cpufreq_table);
+
+void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (arch_clock->clk_exit_cpufreq_table)
+                arch_clock->clk_exit_cpufreq_table(table);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+}
 #endif
 
 /*-------------------------------------------------------------------------*/
@@ -387,14 +439,12 @@ static struct dentry *clk_debugfs_root;
 static int clk_debugfs_register_one(struct clk *c)
 {
         int err;
-        struct dentry *d, *child;
+        struct dentry *d, *child, *child_tmp;
         struct clk *pa = c->parent;
         char s[255];
         char *p = s;
 
         p += sprintf(p, "%s", c->name);
-        if (c->id != 0)
-                sprintf(p, ":%d", c->id);
         d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
         if (!d)
                 return -ENOMEM;
@@ -419,7 +469,7 @@ static int clk_debugfs_register_one(struct clk *c)
 
 err_out:
         d = c->dent;
-        list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
+        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
                 debugfs_remove(child);
         debugfs_remove(c->dent);
         return err;
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index bf1eaf3a27d4..088c1a03b946 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -34,6 +34,7 @@
 #include <plat/control.h>
 #include <plat/mux.h>
 #include <plat/fpga.h>
+#include <plat/serial.h>
 
 #include <plat/clock.h>
 
@@ -126,7 +127,7 @@ static cycle_t omap2430_32k_read(struct clocksource *cs)
 #define omap2430_32k_read       NULL
 #endif
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
 static cycle_t omap34xx_32k_read(struct clocksource *cs)
 {
         return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10);
@@ -172,6 +173,32 @@ unsigned long long sched_clock(void)
                                   clocksource_32k.mult, clocksource_32k.shift);
 }
 
+/**
+ * read_persistent_clock -  Return time from a persistent clock.
+ *
+ * Reads the time from a source which isn't disabled during PM, the
+ * 32k sync timer.  Convert the cycles elapsed since last read into
+ * nsecs and adds to a monotonically increasing timespec.
+ */
+static struct timespec persistent_ts;
+static cycles_t cycles, last_cycles;
+void read_persistent_clock(struct timespec *ts)
+{
+        unsigned long long nsecs;
+        cycles_t delta;
+        struct timespec *tsp = &persistent_ts;
+
+        last_cycles = cycles;
+        cycles = clocksource_32k.read(&clocksource_32k);
+        delta = cycles - last_cycles;
+
+        nsecs = clocksource_cyc2ns(delta,
+                                   clocksource_32k.mult, clocksource_32k.shift);
+
+        timespec_add_ns(tsp, nsecs);
+        *ts = *tsp;
+}
+
 static int __init omap_init_clocksource_32k(void)
 {
         static char err[] __initdata = KERN_ERR
@@ -219,6 +246,7 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
         omap2_set_globals_sdrc(omap2_globals);
         omap2_set_globals_control(omap2_globals);
         omap2_set_globals_prcm(omap2_globals);
+        omap2_set_globals_uart(omap2_globals);
 }
 
 #endif
@@ -228,11 +256,14 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
 static struct omap_globals omap242x_globals = {
         .class  = OMAP242X_CLASS,
         .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
-        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
-        .sms    = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
+        .sdrc   = OMAP2420_SDRC_BASE,
+        .sms    = OMAP2420_SMS_BASE,
+        .ctrl   = OMAP2420_CTRL_BASE,
+        .prm    = OMAP2420_PRM_BASE,
+        .cm     = OMAP2420_CM_BASE,
+        .uart1_phys     = OMAP2_UART1_BASE,
+        .uart2_phys     = OMAP2_UART2_BASE,
+        .uart3_phys     = OMAP2_UART3_BASE,
 };
 
 void __init omap2_set_globals_242x(void)
@@ -246,11 +277,14 @@ void __init omap2_set_globals_242x(void)
 static struct omap_globals omap243x_globals = {
         .class  = OMAP243X_CLASS,
         .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
-        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
-        .sms    = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
+        .sdrc   = OMAP243X_SDRC_BASE,
+        .sms    = OMAP243X_SMS_BASE,
+        .ctrl   = OMAP243X_CTRL_BASE,
+        .prm    = OMAP2430_PRM_BASE,
+        .cm     = OMAP2430_CM_BASE,
+        .uart1_phys     = OMAP2_UART1_BASE,
+        .uart2_phys     = OMAP2_UART2_BASE,
+        .uart3_phys     = OMAP2_UART3_BASE,
 };
 
 void __init omap2_set_globals_243x(void)
@@ -259,21 +293,31 @@ void __init omap2_set_globals_243x(void)
 }
 #endif
 
-#if defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_ARCH_OMAP3)
 
-static struct omap_globals omap343x_globals = {
+static struct omap_globals omap3_globals = {
         .class  = OMAP343X_CLASS,
         .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
-        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
-        .sms    = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
+        .sdrc   = OMAP343X_SDRC_BASE,
+        .sms    = OMAP343X_SMS_BASE,
+        .ctrl   = OMAP343X_CTRL_BASE,
+        .prm    = OMAP3430_PRM_BASE,
+        .cm     = OMAP3430_CM_BASE,
+        .uart1_phys     = OMAP3_UART1_BASE,
+        .uart2_phys     = OMAP3_UART2_BASE,
+        .uart3_phys     = OMAP3_UART3_BASE,
 };
 
 void __init omap2_set_globals_343x(void)
 {
-        __omap2_set_globals(&omap343x_globals);
+        __omap2_set_globals(&omap3_globals);
+}
+
+void __init omap2_set_globals_36xx(void)
+{
+        omap3_globals.uart4_phys = OMAP3_UART4_BASE;
+
+        __omap2_set_globals(&omap3_globals);
 }
 #endif
 
@@ -281,10 +325,14 @@ void __init omap2_set_globals_343x(void)
 static struct omap_globals omap4_globals = {
         .class  = OMAP443X_CLASS,
         .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
-        .cm2    = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
+        .ctrl   = OMAP443X_CTRL_BASE,
+        .prm    = OMAP4430_PRM_BASE,
+        .cm     = OMAP4430_CM_BASE,
+        .cm2    = OMAP4430_CM2_BASE,
+        .uart1_phys     = OMAP4_UART1_BASE,
+        .uart2_phys     = OMAP4_UART2_BASE,
+        .uart3_phys     = OMAP4_UART3_BASE,
+        .uart4_phys     = OMAP4_UART4_BASE,
 };
 
 void __init omap2_set_globals_443x(void)
@@ -292,6 +340,7 @@ void __init omap2_set_globals_443x(void)
         omap2_set_globals_tap(&omap4_globals);
         omap2_set_globals_control(&omap4_globals);
         omap2_set_globals_prcm(&omap4_globals);
+        omap2_set_globals_uart(&omap4_globals);
 }
 #endif
 
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index f8ddbdd8b076..6d3d33360056 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -134,6 +134,7 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy)
 
 static int omap_cpu_exit(struct cpufreq_policy *policy)
 {
+        clk_exit_cpufreq_table(&freq_table);
         clk_put(mpu_clk);
         return 0;
 }
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 30b5db73017a..4a4cd8774aaa 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -28,6 +28,7 @@
 #include <plat/menelaus.h>
 #include <plat/mcbsp.h>
 #include <plat/dsp_common.h>
+#include <plat/omap44xx.h>
 
 #if     defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
 
@@ -192,6 +193,41 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 
 /*-------------------------------------------------------------------------*/
 
+#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
+                defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
+
+static struct resource mcpdm_resources[] = {
+        {
+                .name           = "mcpdm_mem",
+                .start          = OMAP44XX_MCPDM_BASE,
+                .end            = OMAP44XX_MCPDM_BASE + SZ_4K,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .name           = "mcpdm_irq",
+                .start          = OMAP44XX_IRQ_MCPDM,
+                .end            = OMAP44XX_IRQ_MCPDM,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device omap_mcpdm_device = {
+        .name           = "omap-mcpdm",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mcpdm_resources),
+        .resource       = mcpdm_resources,
+};
+
+static void omap_init_mcpdm(void)
+{
+        (void) platform_device_register(&omap_mcpdm_device);
+}
+#else
+static inline void omap_init_mcpdm(void) {}
+#endif
+
+/*-------------------------------------------------------------------------*/
+
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
@@ -244,7 +280,7 @@ fail:
 
 #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
 
-#ifdef CONFIG_ARCH_OMAP24XX
+#ifdef CONFIG_ARCH_OMAP2
 #define OMAP_RNG_BASE           0x480A0000
 #else
 #define OMAP_RNG_BASE           0xfffe5000
@@ -385,6 +421,7 @@ static int __init omap_init_devices(void)
         omap_init_dsp();
         omap_init_kp();
         omap_init_rng();
+        omap_init_mcpdm();
         omap_init_uwire();
         omap_init_wdt();
         return 0;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 09d82b3c66ce..2ab224c8e16c 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1183,7 +1183,7 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
         }
 
         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
-            (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
+            (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
                        "before unlinking\n");
                 dump_stack();
@@ -1870,8 +1870,7 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 #define omap1_dma_irq_handler   NULL
 #endif
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
 
 static int omap2_dma_handle_ch(int ch)
 {
@@ -2133,13 +2132,13 @@ static int __init omap_init_dma(void)
         if (cpu_class_is_omap2()) {
                 int irq;
                 if (cpu_is_omap44xx())
-                        irq = INT_44XX_SDMA_IRQ0;
+                        irq = OMAP44XX_IRQ_SDMA_0;
                 else
                         irq = INT_24XX_SDMA_IRQ0;
                 setup_irq(irq, &omap24xx_dma_irq);
         }
 
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 /* Enable smartidle idlemodes and autoidle */
                 u32 v = dma_read(OCP_SYSCONFIG);
                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
@@ -2150,7 +2149,8 @@ static int __init omap_init_dma(void)
                         DMA_SYSCONFIG_AUTOIDLE);
                 dma_write(v , OCP_SYSCONFIG);
                 /* reserve dma channels 0 and 1 in high security devices */
-                if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+                if (cpu_is_omap34xx() &&
+                        (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
                         printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
                                         "HS ROM code\n");
                         dma_chan[0].dev_id = 0;
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 64f407ee0f4e..4d99dfbc8bef 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -153,8 +153,7 @@
 struct omap_dm_timer {
         unsigned long phys_base;
         int irq;
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
         struct clk *iclk, *fclk;
 #endif
         void __iomem *io_base;
@@ -163,20 +162,9 @@ struct omap_dm_timer {
         unsigned posted:1;
 };
 
-#ifdef CONFIG_ARCH_OMAP1
-
-#define omap_dm_clk_enable(x)
-#define omap_dm_clk_disable(x)
-#define omap2_dm_timers                 NULL
-#define omap2_dm_source_names           NULL
-#define omap2_dm_source_clocks          NULL
-#define omap3_dm_timers                 NULL
-#define omap3_dm_source_names           NULL
-#define omap3_dm_source_clocks          NULL
-#define omap4_dm_timers                 NULL
-#define omap4_dm_source_names           NULL
-#define omap4_dm_source_clocks          NULL
+static int dm_timer_count;
 
+#ifdef CONFIG_ARCH_OMAP1
 static struct omap_dm_timer omap1_dm_timers[] = {
         { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
         { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
@@ -188,20 +176,14 @@ static struct omap_dm_timer omap1_dm_timers[] = {
         { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
 };
 
-static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
-
-#elif defined(CONFIG_ARCH_OMAP2)
+static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
 
-#define omap_dm_clk_enable(x)           clk_enable(x)
-#define omap_dm_clk_disable(x)          clk_disable(x)
+#else
 #define omap1_dm_timers                 NULL
-#define omap3_dm_timers                 NULL
-#define omap3_dm_source_names           NULL
-#define omap3_dm_source_clocks          NULL
-#define omap4_dm_timers                 NULL
-#define omap4_dm_source_names           NULL
-#define omap4_dm_source_clocks          NULL
+#define omap1_dm_timer_count            0
+#endif  /* CONFIG_ARCH_OMAP1 */
 
+#ifdef CONFIG_ARCH_OMAP2
 static struct omap_dm_timer omap2_dm_timers[] = {
         { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
         { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
@@ -225,20 +207,16 @@ static const char *omap2_dm_source_names[] __initdata = {
 };
 
 static struct clk *omap2_dm_source_clocks[3];
-static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
+static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
 
-#elif defined(CONFIG_ARCH_OMAP3)
-
-#define omap_dm_clk_enable(x)           clk_enable(x)
-#define omap_dm_clk_disable(x)          clk_disable(x)
-#define omap1_dm_timers                 NULL
+#else
 #define omap2_dm_timers                 NULL
+#define omap2_dm_timer_count            0
 #define omap2_dm_source_names           NULL
 #define omap2_dm_source_clocks          NULL
-#define omap4_dm_timers                 NULL
-#define omap4_dm_source_names           NULL
-#define omap4_dm_source_clocks          NULL
+#endif  /* CONFIG_ARCH_OMAP2 */
 
+#ifdef CONFIG_ARCH_OMAP3
 static struct omap_dm_timer omap3_dm_timers[] = {
         { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
         { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
@@ -261,33 +239,29 @@ static const char *omap3_dm_source_names[] __initdata = {
 };
 
 static struct clk *omap3_dm_source_clocks[2];
-static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
-
-#elif defined(CONFIG_ARCH_OMAP4)
+static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
 
-#define omap_dm_clk_enable(x)           clk_enable(x)
-#define omap_dm_clk_disable(x)          clk_disable(x)
-#define omap1_dm_timers                 NULL
-#define omap2_dm_timers                 NULL
-#define omap2_dm_source_names           NULL
-#define omap2_dm_source_clocks          NULL
+#else
 #define omap3_dm_timers                 NULL
+#define omap3_dm_timer_count            0
 #define omap3_dm_source_names           NULL
 #define omap3_dm_source_clocks          NULL
+#endif  /* CONFIG_ARCH_OMAP3 */
 
+#ifdef CONFIG_ARCH_OMAP4
 static struct omap_dm_timer omap4_dm_timers[] = {
-        { .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 },
-        { .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 },
-        { .phys_base = 0x48034000, .irq = INT_44XX_GPTIMER3 },
-        { .phys_base = 0x48036000, .irq = INT_44XX_GPTIMER4 },
-        { .phys_base = 0x40138000, .irq = INT_44XX_GPTIMER5 },
-        { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER6 },
-        { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER7 },
-        { .phys_base = 0x4013e000, .irq = INT_44XX_GPTIMER8 },
-        { .phys_base = 0x4803e000, .irq = INT_44XX_GPTIMER9 },
-        { .phys_base = 0x48086000, .irq = INT_44XX_GPTIMER10 },
-        { .phys_base = 0x48088000, .irq = INT_44XX_GPTIMER11 },
-        { .phys_base = 0x4a320000, .irq = INT_44XX_GPTIMER12 },
+        { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 },
+        { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 },
+        { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 },
+        { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 },
+        { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 },
+        { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 },
+        { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 },
+        { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 },
+        { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 },
+        { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 },
+        { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 },
+        { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
 };
 static const char *omap4_dm_source_names[] __initdata = {
         "sys_ck",
@@ -295,13 +269,14 @@ static const char *omap4_dm_source_names[] __initdata = {
         NULL
 };
 static struct clk *omap4_dm_source_clocks[2];
-static const int dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
+static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
 
 #else
-
-#error OMAP architecture not supported!
-
-#endif
+#define omap4_dm_timers                 NULL
+#define omap4_dm_timer_count            0
+#define omap4_dm_source_names           NULL
+#define omap4_dm_source_clocks          NULL
+#endif  /* CONFIG_ARCH_OMAP4 */
 
 static struct omap_dm_timer *dm_timers;
 static const char **dm_source_names;
@@ -450,8 +425,12 @@ void omap_dm_timer_enable(struct omap_dm_timer *timer)
         if (timer->enabled)
                 return;
 
-        omap_dm_clk_enable(timer->fclk);
-        omap_dm_clk_enable(timer->iclk);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+        if (cpu_class_is_omap2()) {
+                clk_enable(timer->fclk);
+                clk_enable(timer->iclk);
+        }
+#endif
 
         timer->enabled = 1;
 }
@@ -462,8 +441,12 @@ void omap_dm_timer_disable(struct omap_dm_timer *timer)
         if (!timer->enabled)
                 return;
 
-        omap_dm_clk_disable(timer->iclk);
-        omap_dm_clk_disable(timer->fclk);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+        if (cpu_class_is_omap2()) {
+                clk_disable(timer->iclk);
+                clk_disable(timer->fclk);
+        }
+#endif
 
         timer->enabled = 0;
 }
@@ -506,8 +489,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 
-#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#else
 
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 {
@@ -551,6 +533,18 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
         if (l & OMAP_TIMER_CTRL_ST) {
                 l &= ~0x1;
                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+                /* Readback to make sure write has completed */
+                omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+                 /*
+                  * Wait for functional clock period x 3.5 to make sure that
+                  * timer is stopped
+                  */
+                udelay(3500000 / clk_get_rate(timer->fclk) + 1);
+                /* Ack possibly pending interrupt */
+                omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
+                                OMAP_TIMER_INT_OVERFLOW);
+#endif
         }
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
@@ -751,17 +745,21 @@ int __init omap_dm_timer_init(void)
 
         if (cpu_class_is_omap1()) {
                 dm_timers = omap1_dm_timers;
+                dm_timer_count = omap1_dm_timer_count;
                 map_size = SZ_2K;
         } else if (cpu_is_omap24xx()) {
                 dm_timers = omap2_dm_timers;
+                dm_timer_count = omap2_dm_timer_count;
                 dm_source_names = omap2_dm_source_names;
                 dm_source_clocks = omap2_dm_source_clocks;
         } else if (cpu_is_omap34xx()) {
                 dm_timers = omap3_dm_timers;
+                dm_timer_count = omap3_dm_timer_count;
                 dm_source_names = omap3_dm_source_names;
                 dm_source_clocks = omap3_dm_source_clocks;
         } else if (cpu_is_omap44xx()) {
                 dm_timers = omap4_dm_timers;
+                dm_timer_count = omap4_dm_timer_count;
                 dm_source_names = omap4_dm_source_names;
                 dm_source_clocks = omap4_dm_source_clocks;
         }
@@ -780,8 +778,7 @@ int __init omap_dm_timer_init(void)
                 timer->io_base = ioremap(timer->phys_base, map_size);
                 BUG_ON(!timer->io_base);
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                                        defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
                 if (cpu_class_is_omap2()) {
                         char clk_name[16];
                         sprintf(clk_name, "gpt%d_ick", i + 1);
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 04846811d0aa..337199ed3479 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -177,13 +177,11 @@ struct gpio_bank {
         u16 irq;
         u16 virtual_irq_start;
         int method;
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) ||  \
-                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
         u32 suspend_wakeup;
         u32 saved_wakeup;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
         u32 non_wakeup_gpios;
         u32 enabled_non_wakeup_gpios;
 
@@ -192,6 +190,7 @@ struct gpio_bank {
         u32 saved_risingdetect;
 #endif
         u32 level_mask;
+        u32 toggle_mask;
         spinlock_t lock;
         struct gpio_chip chip;
         struct clk *dbck;
@@ -203,6 +202,7 @@ struct gpio_bank {
 #define METHOD_GPIO_1610        2
 #define METHOD_GPIO_7XX         3
 #define METHOD_GPIO_24XX        5
+#define METHOD_GPIO_44XX        6
 
 #ifdef CONFIG_ARCH_OMAP16XX
 static struct gpio_bank gpio_bank_1610[5] = {
@@ -247,7 +247,7 @@ static struct gpio_bank gpio_bank_7xx[7] = {
 };
 #endif
 
-#ifdef CONFIG_ARCH_OMAP24XX
+#ifdef CONFIG_ARCH_OMAP2
 
 static struct gpio_bank gpio_bank_242x[4] = {
         { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
@@ -275,7 +275,7 @@ static struct gpio_bank gpio_bank_243x[5] = {
 
 #endif
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
 static struct gpio_bank gpio_bank_34xx[6] = {
         { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
                 METHOD_GPIO_24XX },
@@ -312,18 +312,18 @@ static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
 
 #ifdef CONFIG_ARCH_OMAP4
 static struct gpio_bank gpio_bank_44xx[6] = {
-        { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
-                METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
-                METHOD_GPIO_24XX },
-        { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
-                METHOD_GPIO_24XX },
+        { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
+                METHOD_GPIO_44XX },
+        { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
+                METHOD_GPIO_44XX },
+        { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
+                METHOD_GPIO_44XX },
+        { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
+                METHOD_GPIO_44XX },
+        { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
+                METHOD_GPIO_44XX },
+        { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
+                METHOD_GPIO_44XX },
 };
 
 #endif
@@ -425,13 +425,13 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
                 reg += OMAP7XX_GPIO_DIR_CONTROL;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_OE;
                 break;
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP4_GPIO_OE;
                 break;
 #endif
@@ -492,7 +492,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                         l &= ~(1 << gpio);
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 if (enable)
                         reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -502,7 +502,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                 break;
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 if (enable)
                         reg += OMAP4_GPIO_SETDATAOUT;
                 else
@@ -545,13 +545,13 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
                 reg += OMAP7XX_GPIO_DATA_INPUT;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_DATAIN;
                 break;
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP4_GPIO_DATAIN;
                 break;
 #endif
@@ -591,9 +591,9 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
                 reg += OMAP7XX_GPIO_DATA_OUTPUT;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
         case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP24XX_GPIO_DATAOUT;
                 break;
 #endif
@@ -624,11 +624,12 @@ void omap_set_gpio_debounce(int gpio, int enable)
 
         bank = get_gpio_bank(gpio);
         reg = bank->base;
-#ifdef CONFIG_ARCH_OMAP4
-        reg += OMAP4_GPIO_DEBOUNCENABLE;
-#else
-        reg += OMAP24XX_GPIO_DEBOUNCE_EN;
-#endif
+
+        if (cpu_is_omap44xx())
+                reg += OMAP4_GPIO_DEBOUNCENABLE;
+        else
+                reg += OMAP24XX_GPIO_DEBOUNCE_EN;
+
         if (!(bank->mod_usage & l)) {
                 printk(KERN_ERR "GPIO %d not requested\n", gpio);
                 return;
@@ -674,17 +675,17 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
         }
 
         enc_time &= 0xff;
-#ifdef CONFIG_ARCH_OMAP4
-        reg += OMAP4_GPIO_DEBOUNCINGTIME;
-#else
-        reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
-#endif
+
+        if (cpu_is_omap44xx())
+                reg += OMAP4_GPIO_DEBOUNCINGTIME;
+        else
+                reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
+
         __raw_writel(enc_time, reg);
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
 
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
                                                 int trigger)
 {
@@ -749,6 +750,44 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
 }
 #endif
 
+#ifdef CONFIG_ARCH_OMAP1
+/*
+ * This only applies to chips that can't do both rising and falling edge
+ * detection at once.  For all other chips, this function is a noop.
+ */
+static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
+{
+        void __iomem *reg = bank->base;
+        u32 l = 0;
+
+        switch (bank->method) {
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_GPIO_INT_EDGE;
+                break;
+#ifdef CONFIG_ARCH_OMAP15XX
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_INT_CONTROL;
+                break;
+#endif
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_CONTROL;
+                break;
+#endif
+        default:
+                return;
+        }
+
+        l = __raw_readl(reg);
+        if ((l >> gpio) & 1)
+                l &= ~(1 << gpio);
+        else
+                l |= 1 << gpio;
+
+        __raw_writel(l, reg);
+}
+#endif
+
 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 {
         void __iomem *reg = bank->base;
@@ -759,6 +798,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
         case METHOD_MPUIO:
                 reg += OMAP_MPUIO_GPIO_INT_EDGE;
                 l = __raw_readl(reg);
+                if (trigger & IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
                 if (trigger & IRQ_TYPE_EDGE_RISING)
                         l |= 1 << gpio;
                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -771,6 +812,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
         case METHOD_GPIO_1510:
                 reg += OMAP1510_GPIO_INT_CONTROL;
                 l = __raw_readl(reg);
+                if (trigger & IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
                 if (trigger & IRQ_TYPE_EDGE_RISING)
                         l |= 1 << gpio;
                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -803,6 +846,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
         case METHOD_GPIO_7XX:
                 reg += OMAP7XX_GPIO_INT_CONTROL;
                 l = __raw_readl(reg);
+                if (trigger & IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
                 if (trigger & IRQ_TYPE_EDGE_RISING)
                         l |= 1 << gpio;
                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -811,9 +856,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
                         goto bad;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
         case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 set_24xx_gpio_triggering(bank, gpio, trigger);
                 break;
 #endif
@@ -892,13 +937,13 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
                 reg += OMAP7XX_GPIO_INT_STATUS;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_IRQSTATUS1;
                 break;
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP4_GPIO_IRQSTATUS0;
                 break;
 #endif
@@ -909,12 +954,11 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
         __raw_writel(gpio_mask, reg);
 
         /* Workaround for clearing DSP GPIO interrupts to allow retention */
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-        reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
-#endif
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
+        else if (cpu_is_omap44xx())
+                reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
+
         if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 __raw_writel(gpio_mask, reg);
 
@@ -963,14 +1007,14 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
                 inv = 1;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_IRQENABLE1;
                 mask = 0xffffffff;
                 break;
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP4_GPIO_IRQSTATUSSET0;
                 mask = 0xffffffff;
                 break;
@@ -1032,7 +1076,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                         l |= gpio_mask;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         case METHOD_GPIO_24XX:
                 if (enable)
                         reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -1042,7 +1086,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                 break;
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 if (enable)
                         reg += OMAP4_GPIO_IRQSTATUSSET0;
                 else
@@ -1072,7 +1116,7 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena
  */
 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 {
-        unsigned long flags;
+        unsigned long uninitialized_var(flags);
 
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP16XX
@@ -1086,9 +1130,9 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
                 spin_unlock_irqrestore(&bank->lock, flags);
                 return 0;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
         case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 if (bank->non_wakeup_gpios & (1 << gpio)) {
                         printk(KERN_ERR "Unable to modify wakeup on "
                                         "non-wakeup GPIO%d\n",
@@ -1182,9 +1226,9 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
                 __raw_writel(1 << offset, reg);
         }
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
-        if (bank->method == METHOD_GPIO_24XX) {
+#ifdef CONFIG_ARCH_OMAP2PLUS
+        if ((bank->method == METHOD_GPIO_24XX) ||
+                        (bank->method == METHOD_GPIO_44XX)) {
                 /* Disable wake-up during idle for dynamic tick */
                 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                 __raw_writel(1 << offset, reg);
@@ -1217,7 +1261,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
         void __iomem *isr_reg = NULL;
         u32 isr;
-        unsigned int gpio_irq;
+        unsigned int gpio_irq, gpio_index;
         struct gpio_bank *bank;
         u32 retrigger = 0;
         int unmasked = 0;
@@ -1241,12 +1285,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         if (bank->method == METHOD_GPIO_7XX)
                 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         if (bank->method == METHOD_GPIO_24XX)
                 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
-        if (bank->method == METHOD_GPIO_24XX)
+        if (bank->method == METHOD_GPIO_44XX)
                 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
 #endif
         while(1) {
@@ -1284,9 +1328,23 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
                 gpio_irq = bank->virtual_irq_start;
                 for (; isr != 0; isr >>= 1, gpio_irq++) {
+                        gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
+
                         if (!(isr & 1))
                                 continue;
 
+#ifdef CONFIG_ARCH_OMAP1
+                        /*
+                         * Some chips can't respond to both rising and falling
+                         * at the same time.  If this irq was requested with
+                         * both flags, we need to flip the ICR data for the IRQ
+                         * to respond to the IRQ for the opposite direction.
+                         * This will be indicated in the bank toggle_mask.
+                         */
+                        if (bank->toggle_mask & (1 << gpio_index))
+                                _toggle_gpio_edge_triggering(bank, gpio_index);
+#endif
+
                         generic_handle_irq(gpio_irq);
                 }
         }
@@ -1512,6 +1570,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
                 reg += OMAP7XX_GPIO_DIR_CONTROL;
                 break;
         case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
                 reg += OMAP24XX_GPIO_OE;
                 break;
         }
@@ -1571,7 +1630,7 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
 /*---------------------------------------------------------------------*/
 
 static int initialized;
-#if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
+#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
 static struct clk * gpio_ick;
 #endif
 
@@ -1697,7 +1756,7 @@ static int __init _omap_gpio_init(void)
                 bank_size = SZ_2K;
         }
 #endif
-#ifdef CONFIG_ARCH_OMAP24XX
+#ifdef CONFIG_ARCH_OMAP2
         if (cpu_is_omap242x()) {
                 gpio_bank_count = 4;
                 gpio_bank = gpio_bank_242x;
@@ -1707,7 +1766,7 @@ static int __init _omap_gpio_init(void)
                 gpio_bank = gpio_bank_243x;
         }
 #endif
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
         if (cpu_is_omap34xx()) {
                 gpio_bank_count = OMAP34XX_NR_GPIOS;
                 gpio_bank = gpio_bank_34xx;
@@ -1750,30 +1809,42 @@ static int __init _omap_gpio_init(void)
                         gpio_count = 32; /* 7xx has 32-bit GPIOs */
                 }
 
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
-                if (bank->method == METHOD_GPIO_24XX) {
+#ifdef CONFIG_ARCH_OMAP2PLUS
+                if ((bank->method == METHOD_GPIO_24XX) ||
+                                (bank->method == METHOD_GPIO_44XX)) {
                         static const u32 non_wakeup_gpios[] = {
                                 0xe203ffc0, 0x08700040
                         };
-                if (cpu_is_omap44xx()) {
-                        __raw_writel(0xffffffff, bank->base +
+
+                        if (cpu_is_omap44xx()) {
+                                __raw_writel(0xffffffff, bank->base +
                                                 OMAP4_GPIO_IRQSTATUSCLR0);
-                        __raw_writew(0x0015, bank->base +
+                                __raw_writew(0x0015, bank->base +
                                                 OMAP4_GPIO_SYSCONFIG);
-                        __raw_writel(0x00000000, bank->base +
+                                __raw_writel(0x00000000, bank->base +
                                                  OMAP4_GPIO_DEBOUNCENABLE);
-                        /* Initialize interface clock ungated, module enabled */
-                        __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
-                } else {
-                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
-                        __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
-                        __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
-                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
-
-                        /* Initialize interface clock ungated, module enabled */
-                        __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
-                }
+                                /*
+                                 * Initialize interface clock ungated,
+                                 * module enabled
+                                 */
+                                __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
+                        } else {
+                                __raw_writel(0x00000000, bank->base +
+                                                OMAP24XX_GPIO_IRQENABLE1);
+                                __raw_writel(0xffffffff, bank->base +
+                                                OMAP24XX_GPIO_IRQSTATUS1);
+                                __raw_writew(0x0015, bank->base +
+                                                OMAP24XX_GPIO_SYSCONFIG);
+                                __raw_writel(0x00000000, bank->base +
+                                                OMAP24XX_GPIO_DEBOUNCE_EN);
+
+                                /*
+                                 * Initialize interface clock ungated,
+                                 * module enabled
+                                 */
+                                __raw_writel(0, bank->base +
+                                                OMAP24XX_GPIO_CTRL);
+                        }
                         if (i < ARRAY_SIZE(non_wakeup_gpios))
                                 bank->non_wakeup_gpios = non_wakeup_gpios[i];
                         gpio_count = 32;
@@ -1844,8 +1915,7 @@ static int __init _omap_gpio_init(void)
         return 0;
 }
 
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
-                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
 {
         int i;
@@ -1868,7 +1938,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                         break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
                 case METHOD_GPIO_24XX:
                         wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
@@ -1876,7 +1946,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
                         break;
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-                case METHOD_GPIO_24XX:
+                case METHOD_GPIO_44XX:
                         wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
                         wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
                         wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
@@ -1916,14 +1986,14 @@ static int omap_gpio_resume(struct sys_device *dev)
                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                         break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
                 case METHOD_GPIO_24XX:
                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                         wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
                         break;
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-                case METHOD_GPIO_24XX:
+                case METHOD_GPIO_44XX:
                         wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
                         wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
                         break;
@@ -1954,8 +2024,7 @@ static struct sys_device omap_gpio_device = {
 
 #endif
 
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
 
 static int workaround_enabled;
 
@@ -1971,29 +2040,42 @@ void omap2_gpio_prepare_for_retention(void)
 
                 if (!(bank->enabled_non_wakeup_gpios))
                         continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-                l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                bank->saved_datain = __raw_readl(bank->base +
-                                                        OMAP4_GPIO_DATAIN);
-                l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
-                l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
-#endif
+
+                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                        bank->saved_datain = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_DATAIN);
+                        l1 = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_FALLINGDETECT);
+                        l2 = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_RISINGDETECT);
+                }
+
+                if (cpu_is_omap44xx()) {
+                        bank->saved_datain = __raw_readl(bank->base +
+                                                OMAP4_GPIO_DATAIN);
+                        l1 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_FALLINGDETECT);
+                        l2 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_RISINGDETECT);
+                }
+
                 bank->saved_fallingdetect = l1;
                 bank->saved_risingdetect = l2;
                 l1 &= ~bank->enabled_non_wakeup_gpios;
                 l2 &= ~bank->enabled_non_wakeup_gpios;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
-                __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
-#endif
+
+                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                        __raw_writel(l1, bank->base +
+                                        OMAP24XX_GPIO_FALLINGDETECT);
+                        __raw_writel(l2, bank->base +
+                                        OMAP24XX_GPIO_RISINGDETECT);
+                }
+
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
+                        __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
+                }
+
                 c++;
         }
         if (!c) {
@@ -2015,20 +2097,23 @@ void omap2_gpio_resume_after_retention(void)
 
                 if (!(bank->enabled_non_wakeup_gpios))
                         continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                __raw_writel(bank->saved_fallingdetect,
+
+                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                        __raw_writel(bank->saved_fallingdetect,
                                  bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                __raw_writel(bank->saved_risingdetect,
+                        __raw_writel(bank->saved_risingdetect,
                                  bank->base + OMAP24XX_GPIO_RISINGDETECT);
-                l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                __raw_writel(bank->saved_fallingdetect,
+                        l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
+                }
+
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(bank->saved_fallingdetect,
                                  bank->base + OMAP4_GPIO_FALLINGDETECT);
-                __raw_writel(bank->saved_risingdetect,
+                        __raw_writel(bank->saved_risingdetect,
                                  bank->base + OMAP4_GPIO_RISINGDETECT);
-                l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
-#endif
+                        l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
+                }
+
                 /* Check if any of the non-wakeup interrupt GPIOs have changed
                  * state.  If so, generate an IRQ by software.  This is
                  * horribly racy, but it's the best we can do to work around
@@ -2054,30 +2139,36 @@ void omap2_gpio_resume_after_retention(void)
 
                 if (gen) {
                         u32 old0, old1;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                        old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-                        old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+
+                        if (cpu_is_omap24xx() || cpu_is_omap44xx()) {
+                                old0 = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT0);
+                                old1 = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT1);
                         __raw_writel(old0 | gen, bank->base +
                                         OMAP24XX_GPIO_LEVELDETECT0);
                         __raw_writel(old1 | gen, bank->base +
                                         OMAP24XX_GPIO_LEVELDETECT1);
-                        __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-                        __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                        old0 = __raw_readl(bank->base +
+                        __raw_writel(old0, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT0);
+                        __raw_writel(old1, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT1);
+                        }
+
+                        if (cpu_is_omap44xx()) {
+                                old0 = __raw_readl(bank->base +
                                                 OMAP4_GPIO_LEVELDETECT0);
-                        old1 = __raw_readl(bank->base +
+                                old1 = __raw_readl(bank->base +
                                                 OMAP4_GPIO_LEVELDETECT1);
-                        __raw_writel(old0 | l, bank->base +
+                                __raw_writel(old0 | l, bank->base +
                                                 OMAP4_GPIO_LEVELDETECT0);
-                        __raw_writel(old1 | l, bank->base +
+                                __raw_writel(old1 | l, bank->base +
                                                 OMAP4_GPIO_LEVELDETECT1);
-                        __raw_writel(old0, bank->base +
+                                __raw_writel(old0, bank->base +
                                                 OMAP4_GPIO_LEVELDETECT0);
-                        __raw_writel(old1, bank->base +
+                                __raw_writel(old1, bank->base +
                                                 OMAP4_GPIO_LEVELDETECT1);
-#endif
+                        }
                 }
         }
 
@@ -2085,7 +2176,7 @@ void omap2_gpio_resume_after_retention(void)
 
 #endif
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
 /* save the registers of bank 2-6 */
 void omap_gpio_save_context(void)
 {
@@ -2181,8 +2272,7 @@ static int __init omap_gpio_sysinit(void)
 
         mpuio_init();
 
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
-                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
                 if (ret == 0) {
                         ret = sysdev_class_register(&omap_gpio_sysclass);
@@ -2241,8 +2331,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
 /* FIXME for at least omap2, show pullup/pulldown state */
 
                         irqstat = irq_desc[irq].status;
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) ||   \
-                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
                         if (is_in && ((bank->suspend_wakeup & mask)
                                         || irqstat & IRQ_TYPE_SENSE_MASK)) {
                                 char    *trigger = NULL;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 33fff4ef382d..624e26298faa 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -28,6 +28,7 @@
 #include <linux/i2c.h>
 #include <mach/irqs.h>
 #include <plat/mux.h>
+#include <plat/i2c.h>
 
 #define OMAP_I2C_SIZE           0x3f
 #define OMAP1_I2C_BASE          0xfffb3800
@@ -50,10 +51,10 @@ static const char name[] = "i2c_omap";
 
 static struct resource i2c_resources[][2] = {
         { I2C_RESOURCE_BUILDER(0, 0) },
-#if     defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if     defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) },
 #endif
-#if     defined(CONFIG_ARCH_OMAP34XX)
+#if     defined(CONFIG_ARCH_OMAP3)
         { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) },
 #endif
 };
@@ -72,10 +73,10 @@ static struct resource i2c_resources[][2] = {
 static u32 i2c_rate[ARRAY_SIZE(i2c_resources)];
 static struct platform_device omap_i2c_devices[] = {
         I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]),
-#if     defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if     defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]),
 #endif
-#if     defined(CONFIG_ARCH_OMAP34XX)
+#if     defined(CONFIG_ARCH_OMAP3)
         I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]),
 #endif
 };
@@ -117,6 +118,11 @@ static int __init omap_i2c_add_bus(int bus_id)
                 res[1].start = irq;
         }
 
+        if (cpu_class_is_omap1())
+                omap1_i2c_mux_pins(bus_id);
+        if (cpu_class_is_omap2())
+                omap2_i2c_mux_pins(bus_id);
+
         return platform_device_register(pdev);
 }
 
@@ -169,7 +175,7 @@ out:
 subsys_initcall(omap_register_i2c_bus_cmdline);
 
 /**
- * omap_plat_register_i2c_bus - register I2C bus with device descriptors
+ * omap_register_i2c_bus - register I2C bus with device descriptors
  * @bus_id: bus id counting from number 1
  * @clkrate: clock rate of the bus in kHz
  * @info: pointer into I2C device descriptor table or NULL
@@ -177,7 +183,7 @@ subsys_initcall(omap_register_i2c_bus_cmdline);
  *
  * Returns 0 on success or an error code.
  */
-int __init omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
+int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
                           struct i2c_board_info const *info,
                           unsigned len)
 {
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 376ce18216ff..5cd622039da0 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -99,7 +99,6 @@ struct fb_info;
 struct omap_backlight_config {
         int default_intensity;
         int (*set_power)(struct device *dev, int state);
-        int (*check_fb)(struct fb_info *fb);
 };
 
 struct omap_fbmem_config {
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 35b36caf5f91..bb937f3fabed 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -25,17 +25,25 @@ struct omap_clk {
                 },                      \
         }
 
-
+/* Platform flags for the clkdev-OMAP integration code */
 #define CK_310          (1 << 0)
-#define CK_7XX          (1 << 1)
+#define CK_7XX          (1 << 1)        /* 7xx, 850 */
 #define CK_1510         (1 << 2)
-#define CK_16XX         (1 << 3)
-#define CK_243X         (1 << 4)
-#define CK_242X         (1 << 5)
-#define CK_343X         (1 << 6)
-#define CK_3430ES1      (1 << 7)
-#define CK_3430ES2      (1 << 8)
-#define CK_443X         (1 << 9)
+#define CK_16XX         (1 << 3)        /* 16xx, 17xx, 5912 */
+#define CK_242X         (1 << 4)
+#define CK_243X         (1 << 5)
+#define CK_3XXX         (1 << 6)        /* OMAP3 + AM3 common clocks*/
+#define CK_343X         (1 << 7)        /* OMAP34xx common clocks */
+#define CK_3430ES1      (1 << 8)        /* 34xxES1 only */
+#define CK_3430ES2      (1 << 9)        /* 34xxES2, ES3, non-Sitara 35xx only */
+#define CK_3505         (1 << 10)
+#define CK_3517         (1 << 11)
+#define CK_36XX         (1 << 12)       /* OMAP36xx/37xx-specific clocks */
+#define CK_443X         (1 << 13)
+
+#define CK_AM35XX       (CK_3505 | CK_3517)     /* all Sitara AM35xx */
+
+
 
 #endif
 
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 309b6d1dccdb..34f7fa9ad4c0 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -1,9 +1,9 @@
 /*
- *  arch/arm/plat-omap/include/mach/clock.h
+ * OMAP clock: data structure definitions, function prototypes, shared macros
  *
- *  Copyright (C) 2004 - 2005 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -22,12 +22,13 @@ struct clockdomain;
 struct clkops {
         int                     (*enable)(struct clk *);
         void                    (*disable)(struct clk *);
-        void                    (*find_idlest)(struct clk *, void __iomem **, u8 *);
-        void                    (*find_companion)(struct clk *, void __iomem **, u8 *);
+        void                    (*find_idlest)(struct clk *, void __iomem **,
+                                               u8 *, u8 *);
+        void                    (*find_companion)(struct clk *, void __iomem **,
+                                                  u8 *);
 };
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
 
 struct clksel_rate {
         u32                     val;
@@ -40,6 +41,50 @@ struct clksel {
         const struct clksel_rate *rates;
 };
 
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @rate_tolerance: maximum variance allowed from target rate (in Hz)
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ * NO_DCO_SEL: don't program DCO (only for some J-type DPLLs)
+
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX @rate_tolerance should probably be deprecated - currently there
+ * don't seem to be any usecases for DPLL rounding that is not exact.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a differenct structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
 struct dpll_data {
         void __iomem            *mult_div1_reg;
         u32                     mult_mask;
@@ -51,13 +96,12 @@ struct dpll_data {
         unsigned int            rate_tolerance;
         unsigned long           last_rounded_rate;
         u16                     last_rounded_m;
+        u16                     max_multiplier;
         u8                      last_rounded_n;
         u8                      min_divider;
         u8                      max_divider;
-        u32                     max_tolerance;
-        u16                     max_multiplier;
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
         u8                      modes;
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
         void __iomem            *autoidle_reg;
         void __iomem            *idlest_reg;
         u32                     autoidle_mask;
@@ -66,6 +110,7 @@ struct dpll_data {
         u8                      auto_recal_bit;
         u8                      recal_en_bit;
         u8                      recal_st_bit;
+        u8                      flags;
 #  endif
 };
 
@@ -75,12 +120,10 @@ struct clk {
         struct list_head        node;
         const struct clkops     *ops;
         const char              *name;
-        int                     id;
         struct clk              *parent;
         struct list_head        children;
         struct list_head        sibling;        /* node for children */
         unsigned long           rate;
-        __u32                   flags;
         void __iomem            *enable_reg;
         unsigned long           (*recalc)(struct clk *);
         int                     (*set_rate)(struct clk *, unsigned long);
@@ -88,9 +131,9 @@ struct clk {
         void                    (*init)(struct clk *);
         __u8                    enable_bit;
         __s8                    usecount;
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                defined(CONFIG_ARCH_OMAP4)
         u8                      fixed_div;
+        u8                      flags;
+#ifdef CONFIG_ARCH_OMAP2PLUS
         void __iomem            *clksel_reg;
         u32                     clksel_mask;
         const struct clksel     *clksel;
@@ -119,10 +162,11 @@ struct clk_functions {
         void            (*clk_disable_unused)(struct clk *clk);
 #ifdef CONFIG_CPU_FREQ
         void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
+        void            (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
 #endif
 };
 
-extern unsigned int mpurate;
+extern int mpurate;
 
 extern int clk_init(struct clk_functions *custom_clocks);
 extern void clk_preinit(struct clk *clk);
@@ -133,26 +177,23 @@ extern void propagate_rate(struct clk *clk);
 extern void recalculate_root_clocks(void);
 extern unsigned long followparent_recalc(struct clk *clk);
 extern void clk_enable_init_clocks(void);
+unsigned long omap_fixed_divisor_recalc(struct clk *clk);
 #ifdef CONFIG_CPU_FREQ
 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
+extern struct clk *omap_clk_get_by_name(const char *name);
 
 extern const struct clkops clkops_null;
 
+extern struct clk dummy_ck;
+
 /* Clock flags */
-/* bit 0 is free */
-#define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
-/* bits 2-4 are free */
-#define ENABLE_REG_32BIT        (1 << 5)        /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL      (1 << 7)
-#define CLOCK_NO_IDLE_PARENT    (1 << 8)
-#define DELAYED_APP             (1 << 9)        /* Delay application of clock */
-#define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
-#define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
-#define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
-#define CLOCK_IN_OMAP4430       (1 << 13)
-#define ALWAYS_ENABLED          (1 << 14)
-/* bits 13-31 are currently free */
+#define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL      (1 << 1)
+#define CLOCK_NO_IDLE_PARENT    (1 << 2)
+#define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
+#define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
 
 /* Clksel_rate flags */
 #define DEFAULT_RATE            (1 << 0)
@@ -160,7 +201,8 @@ extern const struct clkops clkops_null;
 #define RATE_IN_243X            (1 << 2)
 #define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
 #define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
-#define RATE_IN_4430            (1 << 5)
+#define RATE_IN_36XX            (1 << 5)
+#define RATE_IN_4430            (1 << 6)
 
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 
diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h
index eb734826e64e..ba0a6c07c0fe 100644
--- a/arch/arm/plat-omap/include/plat/clockdomain.h
+++ b/arch/arm/plat-omap/include/plat/clockdomain.h
@@ -4,7 +4,7 @@
  * OMAP2/3 clockdomain framework functions
  *
  * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -40,65 +40,95 @@
 #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP         0x2
 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO          0x3
 
-/*
- * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
- * and sleepdeps added when a powerdomain should stay active in hwsup mode;
- * and conversely, removed when the powerdomain should be allowed to go
- * inactive in hwsup mode.
+/**
+ * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
+ * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
+ * @omap_chip: OMAP chip types that this autodep is valid on
+ *
+ * A clockdomain that should have wkdeps and sleepdeps added when a
+ * clockdomain should stay active in hwsup mode; and conversely,
+ * removed when the clockdomain should be allowed to go inactive in
+ * hwsup mode.
+ *
+ * Autodeps are deprecated and should be removed after
+ * omap_hwmod-based fine-grained module idle control is added.
  */
-struct clkdm_pwrdm_autodep {
-
+struct clkdm_autodep {
         union {
-                /* Name of the powerdomain to add a wkdep/sleepdep on */
                 const char *name;
-
-                /* Powerdomain pointer (looked up at clkdm_init() time) */
-                struct powerdomain *ptr;
-        } pwrdm;
-
-        /* OMAP chip types that this clockdomain dep is valid on */
+                struct clockdomain *ptr;
+        } clkdm;
         const struct omap_chip_id omap_chip;
+};
 
+/**
+ * struct clkdm_dep - encode dependencies between clockdomains
+ * @clkdm_name: clockdomain name
+ * @clkdm: pointer to the struct clockdomain of @clkdm_name
+ * @omap_chip: OMAP chip types that this dependency is valid on
+ * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
+ * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
+ *
+ * Statically defined.  @clkdm is resolved from @clkdm_name at runtime and
+ * should not be pre-initialized.
+ *
+ * XXX Should also include hardware (fixed) dependencies.
+ */
+struct clkdm_dep {
+        const char *clkdm_name;
+        struct clockdomain *clkdm;
+        atomic_t wkdep_usecount;
+        atomic_t sleepdep_usecount;
+        const struct omap_chip_id omap_chip;
 };
 
+/**
+ * struct clockdomain - OMAP clockdomain
+ * @name: clockdomain name
+ * @pwrdm: powerdomain containing this clockdomain
+ * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
+ * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
+ * @flags: Clockdomain capability flags
+ * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
+ * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
+ * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
+ * @omap_chip: OMAP chip types that this clockdomain is valid on
+ * @usecount: Usecount tracking
+ * @node: list_head to link all clockdomains together
+ */
 struct clockdomain {
-
-        /* Clockdomain name */
         const char *name;
-
         union {
-                /* Powerdomain enclosing this clockdomain */
                 const char *name;
-
-                /* Powerdomain pointer assigned at clkdm_register() */
                 struct powerdomain *ptr;
         } pwrdm;
-
-        /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
+        void __iomem *clkstctrl_reg;
         const u16 clktrctrl_mask;
-
-        /* Clockdomain capability flags */
         const u8 flags;
-
-        /* OMAP chip types that this clockdomain is valid on */
+        const u8 dep_bit;
+        struct clkdm_dep *wkdep_srcs;
+        struct clkdm_dep *sleepdep_srcs;
         const struct omap_chip_id omap_chip;
-
-        /* Usecount tracking */
         atomic_t usecount;
-
         struct list_head node;
-
 };
 
-void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
-int clkdm_register(struct clockdomain *clkdm);
-int clkdm_unregister(struct clockdomain *clkdm);
+void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps);
 struct clockdomain *clkdm_lookup(const char *name);
 
 int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
                         void *user);
 struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
 
+int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
+int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
+
 void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
 void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
 
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 32c22272425d..7556e271942e 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -37,21 +37,30 @@ extern void __iomem *gic_cpu_base_addr;
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
 
-/* IO bases for various OMAP processors */
+/*
+ * IO bases for various OMAP processors
+ * Except the tap base, rest all the io bases
+ * listed are physical addresses.
+ */
 struct omap_globals {
         u32             class;          /* OMAP class to detect */
         void __iomem    *tap;           /* Control module ID code */
-        void __iomem    *sdrc;          /* SDRAM Controller */
-        void __iomem    *sms;           /* SDRAM Memory Scheduler */
-        void __iomem    *ctrl;          /* System Control Module */
-        void __iomem    *prm;           /* Power and Reset Management */
-        void __iomem    *cm;            /* Clock Management */
-        void __iomem    *cm2;
+        unsigned long   sdrc;           /* SDRAM Controller */
+        unsigned long   sms;            /* SDRAM Memory Scheduler */
+        unsigned long   ctrl;           /* System Control Module */
+        unsigned long   prm;            /* Power and Reset Management */
+        unsigned long   cm;             /* Clock Management */
+        unsigned long   cm2;
+        unsigned long   uart1_phys;
+        unsigned long   uart2_phys;
+        unsigned long   uart3_phys;
+        unsigned long   uart4_phys;
 };
 
 void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_343x(void);
+void omap2_set_globals_36xx(void);
 void omap2_set_globals_443x(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
@@ -59,6 +68,7 @@ void omap2_set_globals_tap(struct omap_globals *);
 void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
+void omap2_set_globals_uart(struct omap_globals *);
 
 /**
  * omap_test_timeout - busy-loop, testing a condition
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 2ae884378638..a56deee97676 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -147,7 +147,7 @@
 #define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
 #define OMAP343X_CONTROL_DEBOBS(i)      (OMAP2_CONTROL_GENERAL + 0x01B0 \
-                                        + ((i) >> 1) * 4 + (!(i) & 1) * 2)
+                                        + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
 #define OMAP343X_CONTROL_PROG_IO0       (OMAP2_CONTROL_GENERAL + 0x01D4)
 #define OMAP343X_CONTROL_PROG_IO1       (OMAP2_CONTROL_GENERAL + 0x01D8)
 #define OMAP343X_CONTROL_DSS_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E0)
@@ -160,6 +160,14 @@
 #define OMAP343X_CONTROL_SRAMLDO5       (OMAP2_CONTROL_GENERAL + 0x02C0)
 #define OMAP343X_CONTROL_CSI            (OMAP2_CONTROL_GENERAL + 0x02C4)
 
+/* AM35XX only CONTROL_GENERAL register offsets */
+#define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
+#define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
+#define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
+#define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
+#define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
+#define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
+#define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
 
 /* 34xx PADCONF register offsets */
 #define OMAP343X_PADCONF_ETK(i)         (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
@@ -196,6 +204,9 @@
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 
+/* 44xx control status register offset */
+#define OMAP44XX_CONTROL_STATUS         0x2c4
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
@@ -257,6 +268,32 @@
 #define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
 #define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
 
+/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
+#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
+#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
+#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
+#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
+#define AM35XX_USBOTG_FCLK_SHIFT        8
+#define AM35XX_CPGMAC_FCLK_SHIFT        9
+#define AM35XX_VPFE_FCLK_SHIFT          10
+
+/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
+#define AM35XX_CPGMAC_C0_RX_PULSE_CLR   BIT(1)
+#define AM35XX_CPGMAC_C0_RX_THRESH_CLR  BIT(2)
+#define AM35XX_CPGMAC_C0_TX_PULSE_CLR   BIT(3)
+#define AM35XX_USBOTGSS_INT_CLR         BIT(4)
+#define AM35XX_VPFE_CCDC_VD0_INT_CLR    BIT(5)
+#define AM35XX_VPFE_CCDC_VD1_INT_CLR    BIT(6)
+#define AM35XX_VPFE_CCDC_VD2_INT_CLR    BIT(7)
+
+/*AM35XX CONTROL_IP_SW_RESET bits*/
+#define AM35XX_USBOTGSS_SW_RST          BIT(0)
+#define AM35XX_CPGMACSS_SW_RST          BIT(1)
+#define AM35XX_VPFE_VBUSP_SW_RST        BIT(2)
+#define AM35XX_HECC_SW_RST              BIT(3)
+#define AM35XX_VPFE_PCLK_SW_RST         BIT(4)
+
 /*
  * CONTROL OMAP STATUS register to identify OMAP3 features
  */
@@ -292,8 +329,7 @@
 
 
 #ifndef __ASSEMBLY__
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
 extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 9a028bdebb06..ed8786c41df2 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -31,6 +31,7 @@
 #define __ASM_ARCH_OMAP_CPU_H
 
 #include <linux/bitops.h>
+#include <plat/multi.h>
 
 /*
  * Omap device type i.e. EMU/HS/TST/GP/BAD
@@ -44,7 +45,7 @@
 int omap_type(void);
 
 struct omap_chip_id {
-        u8 oc;
+        u16 oc;
         u8 type;
 };
 
@@ -76,75 +77,6 @@ unsigned int omap_rev(void);
 #define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
 
 /*
- * Test if multicore OMAP support is needed
- */
-#undef MULTI_OMAP1
-#undef MULTI_OMAP2
-#undef OMAP_NAME
-
-#ifdef CONFIG_ARCH_OMAP730
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap730
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap850
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap1510
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap16xx
-# endif
-#endif
-#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
-# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
-#  error "OMAP1 and OMAP2 can't be selected at the same time"
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP2420
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap2420
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP2430
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap2430
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP3430
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap3430
-# endif
-#endif
-
-/*
  * Macros to group OMAP into cpu classes.
  * These can be used in most places.
  * cpu_is_omap7xx():    True for OMAP730, OMAP850
@@ -154,6 +86,7 @@ unsigned int omap_rev(void);
  * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
  * cpu_is_omap243x():   True for OMAP2430
  * cpu_is_omap343x():   True for OMAP3430
+ * cpu_is_omap443x():   True for OMAP4430
  */
 #define GET_OMAP_CLASS  (omap_rev() & 0xff)
 
@@ -232,7 +165,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #endif
 
 #if defined(MULTI_OMAP2)
-# if defined(CONFIG_ARCH_OMAP24XX)
+# if defined(CONFIG_ARCH_OMAP2)
 #  undef  cpu_is_omap24xx
 #  undef  cpu_is_omap242x
 #  undef  cpu_is_omap243x
@@ -240,14 +173,14 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  define cpu_is_omap242x()             is_omap242x()
 #  define cpu_is_omap243x()             is_omap243x()
 # endif
-# if defined(CONFIG_ARCH_OMAP34XX)
+# if defined(CONFIG_ARCH_OMAP3)
 #  undef  cpu_is_omap34xx
 #  undef  cpu_is_omap343x
 #  define cpu_is_omap34xx()             is_omap34xx()
 #  define cpu_is_omap343x()             is_omap343x()
 # endif
 #else
-# if defined(CONFIG_ARCH_OMAP24XX)
+# if defined(CONFIG_ARCH_OMAP2)
 #  undef  cpu_is_omap24xx
 #  define cpu_is_omap24xx()             1
 # endif
@@ -259,7 +192,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  undef  cpu_is_omap243x
 #  define cpu_is_omap243x()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP34XX)
+# if defined(CONFIG_ARCH_OMAP3)
 #  undef  cpu_is_omap34xx
 #  define cpu_is_omap34xx()             1
 # endif
@@ -286,6 +219,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
  * cpu_is_omap2423():   True for OMAP2423
  * cpu_is_omap2430():   True for OMAP2430
  * cpu_is_omap3430():   True for OMAP3430
+ * cpu_is_omap4430():   True for OMAP4430
  * cpu_is_omap3505():   True for OMAP3505
  * cpu_is_omap3517():   True for OMAP3517
  */
@@ -334,6 +268,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define cpu_is_omap3505()               0
 #define cpu_is_omap3517()               0
 #define cpu_is_omap3430()               0
+#define cpu_is_omap4430()               0
 #define cpu_is_omap3630()               0
 
 /*
@@ -371,7 +306,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 # define cpu_is_omap1710()              is_omap1710()
 #endif
 
-#if defined(CONFIG_ARCH_OMAP24XX)
+#if defined(CONFIG_ARCH_OMAP2)
 # undef  cpu_is_omap2420
 # undef  cpu_is_omap2422
 # undef  cpu_is_omap2423
@@ -382,7 +317,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 # define cpu_is_omap2430()              is_omap2430()
 #endif
 
-#if defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP3)
 # undef cpu_is_omap3430
 # undef cpu_is_omap3503
 # undef cpu_is_omap3515
@@ -434,6 +369,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP3430_REV_ES2_1      0x34302034
 #define OMAP3430_REV_ES3_0      0x34303034
 #define OMAP3430_REV_ES3_1      0x34304034
+#define OMAP3430_REV_ES3_1_2    0x34305034
 
 #define OMAP3630_REV_ES1_0      0x36300034
 
@@ -470,9 +406,12 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define CHIP_IS_OMAP3430ES3_0           (1 << 5)
 #define CHIP_IS_OMAP3430ES3_1           (1 << 6)
 #define CHIP_IS_OMAP3630ES1             (1 << 7)
+#define CHIP_IS_OMAP4430ES1             (1 << 8)
 
 #define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
+#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1)
+
 /*
  * "GE" here represents "greater than or equal to" in terms of ES
  * levels.  So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
@@ -500,6 +439,7 @@ extern u32 omap3_features;
 #define OMAP3_HAS_SGX                   BIT(2)
 #define OMAP3_HAS_NEON                  BIT(3)
 #define OMAP3_HAS_ISP                   BIT(4)
+#define OMAP3_HAS_192MHZ_CLK            BIT(5)
 
 #define OMAP3_HAS_FEATURE(feat,flag)                    \
 static inline unsigned int omap3_has_ ##feat(void)      \
@@ -512,5 +452,6 @@ OMAP3_HAS_FEATURE(sgx, SGX)
 OMAP3_HAS_FEATURE(iva, IVA)
 OMAP3_HAS_FEATURE(neon, NEON)
 OMAP3_HAS_FEATURE(isp, ISP)
+OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/dma-44xx.h b/arch/arm/plat-omap/include/plat/dma-44xx.h
new file mode 100644
index 000000000000..1f767cb2f38a
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/dma-44xx.h
@@ -0,0 +1,147 @@
+/*
+ * OMAP4 SDMA channel definitions
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
+
+#define OMAP44XX_DMA_SYS_REQ0                   2
+#define OMAP44XX_DMA_SYS_REQ1                   3
+#define OMAP44XX_DMA_GPMC                       4
+#define OMAP44XX_DMA_DSS_DISPC_REQ              6
+#define OMAP44XX_DMA_SYS_REQ2                   7
+#define OMAP44XX_DMA_MCASP1_AXEVT               8
+#define OMAP44XX_DMA_ISS_REQ1                   9
+#define OMAP44XX_DMA_ISS_REQ2                   10
+#define OMAP44XX_DMA_MCASP1_AREVT               11
+#define OMAP44XX_DMA_ISS_REQ3                   12
+#define OMAP44XX_DMA_ISS_REQ4                   13
+#define OMAP44XX_DMA_DSS_RFBI_REQ               14
+#define OMAP44XX_DMA_SPI3_TX0                   15
+#define OMAP44XX_DMA_SPI3_RX0                   16
+#define OMAP44XX_DMA_MCBSP2_TX                  17
+#define OMAP44XX_DMA_MCBSP2_RX                  18
+#define OMAP44XX_DMA_MCBSP3_TX                  19
+#define OMAP44XX_DMA_MCBSP3_RX                  20
+#define OMAP44XX_DMA_C2C_SSCM_GPO0              21
+#define OMAP44XX_DMA_C2C_SSCM_GPO1              22
+#define OMAP44XX_DMA_SPI3_TX1                   23
+#define OMAP44XX_DMA_SPI3_RX1                   24
+#define OMAP44XX_DMA_I2C3_TX                    25
+#define OMAP44XX_DMA_I2C3_RX                    26
+#define OMAP44XX_DMA_I2C1_TX                    27
+#define OMAP44XX_DMA_I2C1_RX                    28
+#define OMAP44XX_DMA_I2C2_TX                    29
+#define OMAP44XX_DMA_I2C2_RX                    30
+#define OMAP44XX_DMA_MCBSP4_TX                  31
+#define OMAP44XX_DMA_MCBSP4_RX                  32
+#define OMAP44XX_DMA_MCBSP1_TX                  33
+#define OMAP44XX_DMA_MCBSP1_RX                  34
+#define OMAP44XX_DMA_SPI1_TX0                   35
+#define OMAP44XX_DMA_SPI1_RX0                   36
+#define OMAP44XX_DMA_SPI1_TX1                   37
+#define OMAP44XX_DMA_SPI1_RX1                   38
+#define OMAP44XX_DMA_SPI1_TX2                   39
+#define OMAP44XX_DMA_SPI1_RX2                   40
+#define OMAP44XX_DMA_SPI1_TX3                   41
+#define OMAP44XX_DMA_SPI1_RX3                   42
+#define OMAP44XX_DMA_SPI2_TX0                   43
+#define OMAP44XX_DMA_SPI2_RX0                   44
+#define OMAP44XX_DMA_SPI2_TX1                   45
+#define OMAP44XX_DMA_SPI2_RX1                   46
+#define OMAP44XX_DMA_MMC2_TX                    47
+#define OMAP44XX_DMA_MMC2_RX                    48
+#define OMAP44XX_DMA_UART1_TX                   49
+#define OMAP44XX_DMA_UART1_RX                   50
+#define OMAP44XX_DMA_UART2_TX                   51
+#define OMAP44XX_DMA_UART2_RX                   52
+#define OMAP44XX_DMA_UART3_TX                   53
+#define OMAP44XX_DMA_UART3_RX                   54
+#define OMAP44XX_DMA_UART4_TX                   55
+#define OMAP44XX_DMA_UART4_RX                   56
+#define OMAP44XX_DMA_MMC4_TX                    57
+#define OMAP44XX_DMA_MMC4_RX                    58
+#define OMAP44XX_DMA_MMC5_TX                    59
+#define OMAP44XX_DMA_MMC5_RX                    60
+#define OMAP44XX_DMA_MMC1_TX                    61
+#define OMAP44XX_DMA_MMC1_RX                    62
+#define OMAP44XX_DMA_SYS_REQ3                   64
+#define OMAP44XX_DMA_MCPDM_UP                   65
+#define OMAP44XX_DMA_MCPDM_DL                   66
+#define OMAP44XX_DMA_DMIC_REQ                   67
+#define OMAP44XX_DMA_C2C_SSCM_GPO2              68
+#define OMAP44XX_DMA_C2C_SSCM_GPO3              69
+#define OMAP44XX_DMA_SPI4_TX0                   70
+#define OMAP44XX_DMA_SPI4_RX0                   71
+#define OMAP44XX_DMA_DSS_DSI1_REQ0              72
+#define OMAP44XX_DMA_DSS_DSI1_REQ1              73
+#define OMAP44XX_DMA_DSS_DSI1_REQ2              74
+#define OMAP44XX_DMA_DSS_DSI1_REQ3              75
+#define OMAP44XX_DMA_DSS_HDMI_REQ               76
+#define OMAP44XX_DMA_MMC3_TX                    77
+#define OMAP44XX_DMA_MMC3_RX                    78
+#define OMAP44XX_DMA_USIM_TX                    79
+#define OMAP44XX_DMA_USIM_RX                    80
+#define OMAP44XX_DMA_DSS_DSI2_REQ0              81
+#define OMAP44XX_DMA_DSS_DSI2_REQ1              82
+#define OMAP44XX_DMA_DSS_DSI2_REQ2              83
+#define OMAP44XX_DMA_DSS_DSI2_REQ3              84
+#define OMAP44XX_DMA_SLIMBUS1_TX0               85
+#define OMAP44XX_DMA_SLIMBUS1_TX1               86
+#define OMAP44XX_DMA_SLIMBUS1_TX2               87
+#define OMAP44XX_DMA_SLIMBUS1_TX3               88
+#define OMAP44XX_DMA_SLIMBUS1_RX0               89
+#define OMAP44XX_DMA_SLIMBUS1_RX1               90
+#define OMAP44XX_DMA_SLIMBUS1_RX2               91
+#define OMAP44XX_DMA_SLIMBUS1_RX3               92
+#define OMAP44XX_DMA_SLIMBUS2_TX0               93
+#define OMAP44XX_DMA_SLIMBUS2_TX1               94
+#define OMAP44XX_DMA_SLIMBUS2_TX2               95
+#define OMAP44XX_DMA_SLIMBUS2_TX3               96
+#define OMAP44XX_DMA_SLIMBUS2_RX0               97
+#define OMAP44XX_DMA_SLIMBUS2_RX1               98
+#define OMAP44XX_DMA_SLIMBUS2_RX2               99
+#define OMAP44XX_DMA_SLIMBUS2_RX3               100
+#define OMAP44XX_DMA_ABE_REQ_0                  101
+#define OMAP44XX_DMA_ABE_REQ_1                  102
+#define OMAP44XX_DMA_ABE_REQ_2                  103
+#define OMAP44XX_DMA_ABE_REQ_3                  104
+#define OMAP44XX_DMA_ABE_REQ_4                  105
+#define OMAP44XX_DMA_ABE_REQ_5                  106
+#define OMAP44XX_DMA_ABE_REQ_6                  107
+#define OMAP44XX_DMA_ABE_REQ_7                  108
+#define OMAP44XX_DMA_AES1_P_CTX_IN_REQ          109
+#define OMAP44XX_DMA_AES1_P_DATA_IN_REQ         110
+#define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ        111
+#define OMAP44XX_DMA_AES2_P_CTX_IN_REQ          112
+#define OMAP44XX_DMA_AES2_P_DATA_IN_REQ         113
+#define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ        114
+#define OMAP44XX_DMA_DES_P_CTX_IN_REQ           115
+#define OMAP44XX_DMA_DES_P_DATA_IN_REQ          116
+#define OMAP44XX_DMA_DES_P_DATA_OUT_REQ         117
+#define OMAP44XX_DMA_SHA2_CTXIN_P               118
+#define OMAP44XX_DMA_SHA2_DIN_P                 119
+#define OMAP44XX_DMA_SHA2_CTXOUT_P              120
+#define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ     121
+#define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ     122
+#define OMAP44XX_DMA_I2C4_TX                    124
+#define OMAP44XX_DMA_I2C4_RX                    125
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 4ede9e17a0be..02232ca2c37f 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -21,6 +21,9 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
 
+/* Move omap4 specific defines to dma-44xx.h */
+#include "dma-44xx.h"
+
 /* Hardware registers for omap1 */
 #define OMAP1_DMA_BASE                  (0xfffed800)
 
@@ -316,89 +319,6 @@
 #define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
 #define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 
-/* DMA request lines for 44xx */
-#define OMAP44XX_DMA_DSS_DISPC_REQ      6       /* S_DMA_5 */
-#define OMAP44XX_DMA_SYS_REQ2           7       /* S_DMA_6 */
-#define OMAP44XX_DMA_ISS_REQ1           9       /* S_DMA_8 */
-#define OMAP44XX_DMA_ISS_REQ2           10      /* S_DMA_9 */
-#define OMAP44XX_DMA_ISS_REQ3           12      /* S_DMA_11 */
-#define OMAP44XX_DMA_ISS_REQ4           13      /* S_DMA_12 */
-#define OMAP44XX_DMA_DSS_RFBI_REQ       14      /* S_DMA_13 */
-#define OMAP44XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
-#define OMAP44XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
-#define OMAP44XX_DMA_MCBSP2_TX          17      /* S_DMA_16 */
-#define OMAP44XX_DMA_MCBSP2_RX          18      /* S_DMA_17 */
-#define OMAP44XX_DMA_MCBSP3_TX          19      /* S_DMA_18 */
-#define OMAP44XX_DMA_MCBSP3_RX          20      /* S_DMA_19 */
-#define OMAP44XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
-#define OMAP44XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
-#define OMAP44XX_DMA_I2C3_TX            25      /* S_DMA_24 */
-#define OMAP44XX_DMA_I2C3_RX            26      /* S_DMA_25 */
-#define OMAP44XX_DMA_I2C1_TX            27      /* S_DMA_26 */
-#define OMAP44XX_DMA_I2C1_RX            28      /* S_DMA_27 */
-#define OMAP44XX_DMA_I2C2_TX            29      /* S_DMA_28 */
-#define OMAP44XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP44XX_DMA_MCBSP4_TX          31      /* S_DMA_30 */
-#define OMAP44XX_DMA_MCBSP4_RX          32      /* S_DMA_31 */
-#define OMAP44XX_DMA_MCBSP1_TX          33      /* S_DMA_32 */
-#define OMAP44XX_DMA_MCBSP1_RX          34      /* S_DMA_33 */
-#define OMAP44XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
-#define OMAP44XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
-#define OMAP44XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
-#define OMAP44XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
-#define OMAP44XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
-#define OMAP44XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
-#define OMAP44XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
-#define OMAP44XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
-#define OMAP44XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
-#define OMAP44XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
-#define OMAP44XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
-#define OMAP44XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
-#define OMAP44XX_DMA_MMC2_TX            47      /* S_DMA_46 */
-#define OMAP44XX_DMA_MMC2_RX            48      /* S_DMA_47 */
-#define OMAP44XX_DMA_UART1_TX           49      /* S_DMA_48 */
-#define OMAP44XX_DMA_UART1_RX           50      /* S_DMA_49 */
-#define OMAP44XX_DMA_UART2_TX           51      /* S_DMA_50 */
-#define OMAP44XX_DMA_UART2_RX           52      /* S_DMA_51 */
-#define OMAP44XX_DMA_UART3_TX           53      /* S_DMA_52 */
-#define OMAP44XX_DMA_UART3_RX           54      /* S_DMA_53 */
-#define OMAP44XX_DMA_UART4_TX           55      /* S_DMA_54 */
-#define OMAP44XX_DMA_UART4_RX           56      /* S_DMA_55 */
-#define OMAP44XX_DMA_MMC4_TX            57      /* S_DMA_56 */
-#define OMAP44XX_DMA_MMC4_RX            58      /* S_DMA_57 */
-#define OMAP44XX_DMA_MMC5_TX            59      /* S_DMA_58 */
-#define OMAP44XX_DMA_MMC5_RX            60      /* S_DMA_59 */
-#define OMAP44XX_DMA_MMC1_TX            61      /* S_DMA_60 */
-#define OMAP44XX_DMA_MMC1_RX            62      /* S_DMA_61 */
-#define OMAP44XX_DMA_SYS_REQ3           64      /* S_DMA_63 */
-#define OMAP44XX_DMA_MCPDM_UP           65      /* S_DMA_64 */
-#define OMAP44XX_DMA_MCPDM_DL           66      /* S_DMA_65 */
-#define OMAP44XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
-#define OMAP44XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ0      72      /* S_DMA_71 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ1      73      /* S_DMA_72 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ2      74      /* S_DMA_73 */
-#define OMAP44XX_DMA_DSS_DSI1_REQ3      75      /* S_DMA_74 */
-#define OMAP44XX_DMA_DSS_HDMI_REQ       76      /* S_DMA_75 */
-#define OMAP44XX_DMA_MMC3_TX            77      /* S_DMA_76 */
-#define OMAP44XX_DMA_MMC3_RX            78      /* S_DMA_77 */
-#define OMAP44XX_DMA_USIM_TX            79      /* S_DMA_78 */
-#define OMAP44XX_DMA_USIM_RX            80      /* S_DMA_79 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ0      81      /* S_DMA_80 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ1      82      /* S_DMA_81 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ2      83      /* S_DMA_82 */
-#define OMAP44XX_DMA_DSS_DSI2_REQ3      84      /* S_DMA_83 */
-#define OMAP44XX_DMA_ABE_REQ0           101     /* S_DMA_100 */
-#define OMAP44XX_DMA_ABE_REQ1           102     /* S_DMA_101 */
-#define OMAP44XX_DMA_ABE_REQ2           103     /* S_DMA_102 */
-#define OMAP44XX_DMA_ABE_REQ3           104     /* S_DMA_103 */
-#define OMAP44XX_DMA_ABE_REQ4           105     /* S_DMA_104 */
-#define OMAP44XX_DMA_ABE_REQ5           106     /* S_DMA_105 */
-#define OMAP44XX_DMA_ABE_REQ6           107     /* S_DMA_106 */
-#define OMAP44XX_DMA_ABE_REQ7           108     /* S_DMA_107 */
-#define OMAP44XX_DMA_I2C4_TX            124     /* S_DMA_123 */
-#define OMAP44XX_DMA_I2C4_RX            125     /* S_DMA_124 */
-
 /*----------------------------------------------------------------------------*/
 
 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h
new file mode 100644
index 000000000000..3e6327016b40
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/flash.h
@@ -0,0 +1,16 @@
+/*
+ * Flash support for OMAP1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __OMAP_FLASH_H
+#define __OMAP_FLASH_H
+
+#include <linux/mtd/map.h>
+
+extern void omap1_set_vpp(struct map_info *map, int enable);
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index e081338e0b23..145838a81ef6 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -27,6 +27,8 @@
 
 #define GPMC_CONFIG             0x50
 #define GPMC_STATUS             0x54
+#define GPMC_CS0_BASE           0x60
+#define GPMC_CS_SIZE            0x30
 
 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
@@ -110,6 +112,6 @@ extern void gpmc_prefetch_reset(void);
 extern int gpmc_prefetch_status(void);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern void __init gpmc_init(void);
+extern void gpmc_init(void);
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 585d9ca68b97..87f6bf2ea4fa 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -34,6 +34,5 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
 
-int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len);
+void __init omap1_i2c_mux_pins(int bus_id);
+void __init omap2_i2c_mux_pins(int bus_id);
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 7e5319f907d1..128b549c2796 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -122,16 +122,21 @@
 #define OMAP243X_SMS_VIRT       (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP243X_SMS_SIZE       SZ_1M
 
-/* DSP */
-#define DSP_MEM_24XX_PHYS       OMAP2420_DSP_MEM_BASE   /* 0x58000000 */
-#define DSP_MEM_24XX_VIRT       0xe0000000
-#define DSP_MEM_24XX_SIZE       0x28000
-#define DSP_IPI_24XX_PHYS       OMAP2420_DSP_IPI_BASE   /* 0x59000000 */
-#define DSP_IPI_24XX_VIRT       0xe1000000
-#define DSP_IPI_24XX_SIZE       SZ_4K
-#define DSP_MMU_24XX_PHYS       OMAP2420_DSP_MMU_BASE   /* 0x5a000000 */
-#define DSP_MMU_24XX_VIRT       0xe2000000
-#define DSP_MMU_24XX_SIZE       SZ_4K
+/* 2420 IVA */
+#define DSP_MEM_2420_PHYS       OMAP2420_DSP_MEM_BASE
+                                                /* 0x58000000 --> 0xfc100000 */
+#define DSP_MEM_2420_VIRT       0xfc100000
+#define DSP_MEM_2420_SIZE       0x28000
+#define DSP_IPI_2420_PHYS       OMAP2420_DSP_IPI_BASE
+                                                /* 0x59000000 --> 0xfc128000 */
+#define DSP_IPI_2420_VIRT       0xfc128000
+#define DSP_IPI_2420_SIZE       SZ_4K
+#define DSP_MMU_2420_PHYS       OMAP2420_DSP_MMU_BASE
+                                                /* 0x5a000000 --> 0xfc129000 */
+#define DSP_MMU_2420_VIRT       0xfc129000
+#define DSP_MMU_2420_SIZE       SZ_4K
+
+/* 2430 IVA2.1 - currently unmapped */
 
 /*
  * ----------------------------------------------------------------------------
@@ -153,10 +158,6 @@
  * VPOM3430 was not working for Int controller
  */
 
-#define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
-#define L4_WK_34XX_VIRT         (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_WK_34XX_SIZE         SZ_1M
-
 #define L4_PER_34XX_PHYS        L4_PER_34XX_BASE
                                                 /* 0x49000000 --> 0xfb000000 */
 #define L4_PER_34XX_VIRT        (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
@@ -182,16 +183,7 @@
 #define OMAP343X_SDRC_VIRT      (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP343X_SDRC_SIZE      SZ_1M
 
-/* DSP */
-#define DSP_MEM_34XX_PHYS       OMAP34XX_DSP_MEM_BASE   /* 0x58000000 */
-#define DSP_MEM_34XX_VIRT       0xe0000000
-#define DSP_MEM_34XX_SIZE       0x28000
-#define DSP_IPI_34XX_PHYS       OMAP34XX_DSP_IPI_BASE   /* 0x59000000 */
-#define DSP_IPI_34XX_VIRT       0xe1000000
-#define DSP_IPI_34XX_SIZE       SZ_4K
-#define DSP_MMU_34XX_PHYS       OMAP34XX_DSP_MMU_BASE   /* 0x5a000000 */
-#define DSP_MMU_34XX_VIRT       0xe2000000
-#define DSP_MMU_34XX_SIZE       SZ_4K
+/* 3430 IVA - currently unmapped */
 
 /*
  * ----------------------------------------------------------------------------
@@ -208,11 +200,6 @@
 #define L4_44XX_VIRT            (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_44XX_SIZE            SZ_4M
 
-
-#define L4_WK_44XX_PHYS         L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
-#define L4_WK_44XX_VIRT         (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_WK_44XX_SIZE         SZ_1M
-
 #define L4_PER_44XX_PHYS        L4_PER_44XX_BASE
                                                 /* 0x48000000 --> 0xfa000000 */
 #define L4_PER_44XX_VIRT        (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
@@ -272,7 +259,38 @@ struct omap_sdrc_params;
 extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
-extern void omap2_map_common_io(void);
+#ifdef CONFIG_ARCH_OMAP2420
+extern void omap242x_map_common_io(void);
+#else
+static inline void omap242x_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2430
+extern void omap243x_map_common_io(void);
+#else
+static inline void omap243x_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+extern void omap34xx_map_common_io(void);
+#else
+static inline void omap34xx_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP4
+extern void omap44xx_map_common_io(void);
+#else
+static inline void omap44xx_map_common_io(void)
+{
+}
+#endif
+
 extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
                                  struct omap_sdrc_params *sdrc_cs1);
 
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h
new file mode 100644
index 000000000000..518322c80116
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/irqs-44xx.h
@@ -0,0 +1,144 @@
+/*
+ * OMAP4 Interrupt lines definitions
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
+
+/* OMAP44XX IRQs numbers definitions */
+#define OMAP44XX_IRQ_LOCALTIMER                 29
+#define OMAP44XX_IRQ_LOCALWDT                   30
+
+#define OMAP44XX_IRQ_GIC_START                  32
+
+#define OMAP44XX_IRQ_PL310                      (0 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CTI0                       (1 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CTI1                       (2 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_ELM                        (4 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SYS_1N                     (7 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SECURITY_EVENTS            (8 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_L3_DBG                     (9 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_L3_APP                     (10 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_PRCM                       (11 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SDMA_0                     (12 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SDMA_1                     (13 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SDMA_2                     (14 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SDMA_3                     (15 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCBSP4                     (16 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCBSP1                     (17 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SR_MCU                     (18 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SR_CORE                    (19 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPMC                       (20 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GFX                        (21 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCBSP2                     (22 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCBSP3                     (23 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_ISS_5                      (24 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DSS_DISPC                  (25 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MAIL_U0                    (26 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_C2C_SSCM_0                 (27 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_TESLA_MMU                  (28 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO1                      (29 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO2                      (30 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO3                      (31 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO4                      (32 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO5                      (33 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPIO6                      (34 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_USIM                       (35 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_WDT3                       (36 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT1                       (37 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT2                       (38 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT3                       (39 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT4                       (40 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT5                       (41 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT6                       (42 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT7                       (43 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT8                       (44 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT9                       (45 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT10                      (46 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT11                      (47 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SPI4                       (48 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SHA1_S                     (49 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S         (50 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SHA1_P                     (51 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_RNG                        (52 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DSS_DSI1                   (53 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_I2C1                       (56 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_I2C2                       (57 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HDQ                        (58 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MMC5                       (59 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_I2C3                       (61 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_I2C4                       (62 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_AES2_S                     (63 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_AES2_P                     (64 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SPI1                       (65 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SPI2                       (66 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HSI_P1                     (67 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HSI_P2                     (68 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_FDIF_3                     (69 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_UART4                      (70 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HSI_DMA                    (71 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_UART1                      (72 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_UART2                      (73 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_UART3                      (74 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_PBIAS                      (75 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_OHCI                       (76 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_EHCI                       (77 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_TLL                        (78 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_AES1_S                     (79 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_WDT2                       (80 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DES_S                      (81 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DES_P                      (82 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MMC1                       (83 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DSS_DSI2                   (84 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_AES1_P                     (85 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MMC2                       (86 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MPU_ICR                    (87 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_C2C_SSCM_1                 (88 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_FSUSB                      (89 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_FSUSB_SMI                  (90 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SPI3                       (91 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HS_USB_MC_N                (92 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_HS_USB_DMA_N               (93 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MMC3                       (94 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_GPT12                      (95 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MMC4                       (96 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SLIMBUS1                   (97 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SLIMBUS2                   (98 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_ABE                        (99 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DUCATI_MMU                 (100 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DSS_HDMI                   (101 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SR_IVA                     (102 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1     (103 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0     (104 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0      (107 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCASP1_AR                  (108 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCASP1_AX                  (109 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_EMIF4_1                    (110 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_EMIF4_2                    (111 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_MCPDM                      (112 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DMM                        (113 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_DMIC                       (114 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CDMA_0                     (115 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CDMA_1                     (116 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CDMA_2                     (117 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_CDMA_3                     (118 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_SYS_2N                     (119 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_KBD_CTL                    (120 + OMAP44XX_IRQ_GIC_START)
+#define OMAP44XX_IRQ_UNIPRO1                    (124 + OMAP44XX_IRQ_GIC_START)
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 97d6c50c3dcb..b65088a869e9 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -28,6 +28,9 @@
 #ifndef __ASM_ARCH_OMAP15XX_IRQS_H
 #define __ASM_ARCH_OMAP15XX_IRQS_H
 
+/* All OMAP4 specific defines are moved to irqs-44xx.h */
+#include "irqs-44xx.h"
+
 /*
  * IRQ numbers for interrupt handler 1
  *
@@ -344,95 +347,16 @@
 
 #define INT_34XX_BENCH_MPU_EMUL 3
 
-
-#define IRQ_GIC_START           32
-#define INT_44XX_LOCALTIMER_IRQ 29
-#define INT_44XX_LOCALWDT_IRQ   30
-
-#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
-#define INT_44XX_SSM_ABORT_IRQ  (6 + IRQ_GIC_START)
-#define INT_44XX_SYS_NIRQ       (7 + IRQ_GIC_START)
-#define INT_44XX_D2D_FW_IRQ     (8 + IRQ_GIC_START)
-#define INT_44XX_PRCM_MPU_IRQ   (11 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ0      (12 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ1      (13 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ2      (14 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ3      (15 + IRQ_GIC_START)
-#define INT_44XX_ISS_IRQ        (24 + IRQ_GIC_START)
-#define INT_44XX_DSS_IRQ        (25 + IRQ_GIC_START)
-#define INT_44XX_MAIL_U0_MPU    (26 + IRQ_GIC_START)
-#define INT_44XX_DSP_MMU        (28 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER1       (37 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER2       (38 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER3       (39 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER4       (40 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER5       (41 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER6       (42 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER7       (43 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER8       (44 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER9       (45 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER10      (46 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER11      (47 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER12      (95 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD5        (51 + IRQ_GIC_START)
-#define INT_44XX_I2C1_IRQ       (56 + IRQ_GIC_START)
-#define INT_44XX_I2C2_IRQ       (57 + IRQ_GIC_START)
-#define INT_44XX_HDQ_IRQ        (58 + IRQ_GIC_START)
-#define INT_44XX_SPI1_IRQ       (65 + IRQ_GIC_START)
-#define INT_44XX_SPI2_IRQ       (66 + IRQ_GIC_START)
-#define INT_44XX_HSI_1_IRQ0     (67 + IRQ_GIC_START)
-#define INT_44XX_HSI_2_IRQ1     (68 + IRQ_GIC_START)
-#define INT_44XX_HSI_1_DMAIRQ   (71 + IRQ_GIC_START)
-#define INT_44XX_UART1_IRQ      (72 + IRQ_GIC_START)
-#define INT_44XX_UART2_IRQ      (73 + IRQ_GIC_START)
-#define INT_44XX_UART3_IRQ      (74 + IRQ_GIC_START)
-#define INT_44XX_UART4_IRQ      (70 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_NISO   (76 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_ISO    (77 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_HGEN   (78 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_HSOF   (79 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_OTG    (80 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ_TX  (81 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ_RX  (82 + IRQ_GIC_START)
-#define INT_44XX_MMC_IRQ        (83 + IRQ_GIC_START)
-#define INT_44XX_MMC2_IRQ       (86 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ_TX  (89 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ_RX  (90 + IRQ_GIC_START)
-#define INT_44XX_SPI3_IRQ       (91 + IRQ_GIC_START)
-#define INT_44XX_SPI5_IRQ       (69 + IRQ_GIC_START)
-
-#define INT_44XX_MCBSP5_IRQ     (16 + IRQ_GIC_START)
-#define INT_44xX_MCBSP1_IRQ     (17 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ     (22 + IRQ_GIC_START)
-#define INT_44XX_MCBSP3_IRQ     (23 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ     (27 + IRQ_GIC_START)
-#define INT_44XX_HS_USB_MC      (92 + IRQ_GIC_START)
-#define INT_44XX_HS_USB_DMA     (93 + IRQ_GIC_START)
-
-#define INT_44XX_GPIO_BANK1     (29 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK2     (30 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK3     (31 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK4     (32 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK5     (33 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK6     (34 + IRQ_GIC_START)
-#define INT_44XX_USIM_IRQ       (35 + IRQ_GIC_START)
-#define INT_44XX_WDT3_IRQ       (36 + IRQ_GIC_START)
-#define INT_44XX_SPI4_IRQ       (48 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD52_IRQ   (49 + IRQ_GIC_START)
-#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD51_IRQ   (51 + IRQ_GIC_START)
-#define INT_44XX_RNG_IRQ        (52 + IRQ_GIC_START)
-#define INT_44XX_MMC5_IRQ       (59 + IRQ_GIC_START)
-#define INT_44XX_I2C3_IRQ       (61 + IRQ_GIC_START)
-#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
-#define INT_44XX_PBIAS_IRQ      (75 + IRQ_GIC_START)
-#define INT_44XX_OHCI_IRQ       (76 + IRQ_GIC_START)
-#define INT_44XX_EHCI_IRQ       (77 + IRQ_GIC_START)
-#define INT_44XX_TLL_IRQ        (78 + IRQ_GIC_START)
-#define INT_44XX_PARTHASH_IRQ   (79 + IRQ_GIC_START)
-#define INT_44XX_MMC3_IRQ       (94 + IRQ_GIC_START)
-#define INT_44XX_MMC4_IRQ       (96 + IRQ_GIC_START)
-
+#define INT_35XX_HECC0_IRQ              24
+#define INT_35XX_HECC1_IRQ              28
+#define INT_35XX_EMAC_C0_RXTHRESH_IRQ   67
+#define INT_35XX_EMAC_C0_RX_PULSE_IRQ   68
+#define INT_35XX_EMAC_C0_TX_PULSE_IRQ   69
+#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
+#define INT_35XX_USBOTG_IRQ             71
+#define INT_35XX_CCDC_VD0_IRQ           88
+#define INT_35XX_CCDC_VD1_IRQ           92
+#define INT_35XX_CCDC_VD2_IRQ           93
 
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
  * 16 MPUIO lines */
@@ -499,6 +423,9 @@ extern void omap_init_irq(void);
 extern int omap_irq_pending(void);
 void omap_intc_save_context(void);
 void omap_intc_restore_context(void);
+void omap3_intc_suspend(void);
+void omap3_intc_prepare_idle(void);
+void omap3_intc_resume_idle(void);
 #endif
 
 #include <mach/hardware.h>
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 4f22e5bb7ff7..39748354ce45 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -49,6 +49,9 @@
 
 #define OMAP34XX_MCBSP1_BASE    0x48074000
 #define OMAP34XX_MCBSP2_BASE    0x49022000
+#define OMAP34XX_MCBSP2_ST_BASE 0x49028000
+#define OMAP34XX_MCBSP3_BASE    0x49024000
+#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
 #define OMAP34XX_MCBSP3_BASE    0x49024000
 #define OMAP34XX_MCBSP4_BASE    0x49026000
 #define OMAP34XX_MCBSP5_BASE    0x48096000
@@ -103,8 +106,7 @@
 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
 
-#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-        defined(CONFIG_ARCH_OMAP4)
+#else
 
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x04
@@ -147,6 +149,15 @@
 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
 #define OMAP_MCBSP_REG_XCCR     0xAC
 #define OMAP_MCBSP_REG_RCCR     0xB0
+#define OMAP_MCBSP_REG_SSELCR   0xBC
+
+#define OMAP_ST_REG_REV         0x00
+#define OMAP_ST_REG_SYSCONFIG   0x10
+#define OMAP_ST_REG_IRQSTATUS   0x18
+#define OMAP_ST_REG_IRQENABLE   0x1C
+#define OMAP_ST_REG_SGAINCR     0x24
+#define OMAP_ST_REG_SFIRCR      0x28
+#define OMAP_ST_REG_SSELCR      0x2C
 
 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -265,6 +276,24 @@
 #define ENAWAKEUP               0x0004
 #define SOFTRST                 0x0002
 
+/********************** McBSP SSELCR bit definitions ***********************/
+#define SIDETONEEN              0x0400
+
+/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
+#define ST_AUTOIDLE             0x0001
+
+/********************** McBSP Sidetone SGAINCR bit definitions *************/
+#define ST_CH1GAIN(value)       ((value<<16))   /* Bits 16:31 */
+#define ST_CH0GAIN(value)       (value)         /* Bits 0:15 */
+
+/********************** McBSP Sidetone SFIRCR bit definitions **************/
+#define ST_FIRCOEFF(value)      (value)         /* Bits 0:15 */
+
+/********************** McBSP Sidetone SSELCR bit definitions **************/
+#define ST_COEFFWRDONE          0x0004
+#define ST_COEFFWREN            0x0002
+#define ST_SIDETONEEN           0x0001
+
 /********************** McBSP DMA operating modes **************************/
 #define MCBSP_DMA_MODE_ELEMENT          0
 #define MCBSP_DMA_MODE_THRESHOLD        1
@@ -374,11 +403,23 @@ struct omap_mcbsp_platform_data {
         u8 dma_rx_sync, dma_tx_sync;
         u16 rx_irq, tx_irq;
         struct omap_mcbsp_ops *ops;
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
+        /* Sidetone block for McBSP 2 and 3 */
+        unsigned long phys_base_st;
         u16 buffer_size;
 #endif
 };
 
+struct omap_mcbsp_st_data {
+        void __iomem *io_base_st;
+        bool running;
+        bool enabled;
+        s16 taps[128];  /* Sidetone filter coefficients */
+        int nr_taps;    /* Number of filter coefficients in use */
+        s16 ch0gain;
+        s16 ch1gain;
+};
+
 struct omap_mcbsp {
         struct device *dev;
         unsigned long phys_base;
@@ -410,20 +451,22 @@ struct omap_mcbsp {
         struct omap_mcbsp_platform_data *pdata;
         struct clk *iclk;
         struct clk *fclk;
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
+        struct omap_mcbsp_st_data *st_data;
         int dma_op_mode;
         u16 max_tx_thres;
         u16 max_rx_thres;
 #endif
+        void *reg_cache;
 };
 extern struct omap_mcbsp **mcbsp_ptr;
-extern int omap_mcbsp_count;
+extern int omap_mcbsp_count, omap_mcbsp_cache_size;
 
 int omap_mcbsp_init(void);
 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
                                         int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
@@ -459,4 +502,21 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf);
 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 
+#ifdef CONFIG_ARCH_OMAP3
+/* Sidetone specific API */
+int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
+int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
+int omap_st_enable(unsigned int id);
+int omap_st_disable(unsigned int id);
+int omap_st_is_enabled(unsigned int id);
+#else
+static inline int omap_st_set_chgain(unsigned int id, int channel,
+                                     s16 chgain) { return 0; }
+static inline int omap_st_get_chgain(unsigned int id, int channel,
+                                     s16 *chgain) { return 0; }
+static inline int omap_st_enable(unsigned int id) { return 0; }
+static inline int omap_st_disable(unsigned int id) { return 0; }
+static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
+#endif
+
 #endif
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h
index 3325f7b49eaa..d5306bee44b2 100644
--- a/arch/arm/plat-omap/include/plat/memory.h
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -38,8 +38,7 @@
  */
 #if defined(CONFIG_ARCH_OMAP1)
 #define PHYS_OFFSET             UL(0x10000000)
-#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#else
 #define PHYS_OFFSET             UL(0x80000000)
 #endif
 
diff --git a/arch/arm/plat-omap/include/plat/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h
index 3122bf68c7ce..4a970ec62dd1 100644
--- a/arch/arm/plat-omap/include/plat/menelaus.h
+++ b/arch/arm/plat-omap/include/plat/menelaus.h
@@ -40,7 +40,7 @@ extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
 
 extern int menelaus_set_regulator_sleep(int enable, u32 val);
 
-#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
+#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS)
 #define omap_has_menelaus()     1
 #else
 #define omap_has_menelaus()     0
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 29937137bf3e..a1bac07c89eb 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -55,12 +55,12 @@ struct omap_mmc_platform_data {
         unsigned int max_freq;
 
         /* switch the bus to a new slot */
-        int (* switch_slot)(struct device *dev, int slot);
+        int (*switch_slot)(struct device *dev, int slot);
         /* initialize board-specific MMC functionality, can be NULL if
          * not supported */
-        int (* init)(struct device *dev);
-        void (* cleanup)(struct device *dev);
-        void (* shutdown)(struct device *dev);
+        int (*init)(struct device *dev);
+        void (*cleanup)(struct device *dev);
+        void (*shutdown)(struct device *dev);
 
         /* To handle board related suspend/resume functionality for MMC */
         int (*suspend)(struct device *dev, int slot);
@@ -96,14 +96,28 @@ struct omap_mmc_platform_data {
                 /* Try to sleep or power off when possible */
                 unsigned power_saving:1;
 
+                /* If using power_saving and the MMC power is not to go off */
+                unsigned no_off:1;
+
+                /* Regulator off remapped to sleep */
+                unsigned vcc_aux_disable_is_sleep:1;
+
                 int switch_pin;                 /* gpio (card detect) */
                 int gpio_wp;                    /* gpio (write protect) */
 
-                int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
-                int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
-                int (* get_ro)(struct device *dev, int slot);
+                int (*set_bus_mode)(struct device *dev, int slot, int bus_mode);
+                int (*set_power)(struct device *dev, int slot,
+                                 int power_on, int vdd);
+                int (*get_ro)(struct device *dev, int slot);
                 int (*set_sleep)(struct device *dev, int slot, int sleep,
                                  int vdd, int cardsleep);
+                void (*remux)(struct device *dev, int slot, int power_on);
+                /* Call back before enabling / disabling regulators */
+                void (*before_set_reg)(struct device *dev, int slot,
+                                       int power_on, int vdd);
+                /* Call back after enabling / disabling regulators */
+                void (*after_set_reg)(struct device *dev, int slot,
+                                      int power_on, int vdd);
 
                 /* return MMC cover switch state, can be NULL if not supported.
                  *
@@ -111,14 +125,14 @@ struct omap_mmc_platform_data {
                  *   0 - closed
                  *   1 - open
                  */
-                int (* get_cover_state)(struct device *dev, int slot);
+                int (*get_cover_state)(struct device *dev, int slot);
 
                 const char *name;
                 u32 ocr_mask;
 
                 /* Card detection IRQs */
                 int card_detect_irq;
-                int (* card_detect)(int irq);
+                int (*card_detect)(struct device *dev, int slot);
 
                 unsigned int ban_openended:1;
 
@@ -126,7 +140,8 @@ struct omap_mmc_platform_data {
 };
 
 /* called from board-specific card detection service routine */
-extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
+extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
+                                        int is_closed);
 
 #if     defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
new file mode 100644
index 000000000000..f235d32cd942
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -0,0 +1,94 @@
+/*
+ * Support for compiling in multiple OMAP processors
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __PLAT_OMAP_MULTI_H
+#define __PLAT_OMAP_MULTI_H
+
+/*
+ * Test if multicore OMAP support is needed
+ */
+#undef MULTI_OMAP1
+#undef MULTI_OMAP2
+#undef OMAP_NAME
+
+#ifdef CONFIG_ARCH_OMAP730
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap730
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP850
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap850
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap1510
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap16xx
+# endif
+#endif
+#if (defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
+#  error "OMAP1 and OMAP2 can't be selected at the same time"
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP2420
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2420
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP2430
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2430
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP3430
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap3430
+# endif
+#endif
+
+#endif  /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index 8f069cc80350..c7472a28ce24 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -135,7 +135,7 @@ struct pin_config {
         const unsigned int      mux_reg;
         unsigned char           debug;
 
-#if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
+#if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
         const unsigned char mask_offset;
         const unsigned char mask;
 
@@ -183,6 +183,14 @@ enum omap7xx_index {
         /* I2C */
         I2C_7XX_SCL,
         I2C_7XX_SDA,
+
+        /* SPI */
+        SPI_7XX_1,
+        SPI_7XX_2,
+        SPI_7XX_3,
+        SPI_7XX_4,
+        SPI_7XX_5,
+        SPI_7XX_6,
 };
 
 enum omap1xxx_index {
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 631a7bed1eef..6ba88d2630d9 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -15,10 +15,18 @@ struct omap_nand_platform_data {
         int                     cs;
         int                     gpio_irq;
         struct mtd_partition    *parts;
+        struct gpmc_timings     *gpmc_t;
         int                     nr_parts;
-        int                     (*nand_setup)(void __iomem *);
+        int                     (*nand_setup)(void);
         int                     (*dev_ready)(struct omap_nand_platform_data *);
         int                     dma_channel;
+        unsigned long           phys_base;
         void __iomem            *gpmc_cs_baseaddr;
         void __iomem            *gpmc_baseaddr;
+        int                     devsize;
 };
+
+/* size (4 KiB) for IO mapping */
+#define NAND_IO_SIZE    SZ_4K
+
+extern int gpmc_nand_init(struct omap_nand_platform_data *d);
diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h
index 7560b4d583a3..e69e1d857b45 100644
--- a/arch/arm/plat-omap/include/plat/omap16xx.h
+++ b/arch/arm/plat-omap/include/plat/omap16xx.h
@@ -125,43 +125,43 @@
 #define OMAP16XX_MMCSD2_SSW_MPU_CONF    (TIPB_SWITCH_BASE + 0x160)
 
 /* UART3 Registers Mapping through MPU bus */
-#define UART3_RHR               (OMAP_UART3_BASE + 0)
-#define UART3_THR               (OMAP_UART3_BASE + 0)
-#define UART3_DLL               (OMAP_UART3_BASE + 0)
-#define UART3_IER               (OMAP_UART3_BASE + 4)
-#define UART3_DLH               (OMAP_UART3_BASE + 4)
-#define UART3_IIR               (OMAP_UART3_BASE + 8)
-#define UART3_FCR               (OMAP_UART3_BASE + 8)
-#define UART3_EFR               (OMAP_UART3_BASE + 8)
-#define UART3_LCR               (OMAP_UART3_BASE + 0x0C)
-#define UART3_MCR               (OMAP_UART3_BASE + 0x10)
-#define UART3_XON1_ADDR1        (OMAP_UART3_BASE + 0x10)
-#define UART3_XON2_ADDR2        (OMAP_UART3_BASE + 0x14)
-#define UART3_LSR               (OMAP_UART3_BASE + 0x14)
-#define UART3_TCR               (OMAP_UART3_BASE + 0x18)
-#define UART3_MSR               (OMAP_UART3_BASE + 0x18)
-#define UART3_XOFF1             (OMAP_UART3_BASE + 0x18)
-#define UART3_XOFF2             (OMAP_UART3_BASE + 0x1C)
-#define UART3_SPR               (OMAP_UART3_BASE + 0x1C)
-#define UART3_TLR               (OMAP_UART3_BASE + 0x1C)
-#define UART3_MDR1              (OMAP_UART3_BASE + 0x20)
-#define UART3_MDR2              (OMAP_UART3_BASE + 0x24)
-#define UART3_SFLSR             (OMAP_UART3_BASE + 0x28)
-#define UART3_TXFLL             (OMAP_UART3_BASE + 0x28)
-#define UART3_RESUME            (OMAP_UART3_BASE + 0x2C)
-#define UART3_TXFLH             (OMAP_UART3_BASE + 0x2C)
-#define UART3_SFREGL            (OMAP_UART3_BASE + 0x30)
-#define UART3_RXFLL             (OMAP_UART3_BASE + 0x30)
-#define UART3_SFREGH            (OMAP_UART3_BASE + 0x34)
-#define UART3_RXFLH             (OMAP_UART3_BASE + 0x34)
-#define UART3_BLR               (OMAP_UART3_BASE + 0x38)
-#define UART3_ACREG             (OMAP_UART3_BASE + 0x3C)
-#define UART3_DIV16             (OMAP_UART3_BASE + 0x3C)
-#define UART3_SCR               (OMAP_UART3_BASE + 0x40)
-#define UART3_SSR               (OMAP_UART3_BASE + 0x44)
-#define UART3_EBLR              (OMAP_UART3_BASE + 0x48)
-#define UART3_OSC_12M_SEL       (OMAP_UART3_BASE + 0x4C)
-#define UART3_MVR               (OMAP_UART3_BASE + 0x50)
+#define UART3_RHR               (OMAP1_UART3_BASE + 0)
+#define UART3_THR               (OMAP1_UART3_BASE + 0)
+#define UART3_DLL               (OMAP1_UART3_BASE + 0)
+#define UART3_IER               (OMAP1_UART3_BASE + 4)
+#define UART3_DLH               (OMAP1_UART3_BASE + 4)
+#define UART3_IIR               (OMAP1_UART3_BASE + 8)
+#define UART3_FCR               (OMAP1_UART3_BASE + 8)
+#define UART3_EFR               (OMAP1_UART3_BASE + 8)
+#define UART3_LCR               (OMAP1_UART3_BASE + 0x0C)
+#define UART3_MCR               (OMAP1_UART3_BASE + 0x10)
+#define UART3_XON1_ADDR1        (OMAP1_UART3_BASE + 0x10)
+#define UART3_XON2_ADDR2        (OMAP1_UART3_BASE + 0x14)
+#define UART3_LSR               (OMAP1_UART3_BASE + 0x14)
+#define UART3_TCR               (OMAP1_UART3_BASE + 0x18)
+#define UART3_MSR               (OMAP1_UART3_BASE + 0x18)
+#define UART3_XOFF1             (OMAP1_UART3_BASE + 0x18)
+#define UART3_XOFF2             (OMAP1_UART3_BASE + 0x1C)
+#define UART3_SPR               (OMAP1_UART3_BASE + 0x1C)
+#define UART3_TLR               (OMAP1_UART3_BASE + 0x1C)
+#define UART3_MDR1              (OMAP1_UART3_BASE + 0x20)
+#define UART3_MDR2              (OMAP1_UART3_BASE + 0x24)
+#define UART3_SFLSR             (OMAP1_UART3_BASE + 0x28)
+#define UART3_TXFLL             (OMAP1_UART3_BASE + 0x28)
+#define UART3_RESUME            (OMAP1_UART3_BASE + 0x2C)
+#define UART3_TXFLH             (OMAP1_UART3_BASE + 0x2C)
+#define UART3_SFREGL            (OMAP1_UART3_BASE + 0x30)
+#define UART3_RXFLL             (OMAP1_UART3_BASE + 0x30)
+#define UART3_SFREGH            (OMAP1_UART3_BASE + 0x34)
+#define UART3_RXFLH             (OMAP1_UART3_BASE + 0x34)
+#define UART3_BLR               (OMAP1_UART3_BASE + 0x38)
+#define UART3_ACREG             (OMAP1_UART3_BASE + 0x3C)
+#define UART3_DIV16             (OMAP1_UART3_BASE + 0x3C)
+#define UART3_SCR               (OMAP1_UART3_BASE + 0x40)
+#define UART3_SSR               (OMAP1_UART3_BASE + 0x44)
+#define UART3_EBLR              (OMAP1_UART3_BASE + 0x48)
+#define UART3_OSC_12M_SEL       (OMAP1_UART3_BASE + 0x4C)
+#define UART3_MVR               (OMAP1_UART3_BASE + 0x50)
 
 /*
  * ---------------------------------------------------------------------------
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
index 696edfc145a6..7055672a8c68 100644
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
@@ -23,8 +23,8 @@
  *
  */
 
-#ifndef __ASM_ARCH_OMAP24XX_H
-#define __ASM_ARCH_OMAP24XX_H
+#ifndef __ASM_ARCH_OMAP2_H
+#define __ASM_ARCH_OMAP2_H
 
 /*
  * Please place only base defines here and put the rest in device
@@ -85,5 +85,5 @@
 #define OMAP24XX_SEC_AES_BASE   (OMAP24XX_SEC_BASE + 0x6000)
 #define OMAP24XX_SEC_PKA_BASE   (OMAP24XX_SEC_BASE + 0x8000)
 
-#endif /* __ASM_ARCH_OMAP24XX_H */
+#endif /* __ASM_ARCH_OMAP2_H */
 
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index 077f05979f86..2845fdc658b0 100644
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -21,8 +21,8 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_OMAP34XX_H
-#define __ASM_ARCH_OMAP34XX_H
+#ifndef __ASM_ARCH_OMAP3_H
+#define __ASM_ARCH_OMAP3_H
 
 /*
  * Please place only base defines here and put the rest in device
@@ -82,5 +82,5 @@
 
 #define OMAP34XX_MAILBOX_BASE           (L4_34XX_BASE + 0x94000)
 
-#endif /* __ASM_ARCH_OMAP34XX_H */
+#endif /* __ASM_ARCH_OMAP3_H */
 
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index ef870de43c29..2302474a3748 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -40,9 +40,13 @@
 #define OMAP44XX_GIC_CPU_BASE           0x48240100
 #define OMAP44XX_SCU_BASE               0x48240000
 #define OMAP44XX_LOCAL_TWD_BASE         0x48240600
+#define OMAP44XX_L2CACHE_BASE           0x48242000
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
+#define OMAP44XX_MCPDM_BASE             0x40132000
+#define OMAP44XX_MCPDM_L3_BASE          0x49032000
 
 #define OMAP44XX_MAILBOX_BASE           (L4_44XX_BASE + 0xF4000)
+#define OMAP44XX_HSUSB_OTG_BASE         (L4_44XX_BASE + 0xAB000)
 
 #endif /* __ASM_ARCH_OMAP44XX_H */
 
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h
index 53f52414b0e9..48e4757e1e30 100644
--- a/arch/arm/plat-omap/include/plat/omap7xx.h
+++ b/arch/arm/plat-omap/include/plat/omap7xx.h
@@ -46,6 +46,9 @@
 #define OMAP7XX_DSPREG_SIZE     SZ_128K
 #define OMAP7XX_DSPREG_START    0xE1000000
 
+#define OMAP7XX_SPI1_BASE       0xfffc0800
+#define OMAP7XX_SPI2_BASE       0xfffc1000
+
 /*
  * ----------------------------------------------------------------------------
  * OMAP7XX specific configuration registers
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index dc1fac1d805c..3694b622c4ac 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -62,6 +62,7 @@
  *
  */
 struct omap_device {
+        u32                             magic;
         struct platform_device          pdev;
         struct omap_hwmod               **hwmods;
         struct omap_device_pm_latency   *pm_lats;
@@ -81,6 +82,7 @@ int omap_device_shutdown(struct platform_device *pdev);
 
 /* Core code interface */
 
+bool omap_device_is_valid(struct omap_device *od);
 int omap_device_count_resources(struct omap_device *od);
 int omap_device_fill_resources(struct omap_device *od, struct resource *res);
 
@@ -88,15 +90,16 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
                                       struct omap_hwmod *oh, void *pdata,
                                       int pdata_len,
                                       struct omap_device_pm_latency *pm_lats,
-                                      int pm_lats_cnt);
+                                      int pm_lats_cnt, int is_early_device);
 
 struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_hwmod **oh, int oh_cnt,
                                          void *pdata, int pdata_len,
                                          struct omap_device_pm_latency *pm_lats,
-                                         int pm_lats_cnt);
+                                         int pm_lats_cnt, int is_early_device);
 
 int omap_device_register(struct omap_device *od);
+int omap_early_device_register(struct omap_device *od);
 
 /* OMAP PM interface */
 int omap_device_align_pm_lat(struct platform_device *pdev,
@@ -131,11 +134,15 @@ int omap_device_enable_clocks(struct omap_device *od);
  */
 struct omap_device_pm_latency {
         u32 deactivate_lat;
+        u32 deactivate_lat_worst;
         int (*deactivate_func)(struct omap_device *od);
         u32 activate_lat;
+        u32 activate_lat_worst;
         int (*activate_func)(struct omap_device *od);
+        u32 flags;
 };
 
+#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
 
 /* Get omap_device pointer from platform_device pointer */
 #define to_omap_device(x) container_of((x), struct omap_device, pdev)
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 007935a921ea..440b4164f2f6 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -4,7 +4,7 @@
  * Copyright (C) 2009 Nokia Corporation
  * Paul Walmsley
  *
- * Created in collaboration with (alphabetical order): Benoit Cousson,
+ * Created in collaboration with (alphabetical order): Benoît Cousson,
  * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
  * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
  *
@@ -33,25 +33,42 @@
 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
 
 #include <linux/kernel.h>
+#include <linux/list.h>
 #include <linux/ioport.h>
-
 #include <plat/cpu.h>
 
 struct omap_device;
 
-/* OCP SYSCONFIG bit shifts/masks */
-#define SYSC_MIDLEMODE_SHIFT            12
-#define SYSC_MIDLEMODE_MASK             (0x3 << SYSC_MIDLEMODE_SHIFT)
-#define SYSC_CLOCKACTIVITY_SHIFT        8
-#define SYSC_CLOCKACTIVITY_MASK         (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
-#define SYSC_SIDLEMODE_SHIFT            3
-#define SYSC_SIDLEMODE_MASK             (0x3 << SYSC_SIDLEMODE_SHIFT)
-#define SYSC_ENAWAKEUP_SHIFT            2
-#define SYSC_ENAWAKEUP_MASK             (1 << SYSC_ENAWAKEUP_SHIFT)
-#define SYSC_SOFTRESET_SHIFT            1
-#define SYSC_SOFTRESET_MASK             (1 << SYSC_SOFTRESET_SHIFT)
-#define SYSC_AUTOIDLE_SHIFT             0
-#define SYSC_AUTOIDLE_MASK              (1 << SYSC_AUTOIDLE_SHIFT)
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+
+/*
+ * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
+ * with the original PRCM protocol defined for OMAP2420
+ */
+#define SYSC_TYPE1_MIDLEMODE_SHIFT      12
+#define SYSC_TYPE1_MIDLEMODE_MASK       (0x3 << SYSC_MIDLEMODE_SHIFT)
+#define SYSC_TYPE1_CLOCKACTIVITY_SHIFT  8
+#define SYSC_TYPE1_CLOCKACTIVITY_MASK   (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
+#define SYSC_TYPE1_SIDLEMODE_SHIFT      3
+#define SYSC_TYPE1_SIDLEMODE_MASK       (0x3 << SYSC_SIDLEMODE_SHIFT)
+#define SYSC_TYPE1_ENAWAKEUP_SHIFT      2
+#define SYSC_TYPE1_ENAWAKEUP_MASK       (1 << SYSC_ENAWAKEUP_SHIFT)
+#define SYSC_TYPE1_SOFTRESET_SHIFT      1
+#define SYSC_TYPE1_SOFTRESET_MASK       (1 << SYSC_SOFTRESET_SHIFT)
+#define SYSC_TYPE1_AUTOIDLE_SHIFT       0
+#define SYSC_TYPE1_AUTOIDLE_MASK        (1 << SYSC_AUTOIDLE_SHIFT)
+
+/*
+ * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
+ * with the new PRCM protocol defined for new OMAP4 IPs.
+ */
+#define SYSC_TYPE2_SOFTRESET_SHIFT      0
+#define SYSC_TYPE2_SOFTRESET_MASK       (1 << SYSC_TYPE2_SOFTRESET_SHIFT)
+#define SYSC_TYPE2_SIDLEMODE_SHIFT      2
+#define SYSC_TYPE2_SIDLEMODE_MASK       (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
+#define SYSC_TYPE2_MIDLEMODE_SHIFT      4
+#define SYSC_TYPE2_MIDLEMODE_MASK       (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
 
 /* OCP SYSSTATUS bit shifts/masks */
 #define SYSS_RESETDONE_SHIFT            0
@@ -62,7 +79,6 @@ struct omap_device;
 #define HWMOD_IDLEMODE_NO               (1 << 1)
 #define HWMOD_IDLEMODE_SMART            (1 << 2)
 
-
 /**
  * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
  * @name: name of the IRQ channel (module local name)
@@ -94,8 +110,7 @@ struct omap_hwmod_dma_info {
 /**
  * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
  * @role: "sys", "32k", "tv", etc -- for use in clk_get()
- * @clkdev_dev_id: opt clock: clkdev dev_id string
- * @clkdev_con_id: opt clock: clkdev con_id string
+ * @clk: opt clock: OMAP clock name
  * @_clk: pointer to the struct clk (filled in at runtime)
  *
  * The module's interface clock and main functional clock should not
@@ -103,8 +118,7 @@ struct omap_hwmod_dma_info {
  */
 struct omap_hwmod_opt_clk {
         const char      *role;
-        const char      *clkdev_dev_id;
-        const char      *clkdev_con_id;
+        const char      *clk;
         struct clk      *_clk;
 };
 
@@ -171,8 +185,7 @@ struct omap_hwmod_addr_space {
  * @master: struct omap_hwmod that initiates OCP transactions on this link
  * @slave: struct omap_hwmod that responds to OCP transactions on this link
  * @addr: address space associated with this link
- * @clkdev_dev_id: interface clock: clkdev dev_id string
- * @clkdev_con_id: interface clock: clkdev con_id string
+ * @clk: interface clock: OMAP clock name
  * @_clk: pointer to the interface struct clk (filled in at runtime)
  * @fw: interface firewall data
  * @addr_cnt: ARRAY_SIZE(@addr)
@@ -191,8 +204,7 @@ struct omap_hwmod_ocp_if {
         struct omap_hwmod               *master;
         struct omap_hwmod               *slave;
         struct omap_hwmod_addr_space    *addr;
-        const char                      *clkdev_dev_id;
-        const char                      *clkdev_con_id;
+        const char                      *clk;
         struct clk                      *_clk;
         union {
                 struct omap_hwmod_omap2_firewall omap2;
@@ -227,6 +239,7 @@ struct omap_hwmod_ocp_if {
 #define SYSC_HAS_SIDLEMODE      (1 << 5)
 #define SYSC_HAS_MIDLEMODE      (1 << 6)
 #define SYSS_MISSING            (1 << 7)
+#define SYSC_NO_CACHE           (1 << 8)  /* XXX SW flag, belongs elsewhere */
 
 /* omap_hwmod_sysconfig.clockact flags */
 #define CLOCKACT_TEST_BOTH      0x0
@@ -235,7 +248,25 @@ struct omap_hwmod_ocp_if {
 #define CLOCKACT_TEST_NONE      0x3
 
 /**
- * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
+ * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
+ * @midle_shift: Offset of the midle bit
+ * @clkact_shift: Offset of the clockactivity bit
+ * @sidle_shift: Offset of the sidle bit
+ * @enwkup_shift: Offset of the enawakeup bit
+ * @srst_shift: Offset of the softreset bit
+ * @autoidle_shift: Offset of the autoidle bit
+ */
+struct omap_hwmod_sysc_fields {
+        u8 midle_shift;
+        u8 clkact_shift;
+        u8 sidle_shift;
+        u8 enwkup_shift;
+        u8 srst_shift;
+        u8 autoidle_shift;
+};
+
+/**
+ * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
  * @rev_offs: IP block revision register offset (from module base addr)
  * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
  * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
@@ -251,14 +282,22 @@ struct omap_hwmod_ocp_if {
  * been associated with the clocks marked in @clockact.  This field is
  * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
  *
+ * @sysc_fields: structure containing the offset positions of various bits in
+ * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
+ * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
+ * whether the device ip is compliant with the original PRCM protocol
+ * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs.
+ * If the device follows a different scheme for the sysconfig register ,
+ * then this field has to be populated with the correct offset structure.
  */
-struct omap_hwmod_sysconfig {
+struct omap_hwmod_class_sysconfig {
         u16 rev_offs;
         u16 sysc_offs;
         u16 syss_offs;
         u8 idlemodes;
         u8 sysc_flags;
         u8 clockact;
+        struct omap_hwmod_sysc_fields *sysc_fields;
 };
 
 /**
@@ -351,19 +390,33 @@ struct omap_hwmod_omap4_prcm {
 #define _HWMOD_STATE_DISABLED                   6
 
 /**
+ * struct omap_hwmod_class - the type of an IP block
+ * @name: name of the hwmod_class
+ * @sysc: device SYSCONFIG/SYSSTATUS register data
+ * @rev: revision of the IP class
+ *
+ * Represent the class of a OMAP hardware "modules" (e.g. timer,
+ * smartreflex, gpio, uart...)
+ */
+struct omap_hwmod_class {
+        const char                              *name;
+        struct omap_hwmod_class_sysconfig       *sysc;
+        u32                                     rev;
+};
+
+/**
  * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
  * @name: name of the hwmod
+ * @class: struct omap_hwmod_class * to the class of this hwmod
  * @od: struct omap_device currently associated with this hwmod (internal use)
  * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
  * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
  * @prcm: PRCM data pertaining to this hwmod
- * @clkdev_dev_id: main clock: clkdev dev_id string
- * @clkdev_con_id: main clock: clkdev con_id string
+ * @main_clk: main clock: OMAP clock name
  * @_clk: pointer to the main struct clk (filled in at runtime)
  * @opt_clks: other device clocks that drivers can request (0..*)
  * @masters: ptr to array of OCP ifs that this hwmod can initiate on
  * @slaves: ptr to array of OCP ifs that this hwmod can respond on
- * @sysconfig: device SYSCONFIG/SYSSTATUS register data
  * @dev_attr: arbitrary device attributes that can be passed to the driver
  * @_sysc_cache: internal-use hwmod flags
  * @_rt_va: cached register target start address (internal use)
@@ -382,16 +435,17 @@ struct omap_hwmod_omap4_prcm {
  * @omap_chip: OMAP chips this hwmod is present on
  * @node: list node for hwmod list (internal use)
  *
- * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
- * clock," which for our purposes is defined as "the functional clock needed
- * for register accesses to complete."  Modules may not have a main clock if
- * the interface clock also serves as a main clock.
+ * @main_clk refers to this module's "main clock," which for our
+ * purposes is defined as "the functional clock needed for register
+ * accesses to complete."  Modules may not have a main clock if the
+ * interface clock also serves as a main clock.
  *
  * Parameter names beginning with an underscore are managed internally by
  * the omap_hwmod code and should not be set during initialization.
  */
 struct omap_hwmod {
         const char                      *name;
+        struct omap_hwmod_class         *class;
         struct omap_device              *od;
         struct omap_hwmod_irq_info      *mpu_irqs;
         struct omap_hwmod_dma_info      *sdma_chs;
@@ -399,13 +453,11 @@ struct omap_hwmod {
                 struct omap_hwmod_omap2_prcm omap2;
                 struct omap_hwmod_omap4_prcm omap4;
         }                               prcm;
-        const char                      *clkdev_dev_id;
-        const char                      *clkdev_con_id;
+        const char                      *main_clk;
         struct clk                      *_clk;
         struct omap_hwmod_opt_clk       *opt_clks;
         struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
         struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
-        struct omap_hwmod_sysconfig     *sysconfig;
         void                            *dev_attr;
         u32                             _sysc_cache;
         void __iomem                    *_rt_va;
@@ -440,6 +492,8 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh);
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
 
+int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
+
 int omap_hwmod_reset(struct omap_hwmod *oh);
 void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
 
@@ -464,4 +518,17 @@ int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
 
+int omap_hwmod_for_each_by_class(const char *classname,
+                                 int (*fn)(struct omap_hwmod *oh,
+                                           void *user),
+                                 void *user);
+
+/*
+ * Chip variant-specific hwmod init routines - XXX should be converted
+ * to use initcalls once the initial boot ordering is straightened out
+ */
+extern int omap2420_hwmod_init(void);
+extern int omap2430_hwmod_init(void);
+extern int omap3xxx_hwmod_init(void);
+
 #endif
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 0b960051eaed..d82b2c00d4f1 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -1,8 +1,8 @@
 /*
  * OMAP2/3 powerdomain control
  *
- * Copyright (C) 2007-8 Texas Instruments, Inc.
- * Copyright (C) 2007-8 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -37,6 +37,9 @@
 #define PWRSTS_OFF_RET          ((1 << PWRDM_POWER_OFF) | \
                                  (1 << PWRDM_POWER_RET))
 
+#define PWRSTS_RET_ON           ((1 << PWRDM_POWER_RET) | \
+                                 (1 << PWRDM_POWER_ON))
+
 #define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
 
 
@@ -48,16 +51,16 @@
                                           */
 
 /*
- * Number of memory banks that are power-controllable.  On OMAP3430, the
- * maximum is 4.
+ * Number of memory banks that are power-controllable.  On OMAP4430, the
+ * maximum is 5.
  */
-#define PWRDM_MAX_MEM_BANKS     4
+#define PWRDM_MAX_MEM_BANKS     5
 
 /*
  * Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain on OMAP3 is the worst case
+ * CORE powerdomain on OMAP4 is the worst case
  */
-#define PWRDM_MAX_CLKDMS        4
+#define PWRDM_MAX_CLKDMS        9
 
 /* XXX A completely arbitrary number. What is reasonable here? */
 #define PWRDM_TRANSITION_BAILOUT 100000
@@ -65,65 +68,40 @@
 struct clockdomain;
 struct powerdomain;
 
-/* Encodes dependencies between powerdomains - statically defined */
-struct pwrdm_dep {
-
-        /* Powerdomain name */
-        const char *pwrdm_name;
-
-        /* Powerdomain pointer - resolved by the powerdomain code */
-        struct powerdomain *pwrdm;
-
-        /* Flags to mark OMAP chip restrictions, etc. */
-        const struct omap_chip_id omap_chip;
-
-};
-
+/**
+ * struct powerdomain - OMAP powerdomain
+ * @name: Powerdomain name
+ * @omap_chip: represents the OMAP chip types containing this pwrdm
+ * @prcm_offs: the address offset from CM_BASE/PRM_BASE
+ * @pwrsts: Possible powerdomain power states
+ * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
+ * @flags: Powerdomain flags
+ * @banks: Number of software-controllable memory banks in this powerdomain
+ * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
+ * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
+ * @pwrdm_clkdms: Clockdomains in this powerdomain
+ * @node: list_head linking all powerdomains
+ * @state:
+ * @state_counter:
+ * @timer:
+ * @state_timer:
+ */
 struct powerdomain {
-
-        /* Powerdomain name */
         const char *name;
-
-        /* the address offset from CM_BASE/PRM_BASE */
-        const s16 prcm_offs;
-
-        /* Used to represent the OMAP chip types containing this pwrdm */
         const struct omap_chip_id omap_chip;
-
-        /* Powerdomains that can be told to wake this powerdomain up */
-        struct pwrdm_dep *wkdep_srcs;
-
-        /* Powerdomains that can be told to keep this pwrdm from inactivity */
-        struct pwrdm_dep *sleepdep_srcs;
-
-        /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
-        const u8 dep_bit;
-
-        /* Possible powerdomain power states */
+        const s16 prcm_offs;
         const u8 pwrsts;
-
-        /* Possible logic power states when pwrdm in RETENTION */
         const u8 pwrsts_logic_ret;
-
-        /* Powerdomain flags */
         const u8 flags;
-
-        /* Number of software-controllable memory banks in this powerdomain */
         const u8 banks;
-
-        /* Possible memory bank pwrstates when pwrdm in RETENTION */
         const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
-
-        /* Possible memory bank pwrstates when pwrdm is ON */
         const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
-
-        /* Clockdomains in this powerdomain */
         struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
-
         struct list_head node;
-
         int state;
         unsigned state_counter[PWRDM_MAX_PWRSTS];
+        unsigned ret_logic_off_counter;
+        unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
 
 #ifdef CONFIG_PM_DEBUG
         s64 timer;
@@ -134,8 +112,6 @@ struct powerdomain {
 
 void pwrdm_init(struct powerdomain **pwrdm_list);
 
-int pwrdm_register(struct powerdomain *pwrdm);
-int pwrdm_unregister(struct powerdomain *pwrdm);
 struct powerdomain *pwrdm_lookup(const char *name);
 
 int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
@@ -149,13 +125,6 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
                          int (*fn)(struct powerdomain *pwrdm,
                                    struct clockdomain *clkdm));
 
-int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-
 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
 
 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
@@ -170,8 +139,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
 
 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
 
 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index e63e94e18975..d6a0e27d5a7f 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -25,7 +25,8 @@
 
 u32 omap_prcm_get_reset_sources(void);
 void omap_prcm_arch_reset(char mode);
-int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
+                         const char *name);
 
 #define START_PADCONF_SAVE 0x2
 #define PADCONF_SAVE_DONE  0x1
@@ -33,6 +34,14 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
 void omap3_prcm_save_context(void);
 void omap3_prcm_restore_context(void);
 
+u32 prm_read_mod_reg(s16 module, u16 idx);
+void prm_write_mod_reg(u32 val, s16 module, u16 idx);
+u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
+u32 cm_read_mod_reg(s16 module, u16 idx);
+void cm_write_mod_reg(u32 val, s16 module, u16 idx);
+u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+
 #endif
 
 
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index f5a4a92393ef..83dce4c4f7e6 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -15,37 +15,65 @@
 
 #include <linux/init.h>
 
-#if defined(CONFIG_ARCH_OMAP1)
 /* OMAP1 serial ports */
-#define OMAP_UART1_BASE         0xfffb0000
-#define OMAP_UART2_BASE         0xfffb0800
-#define OMAP_UART3_BASE         0xfffb9800
-#elif defined(CONFIG_ARCH_OMAP2)
+#define OMAP1_UART1_BASE        0xfffb0000
+#define OMAP1_UART2_BASE        0xfffb0800
+#define OMAP1_UART3_BASE        0xfffb9800
+
 /* OMAP2 serial ports */
-#define OMAP_UART1_BASE         0x4806a000
-#define OMAP_UART2_BASE         0x4806c000
-#define OMAP_UART3_BASE         0x4806e000
-#elif defined(CONFIG_ARCH_OMAP3)
+#define OMAP2_UART1_BASE        0x4806a000
+#define OMAP2_UART2_BASE        0x4806c000
+#define OMAP2_UART3_BASE        0x4806e000
+
 /* OMAP3 serial ports */
-#define OMAP_UART1_BASE         0x4806a000
-#define OMAP_UART2_BASE         0x4806c000
-#define OMAP_UART3_BASE         0x49020000
-#elif defined(CONFIG_ARCH_OMAP4)
+#define OMAP3_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP3_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP3_UART3_BASE        0x49020000
+#define OMAP3_UART4_BASE        0x49042000      /* Only on 36xx */
+
 /* OMAP4 serial ports */
-#define OMAP_UART1_BASE         0x4806a000
-#define OMAP_UART2_BASE         0x4806c000
-#define OMAP_UART3_BASE         0x48020000
-#define OMAP_UART4_BASE         0x4806e000
-#endif
+#define OMAP4_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP4_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP4_UART3_BASE        0x48020000
+#define OMAP4_UART4_BASE        0x4806e000
+
+/* External port on Zoom2/3 */
+#define ZOOM_UART_BASE          0x10000000
+#define ZOOM_UART_VIRT          0xfb000000
+
+#define OMAP_PORT_SHIFT         2
+#define OMAP7XX_PORT_SHIFT      0
+#define ZOOM_PORT_SHIFT         1
 
 #define OMAP1510_BASE_BAUD      (12000000/16)
 #define OMAP16XX_BASE_BAUD      (48000000/16)
 #define OMAP24XX_BASE_BAUD      (48000000/16)
 
+/*
+ * DEBUG_LL port encoding stored into the UART1 scratchpad register by
+ * decomp_setup in uncompress.h
+ */
+#define OMAP1UART1              11
+#define OMAP1UART2              12
+#define OMAP1UART3              13
+#define OMAP2UART1              21
+#define OMAP2UART2              22
+#define OMAP2UART3              23
+#define OMAP3UART1              OMAP2UART1
+#define OMAP3UART2              OMAP2UART2
+#define OMAP3UART3              33
+#define OMAP3UART4              34              /* Only on 36xx */
+#define OMAP4UART1              OMAP2UART1
+#define OMAP4UART2              OMAP2UART2
+#define OMAP4UART3              43
+#define OMAP4UART4              44
+#define ZOOM_UART               95              /* Only on zoom2/3 */
+
+/* This is only used by 8250.c for omap1510 */
 #define is_omap_port(pt)        ({int __ret = 0;                        \
-                        if ((pt)->port.mapbase == OMAP_UART1_BASE ||    \
-                            (pt)->port.mapbase == OMAP_UART2_BASE ||    \
-                            (pt)->port.mapbase == OMAP_UART3_BASE)      \
+                        if ((pt)->port.mapbase == OMAP1_UART1_BASE ||   \
+                            (pt)->port.mapbase == OMAP1_UART2_BASE ||   \
+                            (pt)->port.mapbase == OMAP1_UART3_BASE)     \
                                 __ret = 1;                              \
                         __ret;                                          \
                         })
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 13c305d62127..81d9ec540fcf 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -19,62 +19,38 @@
 
 #include <linux/types.h>
 #include <linux/serial_reg.h>
+
+#include <asm/mach-types.h>
+
 #include <plat/serial.h>
 
-unsigned int system_rev;
+static volatile u8 *uart1_base;
+static int uart1_shift;
 
-#define UART_OMAP_MDR1          0x08    /* mode definition register */
-#define OMAP_ID_730             0x355F
-#define OMAP_ID_850             0x362C
-#define ID_MASK                 0x7fff
-#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
-#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
+static volatile u8 *uart_base;
+static int uart_shift;
 
-static void putc(int c)
+/*
+ * Store the DEBUG_LL uart number into UART1 scratchpad register.
+ * See also debug-macro.S, and serial.c for related code.
+ *
+ * Please note that we currently assume that:
+ * - UART1 clocks are enabled for register access
+ * - UART1 scratchpad register can be used
+ */
+static void set_uart1_scratchpad(unsigned char port)
 {
-        volatile u8 * uart = 0;
-        int shift = 2;
-
-#ifdef CONFIG_MACH_OMAP_PALMTE
-        return;
-#endif
-
-#ifdef CONFIG_ARCH_OMAP
-#ifdef  CONFIG_OMAP_LL_DEBUG_UART3
-        uart = (volatile u8 *)(OMAP_UART3_BASE);
-#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
-        uart = (volatile u8 *)(OMAP_UART2_BASE);
-#elif defined(CONFIG_OMAP_LL_DEBUG_UART1)
-        uart = (volatile u8 *)(OMAP_UART1_BASE);
-#elif defined(CONFIG_OMAP_LL_DEBUG_NONE)
-        return;
-#else
-        return;
-#endif
-
-#ifdef CONFIG_ARCH_OMAP1
-        /* Determine which serial port to use */
-        do {
-                /* MMU is not on, so cpu_is_omapXXXX() won't work here */
-                unsigned int omap_id = omap_get_id();
-
-                if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
-                        shift = 0;
+        uart1_base[UART_SCR << uart1_shift] = port;
+}
 
-                if (check_port(uart, shift))
-                        break;
-                /* Silent boot if no serial ports are enabled. */
+static void putc(int c)
+{
+        if (!uart_base)
                 return;
-        } while (0);
-#endif /* CONFIG_ARCH_OMAP1 */
-#endif
 
-        /*
-         * Now, xmit each character
-         */
-        while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
                 barrier();
-        uart[UART_TX << shift] = c;
+        uart_base[UART_TX << uart_shift] = c;
 }
 
 static inline void flush(void)
@@ -82,7 +58,116 @@ static inline void flush(void)
 }
 
 /*
+ * Macros to configure UART1 and debug UART
+ */
+#define _DEBUG_LL_ENTRY(mach, uart1_phys, uart1_shft,                   \
+                        dbg_uart, dbg_shft, dbg_id)                     \
+        if (machine_is_##mach()) {                                      \
+                uart1_base = (volatile u8 *)(uart1_phys);               \
+                uart1_shift = (uart1_shft);                             \
+                uart_base = (volatile u8 *)(dbg_uart);                  \
+                uart_shift = (dbg_shft);                                \
+                port = (dbg_id);                                        \
+                set_uart1_scratchpad(port);                             \
+                break;                                                  \
+        }
+
+#define DEBUG_LL_OMAP7XX(p, mach)                                       \
+        _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP7XX_PORT_SHIFT,     \
+                OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, OMAP1UART##p)
+
+#define DEBUG_LL_OMAP1(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP_PORT_SHIFT,        \
+                OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP1UART##p)
+
+#define DEBUG_LL_OMAP2(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT,        \
+                OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP2UART##p)
+
+#define DEBUG_LL_OMAP3(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP3_UART1_BASE, OMAP_PORT_SHIFT,        \
+                OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP3UART##p)
+
+#define DEBUG_LL_OMAP4(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP4_UART1_BASE, OMAP_PORT_SHIFT,        \
+                OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP4UART##p)
+
+/* Zoom2/3 shift is different for UART1 and external port */
+#define DEBUG_LL_ZOOM(mach)                                             \
+        _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT,        \
+                ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
+
+static inline void __arch_decomp_setup(unsigned long arch_id)
+{
+        int port = 0;
+
+        /*
+         * Initialize the port based on the machine ID from the bootloader.
+         * Note that we're using macros here instead of switch statement
+         * as machine_is functions are optimized out for the boards that
+         * are not selected.
+         */
+        do {
+                /* omap7xx/8xx based boards using UART1 with shift 0 */
+                DEBUG_LL_OMAP7XX(1, herald);
+                DEBUG_LL_OMAP7XX(1, omap_perseus2);
+
+                /* omap15xx/16xx based boards using UART1 */
+                DEBUG_LL_OMAP1(1, ams_delta);
+                DEBUG_LL_OMAP1(1, nokia770);
+                DEBUG_LL_OMAP1(1, omap_h2);
+                DEBUG_LL_OMAP1(1, omap_h3);
+                DEBUG_LL_OMAP1(1, omap_innovator);
+                DEBUG_LL_OMAP1(1, omap_osk);
+                DEBUG_LL_OMAP1(1, omap_palmte);
+                DEBUG_LL_OMAP1(1, omap_palmz71);
+
+                /* omap15xx/16xx based boards using UART2 */
+                DEBUG_LL_OMAP1(2, omap_palmtt);
+
+                /* omap15xx/16xx based boards using UART3 */
+                DEBUG_LL_OMAP1(3, sx1);
+
+                /* omap2 based boards using UART1 */
+                DEBUG_LL_OMAP2(1, omap2evm);
+                DEBUG_LL_OMAP2(1, omap_2430sdp);
+                DEBUG_LL_OMAP2(1, omap_apollon);
+                DEBUG_LL_OMAP2(1, omap_h4);
+
+                /* omap2 based boards using UART3 */
+                DEBUG_LL_OMAP2(3, nokia_n800);
+                DEBUG_LL_OMAP2(3, nokia_n810);
+                DEBUG_LL_OMAP2(3, nokia_n810_wimax);
+
+                /* omap3 based boards using UART1 */
+                DEBUG_LL_OMAP2(1, omap3evm);
+                DEBUG_LL_OMAP3(1, omap_3430sdp);
+                DEBUG_LL_OMAP3(1, omap_3630sdp);
+
+                /* omap3 based boards using UART3 */
+                DEBUG_LL_OMAP3(3, cm_t35);
+                DEBUG_LL_OMAP3(3, igep0020);
+                DEBUG_LL_OMAP3(3, nokia_rx51);
+                DEBUG_LL_OMAP3(3, omap3517evm);
+                DEBUG_LL_OMAP3(3, omap3_beagle);
+                DEBUG_LL_OMAP3(3, omap3_pandora);
+                DEBUG_LL_OMAP3(3, omap_ldp);
+                DEBUG_LL_OMAP3(3, overo);
+                DEBUG_LL_OMAP3(3, touchbook);
+
+                /* omap4 based boards using UART3 */
+                DEBUG_LL_OMAP4(3, omap_4430sdp);
+
+                /* zoom2/3 external uart */
+                DEBUG_LL_ZOOM(omap_zoom2);
+                DEBUG_LL_ZOOM(omap_zoom3);
+
+        } while (0);
+}
+
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+
+/*
  * nothing to do
  */
-#define arch_decomp_setup()
 #define arch_decomp_wdog()
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 33a500eb2f93..288e29e1c06f 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -3,6 +3,7 @@
 #ifndef __ASM_ARCH_OMAP_USB_H
 #define __ASM_ARCH_OMAP_USB_H
 
+#include <linux/usb/musb.h>
 #include <plat/board.h>
 
 #define OMAP3_HS_USB_PORTS      3
@@ -42,7 +43,15 @@ struct ehci_hcd_omap_platform_data {
 #define UDC_BASE                        OMAP2_UDC_BASE
 #define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
 
-extern void usb_musb_init(void);
+struct omap_musb_board_data {
+        u8      interface_type;
+        u8      mode;
+        u8      power;
+};
+
+enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
+
+extern void usb_musb_init(struct omap_musb_board_data *board_data);
 
 extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
 
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index 11f5d7961c73..b0078cf96281 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -66,12 +66,12 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                         return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
         }
         if (cpu_is_omap2420()) {
-                if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
-                        return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
-                if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
-                        return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE);
-                if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
-                        return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
+                if (BETWEEN(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_SIZE))
+                        return XLATE(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_VIRT);
+                if (BETWEEN(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE))
+                        return XLATE(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE);
+                if (BETWEEN(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_SIZE))
+                        return XLATE(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_VIRT);
         }
         if (cpu_is_omap2430()) {
                 if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
@@ -90,8 +90,6 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                         return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
                 if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
                         return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
-                if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
-                        return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
                 if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
                         return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
                 if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
@@ -110,8 +108,6 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                         return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT);
                 if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE))
                         return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT);
-                if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE))
-                        return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
                 if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
                         return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
                 if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE))
@@ -128,7 +124,7 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                         return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
         }
 #endif
-        return __arm_ioremap(p, size, type);
+        return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
 }
 EXPORT_SYMBOL(omap_ioremap);
 
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index c0ff1e39d893..905ed832df56 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -1,7 +1,7 @@
 /*
  * omap iommu: tlb and pagetable primitives
  *
- * Copyright (C) 2008-2009 Nokia Corporation
+ * Copyright (C) 2008-2010 Nokia Corporation
  *
  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
  *              Paul Mundt and Toshihiro Kobayashi
@@ -646,7 +646,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
                 if (*iopte & IOPTE_LARGE) {
                         nent *= 16;
                         /* rewind to the 1st entry */
-                        iopte = (u32 *)((u32)iopte & IOLARGE_MASK);
+                        iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
                 }
                 bytes *= nent;
                 memset(iopte, 0, nent * sizeof(*iopte));
@@ -667,7 +667,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
                 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
                         nent *= 16;
                         /* rewind to the 1st entry */
-                        iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK);
+                        iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
                 }
                 bytes *= nent;
         }
@@ -827,7 +827,7 @@ EXPORT_SYMBOL_GPL(iommu_get);
  **/
 void iommu_put(struct iommu *obj)
 {
-        if (!obj && IS_ERR(obj))
+        if (!obj || IS_ERR(obj))
                 return;
 
         mutex_lock(&obj->iommu_lock);
diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h
index 37dac434c7a1..ab23b6a140fd 100644
--- a/arch/arm/plat-omap/iopgtable.h
+++ b/arch/arm/plat-omap/iopgtable.h
@@ -1,7 +1,7 @@
 /*
  * omap iommu: pagetable definitions
  *
- * Copyright (C) 2008-2009 Nokia Corporation
+ * Copyright (C) 2008-2010 Nokia Corporation
  *
  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
  *
@@ -13,26 +13,52 @@
 #ifndef __PLAT_OMAP_IOMMU_H
 #define __PLAT_OMAP_IOMMU_H
 
+/*
+ * "L2 table" address mask and size definitions.
+ */
 #define IOPGD_SHIFT             20
-#define IOPGD_SIZE              (1 << IOPGD_SHIFT)
+#define IOPGD_SIZE              (1UL << IOPGD_SHIFT)
 #define IOPGD_MASK              (~(IOPGD_SIZE - 1))
-#define IOSECTION_MASK          IOPGD_MASK
-#define PTRS_PER_IOPGD          (1 << (32 - IOPGD_SHIFT))
-#define IOPGD_TABLE_SIZE        (PTRS_PER_IOPGD * sizeof(u32))
 
-#define IOSUPER_SIZE            (IOPGD_SIZE << 4)
+/*
+ * "section" address mask and size definitions.
+ */
+#define IOSECTION_SHIFT         20
+#define IOSECTION_SIZE          (1UL << IOSECTION_SHIFT)
+#define IOSECTION_MASK          (~(IOSECTION_SIZE - 1))
+
+/*
+ * "supersection" address mask and size definitions.
+ */
+#define IOSUPER_SHIFT           24
+#define IOSUPER_SIZE            (1UL << IOSUPER_SHIFT)
 #define IOSUPER_MASK            (~(IOSUPER_SIZE - 1))
 
+#define PTRS_PER_IOPGD          (1UL << (32 - IOPGD_SHIFT))
+#define IOPGD_TABLE_SIZE        (PTRS_PER_IOPGD * sizeof(u32))
+
+/*
+ * "small page" address mask and size definitions.
+ */
 #define IOPTE_SHIFT             12
-#define IOPTE_SIZE              (1 << IOPTE_SHIFT)
+#define IOPTE_SIZE              (1UL << IOPTE_SHIFT)
 #define IOPTE_MASK              (~(IOPTE_SIZE - 1))
-#define IOPAGE_MASK             IOPTE_MASK
-#define PTRS_PER_IOPTE          (1 << (IOPGD_SHIFT - IOPTE_SHIFT))
-#define IOPTE_TABLE_SIZE        (PTRS_PER_IOPTE * sizeof(u32))
 
-#define IOLARGE_SIZE            (IOPTE_SIZE << 4)
+/*
+ * "large page" address mask and size definitions.
+ */
+#define IOLARGE_SHIFT           16
+#define IOLARGE_SIZE            (1UL << IOLARGE_SHIFT)
 #define IOLARGE_MASK            (~(IOLARGE_SIZE - 1))
 
+#define PTRS_PER_IOPTE          (1UL << (IOPGD_SHIFT - IOPTE_SHIFT))
+#define IOPTE_TABLE_SIZE        (PTRS_PER_IOPTE * sizeof(u32))
+
+#define IOPAGE_MASK             IOPTE_MASK
+
+/*
+ * some descriptor attributes.
+ */
 #define IOPGD_TABLE             (1 << 0)
 #define IOPGD_SECTION           (2 << 0)
 #define IOPGD_SUPER             (1 << 18 | 2 << 0)
@@ -40,12 +66,14 @@
 #define IOPTE_SMALL             (2 << 0)
 #define IOPTE_LARGE             (1 << 0)
 
+/* to find an entry in a page-table-directory */
 #define iopgd_index(da)         (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
 #define iopgd_offset(obj, da)   ((obj)->iopgd + iopgd_index(da))
 
 #define iopte_paddr(iopgd)      (*iopgd & ~((1 << 10) - 1))
 #define iopte_vaddr(iopgd)      ((u32 *)phys_to_virt(iopte_paddr(iopgd)))
 
+/* to find an entry in the second-level page table. */
 #define iopte_index(da)         (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
 #define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da))
 
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 8e90633e4cb9..4229cec53140 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -28,6 +28,7 @@
 
 #include <plat/mailbox.h>
 
+static struct workqueue_struct *mboxd;
 static struct omap_mbox *mboxes;
 static DEFINE_RWLOCK(mboxes_lock);
 
@@ -188,7 +189,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
         /* no more messages in the fifo. clear IRQ source. */
         ack_mbox_irq(mbox, IRQ_RX);
 nomem:
-        schedule_work(&mbox->rxq->work);
+        queue_work(mboxd, &mbox->rxq->work);
 }
 
 static irqreturn_t mbox_interrupt(int irq, void *p)
@@ -401,12 +402,17 @@ EXPORT_SYMBOL(omap_mbox_unregister);
 
 static int __init omap_mbox_init(void)
 {
+        mboxd = create_workqueue("mboxd");
+        if (!mboxd)
+                return -ENOMEM;
+
         return 0;
 }
 module_init(omap_mbox_init);
 
 static void __exit omap_mbox_exit(void)
 {
+        destroy_workqueue(mboxd);
 }
 module_exit(omap_mbox_exit);
 
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 2cc1cc328bac..e47686e0a633 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -27,64 +27,97 @@
 #include <plat/dma.h>
 #include <plat/mcbsp.h>
 
+#include "../mach-omap2/cm-regbits-34xx.h"
+
 struct omap_mcbsp **mcbsp_ptr;
-int omap_mcbsp_count;
+int omap_mcbsp_count, omap_mcbsp_cache_size;
 
-void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
+void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 {
-        if (cpu_class_is_omap1() || cpu_is_omap2420())
-                __raw_writew((u16)val, io_base + reg);
-        else
-                __raw_writel(val, io_base + reg);
+        if (cpu_class_is_omap1()) {
+                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
+                __raw_writew((u16)val, mcbsp->io_base + reg);
+        } else if (cpu_is_omap2420()) {
+                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
+                __raw_writew((u16)val, mcbsp->io_base + reg);
+        } else {
+                ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
+                __raw_writel(val, mcbsp->io_base + reg);
+        }
 }
 
-int omap_mcbsp_read(void __iomem *io_base, u16 reg)
+int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
 {
-        if (cpu_class_is_omap1() || cpu_is_omap2420())
-                return __raw_readw(io_base + reg);
-        else
-                return __raw_readl(io_base + reg);
+        if (cpu_class_is_omap1()) {
+                return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
+                                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
+        } else if (cpu_is_omap2420()) {
+                return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
+                                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
+        } else {
+                return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
+                                ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
+        }
+}
+
+#ifdef CONFIG_ARCH_OMAP3
+void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
+{
+        __raw_writel(val, mcbsp->st_data->io_base_st + reg);
 }
 
-#define OMAP_MCBSP_READ(base, reg) \
-                        omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
-#define OMAP_MCBSP_WRITE(base, reg, val) \
-                        omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
+int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
+{
+        return __raw_readl(mcbsp->st_data->io_base_st + reg);
+}
+#endif
+
+#define MCBSP_READ(mcbsp, reg) \
+                omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
+#define MCBSP_WRITE(mcbsp, reg, val) \
+                omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
+#define MCBSP_READ_CACHE(mcbsp, reg) \
+                omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
 
 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 
+#define MCBSP_ST_READ(mcbsp, reg) \
+                        omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
+#define MCBSP_ST_WRITE(mcbsp, reg, val) \
+                        omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
+
 static void omap_mcbsp_dump_reg(u8 id)
 {
         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
 
         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
+                        MCBSP_READ(mcbsp, DRR2));
         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
+                        MCBSP_READ(mcbsp, DRR1));
         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
+                        MCBSP_READ(mcbsp, DXR2));
         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
+                        MCBSP_READ(mcbsp, DXR1));
         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
+                        MCBSP_READ(mcbsp, SPCR2));
         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
+                        MCBSP_READ(mcbsp, SPCR1));
         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
+                        MCBSP_READ(mcbsp, RCR2));
         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
+                        MCBSP_READ(mcbsp, RCR1));
         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
+                        MCBSP_READ(mcbsp, XCR2));
         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
+                        MCBSP_READ(mcbsp, XCR1));
         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
+                        MCBSP_READ(mcbsp, SRGR2));
         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
+                        MCBSP_READ(mcbsp, SRGR1));
         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
-                        OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
+                        MCBSP_READ(mcbsp, PCR0));
         dev_dbg(mcbsp->dev, "***********************\n");
 }
 
@@ -93,15 +126,15 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
         struct omap_mcbsp *mcbsp_tx = dev_id;
         u16 irqst_spcr2;
 
-        irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
+        irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 
         if (irqst_spcr2 & XSYNC_ERR) {
                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
                         irqst_spcr2);
                 /* Writing zero to XSYNC_ERR clears the IRQ */
-                OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
-                        irqst_spcr2 & ~(XSYNC_ERR));
+                MCBSP_WRITE(mcbsp_tx, SPCR2,
+                            MCBSP_READ_CACHE(mcbsp_tx, SPCR2) & ~(XSYNC_ERR));
         } else {
                 complete(&mcbsp_tx->tx_irq_completion);
         }
@@ -114,15 +147,15 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
         struct omap_mcbsp *mcbsp_rx = dev_id;
         u16 irqst_spcr1;
 
-        irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
+        irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 
         if (irqst_spcr1 & RSYNC_ERR) {
                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
                         irqst_spcr1);
                 /* Writing zero to RSYNC_ERR clears the IRQ */
-                OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
-                        irqst_spcr1 & ~(RSYNC_ERR));
+                MCBSP_WRITE(mcbsp_rx, SPCR1,
+                            MCBSP_READ_CACHE(mcbsp_rx, SPCR1) & ~(RSYNC_ERR));
         } else {
                 complete(&mcbsp_rx->tx_irq_completion);
         }
@@ -135,7 +168,7 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
         struct omap_mcbsp *mcbsp_dma_tx = data;
 
         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
-                OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
+                MCBSP_READ(mcbsp_dma_tx, SPCR2));
 
         /* We can free the channels */
         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
@@ -149,7 +182,7 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
         struct omap_mcbsp *mcbsp_dma_rx = data;
 
         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
-                OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
+                MCBSP_READ(mcbsp_dma_rx, SPCR2));
 
         /* We can free the channels */
         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
@@ -167,7 +200,6 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
 
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -175,30 +207,280 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
-        io_base = mcbsp->io_base;
         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
                         mcbsp->id, mcbsp->phys_base);
 
         /* We write the given config */
-        OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
-        OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
-        OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
-        OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
-        OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
-        OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
-        OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
-        OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
-        OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
-        OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
-        OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
+        MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
+        MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
+        MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
+        MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
+        MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
+        MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
+        MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
+        MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
+        MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
+        MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
+        MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
-                OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
+                MCBSP_WRITE(mcbsp, XCCR, config->xccr);
+                MCBSP_WRITE(mcbsp, RCCR, config->rccr);
         }
 }
 EXPORT_SYMBOL(omap_mcbsp_config);
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
+static void omap_st_on(struct omap_mcbsp *mcbsp)
+{
+        unsigned int w;
+
+        /*
+         * Sidetone uses McBSP ICLK - which must not idle when sidetones
+         * are enabled or sidetones start sounding ugly.
+         */
+        w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        w &= ~(1 << (mcbsp->id - 2));
+        cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+
+        /* Enable McBSP Sidetone */
+        w = MCBSP_READ(mcbsp, SSELCR);
+        MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
+
+        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
+
+        /* Enable Sidetone from Sidetone Core */
+        w = MCBSP_ST_READ(mcbsp, SSELCR);
+        MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
+}
+
+static void omap_st_off(struct omap_mcbsp *mcbsp)
+{
+        unsigned int w;
+
+        w = MCBSP_ST_READ(mcbsp, SSELCR);
+        MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
+
+        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
+
+        w = MCBSP_READ(mcbsp, SSELCR);
+        MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
+
+        w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        w |= 1 << (mcbsp->id - 2);
+        cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+}
+
+static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
+{
+        u16 val, i;
+
+        val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
+
+        val = MCBSP_ST_READ(mcbsp, SSELCR);
+
+        if (val & ST_COEFFWREN)
+                MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
+
+        MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
+
+        for (i = 0; i < 128; i++)
+                MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
+
+        i = 0;
+
+        val = MCBSP_ST_READ(mcbsp, SSELCR);
+        while (!(val & ST_COEFFWRDONE) && (++i < 1000))
+                val = MCBSP_ST_READ(mcbsp, SSELCR);
+
+        MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
+
+        if (i == 1000)
+                dev_err(mcbsp->dev, "McBSP FIR load error!\n");
+}
+
+static void omap_st_chgain(struct omap_mcbsp *mcbsp)
+{
+        u16 w;
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+
+        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
+
+        w = MCBSP_ST_READ(mcbsp, SSELCR);
+
+        MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
+                      ST_CH1GAIN(st_data->ch1gain));
+}
+
+int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
+{
+        struct omap_mcbsp *mcbsp;
+        struct omap_mcbsp_st_data *st_data;
+        int ret = 0;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        mcbsp = id_to_mcbsp_ptr(id);
+        st_data = mcbsp->st_data;
+
+        if (!st_data)
+                return -ENOENT;
+
+        spin_lock_irq(&mcbsp->lock);
+        if (channel == 0)
+                st_data->ch0gain = chgain;
+        else if (channel == 1)
+                st_data->ch1gain = chgain;
+        else
+                ret = -EINVAL;
+
+        if (st_data->enabled)
+                omap_st_chgain(mcbsp);
+        spin_unlock_irq(&mcbsp->lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(omap_st_set_chgain);
+
+int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
+{
+        struct omap_mcbsp *mcbsp;
+        struct omap_mcbsp_st_data *st_data;
+        int ret = 0;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        mcbsp = id_to_mcbsp_ptr(id);
+        st_data = mcbsp->st_data;
+
+        if (!st_data)
+                return -ENOENT;
+
+        spin_lock_irq(&mcbsp->lock);
+        if (channel == 0)
+                *chgain = st_data->ch0gain;
+        else if (channel == 1)
+                *chgain = st_data->ch1gain;
+        else
+                ret = -EINVAL;
+        spin_unlock_irq(&mcbsp->lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(omap_st_get_chgain);
+
+static int omap_st_start(struct omap_mcbsp *mcbsp)
+{
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+
+        if (st_data && st_data->enabled && !st_data->running) {
+                omap_st_fir_write(mcbsp, st_data->taps);
+                omap_st_chgain(mcbsp);
+
+                if (!mcbsp->free) {
+                        omap_st_on(mcbsp);
+                        st_data->running = 1;
+                }
+        }
+
+        return 0;
+}
+
+int omap_st_enable(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        struct omap_mcbsp_st_data *st_data;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        mcbsp = id_to_mcbsp_ptr(id);
+        st_data = mcbsp->st_data;
+
+        if (!st_data)
+                return -ENODEV;
+
+        spin_lock_irq(&mcbsp->lock);
+        st_data->enabled = 1;
+        omap_st_start(mcbsp);
+        spin_unlock_irq(&mcbsp->lock);
+
+        return 0;
+}
+EXPORT_SYMBOL(omap_st_enable);
+
+static int omap_st_stop(struct omap_mcbsp *mcbsp)
+{
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+
+        if (st_data && st_data->running) {
+                if (!mcbsp->free) {
+                        omap_st_off(mcbsp);
+                        st_data->running = 0;
+                }
+        }
+
+        return 0;
+}
+
+int omap_st_disable(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        struct omap_mcbsp_st_data *st_data;
+        int ret = 0;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        mcbsp = id_to_mcbsp_ptr(id);
+        st_data = mcbsp->st_data;
+
+        if (!st_data)
+                return -ENODEV;
+
+        spin_lock_irq(&mcbsp->lock);
+        omap_st_stop(mcbsp);
+        st_data->enabled = 0;
+        spin_unlock_irq(&mcbsp->lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(omap_st_disable);
+
+int omap_st_is_enabled(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        struct omap_mcbsp_st_data *st_data;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        mcbsp = id_to_mcbsp_ptr(id);
+        st_data = mcbsp->st_data;
+
+        if (!st_data)
+                return -ENODEV;
+
+
+        return st_data->enabled;
+}
+EXPORT_SYMBOL(omap_st_is_enabled);
+
 /*
  * omap_mcbsp_set_tx_threshold configures how to deal
  * with transmit threshold. the threshold value and handler can be
@@ -207,7 +489,6 @@ EXPORT_SYMBOL(omap_mcbsp_config);
 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
 
         if (!cpu_is_omap34xx())
                 return;
@@ -217,9 +498,8 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
                 return;
         }
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
 
-        OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
+        MCBSP_WRITE(mcbsp, THRSH2, threshold);
 }
 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 
@@ -231,7 +511,6 @@ EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
 
         if (!cpu_is_omap34xx())
                 return;
@@ -241,9 +520,8 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
                 return;
         }
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
 
-        OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
+        MCBSP_WRITE(mcbsp, THRSH1, threshold);
 }
 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 
@@ -313,19 +591,18 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
         if (cpu_is_omap34xx()) {
                 u16 syscon;
 
-                syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
+                syscon = MCBSP_READ(mcbsp, SYSCON);
                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 
                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
                                         CLOCKACTIVITY(0x02));
-                        OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
-                                        XRDYEN | RRDYEN);
+                        MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
                 } else {
                         syscon |= SIDLEMODE(0x01);
                 }
 
-                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+                MCBSP_WRITE(mcbsp, SYSCON, syscon);
         }
 }
 
@@ -337,7 +614,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
         if (cpu_is_omap34xx()) {
                 u16 syscon;
 
-                syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
+                syscon = MCBSP_READ(mcbsp, SYSCON);
                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
                 /*
                  * HW bug workaround - If no_idle mode is taken, we need to
@@ -345,17 +622,19 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
                  * device will not hit retention anymore.
                  */
                 syscon |= SIDLEMODE(0x02);
-                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+                MCBSP_WRITE(mcbsp, SYSCON, syscon);
 
                 syscon &= ~(SIDLEMODE(0x03));
-                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+                MCBSP_WRITE(mcbsp, SYSCON, syscon);
 
-                OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
+                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
         }
 }
 #else
 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
+static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
+static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 #endif
 
 /*
@@ -392,6 +671,7 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 int omap_mcbsp_request(unsigned int id)
 {
         struct omap_mcbsp *mcbsp;
+        void *reg_cache;
         int err;
 
         if (!omap_mcbsp_check_valid_id(id)) {
@@ -400,15 +680,21 @@ int omap_mcbsp_request(unsigned int id)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
+        reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
+        if (!reg_cache) {
+                return -ENOMEM;
+        }
+
         spin_lock(&mcbsp->lock);
         if (!mcbsp->free) {
                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
                         mcbsp->id);
-                spin_unlock(&mcbsp->lock);
-                return -EBUSY;
+                err = -EBUSY;
+                goto err_kfree;
         }
 
         mcbsp->free = 0;
+        mcbsp->reg_cache = reg_cache;
         spin_unlock(&mcbsp->lock);
 
         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
@@ -424,8 +710,8 @@ int omap_mcbsp_request(unsigned int id)
          * Make sure that transmitter, receiver and sample-rate generator are
          * not running before activating IRQs.
          */
-        OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
-        OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
+        MCBSP_WRITE(mcbsp, SPCR1, 0);
+        MCBSP_WRITE(mcbsp, SPCR2, 0);
 
         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
                 /* We need to get IRQs here */
@@ -436,7 +722,7 @@ int omap_mcbsp_request(unsigned int id)
                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
                                         "for McBSP%d\n", mcbsp->tx_irq,
                                         mcbsp->id);
-                        return err;
+                        goto err_clk_disable;
                 }
 
                 init_completion(&mcbsp->rx_irq_completion);
@@ -446,18 +732,38 @@ int omap_mcbsp_request(unsigned int id)
                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
                                         "for McBSP%d\n", mcbsp->rx_irq,
                                         mcbsp->id);
-                        free_irq(mcbsp->tx_irq, (void *)mcbsp);
-                        return err;
+                        goto err_free_irq;
                 }
         }
 
         return 0;
+err_free_irq:
+        free_irq(mcbsp->tx_irq, (void *)mcbsp);
+err_clk_disable:
+        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
+                mcbsp->pdata->ops->free(id);
+
+        /* Do procedure specific to omap34xx arch, if applicable */
+        omap34xx_mcbsp_free(mcbsp);
+
+        clk_disable(mcbsp->fclk);
+        clk_disable(mcbsp->iclk);
+
+        spin_lock(&mcbsp->lock);
+        mcbsp->free = 1;
+        mcbsp->reg_cache = NULL;
+err_kfree:
+        spin_unlock(&mcbsp->lock);
+        kfree(reg_cache);
+
+        return err;
 }
 EXPORT_SYMBOL(omap_mcbsp_request);
 
 void omap_mcbsp_free(unsigned int id)
 {
         struct omap_mcbsp *mcbsp;
+        void *reg_cache;
 
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -480,16 +786,18 @@ void omap_mcbsp_free(unsigned int id)
                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
         }
 
-        spin_lock(&mcbsp->lock);
-        if (mcbsp->free) {
-                dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
-                        mcbsp->id);
-                spin_unlock(&mcbsp->lock);
-                return;
-        }
+        reg_cache = mcbsp->reg_cache;
 
-        mcbsp->free = 1;
+        spin_lock(&mcbsp->lock);
+        if (mcbsp->free)
+                dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
+        else
+                mcbsp->free = 1;
+        mcbsp->reg_cache = NULL;
         spin_unlock(&mcbsp->lock);
+
+        if (reg_cache)
+                kfree(reg_cache);
 }
 EXPORT_SYMBOL(omap_mcbsp_free);
 
@@ -501,7 +809,6 @@ EXPORT_SYMBOL(omap_mcbsp_free);
 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
         int idle;
         u16 w;
 
@@ -510,28 +817,30 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
                 return;
         }
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
 
-        mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
-        mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
+        if (cpu_is_omap34xx())
+                omap_st_start(mcbsp);
+
+        mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
+        mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
 
-        idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
-                  OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
+        idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
+                        MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 
         if (idle) {
                 /* Start the sample generator */
-                w = OMAP_MCBSP_READ(io_base, SPCR2);
-                OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
+                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
+                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
         }
 
         /* Enable transmitter and receiver */
         tx &= 1;
-        w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx);
+        w = MCBSP_READ_CACHE(mcbsp, SPCR2);
+        MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 
         rx &= 1;
-        w = OMAP_MCBSP_READ(io_base, SPCR1);
-        OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx);
+        w = MCBSP_READ_CACHE(mcbsp, SPCR1);
+        MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 
         /*
          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
@@ -543,18 +852,18 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
 
         if (idle) {
                 /* Start frame sync */
-                w = OMAP_MCBSP_READ(io_base, SPCR2);
-                OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
+                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
+                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
         }
 
         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
                 /* Release the transmitter and receiver */
-                w = OMAP_MCBSP_READ(io_base, XCCR);
+                w = MCBSP_READ_CACHE(mcbsp, XCCR);
                 w &= ~(tx ? XDISABLE : 0);
-                OMAP_MCBSP_WRITE(io_base, XCCR, w);
-                w = OMAP_MCBSP_READ(io_base, RCCR);
+                MCBSP_WRITE(mcbsp, XCCR, w);
+                w = MCBSP_READ_CACHE(mcbsp, RCCR);
                 w &= ~(rx ? RDISABLE : 0);
-                OMAP_MCBSP_WRITE(io_base, RCCR, w);
+                MCBSP_WRITE(mcbsp, RCCR, w);
         }
 
         /* Dump McBSP Regs */
@@ -565,7 +874,6 @@ EXPORT_SYMBOL(omap_mcbsp_start);
 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
         int idle;
         u16 w;
 
@@ -575,36 +883,38 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
         }
 
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
 
         /* Reset transmitter */
         tx &= 1;
         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
-                w = OMAP_MCBSP_READ(io_base, XCCR);
+                w = MCBSP_READ_CACHE(mcbsp, XCCR);
                 w |= (tx ? XDISABLE : 0);
-                OMAP_MCBSP_WRITE(io_base, XCCR, w);
+                MCBSP_WRITE(mcbsp, XCCR, w);
         }
-        w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx);
+        w = MCBSP_READ_CACHE(mcbsp, SPCR2);
+        MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 
         /* Reset receiver */
         rx &= 1;
         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
-                w = OMAP_MCBSP_READ(io_base, RCCR);
+                w = MCBSP_READ_CACHE(mcbsp, RCCR);
                 w |= (rx ? RDISABLE : 0);
-                OMAP_MCBSP_WRITE(io_base, RCCR, w);
+                MCBSP_WRITE(mcbsp, RCCR, w);
         }
-        w = OMAP_MCBSP_READ(io_base, SPCR1);
-        OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx);
+        w = MCBSP_READ_CACHE(mcbsp, SPCR1);
+        MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 
-        idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
-                  OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
+        idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
+                        MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 
         if (idle) {
                 /* Reset the sample rate generator */
-                w = OMAP_MCBSP_READ(io_base, SPCR2);
-                OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
+                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
+                MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
         }
+
+        if (cpu_is_omap34xx())
+                omap_st_stop(mcbsp);
 }
 EXPORT_SYMBOL(omap_mcbsp_stop);
 
@@ -612,7 +922,6 @@ EXPORT_SYMBOL(omap_mcbsp_stop);
 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *base;
 
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -620,28 +929,27 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
         }
 
         mcbsp = id_to_mcbsp_ptr(id);
-        base = mcbsp->io_base;
 
-        writew(buf, base + OMAP_MCBSP_REG_DXR1);
+        MCBSP_WRITE(mcbsp, DXR1, buf);
         /* if frame sync error - clear the error */
-        if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
+        if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
                 /* clear error */
-                writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
-                       base + OMAP_MCBSP_REG_SPCR2);
+                MCBSP_WRITE(mcbsp, SPCR2,
+                                MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XSYNC_ERR));
                 /* resend */
                 return -1;
         } else {
                 /* wait for transmit confirmation */
                 int attemps = 0;
-                while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
+                while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
                         if (attemps++ > 1000) {
-                                writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
-                                       (~XRST),
-                                       base + OMAP_MCBSP_REG_SPCR2);
+                                MCBSP_WRITE(mcbsp, SPCR2,
+                                                MCBSP_READ_CACHE(mcbsp, SPCR2) &
+                                                (~XRST));
                                 udelay(10);
-                                writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
-                                       (XRST),
-                                       base + OMAP_MCBSP_REG_SPCR2);
+                                MCBSP_WRITE(mcbsp, SPCR2,
+                                                MCBSP_READ_CACHE(mcbsp, SPCR2) |
+                                                (XRST));
                                 udelay(10);
                                 dev_err(mcbsp->dev, "Could not write to"
                                         " McBSP%d Register\n", mcbsp->id);
@@ -657,7 +965,6 @@ EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *base;
 
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -665,26 +972,25 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
-        base = mcbsp->io_base;
         /* if frame sync error - clear the error */
-        if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
+        if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
                 /* clear error */
-                writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
-                       base + OMAP_MCBSP_REG_SPCR1);
+                MCBSP_WRITE(mcbsp, SPCR1,
+                                MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RSYNC_ERR));
                 /* resend */
                 return -1;
         } else {
                 /* wait for recieve confirmation */
                 int attemps = 0;
-                while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
+                while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
                         if (attemps++ > 1000) {
-                                writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
-                                       (~RRST),
-                                       base + OMAP_MCBSP_REG_SPCR1);
+                                MCBSP_WRITE(mcbsp, SPCR1,
+                                                MCBSP_READ_CACHE(mcbsp, SPCR1) &
+                                                (~RRST));
                                 udelay(10);
-                                writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
-                                       (RRST),
-                                       base + OMAP_MCBSP_REG_SPCR1);
+                                MCBSP_WRITE(mcbsp, SPCR1,
+                                                MCBSP_READ_CACHE(mcbsp, SPCR1) |
+                                                (RRST));
                                 udelay(10);
                                 dev_err(mcbsp->dev, "Could not read from"
                                         " McBSP%d Register\n", mcbsp->id);
@@ -692,7 +998,7 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
                         }
                 }
         }
-        *buf = readw(base + OMAP_MCBSP_REG_DRR1);
+        *buf = MCBSP_READ(mcbsp, DRR1);
 
         return 0;
 }
@@ -704,7 +1010,6 @@ EXPORT_SYMBOL(omap_mcbsp_pollread);
 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
         omap_mcbsp_word_length word_length;
 
         if (!omap_mcbsp_check_valid_id(id)) {
@@ -713,21 +1018,19 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word)
         }
 
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
         word_length = mcbsp->tx_word_length;
 
         wait_for_completion(&mcbsp->tx_irq_completion);
 
         if (word_length > OMAP_MCBSP_WORD_16)
-                OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
-        OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
+                MCBSP_WRITE(mcbsp, DXR2, word >> 16);
+        MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
 }
 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 
 u32 omap_mcbsp_recv_word(unsigned int id)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
         u16 word_lsb, word_msb = 0;
         omap_mcbsp_word_length word_length;
 
@@ -738,13 +1041,12 @@ u32 omap_mcbsp_recv_word(unsigned int id)
         mcbsp = id_to_mcbsp_ptr(id);
 
         word_length = mcbsp->rx_word_length;
-        io_base = mcbsp->io_base;
 
         wait_for_completion(&mcbsp->rx_irq_completion);
 
         if (word_length > OMAP_MCBSP_WORD_16)
-                word_msb = OMAP_MCBSP_READ(io_base, DRR2);
-        word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
+                word_msb = MCBSP_READ(mcbsp, DRR2);
+        word_lsb = MCBSP_READ(mcbsp, DRR1);
 
         return (word_lsb | (word_msb << 16));
 }
@@ -753,7 +1055,6 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word);
 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 {
         struct omap_mcbsp *mcbsp;
-        void __iomem *io_base;
         omap_mcbsp_word_length tx_word_length;
         omap_mcbsp_word_length rx_word_length;
         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
@@ -763,7 +1064,6 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
                 return -ENODEV;
         }
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
         tx_word_length = mcbsp->tx_word_length;
         rx_word_length = mcbsp->rx_word_length;
 
@@ -771,14 +1071,16 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
                 return -EINVAL;
 
         /* First we wait for the transmitter to be ready */
-        spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
+        spcr2 = MCBSP_READ(mcbsp, SPCR2);
         while (!(spcr2 & XRDY)) {
-                spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
+                spcr2 = MCBSP_READ(mcbsp, SPCR2);
                 if (attempts++ > 1000) {
                         /* We must reset the transmitter */
-                        OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
+                        MCBSP_WRITE(mcbsp, SPCR2,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
                         udelay(10);
-                        OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
+                        MCBSP_WRITE(mcbsp, SPCR2,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
                         udelay(10);
                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
                                 "ready\n", mcbsp->id);
@@ -788,18 +1090,20 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 
         /* Now we can push the data */
         if (tx_word_length > OMAP_MCBSP_WORD_16)
-                OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
-        OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
+                MCBSP_WRITE(mcbsp, DXR2, word >> 16);
+        MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
 
         /* We wait for the receiver to be ready */
-        spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
+        spcr1 = MCBSP_READ(mcbsp, SPCR1);
         while (!(spcr1 & RRDY)) {
-                spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
+                spcr1 = MCBSP_READ(mcbsp, SPCR1);
                 if (attempts++ > 1000) {
                         /* We must reset the receiver */
-                        OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
+                        MCBSP_WRITE(mcbsp, SPCR1,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
                         udelay(10);
-                        OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
+                        MCBSP_WRITE(mcbsp, SPCR1,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
                         udelay(10);
                         dev_err(mcbsp->dev, "McBSP%d receiver not "
                                 "ready\n", mcbsp->id);
@@ -809,8 +1113,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 
         /* Receiver is ready, let's read the dummy data */
         if (rx_word_length > OMAP_MCBSP_WORD_16)
-                word_msb = OMAP_MCBSP_READ(io_base, DRR2);
-        word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
+                word_msb = MCBSP_READ(mcbsp, DRR2);
+        word_lsb = MCBSP_READ(mcbsp, DRR1);
 
         return 0;
 }
@@ -820,7 +1124,6 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 {
         struct omap_mcbsp *mcbsp;
         u32 clock_word = 0;
-        void __iomem *io_base;
         omap_mcbsp_word_length tx_word_length;
         omap_mcbsp_word_length rx_word_length;
         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
@@ -831,7 +1134,6 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
         }
 
         mcbsp = id_to_mcbsp_ptr(id);
-        io_base = mcbsp->io_base;
 
         tx_word_length = mcbsp->tx_word_length;
         rx_word_length = mcbsp->rx_word_length;
@@ -840,14 +1142,16 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
                 return -EINVAL;
 
         /* First we wait for the transmitter to be ready */
-        spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
+        spcr2 = MCBSP_READ(mcbsp, SPCR2);
         while (!(spcr2 & XRDY)) {
-                spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
+                spcr2 = MCBSP_READ(mcbsp, SPCR2);
                 if (attempts++ > 1000) {
                         /* We must reset the transmitter */
-                        OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
+                        MCBSP_WRITE(mcbsp, SPCR2,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
                         udelay(10);
-                        OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
+                        MCBSP_WRITE(mcbsp, SPCR2,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
                         udelay(10);
                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
                                 "ready\n", mcbsp->id);
@@ -857,18 +1161,20 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 
         /* We first need to enable the bus clock */
         if (tx_word_length > OMAP_MCBSP_WORD_16)
-                OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
-        OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
+                MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
+        MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
 
         /* We wait for the receiver to be ready */
-        spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
+        spcr1 = MCBSP_READ(mcbsp, SPCR1);
         while (!(spcr1 & RRDY)) {
-                spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
+                spcr1 = MCBSP_READ(mcbsp, SPCR1);
                 if (attempts++ > 1000) {
                         /* We must reset the receiver */
-                        OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
+                        MCBSP_WRITE(mcbsp, SPCR1,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
                         udelay(10);
-                        OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
+                        MCBSP_WRITE(mcbsp, SPCR1,
+                                    MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
                         udelay(10);
                         dev_err(mcbsp->dev, "McBSP%d receiver not "
                                 "ready\n", mcbsp->id);
@@ -878,8 +1184,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 
         /* Receiver is ready, there is something for us */
         if (rx_word_length > OMAP_MCBSP_WORD_16)
-                word_msb = OMAP_MCBSP_READ(io_base, DRR2);
-        word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
+                word_msb = MCBSP_READ(mcbsp, DRR2);
+        word_lsb = MCBSP_READ(mcbsp, DRR1);
 
         word[0] = (word_lsb | (word_msb << 16));
 
@@ -1093,7 +1399,7 @@ void omap_mcbsp_set_spi_mode(unsigned int id,
 }
 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 #define THRESHOLD_PROP_BUILDER(prop)                                    \
@@ -1184,6 +1490,64 @@ unlock:
 
 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
 
+static ssize_t st_taps_show(struct device *dev,
+                            struct device_attribute *attr, char *buf)
+{
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+        ssize_t status = 0;
+        int i;
+
+        spin_lock_irq(&mcbsp->lock);
+        for (i = 0; i < st_data->nr_taps; i++)
+                status += sprintf(&buf[status], (i ? ", %d" : "%d"),
+                                  st_data->taps[i]);
+        if (i)
+                status += sprintf(&buf[status], "\n");
+        spin_unlock_irq(&mcbsp->lock);
+
+        return status;
+}
+
+static ssize_t st_taps_store(struct device *dev,
+                             struct device_attribute *attr,
+                             const char *buf, size_t size)
+{
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+        int val, tmp, status, i = 0;
+
+        spin_lock_irq(&mcbsp->lock);
+        memset(st_data->taps, 0, sizeof(st_data->taps));
+        st_data->nr_taps = 0;
+
+        do {
+                status = sscanf(buf, "%d%n", &val, &tmp);
+                if (status < 0 || status == 0) {
+                        size = -EINVAL;
+                        goto out;
+                }
+                if (val < -32768 || val > 32767) {
+                        size = -EINVAL;
+                        goto out;
+                }
+                st_data->taps[i++] = val;
+                buf += tmp;
+                if (*buf != ',')
+                        break;
+                buf++;
+        } while (1);
+
+        st_data->nr_taps = i;
+
+out:
+        spin_unlock_irq(&mcbsp->lock);
+
+        return size;
+}
+
+static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
+
 static const struct attribute *additional_attrs[] = {
         &dev_attr_max_tx_thres.attr,
         &dev_attr_max_rx_thres.attr,
@@ -1205,6 +1569,60 @@ static inline void __devexit omap_additional_remove(struct device *dev)
         sysfs_remove_group(&dev->kobj, &additional_attr_group);
 }
 
+static const struct attribute *sidetone_attrs[] = {
+        &dev_attr_st_taps.attr,
+        NULL,
+};
+
+static const struct attribute_group sidetone_attr_group = {
+        .attrs = (struct attribute **)sidetone_attrs,
+};
+
+int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
+{
+        struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
+        struct omap_mcbsp_st_data *st_data;
+        int err;
+
+        st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
+        if (!st_data) {
+                err = -ENOMEM;
+                goto err1;
+        }
+
+        st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
+        if (!st_data->io_base_st) {
+                err = -ENOMEM;
+                goto err2;
+        }
+
+        err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
+        if (err)
+                goto err3;
+
+        mcbsp->st_data = st_data;
+        return 0;
+
+err3:
+        iounmap(st_data->io_base_st);
+err2:
+        kfree(st_data);
+err1:
+        return err;
+
+}
+
+static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
+{
+        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+
+        if (st_data) {
+                sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
+                iounmap(st_data->io_base_st);
+                kfree(st_data);
+        }
+}
+
 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
 {
         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
@@ -1218,6 +1636,12 @@ static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
                 if (omap_additional_add(mcbsp->dev))
                         dev_warn(mcbsp->dev,
                                 "Unable to create additional controls\n");
+
+                if (mcbsp->id == 2 || mcbsp->id == 3)
+                        if (omap_st_add(mcbsp))
+                                dev_warn(mcbsp->dev,
+                                 "Unable to create sidetone controls\n");
+
         } else {
                 mcbsp->max_tx_thres = -EINVAL;
                 mcbsp->max_rx_thres = -EINVAL;
@@ -1226,13 +1650,17 @@ static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
 
 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
 {
-        if (cpu_is_omap34xx())
+        if (cpu_is_omap34xx()) {
                 omap_additional_remove(mcbsp->dev);
+
+                if (mcbsp->id == 2 || mcbsp->id == 3)
+                        omap_st_remove(mcbsp);
+        }
 }
 #else
 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
-#endif /* CONFIG_ARCH_OMAP34XX */
+#endif /* CONFIG_ARCH_OMAP3 */
 
 /*
  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 1e5648d3e3d8..590435894848 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -89,16 +89,8 @@
 #define USE_WAKEUP_LAT                  0
 #define IGNORE_WAKEUP_LAT               1
 
-/* XXX this should be moved into a separate file */
-#if defined(CONFIG_ARCH_OMAP2420)
-# define OMAP_32KSYNCT_BASE             0x48004000
-#elif defined(CONFIG_ARCH_OMAP2430)
-# define OMAP_32KSYNCT_BASE             0x49020000
-#elif defined(CONFIG_ARCH_OMAP3430)
-# define OMAP_32KSYNCT_BASE             0x48320000
-#else
-# error Unknown OMAP device
-#endif
+
+#define OMAP_DEVICE_MAGIC 0xf00dcafe
 
 /* Private functions */
 
@@ -148,10 +140,22 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
                          "%llu nsec\n", od->pdev.name, od->pm_lat_level,
                          act_lat);
 
-                WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: "
-                     "activate step %d took longer than expected (%llu > %d)\n",
-                     od->pdev.name, od->pdev.id, od->pm_lat_level,
-                     act_lat, odpl->activate_lat);
+                if (act_lat > odpl->activate_lat) {
+                        odpl->activate_lat_worst = act_lat;
+                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
+                                odpl->activate_lat = act_lat;
+                                pr_warning("omap_device: %s.%d: new worst case "
+                                           "activate latency %d: %llu\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, act_lat);
+                        } else
+                                pr_warning("omap_device: %s.%d: activate "
+                                           "latency %d higher than exptected. "
+                                           "(%llu > %d)\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, act_lat,
+                                           odpl->activate_lat);
+                }
 
                 od->dev_wakeup_lat -= odpl->activate_lat;
         }
@@ -204,10 +208,23 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
                          "%llu nsec\n", od->pdev.name, od->pm_lat_level,
                          deact_lat);
 
-                WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: "
-                     "deactivate step %d took longer than expected "
-                     "(%llu > %d)\n", od->pdev.name, od->pdev.id,
-                     od->pm_lat_level, deact_lat, odpl->deactivate_lat);
+                if (deact_lat > odpl->deactivate_lat) {
+                        odpl->deactivate_lat_worst = deact_lat;
+                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
+                                odpl->deactivate_lat = deact_lat;
+                                pr_warning("omap_device: %s.%d: new worst case "
+                                           "deactivate latency %d: %llu\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, deact_lat);
+                        } else
+                                pr_warning("omap_device: %s.%d: deactivate "
+                                           "latency %d higher than exptected. "
+                                           "(%llu > %d)\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, deact_lat,
+                                           odpl->deactivate_lat);
+                }
+
 
                 od->dev_wakeup_lat += odpl->activate_lat;
 
@@ -290,6 +307,7 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res)
  * @pdata_len: amount of memory pointed to by @pdata
  * @pm_lats: pointer to a omap_device_pm_latency array for this device
  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ * @is_early_device: should the device be registered as an early device or not
  *
  * Convenience function for building and registering a single
  * omap_device record, which in turn builds and registers a
@@ -301,7 +319,7 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
                                       struct omap_hwmod *oh, void *pdata,
                                       int pdata_len,
                                       struct omap_device_pm_latency *pm_lats,
-                                      int pm_lats_cnt)
+                                      int pm_lats_cnt, int is_early_device)
 {
         struct omap_hwmod *ohs[] = { oh };
 
@@ -309,7 +327,8 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
                 return ERR_PTR(-EINVAL);
 
         return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata,
-                                    pdata_len, pm_lats, pm_lats_cnt);
+                                    pdata_len, pm_lats, pm_lats_cnt,
+                                    is_early_device);
 }
 
 /**
@@ -321,6 +340,7 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
  * @pdata_len: amount of memory pointed to by @pdata
  * @pm_lats: pointer to a omap_device_pm_latency array for this device
  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ * @is_early_device: should the device be registered as an early device or not
  *
  * Convenience function for building and registering an omap_device
  * subsystem record.  Subsystem records consist of multiple
@@ -332,7 +352,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_hwmod **ohs, int oh_cnt,
                                          void *pdata, int pdata_len,
                                          struct omap_device_pm_latency *pm_lats,
-                                         int pm_lats_cnt)
+                                         int pm_lats_cnt, int is_early_device)
 {
         int ret = -ENOMEM;
         struct omap_device *od;
@@ -388,7 +408,13 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
         od->pm_lats = pm_lats;
         od->pm_lats_cnt = pm_lats_cnt;
 
-        ret = omap_device_register(od);
+        od->magic = OMAP_DEVICE_MAGIC;
+
+        if (is_early_device)
+                ret = omap_early_device_register(od);
+        else
+                ret = omap_device_register(od);
+
         if (ret)
                 goto odbs_exit4;
 
@@ -409,6 +435,24 @@ odbs_exit1:
 }
 
 /**
+ * omap_early_device_register - register an omap_device as an early platform
+ * device.
+ * @od: struct omap_device * to register
+ *
+ * Register the omap_device structure.  This currently just calls
+ * platform_early_add_device() on the underlying platform_device.
+ * Returns 0 by default.
+ */
+int omap_early_device_register(struct omap_device *od)
+{
+        struct platform_device *devices[1];
+
+        devices[0] = &(od->pdev);
+        early_platform_add_devices(devices, 1);
+        return 0;
+}
+
+/**
  * omap_device_register - register an omap_device with one omap_hwmod
  * @od: struct omap_device * to register
  *
@@ -447,8 +491,8 @@ int omap_device_enable(struct platform_device *pdev)
         od = _find_by_pdev(pdev);
 
         if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
-                WARN(1, "omap_device: %s.%d: omap_device_enable() called from "
-                     "invalid state\n", od->pdev.name, od->pdev.id);
+                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+                     od->pdev.name, od->pdev.id, __func__, od->_state);
                 return -EINVAL;
         }
 
@@ -486,8 +530,8 @@ int omap_device_idle(struct platform_device *pdev)
         od = _find_by_pdev(pdev);
 
         if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
-                WARN(1, "omap_device: %s.%d: omap_device_idle() called from "
-                     "invalid state\n", od->pdev.name, od->pdev.id);
+                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+                     od->pdev.name, od->pdev.id, __func__, od->_state);
                 return -EINVAL;
         }
 
@@ -519,8 +563,8 @@ int omap_device_shutdown(struct platform_device *pdev)
 
         if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
             od->_state != OMAP_DEVICE_STATE_IDLE) {
-                WARN(1, "omap_device: %s.%d: omap_device_shutdown() called "
-                     "from invalid state\n", od->pdev.name, od->pdev.id);
+                WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
+                     od->pdev.name, od->pdev.id, __func__, od->_state);
                 return -EINVAL;
         }
 
@@ -574,6 +618,18 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
 }
 
 /**
+ * omap_device_is_valid - Check if pointer is a valid omap_device
+ * @od: struct omap_device *
+ *
+ * Return whether struct omap_device pointer @od points to a valid
+ * omap_device.
+ */
+bool omap_device_is_valid(struct omap_device *od)
+{
+        return (od && od->magic == OMAP_DEVICE_MAGIC);
+}
+
+/**
  * omap_device_get_pwrdm - return the powerdomain * associated with @od
  * @od: struct omap_device *
  *
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index d8d5094b37ed..51f4dfb82e2b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -53,7 +53,7 @@
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
 
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 #define SRAM_BOOTLOADER_SZ      0x00
 #else
 #define SRAM_BOOTLOADER_SZ      0x80