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-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/clock.c5
-rw-r--r--arch/arm/plat-omap/common.c275
-rw-r--r--arch/arm/plat-omap/counter_32k.c183
-rw-r--r--arch/arm/plat-omap/devices.c1
-rw-r--r--arch/arm/plat-omap/include/plat/control.h366
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h22
-rw-r--r--arch/arm/plat-omap/include/plat/omap-serial.h1
-rw-r--r--arch/arm/plat-omap/include/plat/omap24xx.h2
-rw-r--r--arch/arm/plat-omap/mcbsp.c3
-rw-r--r--arch/arm/plat-omap/sram.c3
11 files changed, 210 insertions, 653 deletions
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 2a151917ef52..a4a12859fdd5 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
7 usb.o fb.o io.o 7 usb.o fb.o io.o counter_32k.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 7190cbd92620..fc62fb5fc20b 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -60,7 +60,7 @@ void clk_disable(struct clk *clk)
60 60
61 spin_lock_irqsave(&clockfw_lock, flags); 61 spin_lock_irqsave(&clockfw_lock, flags);
62 if (clk->usecount == 0) { 62 if (clk->usecount == 0) {
63 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", 63 pr_err("Trying disable clock %s with 0 usecount\n",
64 clk->name); 64 clk->name);
65 WARN_ON(1); 65 WARN_ON(1);
66 goto out; 66 goto out;
@@ -397,6 +397,7 @@ static int __init clk_disable_unused(void)
397 struct clk *ck; 397 struct clk *ck;
398 unsigned long flags; 398 unsigned long flags;
399 399
400 pr_info("clock: disabling unused clocks to save power\n");
400 list_for_each_entry(ck, &clocks, node) { 401 list_for_each_entry(ck, &clocks, node) {
401 if (ck->ops == &clkops_null) 402 if (ck->ops == &clkops_null)
402 continue; 403 continue;
@@ -418,7 +419,7 @@ late_initcall(clk_disable_unused);
418int __init clk_init(struct clk_functions * custom_clocks) 419int __init clk_init(struct clk_functions * custom_clocks)
419{ 420{
420 if (!custom_clocks) { 421 if (!custom_clocks) {
421 printk(KERN_ERR "No custom clock functions registered\n"); 422 pr_err("No custom clock functions registered\n");
422 BUG(); 423 BUG();
423 } 424 }
424 425
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 947de3fb93f3..221a675ebbae 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -11,38 +11,15 @@
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14#include <linux/module.h>
15#include <linux/kernel.h> 14#include <linux/kernel.h>
16#include <linux/init.h> 15#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/console.h>
19#include <linux/serial.h>
20#include <linux/tty.h>
21#include <linux/serial_8250.h>
22#include <linux/serial_reg.h>
23#include <linux/clk.h>
24#include <linux/io.h> 16#include <linux/io.h>
25#include <linux/omapfb.h> 17#include <linux/omapfb.h>
26 18
27#include <mach/hardware.h>
28#include <asm/system.h>
29#include <asm/pgtable.h>
30#include <asm/mach/map.h>
31#include <asm/setup.h>
32
33#include <plat/common.h> 19#include <plat/common.h>
34#include <plat/board.h> 20#include <plat/board.h>
35#include <plat/control.h>
36#include <plat/mux.h>
37#include <plat/fpga.h>
38#include <plat/serial.h>
39#include <plat/vram.h> 21#include <plat/vram.h>
40 22
41#include <plat/clock.h>
42
43#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
44# include "../mach-omap2/sdrc.h"
45#endif
46 23
47#define NO_LENGTH_CHECK 0xffffffff 24#define NO_LENGTH_CHECK 0xffffffff
48 25
@@ -88,255 +65,3 @@ void __init omap_reserve(void)
88 omapfb_reserve_sdram_memblock(); 65 omapfb_reserve_sdram_memblock();
89 omap_vram_reserve_sdram_memblock(); 66 omap_vram_reserve_sdram_memblock();
90} 67}
91
92/*
93 * 32KHz clocksource ... always available, on pretty most chips except
94 * OMAP 730 and 1510. Other timers could be used as clocksources, with
95 * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
96 * but systems won't necessarily want to spend resources that way.
97 */
98
99#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
100
101#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
102
103#include <linux/clocksource.h>
104
105/*
106 * offset_32k holds the init time counter value. It is then subtracted
107 * from every counter read to achieve a counter that counts time from the
108 * kernel boot (needed for sched_clock()).
109 */
110static u32 offset_32k __read_mostly;
111
112#ifdef CONFIG_ARCH_OMAP16XX
113static cycle_t omap16xx_32k_read(struct clocksource *cs)
114{
115 return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
116}
117#else
118#define omap16xx_32k_read NULL
119#endif
120
121#ifdef CONFIG_ARCH_OMAP2420
122static cycle_t omap2420_32k_read(struct clocksource *cs)
123{
124 return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
125}
126#else
127#define omap2420_32k_read NULL
128#endif
129
130#ifdef CONFIG_ARCH_OMAP2430
131static cycle_t omap2430_32k_read(struct clocksource *cs)
132{
133 return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
134}
135#else
136#define omap2430_32k_read NULL
137#endif
138
139#ifdef CONFIG_ARCH_OMAP3
140static cycle_t omap34xx_32k_read(struct clocksource *cs)
141{
142 return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
143}
144#else
145#define omap34xx_32k_read NULL
146#endif
147
148#ifdef CONFIG_ARCH_OMAP4
149static cycle_t omap44xx_32k_read(struct clocksource *cs)
150{
151 return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
152}
153#else
154#define omap44xx_32k_read NULL
155#endif
156
157/*
158 * Kernel assumes that sched_clock can be called early but may not have
159 * things ready yet.
160 */
161static cycle_t omap_32k_read_dummy(struct clocksource *cs)
162{
163 return 0;
164}
165
166static struct clocksource clocksource_32k = {
167 .name = "32k_counter",
168 .rating = 250,
169 .read = omap_32k_read_dummy,
170 .mask = CLOCKSOURCE_MASK(32),
171 .shift = 10,
172 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
173};
174
175/*
176 * Returns current time from boot in nsecs. It's OK for this to wrap
177 * around for now, as it's just a relative time stamp.
178 */
179unsigned long long sched_clock(void)
180{
181 return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
182 clocksource_32k.mult, clocksource_32k.shift);
183}
184
185/**
186 * read_persistent_clock - Return time from a persistent clock.
187 *
188 * Reads the time from a source which isn't disabled during PM, the
189 * 32k sync timer. Convert the cycles elapsed since last read into
190 * nsecs and adds to a monotonically increasing timespec.
191 */
192static struct timespec persistent_ts;
193static cycles_t cycles, last_cycles;
194void read_persistent_clock(struct timespec *ts)
195{
196 unsigned long long nsecs;
197 cycles_t delta;
198 struct timespec *tsp = &persistent_ts;
199
200 last_cycles = cycles;
201 cycles = clocksource_32k.read(&clocksource_32k);
202 delta = cycles - last_cycles;
203
204 nsecs = clocksource_cyc2ns(delta,
205 clocksource_32k.mult, clocksource_32k.shift);
206
207 timespec_add_ns(tsp, nsecs);
208 *ts = *tsp;
209}
210
211static int __init omap_init_clocksource_32k(void)
212{
213 static char err[] __initdata = KERN_ERR
214 "%s: can't register clocksource!\n";
215
216 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
217 struct clk *sync_32k_ick;
218
219 if (cpu_is_omap16xx())
220 clocksource_32k.read = omap16xx_32k_read;
221 else if (cpu_is_omap2420())
222 clocksource_32k.read = omap2420_32k_read;
223 else if (cpu_is_omap2430())
224 clocksource_32k.read = omap2430_32k_read;
225 else if (cpu_is_omap34xx())
226 clocksource_32k.read = omap34xx_32k_read;
227 else if (cpu_is_omap44xx())
228 clocksource_32k.read = omap44xx_32k_read;
229 else
230 return -ENODEV;
231
232 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
233 if (sync_32k_ick)
234 clk_enable(sync_32k_ick);
235
236 clocksource_32k.mult = clocksource_hz2mult(32768,
237 clocksource_32k.shift);
238
239 offset_32k = clocksource_32k.read(&clocksource_32k);
240
241 if (clocksource_register(&clocksource_32k))
242 printk(err, clocksource_32k.name);
243 }
244 return 0;
245}
246arch_initcall(omap_init_clocksource_32k);
247
248#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
249
250/* Global address base setup code */
251
252#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
253
254static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
255{
256 omap2_set_globals_tap(omap2_globals);
257 omap2_set_globals_sdrc(omap2_globals);
258 omap2_set_globals_control(omap2_globals);
259 omap2_set_globals_prcm(omap2_globals);
260}
261
262#endif
263
264#if defined(CONFIG_ARCH_OMAP2420)
265
266static struct omap_globals omap242x_globals = {
267 .class = OMAP242X_CLASS,
268 .tap = OMAP2_L4_IO_ADDRESS(0x48014000),
269 .sdrc = OMAP2420_SDRC_BASE,
270 .sms = OMAP2420_SMS_BASE,
271 .ctrl = OMAP2420_CTRL_BASE,
272 .prm = OMAP2420_PRM_BASE,
273 .cm = OMAP2420_CM_BASE,
274};
275
276void __init omap2_set_globals_242x(void)
277{
278 __omap2_set_globals(&omap242x_globals);
279}
280#endif
281
282#if defined(CONFIG_ARCH_OMAP2430)
283
284static struct omap_globals omap243x_globals = {
285 .class = OMAP243X_CLASS,
286 .tap = OMAP2_L4_IO_ADDRESS(0x4900a000),
287 .sdrc = OMAP243X_SDRC_BASE,
288 .sms = OMAP243X_SMS_BASE,
289 .ctrl = OMAP243X_CTRL_BASE,
290 .prm = OMAP2430_PRM_BASE,
291 .cm = OMAP2430_CM_BASE,
292};
293
294void __init omap2_set_globals_243x(void)
295{
296 __omap2_set_globals(&omap243x_globals);
297}
298#endif
299
300#if defined(CONFIG_ARCH_OMAP3)
301
302static struct omap_globals omap3_globals = {
303 .class = OMAP343X_CLASS,
304 .tap = OMAP2_L4_IO_ADDRESS(0x4830A000),
305 .sdrc = OMAP343X_SDRC_BASE,
306 .sms = OMAP343X_SMS_BASE,
307 .ctrl = OMAP343X_CTRL_BASE,
308 .prm = OMAP3430_PRM_BASE,
309 .cm = OMAP3430_CM_BASE,
310};
311
312void __init omap2_set_globals_3xxx(void)
313{
314 __omap2_set_globals(&omap3_globals);
315}
316
317void __init omap3_map_io(void)
318{
319 omap2_set_globals_3xxx();
320 omap34xx_map_common_io();
321}
322#endif
323
324#if defined(CONFIG_ARCH_OMAP4)
325static struct omap_globals omap4_globals = {
326 .class = OMAP443X_CLASS,
327 .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
328 .ctrl = OMAP443X_SCM_BASE,
329 .ctrl_pad = OMAP443X_CTRL_BASE,
330 .prm = OMAP4430_PRM_BASE,
331 .cm = OMAP4430_CM_BASE,
332 .cm2 = OMAP4430_CM2_BASE,
333};
334
335void __init omap2_set_globals_443x(void)
336{
337 omap2_set_globals_tap(&omap4_globals);
338 omap2_set_globals_control(&omap4_globals);
339 omap2_set_globals_prcm(&omap4_globals);
340}
341#endif
342
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
new file mode 100644
index 000000000000..155fe43a672b
--- /dev/null
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -0,0 +1,183 @@
1/*
2 * OMAP 32ksynctimer/counter_32k-related code
3 *
4 * Copyright (C) 2009 Texas Instruments
5 * Copyright (C) 2010 Nokia Corporation
6 * Tony Lindgren <tony@atomide.com>
7 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19
20#include <plat/common.h>
21#include <plat/board.h>
22
23#include <plat/clock.h>
24
25
26/*
27 * 32KHz clocksource ... always available, on pretty most chips except
28 * OMAP 730 and 1510. Other timers could be used as clocksources, with
29 * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
30 * but systems won't necessarily want to spend resources that way.
31 */
32
33#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
34
35#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
36
37#include <linux/clocksource.h>
38
39/*
40 * offset_32k holds the init time counter value. It is then subtracted
41 * from every counter read to achieve a counter that counts time from the
42 * kernel boot (needed for sched_clock()).
43 */
44static u32 offset_32k __read_mostly;
45
46#ifdef CONFIG_ARCH_OMAP16XX
47static cycle_t omap16xx_32k_read(struct clocksource *cs)
48{
49 return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
50}
51#else
52#define omap16xx_32k_read NULL
53#endif
54
55#ifdef CONFIG_ARCH_OMAP2420
56static cycle_t omap2420_32k_read(struct clocksource *cs)
57{
58 return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
59}
60#else
61#define omap2420_32k_read NULL
62#endif
63
64#ifdef CONFIG_ARCH_OMAP2430
65static cycle_t omap2430_32k_read(struct clocksource *cs)
66{
67 return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
68}
69#else
70#define omap2430_32k_read NULL
71#endif
72
73#ifdef CONFIG_ARCH_OMAP3
74static cycle_t omap34xx_32k_read(struct clocksource *cs)
75{
76 return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
77}
78#else
79#define omap34xx_32k_read NULL
80#endif
81
82#ifdef CONFIG_ARCH_OMAP4
83static cycle_t omap44xx_32k_read(struct clocksource *cs)
84{
85 return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
86}
87#else
88#define omap44xx_32k_read NULL
89#endif
90
91/*
92 * Kernel assumes that sched_clock can be called early but may not have
93 * things ready yet.
94 */
95static cycle_t omap_32k_read_dummy(struct clocksource *cs)
96{
97 return 0;
98}
99
100static struct clocksource clocksource_32k = {
101 .name = "32k_counter",
102 .rating = 250,
103 .read = omap_32k_read_dummy,
104 .mask = CLOCKSOURCE_MASK(32),
105 .shift = 10,
106 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
107};
108
109/*
110 * Returns current time from boot in nsecs. It's OK for this to wrap
111 * around for now, as it's just a relative time stamp.
112 */
113unsigned long long sched_clock(void)
114{
115 return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
116 clocksource_32k.mult, clocksource_32k.shift);
117}
118
119/**
120 * read_persistent_clock - Return time from a persistent clock.
121 *
122 * Reads the time from a source which isn't disabled during PM, the
123 * 32k sync timer. Convert the cycles elapsed since last read into
124 * nsecs and adds to a monotonically increasing timespec.
125 */
126static struct timespec persistent_ts;
127static cycles_t cycles, last_cycles;
128void read_persistent_clock(struct timespec *ts)
129{
130 unsigned long long nsecs;
131 cycles_t delta;
132 struct timespec *tsp = &persistent_ts;
133
134 last_cycles = cycles;
135 cycles = clocksource_32k.read(&clocksource_32k);
136 delta = cycles - last_cycles;
137
138 nsecs = clocksource_cyc2ns(delta,
139 clocksource_32k.mult, clocksource_32k.shift);
140
141 timespec_add_ns(tsp, nsecs);
142 *ts = *tsp;
143}
144
145static int __init omap_init_clocksource_32k(void)
146{
147 static char err[] __initdata = KERN_ERR
148 "%s: can't register clocksource!\n";
149
150 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
151 struct clk *sync_32k_ick;
152
153 if (cpu_is_omap16xx())
154 clocksource_32k.read = omap16xx_32k_read;
155 else if (cpu_is_omap2420())
156 clocksource_32k.read = omap2420_32k_read;
157 else if (cpu_is_omap2430())
158 clocksource_32k.read = omap2430_32k_read;
159 else if (cpu_is_omap34xx())
160 clocksource_32k.read = omap34xx_32k_read;
161 else if (cpu_is_omap44xx())
162 clocksource_32k.read = omap44xx_32k_read;
163 else
164 return -ENODEV;
165
166 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
167 if (sync_32k_ick)
168 clk_enable(sync_32k_ick);
169
170 clocksource_32k.mult = clocksource_hz2mult(32768,
171 clocksource_32k.shift);
172
173 offset_32k = clocksource_32k.read(&clocksource_32k);
174
175 if (clocksource_register(&clocksource_32k))
176 printk(err, clocksource_32k.name);
177 }
178 return 0;
179}
180arch_initcall(omap_init_clocksource_32k);
181
182#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
183
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 8e88e0e5d524..1e2383eae638 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -21,7 +21,6 @@
21#include <asm/mach/map.h> 21#include <asm/mach/map.h>
22 22
23#include <plat/tc.h> 23#include <plat/tc.h>
24#include <plat/control.h>
25#include <plat/board.h> 24#include <plat/board.h>
26#include <plat/mmc.h> 25#include <plat/mmc.h>
27#include <mach/gpio.h> 26#include <mach/gpio.h>
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
deleted file mode 100644
index 19c9b2a82046..000000000000
--- a/arch/arm/plat-omap/include/plat/control.h
+++ /dev/null
@@ -1,366 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/control.h
3 *
4 * OMAP2/3/4 System Control Module definitions
5 *
6 * Copyright (C) 2007-2009 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_CONTROL_H
17#define __ASM_ARCH_CONTROL_H
18
19#include <mach/io.h>
20#include <mach/ctrl_module_core_44xx.h>
21#include <mach/ctrl_module_wkup_44xx.h>
22#include <mach/ctrl_module_pad_core_44xx.h>
23#include <mach/ctrl_module_pad_wkup_44xx.h>
24
25#ifndef __ASSEMBLY__
26#define OMAP242X_CTRL_REGADDR(reg) \
27 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
28#define OMAP243X_CTRL_REGADDR(reg) \
29 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
30#define OMAP343X_CTRL_REGADDR(reg) \
31 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
32#else
33#define OMAP242X_CTRL_REGADDR(reg) \
34 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
35#define OMAP243X_CTRL_REGADDR(reg) \
36 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
37#define OMAP343X_CTRL_REGADDR(reg) \
38 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
39#endif /* __ASSEMBLY__ */
40
41/*
42 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
43 * OMAP24XX and OMAP34XX.
44 */
45
46/* Control submodule offsets */
47
48#define OMAP2_CONTROL_INTERFACE 0x000
49#define OMAP2_CONTROL_PADCONFS 0x030
50#define OMAP2_CONTROL_GENERAL 0x270
51#define OMAP343X_CONTROL_MEM_WKUP 0x600
52#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
53#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
54
55/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
56
57#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
58
59/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
60#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
61#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
62#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
63#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
64#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
65#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
66#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
67#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
68#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
69#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
70#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
71#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
72
73/* 242x-only CONTROL_GENERAL register offsets */
74#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
75#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
76
77/* 243x-only CONTROL_GENERAL register offsets */
78/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
79#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
80#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
81#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
82#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
83#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
84#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
85
86/* 24xx-only CONTROL_GENERAL register offsets */
87#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
88#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
89#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
90#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
91#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
92#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
93#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
94#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
95#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
96#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
97#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
98#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
99#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
100#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
101#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
102#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
103#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
104#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
105#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
106#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
107#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
108#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
109#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
110#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
111#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
112#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
113#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
114#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
115#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
116#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
117#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
118
119#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
120
121/* 34xx-only CONTROL_GENERAL register offsets */
122#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
123#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
124#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
125#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
126#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
127#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
128#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
129#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
130#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
131#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
132#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
133#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
134#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
135#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
136#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
137#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
138#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
139#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
140#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
141#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
142#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
143#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
144#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
145#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
146#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
147#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
148#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
149#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
150#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
151#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
152#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
153#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
154 + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
155#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
156#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
157#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
158#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
159#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
160#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
161#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
162#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
163#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
164#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
165#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
166
167/* AM35XX only CONTROL_GENERAL register offsets */
168#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
169#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
170#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314)
171#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320)
172#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324)
173#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328)
174#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C)
175
176/* 34xx PADCONF register offsets */
177#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
178 (i)*2)
179#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
180#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
181#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
182#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
183#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
184#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
185#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
186#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
187#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
188#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
189#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
190#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
191#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
192#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
193#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
194#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
195#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
196#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
197
198/* 34xx GENERAL_WKUP regist offsets */
199#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
200 0x008 + (i))
201#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
202#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
203#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
204#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
205#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
206
207/* 34xx D2D idle-related pins, handled by PM core */
208#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
209#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
210
211/*
212 * REVISIT: This list of registers is not comprehensive - there are more
213 * that should be added.
214 */
215
216/*
217 * Control module register bit defines - these should eventually go into
218 * their own regbits file. Some of these will be complicated, depending
219 * on the device type (general-purpose, emulator, test, secure, bad, other)
220 * and the security mode (secure, non-secure, don't care)
221 */
222/* CONTROL_DEVCONF0 bits */
223#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
224#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
225#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
226#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
227
228/* CONTROL_DEVCONF1 bits */
229#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
230#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
231#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
232#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
233#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
234
235/* CONTROL_STATUS bits */
236#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
237#define OMAP2_SYSBOOT_5_MASK (1 << 5)
238#define OMAP2_SYSBOOT_4_MASK (1 << 4)
239#define OMAP2_SYSBOOT_3_MASK (1 << 3)
240#define OMAP2_SYSBOOT_2_MASK (1 << 2)
241#define OMAP2_SYSBOOT_1_MASK (1 << 1)
242#define OMAP2_SYSBOOT_0_MASK (1 << 0)
243
244/* CONTROL_PBIAS_LITE bits */
245#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
246#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
247#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
248#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
249#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
250#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
251#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
252#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
253#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
254#define OMAP2_PBIASLITEVMODE0 (1 << 0)
255
256/* CONTROL_PROG_IO1 bits */
257#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
258
259/* CONTROL_IVA2_BOOTMOD bits */
260#define OMAP3_IVA2_BOOTMOD_SHIFT 0
261#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
262#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
263
264/* CONTROL_PADCONF_X bits */
265#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
266#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
267
268#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
269#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
270#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
271
272/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
273#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
274#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
275#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
276#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
277#define AM35XX_USBOTG_FCLK_SHIFT 8
278#define AM35XX_CPGMAC_FCLK_SHIFT 9
279#define AM35XX_VPFE_FCLK_SHIFT 10
280
281/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
282#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
283#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
284#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
285#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3)
286#define AM35XX_USBOTGSS_INT_CLR BIT(4)
287#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5)
288#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
289#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
290
291/*AM35XX CONTROL_IP_SW_RESET bits*/
292#define AM35XX_USBOTGSS_SW_RST BIT(0)
293#define AM35XX_CPGMACSS_SW_RST BIT(1)
294#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
295#define AM35XX_HECC_SW_RST BIT(3)
296#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
297
298/*
299 * CONTROL OMAP STATUS register to identify OMAP3 features
300 */
301#define OMAP3_CONTROL_OMAP_STATUS 0x044c
302
303#define OMAP3_SGX_SHIFT 13
304#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
305#define FEAT_SGX_FULL 0
306#define FEAT_SGX_HALF 1
307#define FEAT_SGX_NONE 2
308
309#define OMAP3_IVA_SHIFT 12
310#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
311#define FEAT_IVA 0
312#define FEAT_IVA_NONE 1
313
314#define OMAP3_L2CACHE_SHIFT 10
315#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
316#define FEAT_L2CACHE_NONE 0
317#define FEAT_L2CACHE_64KB 1
318#define FEAT_L2CACHE_128KB 2
319#define FEAT_L2CACHE_256KB 3
320
321#define OMAP3_ISP_SHIFT 5
322#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
323#define FEAT_ISP 0
324#define FEAT_ISP_NONE 1
325
326#define OMAP3_NEON_SHIFT 4
327#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
328#define FEAT_NEON 0
329#define FEAT_NEON_NONE 1
330
331
332#ifndef __ASSEMBLY__
333#ifdef CONFIG_ARCH_OMAP2PLUS
334extern void __iomem *omap_ctrl_base_get(void);
335extern u8 omap_ctrl_readb(u16 offset);
336extern u16 omap_ctrl_readw(u16 offset);
337extern u32 omap_ctrl_readl(u16 offset);
338extern u32 omap4_ctrl_pad_readl(u16 offset);
339extern void omap_ctrl_writeb(u8 val, u16 offset);
340extern void omap_ctrl_writew(u16 val, u16 offset);
341extern void omap_ctrl_writel(u32 val, u16 offset);
342extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
343
344extern void omap3_save_scratchpad_contents(void);
345extern void omap3_clear_scratchpad_contents(void);
346extern u32 *get_restore_pointer(void);
347extern u32 *get_es3_restore_pointer(void);
348extern u32 omap3_arm_context[128];
349extern void omap3_control_save_context(void);
350extern void omap3_control_restore_context(void);
351
352#else
353#define omap_ctrl_base_get() 0
354#define omap_ctrl_readb(x) 0
355#define omap_ctrl_readw(x) 0
356#define omap_ctrl_readl(x) 0
357#define omap4_ctrl_pad_readl(x) 0
358#define omap_ctrl_writeb(x, y) WARN_ON(1)
359#define omap_ctrl_writew(x, y) WARN_ON(1)
360#define omap_ctrl_writel(x, y) WARN_ON(1)
361#define omap4_ctrl_pad_writel(x, y) WARN_ON(1)
362#endif
363#endif /* __ASSEMBLY__ */
364
365#endif /* __ASM_ARCH_CONTROL_H */
366
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index b4ff6a11a8f2..e19abf2c8fe7 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -312,6 +312,18 @@
312#define RFSREN 0x0002 312#define RFSREN 0x0002
313#define RSYNCERREN 0x0001 313#define RSYNCERREN 0x0001
314 314
315/* CLKR signal muxing options */
316#define CLKR_SRC_CLKR 0
317#define CLKR_SRC_CLKX 1
318
319/* FSR signal muxing options */
320#define FSR_SRC_FSR 0
321#define FSR_SRC_FSX 1
322
323/* McBSP functional clock sources */
324#define MCBSP_CLKS_PRCM_SRC 0
325#define MCBSP_CLKS_PAD_SRC 1
326
315/* we don't do multichannel for now */ 327/* we don't do multichannel for now */
316struct omap_mcbsp_reg_cfg { 328struct omap_mcbsp_reg_cfg {
317 u16 spcr2; 329 u16 spcr2;
@@ -398,6 +410,7 @@ struct omap_mcbsp_spi_cfg {
398struct omap_mcbsp_ops { 410struct omap_mcbsp_ops {
399 void (*request)(unsigned int); 411 void (*request)(unsigned int);
400 void (*free)(unsigned int); 412 void (*free)(unsigned int);
413 int (*set_clks_src)(u8, u8);
401}; 414};
402 415
403struct omap_mcbsp_platform_data { 416struct omap_mcbsp_platform_data {
@@ -464,6 +477,9 @@ struct omap_mcbsp {
464extern struct omap_mcbsp **mcbsp_ptr; 477extern struct omap_mcbsp **mcbsp_ptr;
465extern int omap_mcbsp_count, omap_mcbsp_cache_size; 478extern int omap_mcbsp_count, omap_mcbsp_cache_size;
466 479
480#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
481#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
482
467int omap_mcbsp_init(void); 483int omap_mcbsp_init(void);
468void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 484void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
469 int size); 485 int size);
@@ -502,6 +518,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
502int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); 518int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
503 519
504 520
521/* McBSP functional clock source changing function */
522extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
505/* SPI specific API */ 523/* SPI specific API */
506void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); 524void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
507 525
@@ -510,6 +528,10 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf);
510int omap_mcbsp_pollwrite(unsigned int id, u16 buf); 528int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
511int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); 529int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
512 530
531/* McBSP signal muxing API */
532void omap2_mcbsp1_mux_clkr_src(u8 mux);
533void omap2_mcbsp1_mux_fsr_src(u8 mux);
534
513#ifdef CONFIG_ARCH_OMAP3 535#ifdef CONFIG_ARCH_OMAP3
514/* Sidetone specific API */ 536/* Sidetone specific API */
515int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); 537int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 0d6f076cf748..c8dae02f0704 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -20,7 +20,6 @@
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22 22
23#include <plat/control.h>
24#include <plat/mux.h> 23#include <plat/mux.h>
25 24
26#define DRIVER_NAME "omap-hsuart" 25#define DRIVER_NAME "omap-hsuart"
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
index 7055672a8c68..92df9e27cc5c 100644
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
@@ -40,7 +40,7 @@
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) 40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000 41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42 42
43#define OMAP2420_CTRL_BASE L4_24XX_BASE 43#define OMAP242X_CTRL_BASE L4_24XX_BASE
44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
45#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) 45#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
46#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) 46#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index b2e046990d38..45d99e955f7f 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -80,9 +80,6 @@ static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
80#define MCBSP_READ_CACHE(mcbsp, reg) \ 80#define MCBSP_READ_CACHE(mcbsp, reg) \
81 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) 81 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
82 82
83#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
84#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
85
86#define MCBSP_ST_READ(mcbsp, reg) \ 83#define MCBSP_ST_READ(mcbsp, reg) \
87 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg) 84 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
88#define MCBSP_ST_WRITE(mcbsp, reg, val) \ 85#define MCBSP_ST_WRITE(mcbsp, reg, val) \
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index dba5704b77db..c209163563b8 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -31,10 +31,8 @@
31#include <plat/cpu.h> 31#include <plat/cpu.h>
32#include <plat/vram.h> 32#include <plat/vram.h>
33 33
34#include <plat/control.h>
35#include "sram.h" 34#include "sram.h"
36#include "fb.h" 35#include "fb.h"
37
38#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 36#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
39# include "../mach-omap2/prm.h" 37# include "../mach-omap2/prm.h"
40# include "../mach-omap2/cm.h" 38# include "../mach-omap2/cm.h"
@@ -71,7 +69,6 @@
71#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858) 69#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
72#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880) 70#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
73#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048) 71#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
74#define OMAP34XX_VA_CONTROL_STAT OMAP2_L4_IO_ADDRESS(0x480022F0)
75 72
76#define GP_DEVICE 0x300 73#define GP_DEVICE 0x300
77 74
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 07:25:05 -0500