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-rw-r--r--arch/arm/plat-omap/devices.c46
-rw-r--r--arch/arm/plat-omap/dmtimer.c713
-rw-r--r--arch/arm/plat-omap/i2c.c18
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
-rw-r--r--arch/arm/plat-omap/include/plat/common.h13
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h108
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h233
-rw-r--r--arch/arm/plat-omap/include/plat/io.h6
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h208
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h31
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h3
-rw-r--r--arch/arm/plat-omap/include/plat/voltage.h20
-rw-r--r--arch/arm/plat-omap/mcbsp.c385
-rw-r--r--arch/arm/plat-omap/omap_device.c450
14 files changed, 1208 insertions, 1028 deletions
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index ea28f98d5d6a..bd9a06b3ee89 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -26,54 +26,8 @@
26#include <plat/mmc.h> 26#include <plat/mmc.h>
27#include <mach/gpio.h> 27#include <mach/gpio.h>
28#include <plat/menelaus.h> 28#include <plat/menelaus.h>
29#include <plat/mcbsp.h>
30#include <plat/omap44xx.h> 29#include <plat/omap44xx.h>
31 30
32/*-------------------------------------------------------------------------*/
33
34#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
35
36static struct platform_device **omap_mcbsp_devices;
37
38void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
39 struct omap_mcbsp_platform_data *config, int size)
40{
41 int i;
42
43 omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
44 GFP_KERNEL);
45 if (!omap_mcbsp_devices) {
46 printk(KERN_ERR "Could not register McBSP devices\n");
47 return;
48 }
49
50 for (i = 0; i < size; i++) {
51 struct platform_device *new_mcbsp;
52 int ret;
53
54 new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
55 if (!new_mcbsp)
56 continue;
57 platform_device_add_resources(new_mcbsp, &res[i * res_count],
58 res_count);
59 new_mcbsp->dev.platform_data = &config[i];
60 ret = platform_device_add(new_mcbsp);
61 if (ret) {
62 platform_device_put(new_mcbsp);
63 continue;
64 }
65 omap_mcbsp_devices[i] = new_mcbsp;
66 }
67}
68
69#else
70void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
71 struct omap_mcbsp_platform_data *config, int size)
72{ }
73#endif
74
75/*-------------------------------------------------------------------------*/
76
77#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \ 31#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
78 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE) 32 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
79 33
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 75a847dd776a..de7896fd9b33 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -3,6 +3,12 @@
3 * 3 *
4 * OMAP Dual-Mode Timers 4 * OMAP Dual-Mode Timers
5 * 5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
8 * Thara Gopinath <thara@ti.com>
9 *
10 * dmtimer adaptation to platform_driver.
11 *
6 * Copyright (C) 2005 Nokia Corporation 12 * Copyright (C) 2005 Nokia Corporation
7 * OMAP2 support by Juha Yrjola 13 * OMAP2 support by Juha Yrjola
8 * API improvements and OMAP2 clock framework support by Timo Teras 14 * API improvements and OMAP2 clock framework support by Timo Teras
@@ -29,168 +35,80 @@
29 * 675 Mass Ave, Cambridge, MA 02139, USA. 35 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */ 36 */
31 37
32#include <linux/init.h>
33#include <linux/spinlock.h>
34#include <linux/errno.h>
35#include <linux/list.h>
36#include <linux/clk.h>
37#include <linux/delay.h>
38#include <linux/io.h> 38#include <linux/io.h>
39#include <linux/module.h> 39#include <linux/slab.h>
40#include <mach/hardware.h> 40#include <linux/err.h>
41#include <plat/dmtimer.h> 41#include <linux/pm_runtime.h>
42#include <mach/irqs.h>
43
44static int dm_timer_count;
45
46#ifdef CONFIG_ARCH_OMAP1
47static struct omap_dm_timer omap1_dm_timers[] = {
48 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
49 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
50 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
51 { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
52 { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
53 { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
54 { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
55 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
56};
57
58static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
59
60#else
61#define omap1_dm_timers NULL
62#define omap1_dm_timer_count 0
63#endif /* CONFIG_ARCH_OMAP1 */
64
65#ifdef CONFIG_ARCH_OMAP2
66static struct omap_dm_timer omap2_dm_timers[] = {
67 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
68 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
69 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
70 { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
71 { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
72 { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
73 { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
74 { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
75 { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
76 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
77 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
78 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
79};
80
81static const char *omap2_dm_source_names[] __initdata = {
82 "sys_ck",
83 "func_32k_ck",
84 "alt_ck",
85 NULL
86};
87
88static struct clk *omap2_dm_source_clocks[3];
89static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
90
91#else
92#define omap2_dm_timers NULL
93#define omap2_dm_timer_count 0
94#define omap2_dm_source_names NULL
95#define omap2_dm_source_clocks NULL
96#endif /* CONFIG_ARCH_OMAP2 */
97
98#ifdef CONFIG_ARCH_OMAP3
99static struct omap_dm_timer omap3_dm_timers[] = {
100 { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
101 { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
102 { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
103 { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
104 { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
105 { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
106 { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
107 { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
108 { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
109 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
110 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
111 { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ },
112};
113
114static const char *omap3_dm_source_names[] __initdata = {
115 "sys_ck",
116 "omap_32k_fck",
117 NULL
118};
119
120static struct clk *omap3_dm_source_clocks[2];
121static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
122 42
123#else 43#include <plat/dmtimer.h>
124#define omap3_dm_timers NULL
125#define omap3_dm_timer_count 0
126#define omap3_dm_source_names NULL
127#define omap3_dm_source_clocks NULL
128#endif /* CONFIG_ARCH_OMAP3 */
129
130#ifdef CONFIG_ARCH_OMAP4
131static struct omap_dm_timer omap4_dm_timers[] = {
132 { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 },
133 { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 },
134 { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 },
135 { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 },
136 { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 },
137 { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 },
138 { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 },
139 { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 },
140 { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 },
141 { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 },
142 { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 },
143 { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
144};
145static const char *omap4_dm_source_names[] __initdata = {
146 "sys_clkin_ck",
147 "sys_32k_ck",
148 NULL
149};
150static struct clk *omap4_dm_source_clocks[2];
151static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
152
153#else
154#define omap4_dm_timers NULL
155#define omap4_dm_timer_count 0
156#define omap4_dm_source_names NULL
157#define omap4_dm_source_clocks NULL
158#endif /* CONFIG_ARCH_OMAP4 */
159
160static struct omap_dm_timer *dm_timers;
161static const char **dm_source_names;
162static struct clk **dm_source_clocks;
163 44
164static spinlock_t dm_timer_lock; 45static LIST_HEAD(omap_timer_list);
46static DEFINE_SPINLOCK(dm_timer_lock);
165 47
166/* 48/**
167 * Reads timer registers in posted and non-posted mode. The posted mode bit 49 * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
168 * is encoded in reg. Note that in posted mode write pending bit must be 50 * @timer: timer pointer over which read operation to perform
169 * checked. Otherwise a read of a non completed write will produce an error. 51 * @reg: lowest byte holds the register offset
52 *
53 * The posted mode bit is encoded in reg. Note that in posted mode write
54 * pending bit must be checked. Otherwise a read of a non completed write
55 * will produce an error.
170 */ 56 */
171static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) 57static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
172{ 58{
173 return __omap_dm_timer_read(timer->io_base, reg, timer->posted); 59 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
60 return __omap_dm_timer_read(timer, reg, timer->posted);
174} 61}
175 62
176/* 63/**
177 * Writes timer registers in posted and non-posted mode. The posted mode bit 64 * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
178 * is encoded in reg. Note that in posted mode the write pending bit must be 65 * @timer: timer pointer over which write operation is to perform
179 * checked. Otherwise a write on a register which has a pending write will be 66 * @reg: lowest byte holds the register offset
180 * lost. 67 * @value: data to write into the register
68 *
69 * The posted mode bit is encoded in reg. Note that in posted mode the write
70 * pending bit must be checked. Otherwise a write on a register which has a
71 * pending write will be lost.
181 */ 72 */
182static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, 73static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
183 u32 value) 74 u32 value)
184{ 75{
185 __omap_dm_timer_write(timer->io_base, reg, value, timer->posted); 76 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
77 __omap_dm_timer_write(timer, reg, value, timer->posted);
78}
79
80static void omap_timer_restore_context(struct omap_dm_timer *timer)
81{
82 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET,
83 timer->context.tiocp_cfg);
84 if (timer->revision > 1)
85 __raw_writel(timer->context.tistat, timer->sys_stat);
86
87 __raw_writel(timer->context.tisr, timer->irq_stat);
88 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
89 timer->context.twer);
90 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
91 timer->context.tcrr);
92 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
93 timer->context.tldr);
94 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
95 timer->context.tmar);
96 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
97 timer->context.tsicr);
98 __raw_writel(timer->context.tier, timer->irq_ena);
99 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
100 timer->context.tclr);
186} 101}
187 102
188static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) 103static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
189{ 104{
190 int c; 105 int c;
191 106
107 if (!timer->sys_stat)
108 return;
109
192 c = 0; 110 c = 0;
193 while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) { 111 while (!(__raw_readl(timer->sys_stat) & 1)) {
194 c++; 112 c++;
195 if (c > 100000) { 113 if (c > 100000) {
196 printk(KERN_ERR "Timer failed to reset\n"); 114 printk(KERN_ERR "Timer failed to reset\n");
@@ -201,53 +119,65 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
201 119
202static void omap_dm_timer_reset(struct omap_dm_timer *timer) 120static void omap_dm_timer_reset(struct omap_dm_timer *timer)
203{ 121{
204 int autoidle = 0, wakeup = 0; 122 omap_dm_timer_enable(timer);
205 123 if (timer->pdev->id != 1) {
206 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
207 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 124 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
208 omap_dm_timer_wait_for_reset(timer); 125 omap_dm_timer_wait_for_reset(timer);
209 } 126 }
210 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
211
212 /* Enable autoidle on OMAP2+ */
213 if (cpu_class_is_omap2())
214 autoidle = 1;
215
216 /*
217 * Enable wake-up on OMAP2 CPUs.
218 */
219 if (cpu_class_is_omap2())
220 wakeup = 1;
221 127
222 __omap_dm_timer_reset(timer->io_base, autoidle, wakeup); 128 __omap_dm_timer_reset(timer, 0, 0);
129 omap_dm_timer_disable(timer);
223 timer->posted = 1; 130 timer->posted = 1;
224} 131}
225 132
226void omap_dm_timer_prepare(struct omap_dm_timer *timer) 133int omap_dm_timer_prepare(struct omap_dm_timer *timer)
227{ 134{
228 omap_dm_timer_enable(timer); 135 struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
229 omap_dm_timer_reset(timer); 136 int ret;
137
138 timer->fclk = clk_get(&timer->pdev->dev, "fck");
139 if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
140 timer->fclk = NULL;
141 dev_err(&timer->pdev->dev, ": No fclk handle.\n");
142 return -EINVAL;
143 }
144
145 if (pdata->needs_manual_reset)
146 omap_dm_timer_reset(timer);
147
148 ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
149
150 timer->posted = 1;
151 return ret;
230} 152}
231 153
232struct omap_dm_timer *omap_dm_timer_request(void) 154struct omap_dm_timer *omap_dm_timer_request(void)
233{ 155{
234 struct omap_dm_timer *timer = NULL; 156 struct omap_dm_timer *timer = NULL, *t;
235 unsigned long flags; 157 unsigned long flags;
236 int i; 158 int ret = 0;
237 159
238 spin_lock_irqsave(&dm_timer_lock, flags); 160 spin_lock_irqsave(&dm_timer_lock, flags);
239 for (i = 0; i < dm_timer_count; i++) { 161 list_for_each_entry(t, &omap_timer_list, node) {
240 if (dm_timers[i].reserved) 162 if (t->reserved)
241 continue; 163 continue;
242 164
243 timer = &dm_timers[i]; 165 timer = t;
244 timer->reserved = 1; 166 timer->reserved = 1;
245 break; 167 break;
246 } 168 }
169
170 if (timer) {
171 ret = omap_dm_timer_prepare(timer);
172 if (ret) {
173 timer->reserved = 0;
174 timer = NULL;
175 }
176 }
247 spin_unlock_irqrestore(&dm_timer_lock, flags); 177 spin_unlock_irqrestore(&dm_timer_lock, flags);
248 178
249 if (timer != NULL) 179 if (!timer)
250 omap_dm_timer_prepare(timer); 180 pr_debug("%s: timer request failed!\n", __func__);
251 181
252 return timer; 182 return timer;
253} 183}
@@ -255,74 +185,65 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_request);
255 185
256struct omap_dm_timer *omap_dm_timer_request_specific(int id) 186struct omap_dm_timer *omap_dm_timer_request_specific(int id)
257{ 187{
258 struct omap_dm_timer *timer; 188 struct omap_dm_timer *timer = NULL, *t;
259 unsigned long flags; 189 unsigned long flags;
190 int ret = 0;
260 191
261 spin_lock_irqsave(&dm_timer_lock, flags); 192 spin_lock_irqsave(&dm_timer_lock, flags);
262 if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) { 193 list_for_each_entry(t, &omap_timer_list, node) {
263 spin_unlock_irqrestore(&dm_timer_lock, flags); 194 if (t->pdev->id == id && !t->reserved) {
264 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n", 195 timer = t;
265 __FILE__, __LINE__, __func__, id); 196 timer->reserved = 1;
266 dump_stack(); 197 break;
267 return NULL; 198 }
268 } 199 }
269 200
270 timer = &dm_timers[id-1]; 201 if (timer) {
271 timer->reserved = 1; 202 ret = omap_dm_timer_prepare(timer);
203 if (ret) {
204 timer->reserved = 0;
205 timer = NULL;
206 }
207 }
272 spin_unlock_irqrestore(&dm_timer_lock, flags); 208 spin_unlock_irqrestore(&dm_timer_lock, flags);
273 209
274 omap_dm_timer_prepare(timer); 210 if (!timer)
211 pr_debug("%s: timer%d request failed!\n", __func__, id);
275 212
276 return timer; 213 return timer;
277} 214}
278EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); 215EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
279 216
280void omap_dm_timer_free(struct omap_dm_timer *timer) 217int omap_dm_timer_free(struct omap_dm_timer *timer)
281{ 218{
282 omap_dm_timer_enable(timer); 219 if (unlikely(!timer))
283 omap_dm_timer_reset(timer); 220 return -EINVAL;
284 omap_dm_timer_disable(timer); 221
222 clk_put(timer->fclk);
285 223
286 WARN_ON(!timer->reserved); 224 WARN_ON(!timer->reserved);
287 timer->reserved = 0; 225 timer->reserved = 0;
226 return 0;
288} 227}
289EXPORT_SYMBOL_GPL(omap_dm_timer_free); 228EXPORT_SYMBOL_GPL(omap_dm_timer_free);
290 229
291void omap_dm_timer_enable(struct omap_dm_timer *timer) 230void omap_dm_timer_enable(struct omap_dm_timer *timer)
292{ 231{
293 if (timer->enabled) 232 pm_runtime_get_sync(&timer->pdev->dev);
294 return;
295
296#ifdef CONFIG_ARCH_OMAP2PLUS
297 if (cpu_class_is_omap2()) {
298 clk_enable(timer->fclk);
299 clk_enable(timer->iclk);
300 }
301#endif
302
303 timer->enabled = 1;
304} 233}
305EXPORT_SYMBOL_GPL(omap_dm_timer_enable); 234EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
306 235
307void omap_dm_timer_disable(struct omap_dm_timer *timer) 236void omap_dm_timer_disable(struct omap_dm_timer *timer)
308{ 237{
309 if (!timer->enabled) 238 pm_runtime_put(&timer->pdev->dev);
310 return;
311
312#ifdef CONFIG_ARCH_OMAP2PLUS
313 if (cpu_class_is_omap2()) {
314 clk_disable(timer->iclk);
315 clk_disable(timer->fclk);
316 }
317#endif
318
319 timer->enabled = 0;
320} 239}
321EXPORT_SYMBOL_GPL(omap_dm_timer_disable); 240EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
322 241
323int omap_dm_timer_get_irq(struct omap_dm_timer *timer) 242int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
324{ 243{
325 return timer->irq; 244 if (timer)
245 return timer->irq;
246 return -EINVAL;
326} 247}
327EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); 248EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
328 249
@@ -334,24 +255,29 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
334 */ 255 */
335__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 256__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
336{ 257{
337 int i; 258 int i = 0;
259 struct omap_dm_timer *timer = NULL;
260 unsigned long flags;
338 261
339 /* If ARMXOR cannot be idled this function call is unnecessary */ 262 /* If ARMXOR cannot be idled this function call is unnecessary */
340 if (!(inputmask & (1 << 1))) 263 if (!(inputmask & (1 << 1)))
341 return inputmask; 264 return inputmask;
342 265
343 /* If any active timer is using ARMXOR return modified mask */ 266 /* If any active timer is using ARMXOR return modified mask */
344 for (i = 0; i < dm_timer_count; i++) { 267 spin_lock_irqsave(&dm_timer_lock, flags);
268 list_for_each_entry(timer, &omap_timer_list, node) {
345 u32 l; 269 u32 l;
346 270
347 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG); 271 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
348 if (l & OMAP_TIMER_CTRL_ST) { 272 if (l & OMAP_TIMER_CTRL_ST) {
349 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) 273 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
350 inputmask &= ~(1 << 1); 274 inputmask &= ~(1 << 1);
351 else 275 else
352 inputmask &= ~(1 << 2); 276 inputmask &= ~(1 << 2);
353 } 277 }
278 i++;
354 } 279 }
280 spin_unlock_irqrestore(&dm_timer_lock, flags);
355 281
356 return inputmask; 282 return inputmask;
357} 283}
@@ -361,7 +287,9 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
361 287
362struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 288struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
363{ 289{
364 return timer->fclk; 290 if (timer)
291 return timer->fclk;
292 return NULL;
365} 293}
366EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); 294EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
367 295
@@ -375,70 +303,91 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
375 303
376#endif 304#endif
377 305
378void omap_dm_timer_trigger(struct omap_dm_timer *timer) 306int omap_dm_timer_trigger(struct omap_dm_timer *timer)
379{ 307{
308 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
309 pr_err("%s: timer not available or enabled.\n", __func__);
310 return -EINVAL;
311 }
312
380 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); 313 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
314 return 0;
381} 315}
382EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); 316EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
383 317
384void omap_dm_timer_start(struct omap_dm_timer *timer) 318int omap_dm_timer_start(struct omap_dm_timer *timer)
385{ 319{
386 u32 l; 320 u32 l;
387 321
322 if (unlikely(!timer))
323 return -EINVAL;
324
325 omap_dm_timer_enable(timer);
326
327 if (timer->loses_context) {
328 u32 ctx_loss_cnt_after =
329 timer->get_context_loss_count(&timer->pdev->dev);
330 if (ctx_loss_cnt_after != timer->ctx_loss_count)
331 omap_timer_restore_context(timer);
332 }
333
388 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 334 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
389 if (!(l & OMAP_TIMER_CTRL_ST)) { 335 if (!(l & OMAP_TIMER_CTRL_ST)) {
390 l |= OMAP_TIMER_CTRL_ST; 336 l |= OMAP_TIMER_CTRL_ST;
391 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 337 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
392 } 338 }
339
340 /* Save the context */
341 timer->context.tclr = l;
342 return 0;
393} 343}
394EXPORT_SYMBOL_GPL(omap_dm_timer_start); 344EXPORT_SYMBOL_GPL(omap_dm_timer_start);
395 345
396void omap_dm_timer_stop(struct omap_dm_timer *timer) 346int omap_dm_timer_stop(struct omap_dm_timer *timer)
397{ 347{
398 unsigned long rate = 0; 348 unsigned long rate = 0;
349 struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
399 350
400#ifdef CONFIG_ARCH_OMAP2PLUS 351 if (unlikely(!timer))
401 rate = clk_get_rate(timer->fclk); 352 return -EINVAL;
402#endif
403 353
404 __omap_dm_timer_stop(timer->io_base, timer->posted, rate); 354 if (!pdata->needs_manual_reset)
355 rate = clk_get_rate(timer->fclk);
356
357 __omap_dm_timer_stop(timer, timer->posted, rate);
358
359 return 0;
405} 360}
406EXPORT_SYMBOL_GPL(omap_dm_timer_stop); 361EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
407 362
408#ifdef CONFIG_ARCH_OMAP1
409
410int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) 363int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
411{ 364{
412 int n = (timer - dm_timers) << 1; 365 int ret;
413 u32 l; 366 struct dmtimer_platform_data *pdata;
414
415 l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
416 l |= source << n;
417 omap_writel(l, MOD_CONF_CTRL_1);
418 367
419 return 0; 368 if (unlikely(!timer))
420} 369 return -EINVAL;
421EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
422 370
423#else 371 pdata = timer->pdev->dev.platform_data;
424 372
425int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
426{
427 if (source < 0 || source >= 3) 373 if (source < 0 || source >= 3)
428 return -EINVAL; 374 return -EINVAL;
429 375
430 return __omap_dm_timer_set_source(timer->fclk, 376 ret = pdata->set_timer_src(timer->pdev, source);
431 dm_source_clocks[source]); 377
378 return ret;
432} 379}
433EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); 380EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
434 381
435#endif 382int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
436
437void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
438 unsigned int load) 383 unsigned int load)
439{ 384{
440 u32 l; 385 u32 l;
441 386
387 if (unlikely(!timer))
388 return -EINVAL;
389
390 omap_dm_timer_enable(timer);
442 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 391 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
443 if (autoreload) 392 if (autoreload)
444 l |= OMAP_TIMER_CTRL_AR; 393 l |= OMAP_TIMER_CTRL_AR;
@@ -448,15 +397,32 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
448 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); 397 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
449 398
450 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); 399 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
400 /* Save the context */
401 timer->context.tclr = l;
402 timer->context.tldr = load;
403 omap_dm_timer_disable(timer);
404 return 0;
451} 405}
452EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); 406EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
453 407
454/* Optimized set_load which removes costly spin wait in timer_start */ 408/* Optimized set_load which removes costly spin wait in timer_start */
455void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, 409int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
456 unsigned int load) 410 unsigned int load)
457{ 411{
458 u32 l; 412 u32 l;
459 413
414 if (unlikely(!timer))
415 return -EINVAL;
416
417 omap_dm_timer_enable(timer);
418
419 if (timer->loses_context) {
420 u32 ctx_loss_cnt_after =
421 timer->get_context_loss_count(&timer->pdev->dev);
422 if (ctx_loss_cnt_after != timer->ctx_loss_count)
423 omap_timer_restore_context(timer);
424 }
425
460 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 426 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
461 if (autoreload) { 427 if (autoreload) {
462 l |= OMAP_TIMER_CTRL_AR; 428 l |= OMAP_TIMER_CTRL_AR;
@@ -466,15 +432,25 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
466 } 432 }
467 l |= OMAP_TIMER_CTRL_ST; 433 l |= OMAP_TIMER_CTRL_ST;
468 434
469 __omap_dm_timer_load_start(timer->io_base, l, load, timer->posted); 435 __omap_dm_timer_load_start(timer, l, load, timer->posted);
436
437 /* Save the context */
438 timer->context.tclr = l;
439 timer->context.tldr = load;
440 timer->context.tcrr = load;
441 return 0;
470} 442}
471EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); 443EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
472 444
473void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, 445int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
474 unsigned int match) 446 unsigned int match)
475{ 447{
476 u32 l; 448 u32 l;
477 449
450 if (unlikely(!timer))
451 return -EINVAL;
452
453 omap_dm_timer_enable(timer);
478 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 454 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
479 if (enable) 455 if (enable)
480 l |= OMAP_TIMER_CTRL_CE; 456 l |= OMAP_TIMER_CTRL_CE;
@@ -482,14 +458,24 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
482 l &= ~OMAP_TIMER_CTRL_CE; 458 l &= ~OMAP_TIMER_CTRL_CE;
483 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 459 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
484 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); 460 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
461
462 /* Save the context */
463 timer->context.tclr = l;
464 timer->context.tmar = match;
465 omap_dm_timer_disable(timer);
466 return 0;
485} 467}
486EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); 468EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
487 469
488void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, 470int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
489 int toggle, int trigger) 471 int toggle, int trigger)
490{ 472{
491 u32 l; 473 u32 l;
492 474
475 if (unlikely(!timer))
476 return -EINVAL;
477
478 omap_dm_timer_enable(timer);
493 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 479 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
494 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | 480 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
495 OMAP_TIMER_CTRL_PT | (0x03 << 10)); 481 OMAP_TIMER_CTRL_PT | (0x03 << 10));
@@ -499,13 +485,22 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
499 l |= OMAP_TIMER_CTRL_PT; 485 l |= OMAP_TIMER_CTRL_PT;
500 l |= trigger << 10; 486 l |= trigger << 10;
501 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 487 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
488
489 /* Save the context */
490 timer->context.tclr = l;
491 omap_dm_timer_disable(timer);
492 return 0;
502} 493}
503EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); 494EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
504 495
505void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) 496int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
506{ 497{
507 u32 l; 498 u32 l;
508 499
500 if (unlikely(!timer))
501 return -EINVAL;
502
503 omap_dm_timer_enable(timer);
509 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 504 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
510 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); 505 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
511 if (prescaler >= 0x00 && prescaler <= 0x07) { 506 if (prescaler >= 0x00 && prescaler <= 0x07) {
@@ -513,13 +508,28 @@ void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
513 l |= prescaler << 2; 508 l |= prescaler << 2;
514 } 509 }
515 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 510 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
511
512 /* Save the context */
513 timer->context.tclr = l;
514 omap_dm_timer_disable(timer);
515 return 0;
516} 516}
517EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); 517EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
518 518
519void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, 519int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
520 unsigned int value) 520 unsigned int value)
521{ 521{
522 __omap_dm_timer_int_enable(timer->io_base, value); 522 if (unlikely(!timer))
523 return -EINVAL;
524
525 omap_dm_timer_enable(timer);
526 __omap_dm_timer_int_enable(timer, value);
527
528 /* Save the context */
529 timer->context.tier = value;
530 timer->context.twer = value;
531 omap_dm_timer_disable(timer);
532 return 0;
523} 533}
524EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); 534EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
525 535
@@ -527,40 +537,61 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
527{ 537{
528 unsigned int l; 538 unsigned int l;
529 539
530 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG); 540 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
541 pr_err("%s: timer not available or enabled.\n", __func__);
542 return 0;
543 }
544
545 l = __raw_readl(timer->irq_stat);
531 546
532 return l; 547 return l;
533} 548}
534EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); 549EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
535 550
536void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) 551int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
537{ 552{
538 __omap_dm_timer_write_status(timer->io_base, value); 553 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
554 return -EINVAL;
555
556 __omap_dm_timer_write_status(timer, value);
557 /* Save the context */
558 timer->context.tisr = value;
559 return 0;
539} 560}
540EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); 561EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
541 562
542unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) 563unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
543{ 564{
544 return __omap_dm_timer_read_counter(timer->io_base, timer->posted); 565 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
566 pr_err("%s: timer not iavailable or enabled.\n", __func__);
567 return 0;
568 }
569
570 return __omap_dm_timer_read_counter(timer, timer->posted);
545} 571}
546EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); 572EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
547 573
548void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) 574int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
549{ 575{
576 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
577 pr_err("%s: timer not available or enabled.\n", __func__);
578 return -EINVAL;
579 }
580
550 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); 581 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
582
583 /* Save the context */
584 timer->context.tcrr = value;
585 return 0;
551} 586}
552EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); 587EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
553 588
554int omap_dm_timers_active(void) 589int omap_dm_timers_active(void)
555{ 590{
556 int i; 591 struct omap_dm_timer *timer;
557
558 for (i = 0; i < dm_timer_count; i++) {
559 struct omap_dm_timer *timer;
560
561 timer = &dm_timers[i];
562 592
563 if (!timer->enabled) 593 list_for_each_entry(timer, &omap_timer_list, node) {
594 if (!timer->reserved)
564 continue; 595 continue;
565 596
566 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & 597 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
@@ -572,69 +603,147 @@ int omap_dm_timers_active(void)
572} 603}
573EXPORT_SYMBOL_GPL(omap_dm_timers_active); 604EXPORT_SYMBOL_GPL(omap_dm_timers_active);
574 605
575static int __init omap_dm_timer_init(void) 606/**
607 * omap_dm_timer_probe - probe function called for every registered device
608 * @pdev: pointer to current timer platform device
609 *
610 * Called by driver framework at the end of device registration for all
611 * timer devices.
612 */
613static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
576{ 614{
615 int ret;
616 unsigned long flags;
577 struct omap_dm_timer *timer; 617 struct omap_dm_timer *timer;
578 int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ 618 struct resource *mem, *irq, *ioarea;
619 struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
579 620
580 if (!(cpu_is_omap16xx() || cpu_class_is_omap2())) 621 if (!pdata) {
622 dev_err(&pdev->dev, "%s: no platform data.\n", __func__);
581 return -ENODEV; 623 return -ENODEV;
624 }
582 625
583 spin_lock_init(&dm_timer_lock); 626 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
584 627 if (unlikely(!irq)) {
585 if (cpu_class_is_omap1()) { 628 dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__);
586 dm_timers = omap1_dm_timers; 629 return -ENODEV;
587 dm_timer_count = omap1_dm_timer_count;
588 map_size = SZ_2K;
589 } else if (cpu_is_omap24xx()) {
590 dm_timers = omap2_dm_timers;
591 dm_timer_count = omap2_dm_timer_count;
592 dm_source_names = omap2_dm_source_names;
593 dm_source_clocks = omap2_dm_source_clocks;
594 } else if (cpu_is_omap34xx()) {
595 dm_timers = omap3_dm_timers;
596 dm_timer_count = omap3_dm_timer_count;
597 dm_source_names = omap3_dm_source_names;
598 dm_source_clocks = omap3_dm_source_clocks;
599 } else if (cpu_is_omap44xx()) {
600 dm_timers = omap4_dm_timers;
601 dm_timer_count = omap4_dm_timer_count;
602 dm_source_names = omap4_dm_source_names;
603 dm_source_clocks = omap4_dm_source_clocks;
604 } 630 }
605 631
606 if (cpu_class_is_omap2()) 632 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
607 for (i = 0; dm_source_names[i] != NULL; i++) 633 if (unlikely(!mem)) {
608 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); 634 dev_err(&pdev->dev, "%s: no memory resource.\n", __func__);
635 return -ENODEV;
636 }
609 637
610 if (cpu_is_omap243x()) 638 ioarea = request_mem_region(mem->start, resource_size(mem),
611 dm_timers[0].phys_base = 0x49018000; 639 pdev->name);
640 if (!ioarea) {
641 dev_err(&pdev->dev, "%s: region already claimed.\n", __func__);
642 return -EBUSY;
643 }
612 644
613 for (i = 0; i < dm_timer_count; i++) { 645 timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
614 timer = &dm_timers[i]; 646 if (!timer) {
647 dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n",
648 __func__);
649 ret = -ENOMEM;
650 goto err_free_ioregion;
651 }
615 652
616 /* Static mapping, never released */ 653 timer->io_base = ioremap(mem->start, resource_size(mem));
617 timer->io_base = ioremap(timer->phys_base, map_size); 654 if (!timer->io_base) {
618 BUG_ON(!timer->io_base); 655 dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__);
656 ret = -ENOMEM;
657 goto err_free_mem;
658 }
619 659
620#ifdef CONFIG_ARCH_OMAP2PLUS 660 timer->id = pdev->id;
621 if (cpu_class_is_omap2()) { 661 timer->irq = irq->start;
622 char clk_name[16]; 662 timer->reserved = pdata->reserved;
623 sprintf(clk_name, "gpt%d_ick", i + 1); 663 timer->pdev = pdev;
624 timer->iclk = clk_get(NULL, clk_name); 664 timer->loses_context = pdata->loses_context;
625 sprintf(clk_name, "gpt%d_fck", i + 1); 665 timer->get_context_loss_count = pdata->get_context_loss_count;
626 timer->fclk = clk_get(NULL, clk_name); 666
627 } 667 /* Skip pm_runtime_enable for OMAP1 */
668 if (!pdata->needs_manual_reset) {
669 pm_runtime_enable(&pdev->dev);
670 pm_runtime_irq_safe(&pdev->dev);
671 }
628 672
629 /* One or two timers may be set up early for sys_timer */ 673 if (!timer->reserved) {
630 if (sys_timer_reserved & (1 << i)) { 674 pm_runtime_get_sync(&pdev->dev);
631 timer->reserved = 1; 675 __omap_dm_timer_init_regs(timer);
632 timer->posted = 1; 676 pm_runtime_put(&pdev->dev);
633 }
634#endif
635 } 677 }
636 678
679 /* add the timer element to the list */
680 spin_lock_irqsave(&dm_timer_lock, flags);
681 list_add_tail(&timer->node, &omap_timer_list);
682 spin_unlock_irqrestore(&dm_timer_lock, flags);
683
684 dev_dbg(&pdev->dev, "Device Probed.\n");
685
637 return 0; 686 return 0;
687
688err_free_mem:
689 kfree(timer);
690
691err_free_ioregion:
692 release_mem_region(mem->start, resource_size(mem));
693
694 return ret;
638} 695}
639 696
640arch_initcall(omap_dm_timer_init); 697/**
698 * omap_dm_timer_remove - cleanup a registered timer device
699 * @pdev: pointer to current timer platform device
700 *
701 * Called by driver framework whenever a timer device is unregistered.
702 * In addition to freeing platform resources it also deletes the timer
703 * entry from the local list.
704 */
705static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
706{
707 struct omap_dm_timer *timer;
708 unsigned long flags;
709 int ret = -EINVAL;
710
711 spin_lock_irqsave(&dm_timer_lock, flags);
712 list_for_each_entry(timer, &omap_timer_list, node)
713 if (timer->pdev->id == pdev->id) {
714 list_del(&timer->node);
715 kfree(timer);
716 ret = 0;
717 break;
718 }
719 spin_unlock_irqrestore(&dm_timer_lock, flags);
720
721 return ret;
722}
723
724static struct platform_driver omap_dm_timer_driver = {
725 .probe = omap_dm_timer_probe,
726 .remove = omap_dm_timer_remove,
727 .driver = {
728 .name = "omap_timer",
729 },
730};
731
732static int __init omap_dm_timer_driver_init(void)
733{
734 return platform_driver_register(&omap_dm_timer_driver);
735}
736
737static void __exit omap_dm_timer_driver_exit(void)
738{
739 platform_driver_unregister(&omap_dm_timer_driver);
740}
741
742early_platform_init("earlytimer", &omap_dm_timer_driver);
743module_init(omap_dm_timer_driver_init);
744module_exit(omap_dm_timer_driver_exit);
745
746MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
747MODULE_LICENSE("GPL");
748MODULE_ALIAS("platform:" DRIVER_NAME);
749MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 3341ca4703e9..c20beb8ed38b 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -123,19 +123,11 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
123 omap_pm_set_max_mpu_wakeup_lat(dev, t); 123 omap_pm_set_max_mpu_wakeup_lat(dev, t);
124} 124}
125 125
126static struct omap_device_pm_latency omap_i2c_latency[] = {
127 [0] = {
128 .deactivate_func = omap_device_idle_hwmods,
129 .activate_func = omap_device_enable_hwmods,
130 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
131 },
132};
133
134static inline int omap2_i2c_add_bus(int bus_id) 126static inline int omap2_i2c_add_bus(int bus_id)
135{ 127{
136 int l; 128 int l;
137 struct omap_hwmod *oh; 129 struct omap_hwmod *oh;
138 struct omap_device *od; 130 struct platform_device *pdev;
139 char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN]; 131 char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
140 struct omap_i2c_bus_platform_data *pdata; 132 struct omap_i2c_bus_platform_data *pdata;
141 133
@@ -160,12 +152,12 @@ static inline int omap2_i2c_add_bus(int bus_id)
160 */ 152 */
161 if (cpu_is_omap34xx()) 153 if (cpu_is_omap34xx())
162 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; 154 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
163 od = omap_device_build(name, bus_id, oh, pdata, 155 pdev = omap_device_build(name, bus_id, oh, pdata,
164 sizeof(struct omap_i2c_bus_platform_data), 156 sizeof(struct omap_i2c_bus_platform_data),
165 omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0); 157 NULL, 0, 0);
166 WARN(IS_ERR(od), "Could not build omap_device for %s\n", name); 158 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
167 159
168 return PTR_ERR(od); 160 return PTR_ERR(pdev);
169} 161}
170#else 162#else
171static inline int omap2_i2c_add_bus(int bus_id) 163static inline int omap2_i2c_add_bus(int bus_id)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index df4b9683f17f..197ca03c3f7d 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -80,8 +80,6 @@ struct clkops {
80 * 80 *
81 * @div is the divisor that should be applied to the parent clock's rate 81 * @div is the divisor that should be applied to the parent clock's rate
82 * to produce the current clock's rate. 82 * to produce the current clock's rate.
83 *
84 * XXX @flags probably should be replaced with an struct omap_chip.
85 */ 83 */
86struct clksel_rate { 84struct clksel_rate {
87 u32 val; 85 u32 val;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 4564cc697d7f..abda2c7e499b 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -45,6 +45,15 @@ extern unsigned long long notrace omap_32k_sched_clock(void);
45 45
46extern void omap_reserve(void); 46extern void omap_reserve(void);
47 47
48void omap2420_init_early(void);
49void omap2430_init_early(void);
50void omap3430_init_early(void);
51void omap35xx_init_early(void);
52void omap3630_init_early(void);
53void am35xx_init_early(void);
54void ti816x_init_early(void);
55void omap4430_init_early(void);
56
48/* 57/*
49 * IO bases for various OMAP processors 58 * IO bases for various OMAP processors
50 * Except the tap base, rest all the io bases 59 * Except the tap base, rest all the io bases
@@ -74,7 +83,11 @@ void omap2_set_globals_sdrc(struct omap_globals *);
74void omap2_set_globals_control(struct omap_globals *); 83void omap2_set_globals_control(struct omap_globals *);
75void omap2_set_globals_prcm(struct omap_globals *); 84void omap2_set_globals_prcm(struct omap_globals *);
76 85
86void omap242x_map_io(void);
87void omap243x_map_io(void);
77void omap3_map_io(void); 88void omap3_map_io(void);
89void omap4_map_io(void);
90
78 91
79/** 92/**
80 * omap_test_timeout - busy-loop, testing a condition 93 * omap_test_timeout - busy-loop, testing a condition
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 67b3d75884cd..2f9026942229 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -44,13 +44,6 @@
44 44
45int omap_type(void); 45int omap_type(void);
46 46
47struct omap_chip_id {
48 u16 oc;
49 u8 type;
50};
51
52#define OMAP_CHIP_INIT(x) { .oc = x }
53
54/* 47/*
55 * omap_rev bits: 48 * omap_rev bits:
56 * CPU id bits (0730, 1510, 1710, 2422...) [31:16] 49 * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
@@ -60,19 +53,6 @@ struct omap_chip_id {
60unsigned int omap_rev(void); 53unsigned int omap_rev(void);
61 54
62/* 55/*
63 * Define CPU revision bits
64 *
65 * Verbose meaning of the revision bits may be different for a silicon
66 * family. This difference can be handled separately.
67 */
68#define OMAP_REVBITS_00 0x00
69#define OMAP_REVBITS_01 0x01
70#define OMAP_REVBITS_02 0x02
71#define OMAP_REVBITS_03 0x03
72#define OMAP_REVBITS_04 0x04
73#define OMAP_REVBITS_05 0x05
74
75/*
76 * Get the CPU revision for OMAP devices 56 * Get the CPU revision for OMAP devices
77 */ 57 */
78#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) 58#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
@@ -262,7 +242,7 @@ IS_OMAP_TYPE(2422, 0x2422)
262IS_OMAP_TYPE(2423, 0x2423) 242IS_OMAP_TYPE(2423, 0x2423)
263IS_OMAP_TYPE(2430, 0x2430) 243IS_OMAP_TYPE(2430, 0x2430)
264IS_OMAP_TYPE(3430, 0x3430) 244IS_OMAP_TYPE(3430, 0x3430)
265IS_OMAP_TYPE(3505, 0x3505) 245IS_OMAP_TYPE(3505, 0x3517)
266IS_OMAP_TYPE(3517, 0x3517) 246IS_OMAP_TYPE(3517, 0x3517)
267 247
268#define cpu_is_omap310() 0 248#define cpu_is_omap310() 0
@@ -354,8 +334,9 @@ IS_OMAP_TYPE(3517, 0x3517)
354 (!omap3_has_sgx()) && \ 334 (!omap3_has_sgx()) && \
355 (omap3_has_iva())) 335 (omap3_has_iva()))
356# define cpu_is_omap3530() (cpu_is_omap3430()) 336# define cpu_is_omap3530() (cpu_is_omap3430())
357# define cpu_is_omap3505() is_omap3505()
358# define cpu_is_omap3517() is_omap3517() 337# define cpu_is_omap3517() is_omap3517()
338# define cpu_is_omap3505() (cpu_is_omap3517() && \
339 !omap3_has_sgx())
359# undef cpu_is_omap3630 340# undef cpu_is_omap3630
360# define cpu_is_omap3630() is_omap363x() 341# define cpu_is_omap3630() is_omap363x()
361# define cpu_is_ti816x() is_ti816x() 342# define cpu_is_ti816x() is_ti816x()
@@ -379,35 +360,31 @@ IS_OMAP_TYPE(3517, 0x3517)
379/* Various silicon revisions for omap2 */ 360/* Various silicon revisions for omap2 */
380#define OMAP242X_CLASS 0x24200024 361#define OMAP242X_CLASS 0x24200024
381#define OMAP2420_REV_ES1_0 OMAP242X_CLASS 362#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
382#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8)) 363#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
383 364
384#define OMAP243X_CLASS 0x24300024 365#define OMAP243X_CLASS 0x24300024
385#define OMAP2430_REV_ES1_0 OMAP243X_CLASS 366#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
386 367
387#define OMAP343X_CLASS 0x34300034 368#define OMAP343X_CLASS 0x34300034
388#define OMAP3430_REV_ES1_0 OMAP343X_CLASS 369#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
389#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8)) 370#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
390#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8)) 371#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8))
391#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8)) 372#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8))
392#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8)) 373#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8))
393#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8)) 374#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8))
394 375
395#define OMAP363X_CLASS 0x36300034 376#define OMAP363X_CLASS 0x36300034
396#define OMAP3630_REV_ES1_0 OMAP363X_CLASS 377#define OMAP3630_REV_ES1_0 OMAP363X_CLASS
397#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8)) 378#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8))
398#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8)) 379#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8))
399 380
400#define OMAP35XX_CLASS 0x35000034 381#define OMAP3517_CLASS 0x35170034
401#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) 382#define OMAP3517_REV_ES1_0 OMAP3517_CLASS
402#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8)) 383#define OMAP3517_REV_ES1_1 (OMAP3517_CLASS | (0x1 << 8))
403#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
404#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
405#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
406#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
407 384
408#define TI816X_CLASS 0x81600034 385#define TI816X_CLASS 0x81600034
409#define TI8168_REV_ES1_0 TI816X_CLASS 386#define TI8168_REV_ES1_0 TI816X_CLASS
410#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) 387#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
411 388
412#define OMAP443X_CLASS 0x44300044 389#define OMAP443X_CLASS 0x44300044
413#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) 390#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
@@ -418,61 +395,6 @@ IS_OMAP_TYPE(3517, 0x3517)
418#define OMAP446X_CLASS 0x44600044 395#define OMAP446X_CLASS 0x44600044
419#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8)) 396#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
420 397
421/*
422 * omap_chip bits
423 *
424 * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
425 * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
426 * something that is only valid on that particular ES revision.
427 *
428 * These bits may be ORed together to indicate structures that are
429 * available on multiple chip types.
430 *
431 * To test whether a particular structure matches the current OMAP chip type,
432 * use omap_chip_is().
433 *
434 */
435#define CHIP_IS_OMAP2420 (1 << 0)
436#define CHIP_IS_OMAP2430 (1 << 1)
437#define CHIP_IS_OMAP3430 (1 << 2)
438#define CHIP_IS_OMAP3430ES1 (1 << 3)
439#define CHIP_IS_OMAP3430ES2 (1 << 4)
440#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
441#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
442#define CHIP_IS_OMAP3630ES1 (1 << 7)
443#define CHIP_IS_OMAP4430ES1 (1 << 8)
444#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
445#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
446#define CHIP_IS_OMAP4430ES2 (1 << 11)
447#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
448#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
449#define CHIP_IS_TI816X (1 << 14)
450#define CHIP_IS_OMAP4460ES1_0 (1 << 15)
451
452#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
453
454#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
455 CHIP_IS_OMAP4430ES2 | \
456 CHIP_IS_OMAP4430ES2_1 | \
457 CHIP_IS_OMAP4430ES2_2 | \
458 CHIP_IS_OMAP4460ES1_0)
459
460/*
461 * "GE" here represents "greater than or equal to" in terms of ES
462 * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
463 * chips at ES2 and beyond, but not, for example, any OMAP lines after
464 * OMAP3.
465 */
466#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
467 CHIP_IS_OMAP3430ES3_0 | \
468 CHIP_GE_OMAP3430ES3_1)
469#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
470 CHIP_IS_OMAP3630ES1 | \
471 CHIP_GE_OMAP3630ES1_1)
472#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \
473 CHIP_IS_OMAP3630ES1_2)
474
475int omap_chip_is(struct omap_chip_id oci);
476void omap2_check_revision(void); 398void omap2_check_revision(void);
477 399
478/* 400/*
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index eb5d16c60cd9..d11025e6e7a4 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/dmtimer.h 2 * arch/arm/plat-omap/include/plat/dmtimer.h
3 * 3 *
4 * OMAP Dual-Mode Timers 4 * OMAP Dual-Mode Timers
5 * 5 *
@@ -35,6 +35,7 @@
35#include <linux/clk.h> 35#include <linux/clk.h>
36#include <linux/delay.h> 36#include <linux/delay.h>
37#include <linux/io.h> 37#include <linux/io.h>
38#include <linux/platform_device.h>
38 39
39#ifndef __ASM_ARCH_DMTIMER_H 40#ifndef __ASM_ARCH_DMTIMER_H
40#define __ASM_ARCH_DMTIMER_H 41#define __ASM_ARCH_DMTIMER_H
@@ -59,12 +60,56 @@
59 * in OMAP4 can be distinguished. 60 * in OMAP4 can be distinguished.
60 */ 61 */
61#define OMAP_TIMER_IP_VERSION_1 0x1 62#define OMAP_TIMER_IP_VERSION_1 0x1
63
64/* timer capabilities used in hwmod database */
65#define OMAP_TIMER_SECURE 0x80000000
66#define OMAP_TIMER_ALWON 0x40000000
67#define OMAP_TIMER_HAS_PWM 0x20000000
68
69struct omap_timer_capability_dev_attr {
70 u32 timer_capability;
71};
72
62struct omap_dm_timer; 73struct omap_dm_timer;
63struct clk; 74struct clk;
64 75
76struct timer_regs {
77 u32 tidr;
78 u32 tiocp_cfg;
79 u32 tistat;
80 u32 tisr;
81 u32 tier;
82 u32 twer;
83 u32 tclr;
84 u32 tcrr;
85 u32 tldr;
86 u32 ttrg;
87 u32 twps;
88 u32 tmar;
89 u32 tcar1;
90 u32 tsicr;
91 u32 tcar2;
92 u32 tpir;
93 u32 tnir;
94 u32 tcvr;
95 u32 tocr;
96 u32 towr;
97};
98
99struct dmtimer_platform_data {
100 int (*set_timer_src)(struct platform_device *pdev, int source);
101 int timer_ip_version;
102 u32 needs_manual_reset:1;
103 bool reserved;
104
105 bool loses_context;
106
107 u32 (*get_context_loss_count)(struct device *dev);
108};
109
65struct omap_dm_timer *omap_dm_timer_request(void); 110struct omap_dm_timer *omap_dm_timer_request(void);
66struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); 111struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
67void omap_dm_timer_free(struct omap_dm_timer *timer); 112int omap_dm_timer_free(struct omap_dm_timer *timer);
68void omap_dm_timer_enable(struct omap_dm_timer *timer); 113void omap_dm_timer_enable(struct omap_dm_timer *timer);
69void omap_dm_timer_disable(struct omap_dm_timer *timer); 114void omap_dm_timer_disable(struct omap_dm_timer *timer);
70 115
@@ -73,23 +118,23 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
73u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); 118u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
74struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer); 119struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
75 120
76void omap_dm_timer_trigger(struct omap_dm_timer *timer); 121int omap_dm_timer_trigger(struct omap_dm_timer *timer);
77void omap_dm_timer_start(struct omap_dm_timer *timer); 122int omap_dm_timer_start(struct omap_dm_timer *timer);
78void omap_dm_timer_stop(struct omap_dm_timer *timer); 123int omap_dm_timer_stop(struct omap_dm_timer *timer);
79 124
80int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); 125int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
81void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); 126int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
82void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); 127int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
83void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); 128int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
84void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); 129int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
85void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); 130int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
86 131
87void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); 132int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
88 133
89unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); 134unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
90void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); 135int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
91unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); 136unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
92void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value); 137int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
93 138
94int omap_dm_timers_active(void); 139int omap_dm_timers_active(void);
95 140
@@ -98,12 +143,30 @@ int omap_dm_timers_active(void);
98 * used by dmtimer.c and sys_timer related code. 143 * used by dmtimer.c and sys_timer related code.
99 */ 144 */
100 145
101/* register offsets */ 146/*
102#define _OMAP_TIMER_ID_OFFSET 0x00 147 * The interrupt registers are different between v1 and v2 ip.
103#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10 148 * These registers are offsets from timer->iobase.
104#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14 149 */
105#define _OMAP_TIMER_STAT_OFFSET 0x18 150#define OMAP_TIMER_ID_OFFSET 0x00
106#define _OMAP_TIMER_INT_EN_OFFSET 0x1c 151#define OMAP_TIMER_OCP_CFG_OFFSET 0x10
152
153#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
154#define OMAP_TIMER_V1_STAT_OFFSET 0x18
155#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
156
157#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
158#define OMAP_TIMER_V2_IRQSTATUS 0x28
159#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
160#define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
161
162/*
163 * The functional registers have a different base on v1 and v2 ip.
164 * These registers are offsets from timer->func_base. The func_base
165 * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
166 *
167 */
168#define OMAP_TIMER_V2_FUNC_OFFSET 0x14
169
107#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20 170#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
108#define _OMAP_TIMER_CTRL_OFFSET 0x24 171#define _OMAP_TIMER_CTRL_OFFSET 0x24
109#define OMAP_TIMER_CTRL_GPOCFG (1 << 14) 172#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
@@ -147,21 +210,6 @@ int omap_dm_timers_active(void);
147/* register offsets with the write pending bit encoded */ 210/* register offsets with the write pending bit encoded */
148#define WPSHIFT 16 211#define WPSHIFT 16
149 212
150#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
151 | (WP_NONE << WPSHIFT))
152
153#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
154 | (WP_NONE << WPSHIFT))
155
156#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
157 | (WP_NONE << WPSHIFT))
158
159#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
160 | (WP_NONE << WPSHIFT))
161
162#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
163 | (WP_NONE << WPSHIFT))
164
165#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ 213#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
166 | (WP_NONE << WPSHIFT)) 214 | (WP_NONE << WPSHIFT))
167 215
@@ -209,49 +257,88 @@ int omap_dm_timers_active(void);
209 257
210struct omap_dm_timer { 258struct omap_dm_timer {
211 unsigned long phys_base; 259 unsigned long phys_base;
260 int id;
212 int irq; 261 int irq;
213#ifdef CONFIG_ARCH_OMAP2PLUS
214 struct clk *iclk, *fclk; 262 struct clk *iclk, *fclk;
215#endif 263
216 void __iomem *io_base; 264 void __iomem *io_base;
265 void __iomem *sys_stat; /* TISTAT timer status */
266 void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
267 void __iomem *irq_ena; /* irq enable */
268 void __iomem *irq_dis; /* irq disable, only on v2 ip */
269 void __iomem *pend; /* write pending */
270 void __iomem *func_base; /* function register base */
271
217 unsigned long rate; 272 unsigned long rate;
218 unsigned reserved:1; 273 unsigned reserved:1;
219 unsigned enabled:1;
220 unsigned posted:1; 274 unsigned posted:1;
275 struct timer_regs context;
276 bool loses_context;
277 int ctx_loss_count;
278 int revision;
279 struct platform_device *pdev;
280 struct list_head node;
281
282 u32 (*get_context_loss_count)(struct device *dev);
221}; 283};
222 284
223extern u32 sys_timer_reserved; 285int omap_dm_timer_prepare(struct omap_dm_timer *timer);
224void omap_dm_timer_prepare(struct omap_dm_timer *timer);
225 286
226static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg, 287static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
227 int posted) 288 int posted)
228{ 289{
229 if (posted) 290 if (posted)
230 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) 291 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
231 & (reg >> WPSHIFT))
232 cpu_relax(); 292 cpu_relax();
233 293
234 return __raw_readl(base + (reg & 0xff)); 294 return __raw_readl(timer->func_base + (reg & 0xff));
235} 295}
236 296
237static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val, 297static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
238 int posted) 298 u32 reg, u32 val, int posted)
239{ 299{
240 if (posted) 300 if (posted)
241 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) 301 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
242 & (reg >> WPSHIFT))
243 cpu_relax(); 302 cpu_relax();
244 303
245 __raw_writel(val, base + (reg & 0xff)); 304 __raw_writel(val, timer->func_base + (reg & 0xff));
305}
306
307static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
308{
309 u32 tidr;
310
311 /* Assume v1 ip if bits [31:16] are zero */
312 tidr = __raw_readl(timer->io_base);
313 if (!(tidr >> 16)) {
314 timer->revision = 1;
315 timer->sys_stat = timer->io_base +
316 OMAP_TIMER_V1_SYS_STAT_OFFSET;
317 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
318 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
319 timer->irq_dis = 0;
320 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
321 timer->func_base = timer->io_base;
322 } else {
323 timer->revision = 2;
324 timer->sys_stat = 0;
325 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
326 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
327 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
328 timer->pend = timer->io_base +
329 _OMAP_TIMER_WRITE_PEND_OFFSET +
330 OMAP_TIMER_V2_FUNC_OFFSET;
331 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
332 }
246} 333}
247 334
248/* Assumes the source clock has been set by caller */ 335/* Assumes the source clock has been set by caller */
249static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle, 336static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
250 int wakeup) 337 int autoidle, int wakeup)
251{ 338{
252 u32 l; 339 u32 l;
253 340
254 l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0); 341 l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
255 l |= 0x02 << 3; /* Set to smart-idle mode */ 342 l |= 0x02 << 3; /* Set to smart-idle mode */
256 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ 343 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
257 344
@@ -261,10 +348,10 @@ static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
261 if (wakeup) 348 if (wakeup)
262 l |= 1 << 2; 349 l |= 1 << 2;
263 350
264 __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0); 351 __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
265 352
266 /* Match hardware reset default of posted mode */ 353 /* Match hardware reset default of posted mode */
267 __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG, 354 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
268 OMAP_TIMER_CTRL_POSTED, 0); 355 OMAP_TIMER_CTRL_POSTED, 0);
269} 356}
270 357
@@ -286,18 +373,18 @@ static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
286 return ret; 373 return ret;
287} 374}
288 375
289static inline void __omap_dm_timer_stop(void __iomem *base, int posted, 376static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
290 unsigned long rate) 377 int posted, unsigned long rate)
291{ 378{
292 u32 l; 379 u32 l;
293 380
294 l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted); 381 l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
295 if (l & OMAP_TIMER_CTRL_ST) { 382 if (l & OMAP_TIMER_CTRL_ST) {
296 l &= ~0x1; 383 l &= ~0x1;
297 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted); 384 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
298#ifdef CONFIG_ARCH_OMAP2PLUS 385#ifdef CONFIG_ARCH_OMAP2PLUS
299 /* Readback to make sure write has completed */ 386 /* Readback to make sure write has completed */
300 __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted); 387 __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
301 /* 388 /*
302 * Wait for functional clock period x 3.5 to make sure that 389 * Wait for functional clock period x 3.5 to make sure that
303 * timer is stopped 390 * timer is stopped
@@ -307,34 +394,34 @@ static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
307 } 394 }
308 395
309 /* Ack possibly pending interrupt */ 396 /* Ack possibly pending interrupt */
310 __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, 397 __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
311 OMAP_TIMER_INT_OVERFLOW, 0);
312} 398}
313 399
314static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl, 400static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
315 unsigned int load, int posted) 401 u32 ctrl, unsigned int load,
402 int posted)
316{ 403{
317 __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted); 404 __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
318 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted); 405 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
319} 406}
320 407
321static inline void __omap_dm_timer_int_enable(void __iomem *base, 408static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
322 unsigned int value) 409 unsigned int value)
323{ 410{
324 __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0); 411 __raw_writel(value, timer->irq_ena);
325 __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0); 412 __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
326} 413}
327 414
328static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base, 415static inline unsigned int
329 int posted) 416__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
330{ 417{
331 return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted); 418 return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
332} 419}
333 420
334static inline void __omap_dm_timer_write_status(void __iomem *base, 421static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
335 unsigned int value) 422 unsigned int value)
336{ 423{
337 __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0); 424 __raw_writel(value, timer->irq_stat);
338} 425}
339 426
340#endif /* __ASM_ARCH_DMTIMER_H */ 427#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index d72ec85c97e6..6591875486d5 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -228,13 +228,13 @@
228 228
229#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE 229#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
230 /* 0x4d000000 --> 0xfd200000 */ 230 /* 0x4d000000 --> 0xfd200000 */
231#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
232#define OMAP44XX_EMIF2_SIZE SZ_1M 231#define OMAP44XX_EMIF2_SIZE SZ_1M
232#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
233 233
234#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE 234#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
235 /* 0x4e000000 --> 0xfd300000 */ 235 /* 0x4e000000 --> 0xfd300000 */
236#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
237#define OMAP44XX_DMM_SIZE SZ_1M 236#define OMAP44XX_DMM_SIZE SZ_1M
237#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
238/* 238/*
239 * ---------------------------------------------------------------------------- 239 * ----------------------------------------------------------------------------
240 * Omap specific register access 240 * Omap specific register access
@@ -300,7 +300,7 @@ static inline void omap44xx_map_common_io(void)
300#endif 300#endif
301 301
302extern void omap2_init_common_infrastructure(void); 302extern void omap2_init_common_infrastructure(void);
303extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, 303extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
304 struct omap_sdrc_params *sdrc_cs1); 304 struct omap_sdrc_params *sdrc_cs1);
305 305
306#define __arch_ioremap omap_ioremap 306#define __arch_ioremap omap_ioremap
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 9882c657b2d4..8fa74e2c9d6e 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -25,9 +25,7 @@
25#define __ASM_ARCH_OMAP_MCBSP_H 25#define __ASM_ARCH_OMAP_MCBSP_H
26 26
27#include <linux/spinlock.h> 27#include <linux/spinlock.h>
28 28#include <linux/clk.h>
29#include <mach/hardware.h>
30#include <plat/clock.h>
31 29
32/* macro for building platform_device for McBSP ports */ 30/* macro for building platform_device for McBSP ports */
33#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \ 31#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
@@ -40,104 +38,60 @@ static struct platform_device omap_mcbsp##port_nr = { \
40#define MCBSP_CONFIG_TYPE3 0x3 38#define MCBSP_CONFIG_TYPE3 0x3
41#define MCBSP_CONFIG_TYPE4 0x4 39#define MCBSP_CONFIG_TYPE4 0x4
42 40
43#define OMAP7XX_MCBSP1_BASE 0xfffb1000 41/* McBSP register numbers. Register address offset = num * reg_step */
44#define OMAP7XX_MCBSP2_BASE 0xfffb1800 42enum {
45 43 /* Common registers */
46#define OMAP1510_MCBSP1_BASE 0xe1011800 44 OMAP_MCBSP_REG_SPCR2 = 4,
47#define OMAP1510_MCBSP2_BASE 0xfffb1000 45 OMAP_MCBSP_REG_SPCR1,
48#define OMAP1510_MCBSP3_BASE 0xe1017000 46 OMAP_MCBSP_REG_RCR2,
49 47 OMAP_MCBSP_REG_RCR1,
50#define OMAP1610_MCBSP1_BASE 0xe1011800 48 OMAP_MCBSP_REG_XCR2,
51#define OMAP1610_MCBSP2_BASE 0xfffb1000 49 OMAP_MCBSP_REG_XCR1,
52#define OMAP1610_MCBSP3_BASE 0xe1017000 50 OMAP_MCBSP_REG_SRGR2,
53 51 OMAP_MCBSP_REG_SRGR1,
54#ifdef CONFIG_ARCH_OMAP1 52 OMAP_MCBSP_REG_MCR2,
55 53 OMAP_MCBSP_REG_MCR1,
56#define OMAP_MCBSP_REG_DRR2 0x00 54 OMAP_MCBSP_REG_RCERA,
57#define OMAP_MCBSP_REG_DRR1 0x02 55 OMAP_MCBSP_REG_RCERB,
58#define OMAP_MCBSP_REG_DXR2 0x04 56 OMAP_MCBSP_REG_XCERA,
59#define OMAP_MCBSP_REG_DXR1 0x06 57 OMAP_MCBSP_REG_XCERB,
60#define OMAP_MCBSP_REG_DRR 0x02 58 OMAP_MCBSP_REG_PCR0,
61#define OMAP_MCBSP_REG_DXR 0x06 59 OMAP_MCBSP_REG_RCERC,
62#define OMAP_MCBSP_REG_SPCR2 0x08 60 OMAP_MCBSP_REG_RCERD,
63#define OMAP_MCBSP_REG_SPCR1 0x0a 61 OMAP_MCBSP_REG_XCERC,
64#define OMAP_MCBSP_REG_RCR2 0x0c 62 OMAP_MCBSP_REG_XCERD,
65#define OMAP_MCBSP_REG_RCR1 0x0e 63 OMAP_MCBSP_REG_RCERE,
66#define OMAP_MCBSP_REG_XCR2 0x10 64 OMAP_MCBSP_REG_RCERF,
67#define OMAP_MCBSP_REG_XCR1 0x12 65 OMAP_MCBSP_REG_XCERE,
68#define OMAP_MCBSP_REG_SRGR2 0x14 66 OMAP_MCBSP_REG_XCERF,
69#define OMAP_MCBSP_REG_SRGR1 0x16 67 OMAP_MCBSP_REG_RCERG,
70#define OMAP_MCBSP_REG_MCR2 0x18 68 OMAP_MCBSP_REG_RCERH,
71#define OMAP_MCBSP_REG_MCR1 0x1a 69 OMAP_MCBSP_REG_XCERG,
72#define OMAP_MCBSP_REG_RCERA 0x1c 70 OMAP_MCBSP_REG_XCERH,
73#define OMAP_MCBSP_REG_RCERB 0x1e 71
74#define OMAP_MCBSP_REG_XCERA 0x20 72 /* OMAP1-OMAP2420 registers */
75#define OMAP_MCBSP_REG_XCERB 0x22 73 OMAP_MCBSP_REG_DRR2 = 0,
76#define OMAP_MCBSP_REG_PCR0 0x24 74 OMAP_MCBSP_REG_DRR1,
77#define OMAP_MCBSP_REG_RCERC 0x26 75 OMAP_MCBSP_REG_DXR2,
78#define OMAP_MCBSP_REG_RCERD 0x28 76 OMAP_MCBSP_REG_DXR1,
79#define OMAP_MCBSP_REG_XCERC 0x2A 77
80#define OMAP_MCBSP_REG_XCERD 0x2C 78 /* OMAP2430 and onwards */
81#define OMAP_MCBSP_REG_RCERE 0x2E 79 OMAP_MCBSP_REG_DRR = 0,
82#define OMAP_MCBSP_REG_RCERF 0x30 80 OMAP_MCBSP_REG_DXR = 2,
83#define OMAP_MCBSP_REG_XCERE 0x32 81 OMAP_MCBSP_REG_SYSCON = 35,
84#define OMAP_MCBSP_REG_XCERF 0x34 82 OMAP_MCBSP_REG_THRSH2,
85#define OMAP_MCBSP_REG_RCERG 0x36 83 OMAP_MCBSP_REG_THRSH1,
86#define OMAP_MCBSP_REG_RCERH 0x38 84 OMAP_MCBSP_REG_IRQST = 40,
87#define OMAP_MCBSP_REG_XCERG 0x3A 85 OMAP_MCBSP_REG_IRQEN,
88#define OMAP_MCBSP_REG_XCERH 0x3C 86 OMAP_MCBSP_REG_WAKEUPEN,
89 87 OMAP_MCBSP_REG_XCCR,
90/* Dummy defines, these are not available on omap1 */ 88 OMAP_MCBSP_REG_RCCR,
91#define OMAP_MCBSP_REG_XCCR 0x00 89 OMAP_MCBSP_REG_XBUFFSTAT,
92#define OMAP_MCBSP_REG_RCCR 0x00 90 OMAP_MCBSP_REG_RBUFFSTAT,
93 91 OMAP_MCBSP_REG_SSELCR,
94#else 92};
95
96#define OMAP_MCBSP_REG_DRR2 0x00
97#define OMAP_MCBSP_REG_DRR1 0x04
98#define OMAP_MCBSP_REG_DXR2 0x08
99#define OMAP_MCBSP_REG_DXR1 0x0C
100#define OMAP_MCBSP_REG_DRR 0x00
101#define OMAP_MCBSP_REG_DXR 0x08
102#define OMAP_MCBSP_REG_SPCR2 0x10
103#define OMAP_MCBSP_REG_SPCR1 0x14
104#define OMAP_MCBSP_REG_RCR2 0x18
105#define OMAP_MCBSP_REG_RCR1 0x1C
106#define OMAP_MCBSP_REG_XCR2 0x20
107#define OMAP_MCBSP_REG_XCR1 0x24
108#define OMAP_MCBSP_REG_SRGR2 0x28
109#define OMAP_MCBSP_REG_SRGR1 0x2C
110#define OMAP_MCBSP_REG_MCR2 0x30
111#define OMAP_MCBSP_REG_MCR1 0x34
112#define OMAP_MCBSP_REG_RCERA 0x38
113#define OMAP_MCBSP_REG_RCERB 0x3C
114#define OMAP_MCBSP_REG_XCERA 0x40
115#define OMAP_MCBSP_REG_XCERB 0x44
116#define OMAP_MCBSP_REG_PCR0 0x48
117#define OMAP_MCBSP_REG_RCERC 0x4C
118#define OMAP_MCBSP_REG_RCERD 0x50
119#define OMAP_MCBSP_REG_XCERC 0x54
120#define OMAP_MCBSP_REG_XCERD 0x58
121#define OMAP_MCBSP_REG_RCERE 0x5C
122#define OMAP_MCBSP_REG_RCERF 0x60
123#define OMAP_MCBSP_REG_XCERE 0x64
124#define OMAP_MCBSP_REG_XCERF 0x68
125#define OMAP_MCBSP_REG_RCERG 0x6C
126#define OMAP_MCBSP_REG_RCERH 0x70
127#define OMAP_MCBSP_REG_XCERG 0x74
128#define OMAP_MCBSP_REG_XCERH 0x78
129#define OMAP_MCBSP_REG_SYSCON 0x8C
130#define OMAP_MCBSP_REG_THRSH2 0x90
131#define OMAP_MCBSP_REG_THRSH1 0x94
132#define OMAP_MCBSP_REG_IRQST 0xA0
133#define OMAP_MCBSP_REG_IRQEN 0xA4
134#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
135#define OMAP_MCBSP_REG_XCCR 0xAC
136#define OMAP_MCBSP_REG_RCCR 0xB0
137#define OMAP_MCBSP_REG_XBUFFSTAT 0xB4
138#define OMAP_MCBSP_REG_RBUFFSTAT 0xB8
139#define OMAP_MCBSP_REG_SSELCR 0xBC
140 93
94/* OMAP3 sidetone control registers */
141#define OMAP_ST_REG_REV 0x00 95#define OMAP_ST_REG_REV 0x00
142#define OMAP_ST_REG_SYSCONFIG 0x10 96#define OMAP_ST_REG_SYSCONFIG 0x10
143#define OMAP_ST_REG_IRQSTATUS 0x18 97#define OMAP_ST_REG_IRQSTATUS 0x18
@@ -146,8 +100,6 @@ static struct platform_device omap_mcbsp##port_nr = { \
146#define OMAP_ST_REG_SFIRCR 0x28 100#define OMAP_ST_REG_SFIRCR 0x28
147#define OMAP_ST_REG_SSELCR 0x2C 101#define OMAP_ST_REG_SSELCR 0x2C
148 102
149#endif
150
151/************************** McBSP SPCR1 bit definitions ***********************/ 103/************************** McBSP SPCR1 bit definitions ***********************/
152#define RRST 0x0001 104#define RRST 0x0001
153#define RRDY 0x0002 105#define RRDY 0x0002
@@ -344,20 +296,20 @@ typedef enum {
344struct omap_mcbsp_ops { 296struct omap_mcbsp_ops {
345 void (*request)(unsigned int); 297 void (*request)(unsigned int);
346 void (*free)(unsigned int); 298 void (*free)(unsigned int);
347 int (*set_clks_src)(u8, u8);
348}; 299};
349 300
350struct omap_mcbsp_platform_data { 301struct omap_mcbsp_platform_data {
351 unsigned long phys_base;
352 u8 dma_rx_sync, dma_tx_sync;
353 u16 rx_irq, tx_irq;
354 struct omap_mcbsp_ops *ops; 302 struct omap_mcbsp_ops *ops;
355#ifdef CONFIG_ARCH_OMAP3
356 /* Sidetone block for McBSP 2 and 3 */
357 unsigned long phys_base_st;
358#endif
359 u16 buffer_size; 303 u16 buffer_size;
360 unsigned int mcbsp_config_type; 304 u8 reg_size;
305 u8 reg_step;
306
307 /* McBSP platform and instance specific features */
308 bool has_wakeup; /* Wakeup capability */
309 bool has_ccr; /* Transceiver has configuration control registers */
310 int (*enable_st_clock)(unsigned int, bool);
311 int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
312 int (*mux_signal)(struct device *dev, const char *signal, const char *src);
361}; 313};
362 314
363struct omap_mcbsp_st_data { 315struct omap_mcbsp_st_data {
@@ -389,14 +341,12 @@ struct omap_mcbsp {
389 spinlock_t lock; 341 spinlock_t lock;
390 struct omap_mcbsp_platform_data *pdata; 342 struct omap_mcbsp_platform_data *pdata;
391 struct clk *fclk; 343 struct clk *fclk;
392#ifdef CONFIG_ARCH_OMAP3
393 struct omap_mcbsp_st_data *st_data; 344 struct omap_mcbsp_st_data *st_data;
394 int dma_op_mode; 345 int dma_op_mode;
395 u16 max_tx_thres; 346 u16 max_tx_thres;
396 u16 max_rx_thres; 347 u16 max_rx_thres;
397#endif
398 void *reg_cache; 348 void *reg_cache;
399 unsigned int mcbsp_config_type; 349 int reg_cache_size;
400}; 350};
401 351
402/** 352/**
@@ -408,16 +358,10 @@ struct omap_mcbsp_dev_attr {
408}; 358};
409 359
410extern struct omap_mcbsp **mcbsp_ptr; 360extern struct omap_mcbsp **mcbsp_ptr;
411extern int omap_mcbsp_count, omap_mcbsp_cache_size; 361extern int omap_mcbsp_count;
412
413#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
414#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
415 362
416int omap_mcbsp_init(void); 363int omap_mcbsp_init(void);
417void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
418 struct omap_mcbsp_platform_data *config, int size);
419void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 364void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
420#ifdef CONFIG_ARCH_OMAP3
421void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); 365void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
422void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); 366void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
423u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); 367u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
@@ -426,18 +370,6 @@ u16 omap_mcbsp_get_fifo_size(unsigned int id);
426u16 omap_mcbsp_get_tx_delay(unsigned int id); 370u16 omap_mcbsp_get_tx_delay(unsigned int id);
427u16 omap_mcbsp_get_rx_delay(unsigned int id); 371u16 omap_mcbsp_get_rx_delay(unsigned int id);
428int omap_mcbsp_get_dma_op_mode(unsigned int id); 372int omap_mcbsp_get_dma_op_mode(unsigned int id);
429#else
430static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
431{ }
432static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
433{ }
434static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
435static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
436static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
437static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
438static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
439static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
440#endif
441int omap_mcbsp_request(unsigned int id); 373int omap_mcbsp_request(unsigned int id);
442void omap_mcbsp_free(unsigned int id); 374void omap_mcbsp_free(unsigned int id);
443void omap_mcbsp_start(unsigned int id, int tx, int rx); 375void omap_mcbsp_start(unsigned int id, int tx, int rx);
@@ -453,21 +385,11 @@ void omap2_mcbsp1_mux_fsr_src(u8 mux);
453int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); 385int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
454int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream); 386int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
455 387
456#ifdef CONFIG_ARCH_OMAP3
457/* Sidetone specific API */ 388/* Sidetone specific API */
458int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); 389int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
459int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain); 390int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
460int omap_st_enable(unsigned int id); 391int omap_st_enable(unsigned int id);
461int omap_st_disable(unsigned int id); 392int omap_st_disable(unsigned int id);
462int omap_st_is_enabled(unsigned int id); 393int omap_st_is_enabled(unsigned int id);
463#else
464static inline int omap_st_set_chgain(unsigned int id, int channel,
465 s16 chgain) { return 0; }
466static inline int omap_st_get_chgain(unsigned int id, int channel,
467 s16 *chgain) { return 0; }
468static inline int omap_st_enable(unsigned int id) { return 0; }
469static inline int omap_st_disable(unsigned int id) { return 0; }
470static inline int omap_st_is_enabled(unsigned int id) { return 0; }
471#endif
472 394
473#endif 395#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index ee405b36df4b..12c5b0c345bf 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -68,7 +68,7 @@ extern struct device omap_device_parent;
68 * 68 *
69 */ 69 */
70struct omap_device { 70struct omap_device {
71 struct platform_device pdev; 71 struct platform_device *pdev;
72 struct omap_hwmod **hwmods; 72 struct omap_hwmod **hwmods;
73 struct omap_device_pm_latency *pm_lats; 73 struct omap_device_pm_latency *pm_lats;
74 u32 dev_wakeup_lat; 74 u32 dev_wakeup_lat;
@@ -88,25 +88,20 @@ int omap_device_shutdown(struct platform_device *pdev);
88 88
89/* Core code interface */ 89/* Core code interface */
90 90
91int omap_device_count_resources(struct omap_device *od); 91struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
92int omap_device_fill_resources(struct omap_device *od, struct resource *res);
93
94struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
95 struct omap_hwmod *oh, void *pdata, 92 struct omap_hwmod *oh, void *pdata,
96 int pdata_len, 93 int pdata_len,
97 struct omap_device_pm_latency *pm_lats, 94 struct omap_device_pm_latency *pm_lats,
98 int pm_lats_cnt, int is_early_device); 95 int pm_lats_cnt, int is_early_device);
99 96
100struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, 97struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
101 struct omap_hwmod **oh, int oh_cnt, 98 struct omap_hwmod **oh, int oh_cnt,
102 void *pdata, int pdata_len, 99 void *pdata, int pdata_len,
103 struct omap_device_pm_latency *pm_lats, 100 struct omap_device_pm_latency *pm_lats,
104 int pm_lats_cnt, int is_early_device); 101 int pm_lats_cnt, int is_early_device);
105 102
106int omap_device_register(struct omap_device *od);
107int omap_early_device_register(struct omap_device *od);
108
109void __iomem *omap_device_get_rt_va(struct omap_device *od); 103void __iomem *omap_device_get_rt_va(struct omap_device *od);
104struct device *omap_device_get_by_hwmod_name(const char *oh_name);
110 105
111/* OMAP PM interface */ 106/* OMAP PM interface */
112int omap_device_align_pm_lat(struct platform_device *pdev, 107int omap_device_align_pm_lat(struct platform_device *pdev,
@@ -122,11 +117,6 @@ int omap_device_enable_hwmods(struct omap_device *od);
122int omap_device_disable_clocks(struct omap_device *od); 117int omap_device_disable_clocks(struct omap_device *od);
123int omap_device_enable_clocks(struct omap_device *od); 118int omap_device_enable_clocks(struct omap_device *od);
124 119
125static inline void omap_device_disable_idle_on_suspend(struct omap_device *od)
126{
127 od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
128}
129
130/* 120/*
131 * Entries should be kept in latency order ascending 121 * Entries should be kept in latency order ascending
132 * 122 *
@@ -157,6 +147,17 @@ struct omap_device_pm_latency {
157#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1) 147#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
158 148
159/* Get omap_device pointer from platform_device pointer */ 149/* Get omap_device pointer from platform_device pointer */
160#define to_omap_device(x) container_of((x), struct omap_device, pdev) 150static inline struct omap_device *to_omap_device(struct platform_device *pdev)
151{
152 return pdev ? pdev->archdata.od : NULL;
153}
154
155static inline
156void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
157{
158 struct omap_device *od = to_omap_device(pdev);
159
160 od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
161}
161 162
162#endif 163#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 0e329ca88a70..5419f1a2aaa4 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -496,7 +496,6 @@ struct omap_hwmod_class {
496 * @_state: internal-use hwmod state 496 * @_state: internal-use hwmod state
497 * @_postsetup_state: internal-use state to leave the hwmod in after _setup() 497 * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
498 * @flags: hwmod flags (documented below) 498 * @flags: hwmod flags (documented below)
499 * @omap_chip: OMAP chips this hwmod is present on
500 * @_lock: spinlock serializing operations on this hwmod 499 * @_lock: spinlock serializing operations on this hwmod
501 * @node: list node for hwmod list (internal use) 500 * @node: list node for hwmod list (internal use)
502 * 501 *
@@ -526,7 +525,6 @@ struct omap_hwmod {
526 char *clkdm_name; 525 char *clkdm_name;
527 struct clockdomain *clkdm; 526 struct clockdomain *clkdm;
528 char *vdd_name; 527 char *vdd_name;
529 struct voltagedomain *voltdm;
530 struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ 528 struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
531 struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ 529 struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
532 void *dev_attr; 530 void *dev_attr;
@@ -545,7 +543,6 @@ struct omap_hwmod {
545 u8 _int_flags; 543 u8 _int_flags;
546 u8 _state; 544 u8 _state;
547 u8 _postsetup_state; 545 u8 _postsetup_state;
548 const struct omap_chip_id omap_chip;
549}; 546};
550 547
551int omap_hwmod_register(struct omap_hwmod **ohs); 548int omap_hwmod_register(struct omap_hwmod **ohs);
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
new file mode 100644
index 000000000000..0a6a482ec014
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -0,0 +1,20 @@
1/*
2 * OMAP Voltage Management Routines
3 *
4 * Copyright (C) 2011, Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_OMAP_VOLTAGE_H
12#define __ARCH_ARM_OMAP_VOLTAGE_H
13
14struct voltagedomain;
15
16struct voltagedomain *voltdm_lookup(const char *name);
17int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
18unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
19
20#endif
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 6c62af108710..4b15cd7926d7 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -24,45 +24,40 @@
24#include <linux/slab.h> 24#include <linux/slab.h>
25 25
26#include <plat/mcbsp.h> 26#include <plat/mcbsp.h>
27#include <plat/omap_device.h>
28#include <linux/pm_runtime.h> 27#include <linux/pm_runtime.h>
29 28
30/* XXX These "sideways" includes are a sign that something is wrong */
31#include "../mach-omap2/cm2xxx_3xxx.h"
32#include "../mach-omap2/cm-regbits-34xx.h"
33
34struct omap_mcbsp **mcbsp_ptr; 29struct omap_mcbsp **mcbsp_ptr;
35int omap_mcbsp_count, omap_mcbsp_cache_size; 30int omap_mcbsp_count;
31
32#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
33#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
36 34
37static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) 35static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
38{ 36{
39 if (cpu_class_is_omap1()) { 37 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
40 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; 38
41 __raw_writew((u16)val, mcbsp->io_base + reg); 39 if (mcbsp->pdata->reg_size == 2) {
42 } else if (cpu_is_omap2420()) { 40 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
43 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val; 41 __raw_writew((u16)val, addr);
44 __raw_writew((u16)val, mcbsp->io_base + reg);
45 } else { 42 } else {
46 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val; 43 ((u32 *)mcbsp->reg_cache)[reg] = val;
47 __raw_writel(val, mcbsp->io_base + reg); 44 __raw_writel(val, addr);
48 } 45 }
49} 46}
50 47
51static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) 48static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
52{ 49{
53 if (cpu_class_is_omap1()) { 50 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
54 return !from_cache ? __raw_readw(mcbsp->io_base + reg) : 51
55 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)]; 52 if (mcbsp->pdata->reg_size == 2) {
56 } else if (cpu_is_omap2420()) { 53 return !from_cache ? __raw_readw(addr) :
57 return !from_cache ? __raw_readw(mcbsp->io_base + reg) : 54 ((u16 *)mcbsp->reg_cache)[reg];
58 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
59 } else { 55 } else {
60 return !from_cache ? __raw_readl(mcbsp->io_base + reg) : 56 return !from_cache ? __raw_readl(addr) :
61 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)]; 57 ((u32 *)mcbsp->reg_cache)[reg];
62 } 58 }
63} 59}
64 60
65#ifdef CONFIG_ARCH_OMAP3
66static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) 61static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
67{ 62{
68 __raw_writel(val, mcbsp->st_data->io_base_st + reg); 63 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
@@ -72,7 +67,6 @@ static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
72{ 67{
73 return __raw_readl(mcbsp->st_data->io_base_st + reg); 68 return __raw_readl(mcbsp->st_data->io_base_st + reg);
74} 69}
75#endif
76 70
77#define MCBSP_READ(mcbsp, reg) \ 71#define MCBSP_READ(mcbsp, reg) \
78 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0) 72 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
@@ -187,7 +181,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
187 MCBSP_WRITE(mcbsp, MCR2, config->mcr2); 181 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
188 MCBSP_WRITE(mcbsp, MCR1, config->mcr1); 182 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
189 MCBSP_WRITE(mcbsp, PCR0, config->pcr0); 183 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
190 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 184 if (mcbsp->pdata->has_ccr) {
191 MCBSP_WRITE(mcbsp, XCCR, config->xccr); 185 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
192 MCBSP_WRITE(mcbsp, RCCR, config->rccr); 186 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
193 } 187 }
@@ -239,46 +233,28 @@ int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
239 } 233 }
240 mcbsp = id_to_mcbsp_ptr(id); 234 mcbsp = id_to_mcbsp_ptr(id);
241 235
242 data_reg = mcbsp->phys_dma_base; 236 if (mcbsp->pdata->reg_size == 2) {
243
244 if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
245 if (stream) 237 if (stream)
246 data_reg += OMAP_MCBSP_REG_DRR1; 238 data_reg = OMAP_MCBSP_REG_DRR1;
247 else 239 else
248 data_reg += OMAP_MCBSP_REG_DXR1; 240 data_reg = OMAP_MCBSP_REG_DXR1;
249 } else { 241 } else {
250 if (stream) 242 if (stream)
251 data_reg += OMAP_MCBSP_REG_DRR; 243 data_reg = OMAP_MCBSP_REG_DRR;
252 else 244 else
253 data_reg += OMAP_MCBSP_REG_DXR; 245 data_reg = OMAP_MCBSP_REG_DXR;
254 } 246 }
255 247
256 return data_reg; 248 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
257} 249}
258EXPORT_SYMBOL(omap_mcbsp_dma_reg_params); 250EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
259 251
260#ifdef CONFIG_ARCH_OMAP3
261static struct omap_device *find_omap_device_by_dev(struct device *dev)
262{
263 struct platform_device *pdev = container_of(dev,
264 struct platform_device, dev);
265 return container_of(pdev, struct omap_device, pdev);
266}
267
268static void omap_st_on(struct omap_mcbsp *mcbsp) 252static void omap_st_on(struct omap_mcbsp *mcbsp)
269{ 253{
270 unsigned int w; 254 unsigned int w;
271 struct omap_device *od;
272 255
273 od = find_omap_device_by_dev(mcbsp->dev); 256 if (mcbsp->pdata->enable_st_clock)
274 257 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
275 /*
276 * Sidetone uses McBSP ICLK - which must not idle when sidetones
277 * are enabled or sidetones start sounding ugly.
278 */
279 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
280 w &= ~(1 << (mcbsp->id - 2));
281 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
282 258
283 /* Enable McBSP Sidetone */ 259 /* Enable McBSP Sidetone */
284 w = MCBSP_READ(mcbsp, SSELCR); 260 w = MCBSP_READ(mcbsp, SSELCR);
@@ -292,9 +268,6 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
292static void omap_st_off(struct omap_mcbsp *mcbsp) 268static void omap_st_off(struct omap_mcbsp *mcbsp)
293{ 269{
294 unsigned int w; 270 unsigned int w;
295 struct omap_device *od;
296
297 od = find_omap_device_by_dev(mcbsp->dev);
298 271
299 w = MCBSP_ST_READ(mcbsp, SSELCR); 272 w = MCBSP_ST_READ(mcbsp, SSELCR);
300 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN)); 273 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
@@ -302,17 +275,13 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
302 w = MCBSP_READ(mcbsp, SSELCR); 275 w = MCBSP_READ(mcbsp, SSELCR);
303 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); 276 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
304 277
305 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); 278 if (mcbsp->pdata->enable_st_clock)
306 w |= 1 << (mcbsp->id - 2); 279 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
307 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
308} 280}
309 281
310static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) 282static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
311{ 283{
312 u16 val, i; 284 u16 val, i;
313 struct omap_device *od;
314
315 od = find_omap_device_by_dev(mcbsp->dev);
316 285
317 val = MCBSP_ST_READ(mcbsp, SSELCR); 286 val = MCBSP_ST_READ(mcbsp, SSELCR);
318 287
@@ -340,9 +309,6 @@ static void omap_st_chgain(struct omap_mcbsp *mcbsp)
340{ 309{
341 u16 w; 310 u16 w;
342 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 311 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
343 struct omap_device *od;
344
345 od = find_omap_device_by_dev(mcbsp->dev);
346 312
347 w = MCBSP_ST_READ(mcbsp, SSELCR); 313 w = MCBSP_ST_READ(mcbsp, SSELCR);
348 314
@@ -525,14 +491,13 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
525{ 491{
526 struct omap_mcbsp *mcbsp; 492 struct omap_mcbsp *mcbsp;
527 493
528 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
529 return;
530
531 if (!omap_mcbsp_check_valid_id(id)) { 494 if (!omap_mcbsp_check_valid_id(id)) {
532 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 495 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
533 return; 496 return;
534 } 497 }
535 mcbsp = id_to_mcbsp_ptr(id); 498 mcbsp = id_to_mcbsp_ptr(id);
499 if (mcbsp->pdata->buffer_size == 0)
500 return;
536 501
537 if (threshold && threshold <= mcbsp->max_tx_thres) 502 if (threshold && threshold <= mcbsp->max_tx_thres)
538 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); 503 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
@@ -548,14 +513,13 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
548{ 513{
549 struct omap_mcbsp *mcbsp; 514 struct omap_mcbsp *mcbsp;
550 515
551 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
552 return;
553
554 if (!omap_mcbsp_check_valid_id(id)) { 516 if (!omap_mcbsp_check_valid_id(id)) {
555 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 517 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
556 return; 518 return;
557 } 519 }
558 mcbsp = id_to_mcbsp_ptr(id); 520 mcbsp = id_to_mcbsp_ptr(id);
521 if (mcbsp->pdata->buffer_size == 0)
522 return;
559 523
560 if (threshold && threshold <= mcbsp->max_rx_thres) 524 if (threshold && threshold <= mcbsp->max_rx_thres)
561 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); 525 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
@@ -625,6 +589,8 @@ u16 omap_mcbsp_get_tx_delay(unsigned int id)
625 return -ENODEV; 589 return -ENODEV;
626 } 590 }
627 mcbsp = id_to_mcbsp_ptr(id); 591 mcbsp = id_to_mcbsp_ptr(id);
592 if (mcbsp->pdata->buffer_size == 0)
593 return 0;
628 594
629 /* Returns the number of free locations in the buffer */ 595 /* Returns the number of free locations in the buffer */
630 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); 596 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
@@ -648,6 +614,8 @@ u16 omap_mcbsp_get_rx_delay(unsigned int id)
648 return -ENODEV; 614 return -ENODEV;
649 } 615 }
650 mcbsp = id_to_mcbsp_ptr(id); 616 mcbsp = id_to_mcbsp_ptr(id);
617 if (mcbsp->pdata->buffer_size == 0)
618 return 0;
651 619
652 /* Returns the number of used locations in the buffer */ 620 /* Returns the number of used locations in the buffer */
653 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT); 621 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
@@ -683,46 +651,6 @@ int omap_mcbsp_get_dma_op_mode(unsigned int id)
683} 651}
684EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode); 652EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
685 653
686static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
687{
688 struct omap_device *od;
689
690 od = find_omap_device_by_dev(mcbsp->dev);
691 /*
692 * Enable wakup behavior, smart idle and all wakeups
693 * REVISIT: some wakeups may be unnecessary
694 */
695 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
696 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
697 }
698}
699
700static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
701{
702 struct omap_device *od;
703
704 od = find_omap_device_by_dev(mcbsp->dev);
705
706 /*
707 * Disable wakup behavior, smart idle and all wakeups
708 */
709 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
710 /*
711 * HW bug workaround - If no_idle mode is taken, we need to
712 * go to smart_idle before going to always_idle, or the
713 * device will not hit retention anymore.
714 */
715
716 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
717 }
718}
719#else
720static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
721static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
722static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
723static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
724#endif
725
726int omap_mcbsp_request(unsigned int id) 654int omap_mcbsp_request(unsigned int id)
727{ 655{
728 struct omap_mcbsp *mcbsp; 656 struct omap_mcbsp *mcbsp;
@@ -735,7 +663,7 @@ int omap_mcbsp_request(unsigned int id)
735 } 663 }
736 mcbsp = id_to_mcbsp_ptr(id); 664 mcbsp = id_to_mcbsp_ptr(id);
737 665
738 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL); 666 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
739 if (!reg_cache) { 667 if (!reg_cache) {
740 return -ENOMEM; 668 return -ENOMEM;
741 } 669 }
@@ -757,8 +685,9 @@ int omap_mcbsp_request(unsigned int id)
757 685
758 pm_runtime_get_sync(mcbsp->dev); 686 pm_runtime_get_sync(mcbsp->dev);
759 687
760 /* Do procedure specific to omap34xx arch, if applicable */ 688 /* Enable wakeup behavior */
761 omap34xx_mcbsp_request(mcbsp); 689 if (mcbsp->pdata->has_wakeup)
690 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
762 691
763 /* 692 /*
764 * Make sure that transmitter, receiver and sample-rate generator are 693 * Make sure that transmitter, receiver and sample-rate generator are
@@ -795,8 +724,9 @@ err_clk_disable:
795 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) 724 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
796 mcbsp->pdata->ops->free(id); 725 mcbsp->pdata->ops->free(id);
797 726
798 /* Do procedure specific to omap34xx arch, if applicable */ 727 /* Disable wakeup behavior */
799 omap34xx_mcbsp_free(mcbsp); 728 if (mcbsp->pdata->has_wakeup)
729 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
800 730
801 pm_runtime_put_sync(mcbsp->dev); 731 pm_runtime_put_sync(mcbsp->dev);
802 732
@@ -825,8 +755,9 @@ void omap_mcbsp_free(unsigned int id)
825 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) 755 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
826 mcbsp->pdata->ops->free(id); 756 mcbsp->pdata->ops->free(id);
827 757
828 /* Do procedure specific to omap34xx arch, if applicable */ 758 /* Disable wakeup behavior */
829 omap34xx_mcbsp_free(mcbsp); 759 if (mcbsp->pdata->has_wakeup)
760 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
830 761
831 pm_runtime_put_sync(mcbsp->dev); 762 pm_runtime_put_sync(mcbsp->dev);
832 763
@@ -866,7 +797,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
866 } 797 }
867 mcbsp = id_to_mcbsp_ptr(id); 798 mcbsp = id_to_mcbsp_ptr(id);
868 799
869 if (cpu_is_omap34xx()) 800 if (mcbsp->st_data)
870 omap_st_start(mcbsp); 801 omap_st_start(mcbsp);
871 802
872 /* Only enable SRG, if McBSP is master */ 803 /* Only enable SRG, if McBSP is master */
@@ -904,7 +835,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
904 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); 835 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
905 } 836 }
906 837
907 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 838 if (mcbsp->pdata->has_ccr) {
908 /* Release the transmitter and receiver */ 839 /* Release the transmitter and receiver */
909 w = MCBSP_READ_CACHE(mcbsp, XCCR); 840 w = MCBSP_READ_CACHE(mcbsp, XCCR);
910 w &= ~(tx ? XDISABLE : 0); 841 w &= ~(tx ? XDISABLE : 0);
@@ -934,7 +865,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
934 865
935 /* Reset transmitter */ 866 /* Reset transmitter */
936 tx &= 1; 867 tx &= 1;
937 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 868 if (mcbsp->pdata->has_ccr) {
938 w = MCBSP_READ_CACHE(mcbsp, XCCR); 869 w = MCBSP_READ_CACHE(mcbsp, XCCR);
939 w |= (tx ? XDISABLE : 0); 870 w |= (tx ? XDISABLE : 0);
940 MCBSP_WRITE(mcbsp, XCCR, w); 871 MCBSP_WRITE(mcbsp, XCCR, w);
@@ -944,7 +875,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
944 875
945 /* Reset receiver */ 876 /* Reset receiver */
946 rx &= 1; 877 rx &= 1;
947 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 878 if (mcbsp->pdata->has_ccr) {
948 w = MCBSP_READ_CACHE(mcbsp, RCCR); 879 w = MCBSP_READ_CACHE(mcbsp, RCCR);
949 w |= (rx ? RDISABLE : 0); 880 w |= (rx ? RDISABLE : 0);
950 MCBSP_WRITE(mcbsp, RCCR, w); 881 MCBSP_WRITE(mcbsp, RCCR, w);
@@ -961,39 +892,72 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
961 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); 892 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
962 } 893 }
963 894
964 if (cpu_is_omap34xx()) 895 if (mcbsp->st_data)
965 omap_st_stop(mcbsp); 896 omap_st_stop(mcbsp);
966} 897}
967EXPORT_SYMBOL(omap_mcbsp_stop); 898EXPORT_SYMBOL(omap_mcbsp_stop);
968 899
969/*
970 * The following functions are only required on an OMAP1-only build.
971 * mach-omap2/mcbsp.c contains the real functions
972 */
973#ifndef CONFIG_ARCH_OMAP2PLUS
974int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) 900int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
975{ 901{
976 WARN(1, "%s: should never be called on an OMAP1-only kernel\n", 902 struct omap_mcbsp *mcbsp;
977 __func__); 903 const char *src;
978 return -EINVAL; 904
905 if (!omap_mcbsp_check_valid_id(id)) {
906 pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
907 return -EINVAL;
908 }
909 mcbsp = id_to_mcbsp_ptr(id);
910
911 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
912 src = "clks_ext";
913 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
914 src = "clks_fclk";
915 else
916 return -EINVAL;
917
918 if (mcbsp->pdata->set_clk_src)
919 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
920 else
921 return -EINVAL;
979} 922}
923EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
980 924
981void omap2_mcbsp1_mux_clkr_src(u8 mux) 925void omap2_mcbsp1_mux_clkr_src(u8 mux)
982{ 926{
983 WARN(1, "%s: should never be called on an OMAP1-only kernel\n", 927 struct omap_mcbsp *mcbsp;
984 __func__); 928 const char *src;
985 return; 929
930 if (mux == CLKR_SRC_CLKR)
931 src = "clkr";
932 else if (mux == CLKR_SRC_CLKX)
933 src = "clkx";
934 else
935 return;
936
937 mcbsp = id_to_mcbsp_ptr(0);
938 if (mcbsp->pdata->mux_signal)
939 mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src);
986} 940}
941EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
987 942
988void omap2_mcbsp1_mux_fsr_src(u8 mux) 943void omap2_mcbsp1_mux_fsr_src(u8 mux)
989{ 944{
990 WARN(1, "%s: should never be called on an OMAP1-only kernel\n", 945 struct omap_mcbsp *mcbsp;
991 __func__); 946 const char *src;
992 return; 947
948 if (mux == FSR_SRC_FSR)
949 src = "fsr";
950 else if (mux == FSR_SRC_FSX)
951 src = "fsx";
952 else
953 return;
954
955 mcbsp = id_to_mcbsp_ptr(0);
956 if (mcbsp->pdata->mux_signal)
957 mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src);
993} 958}
994#endif 959EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
995 960
996#ifdef CONFIG_ARCH_OMAP3
997#define max_thres(m) (mcbsp->pdata->buffer_size) 961#define max_thres(m) (mcbsp->pdata->buffer_size)
998#define valid_threshold(m, val) ((val) <= max_thres(m)) 962#define valid_threshold(m, val) ((val) <= max_thres(m))
999#define THRESHOLD_PROP_BUILDER(prop) \ 963#define THRESHOLD_PROP_BUILDER(prop) \
@@ -1084,6 +1048,17 @@ unlock:
1084 1048
1085static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store); 1049static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1086 1050
1051static const struct attribute *additional_attrs[] = {
1052 &dev_attr_max_tx_thres.attr,
1053 &dev_attr_max_rx_thres.attr,
1054 &dev_attr_dma_op_mode.attr,
1055 NULL,
1056};
1057
1058static const struct attribute_group additional_attr_group = {
1059 .attrs = (struct attribute **)additional_attrs,
1060};
1061
1087static ssize_t st_taps_show(struct device *dev, 1062static ssize_t st_taps_show(struct device *dev,
1088 struct device_attribute *attr, char *buf) 1063 struct device_attribute *attr, char *buf)
1089{ 1064{
@@ -1142,27 +1117,6 @@ out:
1142 1117
1143static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store); 1118static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1144 1119
1145static const struct attribute *additional_attrs[] = {
1146 &dev_attr_max_tx_thres.attr,
1147 &dev_attr_max_rx_thres.attr,
1148 &dev_attr_dma_op_mode.attr,
1149 NULL,
1150};
1151
1152static const struct attribute_group additional_attr_group = {
1153 .attrs = (struct attribute **)additional_attrs,
1154};
1155
1156static inline int __devinit omap_additional_add(struct device *dev)
1157{
1158 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1159}
1160
1161static inline void __devexit omap_additional_remove(struct device *dev)
1162{
1163 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1164}
1165
1166static const struct attribute *sidetone_attrs[] = { 1120static const struct attribute *sidetone_attrs[] = {
1167 &dev_attr_st_taps.attr, 1121 &dev_attr_st_taps.attr,
1168 NULL, 1122 NULL,
@@ -1172,10 +1126,9 @@ static const struct attribute_group sidetone_attr_group = {
1172 .attrs = (struct attribute **)sidetone_attrs, 1126 .attrs = (struct attribute **)sidetone_attrs,
1173}; 1127};
1174 1128
1175static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) 1129static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
1130 struct resource *res)
1176{ 1131{
1177 struct platform_device *pdev;
1178 struct resource *res;
1179 struct omap_mcbsp_st_data *st_data; 1132 struct omap_mcbsp_st_data *st_data;
1180 int err; 1133 int err;
1181 1134
@@ -1185,9 +1138,6 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1185 goto err1; 1138 goto err1;
1186 } 1139 }
1187 1140
1188 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1189
1190 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1191 st_data->io_base_st = ioremap(res->start, resource_size(res)); 1141 st_data->io_base_st = ioremap(res->start, resource_size(res));
1192 if (!st_data->io_base_st) { 1142 if (!st_data->io_base_st) {
1193 err = -ENOMEM; 1143 err = -ENOMEM;
@@ -1214,59 +1164,10 @@ static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1214{ 1164{
1215 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 1165 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1216 1166
1217 if (st_data) { 1167 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1218 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group); 1168 iounmap(st_data->io_base_st);
1219 iounmap(st_data->io_base_st); 1169 kfree(st_data);
1220 kfree(st_data);
1221 }
1222}
1223
1224static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1225{
1226 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1227 if (cpu_is_omap34xx()) {
1228 /*
1229 * Initially configure the maximum thresholds to a safe value.
1230 * The McBSP FIFO usage with these values should not go under
1231 * 16 locations.
1232 * If the whole FIFO without safety buffer is used, than there
1233 * is a possibility that the DMA will be not able to push the
1234 * new data on time, causing channel shifts in runtime.
1235 */
1236 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1237 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1238 /*
1239 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1240 * for mcbsp2 instances.
1241 */
1242 if (omap_additional_add(mcbsp->dev))
1243 dev_warn(mcbsp->dev,
1244 "Unable to create additional controls\n");
1245
1246 if (mcbsp->id == 2 || mcbsp->id == 3)
1247 if (omap_st_add(mcbsp))
1248 dev_warn(mcbsp->dev,
1249 "Unable to create sidetone controls\n");
1250
1251 } else {
1252 mcbsp->max_tx_thres = -EINVAL;
1253 mcbsp->max_rx_thres = -EINVAL;
1254 }
1255}
1256
1257static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1258{
1259 if (cpu_is_omap34xx()) {
1260 omap_additional_remove(mcbsp->dev);
1261
1262 if (mcbsp->id == 2 || mcbsp->id == 3)
1263 omap_st_remove(mcbsp);
1264 }
1265} 1170}
1266#else
1267static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1268static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1269#endif /* CONFIG_ARCH_OMAP3 */
1270 1171
1271/* 1172/*
1272 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 1173 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
@@ -1316,7 +1217,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1316 } 1217 }
1317 } 1218 }
1318 mcbsp->phys_base = res->start; 1219 mcbsp->phys_base = res->start;
1319 omap_mcbsp_cache_size = resource_size(res); 1220 mcbsp->reg_cache_size = resource_size(res);
1320 mcbsp->io_base = ioremap(res->start, resource_size(res)); 1221 mcbsp->io_base = ioremap(res->start, resource_size(res));
1321 if (!mcbsp->io_base) { 1222 if (!mcbsp->io_base) {
1322 ret = -ENOMEM; 1223 ret = -ENOMEM;
@@ -1364,15 +1265,52 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1364 mcbsp->pdata = pdata; 1265 mcbsp->pdata = pdata;
1365 mcbsp->dev = &pdev->dev; 1266 mcbsp->dev = &pdev->dev;
1366 mcbsp_ptr[id] = mcbsp; 1267 mcbsp_ptr[id] = mcbsp;
1367 mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
1368 platform_set_drvdata(pdev, mcbsp); 1268 platform_set_drvdata(pdev, mcbsp);
1369 pm_runtime_enable(mcbsp->dev); 1269 pm_runtime_enable(mcbsp->dev);
1370 1270
1371 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */ 1271 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1372 omap34xx_device_init(mcbsp); 1272 if (mcbsp->pdata->buffer_size) {
1273 /*
1274 * Initially configure the maximum thresholds to a safe value.
1275 * The McBSP FIFO usage with these values should not go under
1276 * 16 locations.
1277 * If the whole FIFO without safety buffer is used, than there
1278 * is a possibility that the DMA will be not able to push the
1279 * new data on time, causing channel shifts in runtime.
1280 */
1281 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1282 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1283
1284 ret = sysfs_create_group(&mcbsp->dev->kobj,
1285 &additional_attr_group);
1286 if (ret) {
1287 dev_err(mcbsp->dev,
1288 "Unable to create additional controls\n");
1289 goto err_thres;
1290 }
1291 } else {
1292 mcbsp->max_tx_thres = -EINVAL;
1293 mcbsp->max_rx_thres = -EINVAL;
1294 }
1295
1296 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1297 if (res) {
1298 ret = omap_st_add(mcbsp, res);
1299 if (ret) {
1300 dev_err(mcbsp->dev,
1301 "Unable to create sidetone controls\n");
1302 goto err_st;
1303 }
1304 }
1373 1305
1374 return 0; 1306 return 0;
1375 1307
1308err_st:
1309 if (mcbsp->pdata->buffer_size)
1310 sysfs_remove_group(&mcbsp->dev->kobj,
1311 &additional_attr_group);
1312err_thres:
1313 clk_put(mcbsp->fclk);
1376err_res: 1314err_res:
1377 iounmap(mcbsp->io_base); 1315 iounmap(mcbsp->io_base);
1378err_ioremap: 1316err_ioremap:
@@ -1392,7 +1330,12 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1392 mcbsp->pdata->ops->free) 1330 mcbsp->pdata->ops->free)
1393 mcbsp->pdata->ops->free(mcbsp->id); 1331 mcbsp->pdata->ops->free(mcbsp->id);
1394 1332
1395 omap34xx_device_exit(mcbsp); 1333 if (mcbsp->pdata->buffer_size)
1334 sysfs_remove_group(&mcbsp->dev->kobj,
1335 &additional_attr_group);
1336
1337 if (mcbsp->st_data)
1338 omap_st_remove(mcbsp);
1396 1339
1397 clk_put(mcbsp->fclk); 1340 clk_put(mcbsp->fclk);
1398 1341
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 02609eee0562..cd90bedd9306 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -85,6 +85,8 @@
85#include <linux/clk.h> 85#include <linux/clk.h>
86#include <linux/clkdev.h> 86#include <linux/clkdev.h>
87#include <linux/pm_runtime.h> 87#include <linux/pm_runtime.h>
88#include <linux/of.h>
89#include <linux/notifier.h>
88 90
89#include <plat/omap_device.h> 91#include <plat/omap_device.h>
90#include <plat/omap_hwmod.h> 92#include <plat/omap_hwmod.h>
@@ -94,6 +96,23 @@
94#define USE_WAKEUP_LAT 0 96#define USE_WAKEUP_LAT 0
95#define IGNORE_WAKEUP_LAT 1 97#define IGNORE_WAKEUP_LAT 1
96 98
99static int omap_device_register(struct platform_device *pdev);
100static int omap_early_device_register(struct platform_device *pdev);
101static struct omap_device *omap_device_alloc(struct platform_device *pdev,
102 struct omap_hwmod **ohs, int oh_cnt,
103 struct omap_device_pm_latency *pm_lats,
104 int pm_lats_cnt);
105static void omap_device_delete(struct omap_device *od);
106
107
108static struct omap_device_pm_latency omap_default_latency[] = {
109 {
110 .deactivate_func = omap_device_idle_hwmods,
111 .activate_func = omap_device_enable_hwmods,
112 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
113 }
114};
115
97/* Private functions */ 116/* Private functions */
98 117
99/** 118/**
@@ -114,7 +133,7 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
114{ 133{
115 struct timespec a, b, c; 134 struct timespec a, b, c;
116 135
117 pr_debug("omap_device: %s: activating\n", od->pdev.name); 136 dev_dbg(&od->pdev->dev, "omap_device: activating\n");
118 137
119 while (od->pm_lat_level > 0) { 138 while (od->pm_lat_level > 0) {
120 struct omap_device_pm_latency *odpl; 139 struct omap_device_pm_latency *odpl;
@@ -138,25 +157,24 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
138 c = timespec_sub(b, a); 157 c = timespec_sub(b, a);
139 act_lat = timespec_to_ns(&c); 158 act_lat = timespec_to_ns(&c);
140 159
141 pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time " 160 dev_dbg(&od->pdev->dev,
142 "%llu nsec\n", od->pdev.name, od->pm_lat_level, 161 "omap_device: pm_lat %d: activate: elapsed time "
143 act_lat); 162 "%llu nsec\n", od->pm_lat_level, act_lat);
144 163
145 if (act_lat > odpl->activate_lat) { 164 if (act_lat > odpl->activate_lat) {
146 odpl->activate_lat_worst = act_lat; 165 odpl->activate_lat_worst = act_lat;
147 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { 166 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
148 odpl->activate_lat = act_lat; 167 odpl->activate_lat = act_lat;
149 pr_warning("omap_device: %s.%d: new worst case " 168 dev_dbg(&od->pdev->dev,
150 "activate latency %d: %llu\n", 169 "new worst case activate latency "
151 od->pdev.name, od->pdev.id, 170 "%d: %llu\n",
152 od->pm_lat_level, act_lat); 171 od->pm_lat_level, act_lat);
153 } else 172 } else
154 pr_warning("omap_device: %s.%d: activate " 173 dev_warn(&od->pdev->dev,
155 "latency %d higher than exptected. " 174 "activate latency %d "
156 "(%llu > %d)\n", 175 "higher than exptected. (%llu > %d)\n",
157 od->pdev.name, od->pdev.id, 176 od->pm_lat_level, act_lat,
158 od->pm_lat_level, act_lat, 177 odpl->activate_lat);
159 odpl->activate_lat);
160 } 178 }
161 179
162 od->dev_wakeup_lat -= odpl->activate_lat; 180 od->dev_wakeup_lat -= odpl->activate_lat;
@@ -183,7 +201,7 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
183{ 201{
184 struct timespec a, b, c; 202 struct timespec a, b, c;
185 203
186 pr_debug("omap_device: %s: deactivating\n", od->pdev.name); 204 dev_dbg(&od->pdev->dev, "omap_device: deactivating\n");
187 205
188 while (od->pm_lat_level < od->pm_lats_cnt) { 206 while (od->pm_lat_level < od->pm_lats_cnt) {
189 struct omap_device_pm_latency *odpl; 207 struct omap_device_pm_latency *odpl;
@@ -206,28 +224,26 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
206 c = timespec_sub(b, a); 224 c = timespec_sub(b, a);
207 deact_lat = timespec_to_ns(&c); 225 deact_lat = timespec_to_ns(&c);
208 226
209 pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time " 227 dev_dbg(&od->pdev->dev,
210 "%llu nsec\n", od->pdev.name, od->pm_lat_level, 228 "omap_device: pm_lat %d: deactivate: elapsed time "
211 deact_lat); 229 "%llu nsec\n", od->pm_lat_level, deact_lat);
212 230
213 if (deact_lat > odpl->deactivate_lat) { 231 if (deact_lat > odpl->deactivate_lat) {
214 odpl->deactivate_lat_worst = deact_lat; 232 odpl->deactivate_lat_worst = deact_lat;
215 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { 233 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
216 odpl->deactivate_lat = deact_lat; 234 odpl->deactivate_lat = deact_lat;
217 pr_warning("omap_device: %s.%d: new worst case " 235 dev_dbg(&od->pdev->dev,
218 "deactivate latency %d: %llu\n", 236 "new worst case deactivate latency "
219 od->pdev.name, od->pdev.id, 237 "%d: %llu\n",
220 od->pm_lat_level, deact_lat); 238 od->pm_lat_level, deact_lat);
221 } else 239 } else
222 pr_warning("omap_device: %s.%d: deactivate " 240 dev_warn(&od->pdev->dev,
223 "latency %d higher than exptected. " 241 "deactivate latency %d "
224 "(%llu > %d)\n", 242 "higher than exptected. (%llu > %d)\n",
225 od->pdev.name, od->pdev.id, 243 od->pm_lat_level, deact_lat,
226 od->pm_lat_level, deact_lat, 244 odpl->deactivate_lat);
227 odpl->deactivate_lat);
228 } 245 }
229 246
230
231 od->dev_wakeup_lat += odpl->activate_lat; 247 od->dev_wakeup_lat += odpl->activate_lat;
232 248
233 od->pm_lat_level++; 249 od->pm_lat_level++;
@@ -245,28 +261,27 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
245 if (!clk_alias || !clk_name) 261 if (!clk_alias || !clk_name)
246 return; 262 return;
247 263
248 pr_debug("omap_device: %s: Creating %s -> %s\n", 264 dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);
249 dev_name(&od->pdev.dev), clk_alias, clk_name);
250 265
251 r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias); 266 r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
252 if (!IS_ERR(r)) { 267 if (!IS_ERR(r)) {
253 pr_warning("omap_device: %s: alias %s already exists\n", 268 dev_warn(&od->pdev->dev,
254 dev_name(&od->pdev.dev), clk_alias); 269 "alias %s already exists\n", clk_alias);
255 clk_put(r); 270 clk_put(r);
256 return; 271 return;
257 } 272 }
258 273
259 r = omap_clk_get_by_name(clk_name); 274 r = omap_clk_get_by_name(clk_name);
260 if (IS_ERR(r)) { 275 if (IS_ERR(r)) {
261 pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n", 276 dev_err(&od->pdev->dev,
262 dev_name(&od->pdev.dev), clk_name); 277 "omap_clk_get_by_name for %s failed\n", clk_name);
263 return; 278 return;
264 } 279 }
265 280
266 l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev)); 281 l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev->dev));
267 if (!l) { 282 if (!l) {
268 pr_err("omap_device: %s: clkdev_alloc for %s failed\n", 283 dev_err(&od->pdev->dev,
269 dev_name(&od->pdev.dev), clk_alias); 284 "clkdev_alloc for %s failed\n", clk_alias);
270 return; 285 return;
271 } 286 }
272 287
@@ -304,6 +319,96 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od,
304} 319}
305 320
306 321
322static struct dev_pm_domain omap_device_pm_domain;
323
324/**
325 * omap_device_build_from_dt - build an omap_device with multiple hwmods
326 * @pdev_name: name of the platform_device driver to use
327 * @pdev_id: this platform_device's connection ID
328 * @oh: ptr to the single omap_hwmod that backs this omap_device
329 * @pdata: platform_data ptr to associate with the platform_device
330 * @pdata_len: amount of memory pointed to by @pdata
331 * @pm_lats: pointer to a omap_device_pm_latency array for this device
332 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
333 * @is_early_device: should the device be registered as an early device or not
334 *
335 * Function for building an omap_device already registered from device-tree
336 *
337 * Returns 0 or PTR_ERR() on error.
338 */
339static int omap_device_build_from_dt(struct platform_device *pdev)
340{
341 struct omap_hwmod **hwmods;
342 struct omap_device *od;
343 struct omap_hwmod *oh;
344 struct device_node *node = pdev->dev.of_node;
345 const char *oh_name;
346 int oh_cnt, i, ret = 0;
347
348 oh_cnt = of_property_count_strings(node, "ti,hwmods");
349 if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
350 dev_warn(&pdev->dev, "No 'hwmods' to build omap_device\n");
351 return -ENODEV;
352 }
353
354 hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
355 if (!hwmods) {
356 ret = -ENOMEM;
357 goto odbfd_exit;
358 }
359
360 for (i = 0; i < oh_cnt; i++) {
361 of_property_read_string_index(node, "ti,hwmods", i, &oh_name);
362 oh = omap_hwmod_lookup(oh_name);
363 if (!oh) {
364 dev_err(&pdev->dev, "Cannot lookup hwmod '%s'\n",
365 oh_name);
366 ret = -EINVAL;
367 goto odbfd_exit1;
368 }
369 hwmods[i] = oh;
370 }
371
372 od = omap_device_alloc(pdev, hwmods, oh_cnt, NULL, 0);
373 if (!od) {
374 dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
375 oh_name);
376 ret = PTR_ERR(od);
377 goto odbfd_exit1;
378 }
379
380 if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
381 omap_device_disable_idle_on_suspend(pdev);
382
383 pdev->dev.pm_domain = &omap_device_pm_domain;
384
385odbfd_exit1:
386 kfree(hwmods);
387odbfd_exit:
388 return ret;
389}
390
391static int _omap_device_notifier_call(struct notifier_block *nb,
392 unsigned long event, void *dev)
393{
394 struct platform_device *pdev = to_platform_device(dev);
395
396 switch (event) {
397 case BUS_NOTIFY_ADD_DEVICE:
398 if (pdev->dev.of_node)
399 omap_device_build_from_dt(pdev);
400 break;
401
402 case BUS_NOTIFY_DEL_DEVICE:
403 if (pdev->archdata.od)
404 omap_device_delete(pdev->archdata.od);
405 break;
406 }
407
408 return NOTIFY_DONE;
409}
410
411
307/* Public functions for use by core code */ 412/* Public functions for use by core code */
308 413
309/** 414/**
@@ -343,7 +448,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
343 * much memory to allocate before calling 448 * much memory to allocate before calling
344 * omap_device_fill_resources(). Returns the count. 449 * omap_device_fill_resources(). Returns the count.
345 */ 450 */
346int omap_device_count_resources(struct omap_device *od) 451static int omap_device_count_resources(struct omap_device *od)
347{ 452{
348 int c = 0; 453 int c = 0;
349 int i; 454 int i;
@@ -352,7 +457,7 @@ int omap_device_count_resources(struct omap_device *od)
352 c += omap_hwmod_count_resources(od->hwmods[i]); 457 c += omap_hwmod_count_resources(od->hwmods[i]);
353 458
354 pr_debug("omap_device: %s: counted %d total resources across %d " 459 pr_debug("omap_device: %s: counted %d total resources across %d "
355 "hwmods\n", od->pdev.name, c, od->hwmods_cnt); 460 "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
356 461
357 return c; 462 return c;
358} 463}
@@ -374,7 +479,8 @@ int omap_device_count_resources(struct omap_device *od)
374 * functions to get device resources. Hacking around the existing 479 * functions to get device resources. Hacking around the existing
375 * platform_device code wastes memory. Returns 0. 480 * platform_device code wastes memory. Returns 0.
376 */ 481 */
377int omap_device_fill_resources(struct omap_device *od, struct resource *res) 482static int omap_device_fill_resources(struct omap_device *od,
483 struct resource *res)
378{ 484{
379 int c = 0; 485 int c = 0;
380 int i, r; 486 int i, r;
@@ -389,6 +495,113 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res)
389} 495}
390 496
391/** 497/**
498 * omap_device_alloc - allocate an omap_device
499 * @pdev: platform_device that will be included in this omap_device
500 * @oh: ptr to the single omap_hwmod that backs this omap_device
501 * @pdata: platform_data ptr to associate with the platform_device
502 * @pdata_len: amount of memory pointed to by @pdata
503 * @pm_lats: pointer to a omap_device_pm_latency array for this device
504 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
505 *
506 * Convenience function for allocating an omap_device structure and filling
507 * hwmods, resources and pm_latency attributes.
508 *
509 * Returns an struct omap_device pointer or ERR_PTR() on error;
510 */
511static struct omap_device *omap_device_alloc(struct platform_device *pdev,
512 struct omap_hwmod **ohs, int oh_cnt,
513 struct omap_device_pm_latency *pm_lats,
514 int pm_lats_cnt)
515{
516 int ret = -ENOMEM;
517 struct omap_device *od;
518 struct resource *res = NULL;
519 int i, res_count;
520 struct omap_hwmod **hwmods;
521
522 od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
523 if (!od) {
524 ret = -ENOMEM;
525 goto oda_exit1;
526 }
527 od->hwmods_cnt = oh_cnt;
528
529 hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
530 if (!hwmods)
531 goto oda_exit2;
532
533 od->hwmods = hwmods;
534 od->pdev = pdev;
535
536 /*
537 * HACK: Ideally the resources from DT should match, and hwmod
538 * should just add the missing ones. Since the name is not
539 * properly populated by DT, stick to hwmod resources only.
540 */
541 if (pdev->num_resources && pdev->resource)
542 dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
543 __func__, pdev->num_resources);
544
545 res_count = omap_device_count_resources(od);
546 if (res_count > 0) {
547 dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
548 __func__, res_count);
549 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
550 if (!res)
551 goto oda_exit3;
552
553 omap_device_fill_resources(od, res);
554
555 ret = platform_device_add_resources(pdev, res, res_count);
556 kfree(res);
557
558 if (ret)
559 goto oda_exit3;
560 }
561
562 if (!pm_lats) {
563 pm_lats = omap_default_latency;
564 pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
565 }
566
567 od->pm_lats_cnt = pm_lats_cnt;
568 od->pm_lats = kmemdup(pm_lats,
569 sizeof(struct omap_device_pm_latency) * pm_lats_cnt,
570 GFP_KERNEL);
571 if (!od->pm_lats)
572 goto oda_exit3;
573
574 pdev->archdata.od = od;
575
576 for (i = 0; i < oh_cnt; i++) {
577 hwmods[i]->od = od;
578 _add_hwmod_clocks_clkdev(od, hwmods[i]);
579 }
580
581 return od;
582
583oda_exit3:
584 kfree(hwmods);
585oda_exit2:
586 kfree(od);
587oda_exit1:
588 dev_err(&pdev->dev, "omap_device: build failed (%d)\n", ret);
589
590 return ERR_PTR(ret);
591}
592
593static void omap_device_delete(struct omap_device *od)
594{
595 if (!od)
596 return;
597
598 od->pdev->archdata.od = NULL;
599 kfree(od->pm_lats);
600 kfree(od->hwmods);
601 kfree(od);
602}
603
604/**
392 * omap_device_build - build and register an omap_device with one omap_hwmod 605 * omap_device_build - build and register an omap_device with one omap_hwmod
393 * @pdev_name: name of the platform_device driver to use 606 * @pdev_name: name of the platform_device driver to use
394 * @pdev_id: this platform_device's connection ID 607 * @pdev_id: this platform_device's connection ID
@@ -405,7 +618,7 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res)
405 * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise, 618 * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
406 * passes along the return value of omap_device_build_ss(). 619 * passes along the return value of omap_device_build_ss().
407 */ 620 */
408struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, 621struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
409 struct omap_hwmod *oh, void *pdata, 622 struct omap_hwmod *oh, void *pdata,
410 int pdata_len, 623 int pdata_len,
411 struct omap_device_pm_latency *pm_lats, 624 struct omap_device_pm_latency *pm_lats,
@@ -438,18 +651,15 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
438 * platform_device record. Returns an ERR_PTR() on error, or passes 651 * platform_device record. Returns an ERR_PTR() on error, or passes
439 * along the return value of omap_device_register(). 652 * along the return value of omap_device_register().
440 */ 653 */
441struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, 654struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
442 struct omap_hwmod **ohs, int oh_cnt, 655 struct omap_hwmod **ohs, int oh_cnt,
443 void *pdata, int pdata_len, 656 void *pdata, int pdata_len,
444 struct omap_device_pm_latency *pm_lats, 657 struct omap_device_pm_latency *pm_lats,
445 int pm_lats_cnt, int is_early_device) 658 int pm_lats_cnt, int is_early_device)
446{ 659{
447 int ret = -ENOMEM; 660 int ret = -ENOMEM;
661 struct platform_device *pdev;
448 struct omap_device *od; 662 struct omap_device *od;
449 char *pdev_name2;
450 struct resource *res = NULL;
451 int i, res_count;
452 struct omap_hwmod **hwmods;
453 663
454 if (!ohs || oh_cnt == 0 || !pdev_name) 664 if (!ohs || oh_cnt == 0 || !pdev_name)
455 return ERR_PTR(-EINVAL); 665 return ERR_PTR(-EINVAL);
@@ -457,72 +667,40 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
457 if (!pdata && pdata_len > 0) 667 if (!pdata && pdata_len > 0)
458 return ERR_PTR(-EINVAL); 668 return ERR_PTR(-EINVAL);
459 669
460 pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name, 670 pdev = platform_device_alloc(pdev_name, pdev_id);
461 oh_cnt); 671 if (!pdev) {
462 672 ret = -ENOMEM;
463 od = kzalloc(sizeof(struct omap_device), GFP_KERNEL); 673 goto odbs_exit;
464 if (!od) 674 }
465 return ERR_PTR(-ENOMEM);
466 675
467 od->hwmods_cnt = oh_cnt; 676 /* Set the dev_name early to allow dev_xxx in omap_device_alloc */
677 if (pdev->id != -1)
678 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
679 else
680 dev_set_name(&pdev->dev, "%s", pdev->name);
468 681
469 hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, 682 od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt);
470 GFP_KERNEL); 683 if (!od)
471 if (!hwmods)
472 goto odbs_exit1; 684 goto odbs_exit1;
473 685
474 memcpy(hwmods, ohs, sizeof(struct omap_hwmod *) * oh_cnt); 686 ret = platform_device_add_data(pdev, pdata, pdata_len);
475 od->hwmods = hwmods;
476
477 pdev_name2 = kzalloc(strlen(pdev_name) + 1, GFP_KERNEL);
478 if (!pdev_name2)
479 goto odbs_exit2;
480 strcpy(pdev_name2, pdev_name);
481
482 od->pdev.name = pdev_name2;
483 od->pdev.id = pdev_id;
484
485 res_count = omap_device_count_resources(od);
486 if (res_count > 0) {
487 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
488 if (!res)
489 goto odbs_exit3;
490 }
491 omap_device_fill_resources(od, res);
492
493 od->pdev.num_resources = res_count;
494 od->pdev.resource = res;
495
496 ret = platform_device_add_data(&od->pdev, pdata, pdata_len);
497 if (ret) 687 if (ret)
498 goto odbs_exit4; 688 goto odbs_exit2;
499
500 od->pm_lats = pm_lats;
501 od->pm_lats_cnt = pm_lats_cnt;
502 689
503 if (is_early_device) 690 if (is_early_device)
504 ret = omap_early_device_register(od); 691 ret = omap_early_device_register(pdev);
505 else 692 else
506 ret = omap_device_register(od); 693 ret = omap_device_register(pdev);
507
508 for (i = 0; i < oh_cnt; i++) {
509 hwmods[i]->od = od;
510 _add_hwmod_clocks_clkdev(od, hwmods[i]);
511 }
512
513 if (ret) 694 if (ret)
514 goto odbs_exit4; 695 goto odbs_exit2;
515 696
516 return od; 697 return pdev;
517 698
518odbs_exit4:
519 kfree(res);
520odbs_exit3:
521 kfree(pdev_name2);
522odbs_exit2: 699odbs_exit2:
523 kfree(hwmods); 700 omap_device_delete(od);
524odbs_exit1: 701odbs_exit1:
525 kfree(od); 702 platform_device_put(pdev);
703odbs_exit:
526 704
527 pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret); 705 pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
528 706
@@ -538,11 +716,11 @@ odbs_exit1:
538 * platform_early_add_device() on the underlying platform_device. 716 * platform_early_add_device() on the underlying platform_device.
539 * Returns 0 by default. 717 * Returns 0 by default.
540 */ 718 */
541int omap_early_device_register(struct omap_device *od) 719static int omap_early_device_register(struct platform_device *pdev)
542{ 720{
543 struct platform_device *devices[1]; 721 struct platform_device *devices[1];
544 722
545 devices[0] = &(od->pdev); 723 devices[0] = pdev;
546 early_platform_add_devices(devices, 1); 724 early_platform_add_devices(devices, 1);
547 return 0; 725 return 0;
548} 726}
@@ -638,13 +816,13 @@ static struct dev_pm_domain omap_device_pm_domain = {
638 * platform_device_register() on the underlying platform_device. 816 * platform_device_register() on the underlying platform_device.
639 * Returns the return value of platform_device_register(). 817 * Returns the return value of platform_device_register().
640 */ 818 */
641int omap_device_register(struct omap_device *od) 819static int omap_device_register(struct platform_device *pdev)
642{ 820{
643 pr_debug("omap_device: %s: registering\n", od->pdev.name); 821 pr_debug("omap_device: %s: registering\n", pdev->name);
644 822
645 od->pdev.dev.parent = &omap_device_parent; 823 pdev->dev.parent = &omap_device_parent;
646 od->pdev.dev.pm_domain = &omap_device_pm_domain; 824 pdev->dev.pm_domain = &omap_device_pm_domain;
647 return platform_device_register(&od->pdev); 825 return platform_device_add(pdev);
648} 826}
649 827
650 828
@@ -671,8 +849,9 @@ int omap_device_enable(struct platform_device *pdev)
671 od = to_omap_device(pdev); 849 od = to_omap_device(pdev);
672 850
673 if (od->_state == OMAP_DEVICE_STATE_ENABLED) { 851 if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
674 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", 852 dev_warn(&pdev->dev,
675 od->pdev.name, od->pdev.id, __func__, od->_state); 853 "omap_device: %s() called from invalid state %d\n",
854 __func__, od->_state);
676 return -EINVAL; 855 return -EINVAL;
677 } 856 }
678 857
@@ -710,8 +889,9 @@ int omap_device_idle(struct platform_device *pdev)
710 od = to_omap_device(pdev); 889 od = to_omap_device(pdev);
711 890
712 if (od->_state != OMAP_DEVICE_STATE_ENABLED) { 891 if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
713 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", 892 dev_warn(&pdev->dev,
714 od->pdev.name, od->pdev.id, __func__, od->_state); 893 "omap_device: %s() called from invalid state %d\n",
894 __func__, od->_state);
715 return -EINVAL; 895 return -EINVAL;
716 } 896 }
717 897
@@ -742,8 +922,9 @@ int omap_device_shutdown(struct platform_device *pdev)
742 922
743 if (od->_state != OMAP_DEVICE_STATE_ENABLED && 923 if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
744 od->_state != OMAP_DEVICE_STATE_IDLE) { 924 od->_state != OMAP_DEVICE_STATE_IDLE) {
745 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", 925 dev_warn(&pdev->dev,
746 od->pdev.name, od->pdev.id, __func__, od->_state); 926 "omap_device: %s() called from invalid state %d\n",
927 __func__, od->_state);
747 return -EINVAL; 928 return -EINVAL;
748 } 929 }
749 930
@@ -837,6 +1018,42 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od)
837 return omap_hwmod_get_mpu_rt_va(od->hwmods[0]); 1018 return omap_hwmod_get_mpu_rt_va(od->hwmods[0]);
838} 1019}
839 1020
1021/**
1022 * omap_device_get_by_hwmod_name() - convert a hwmod name to
1023 * device pointer.
1024 * @oh_name: name of the hwmod device
1025 *
1026 * Returns back a struct device * pointer associated with a hwmod
1027 * device represented by a hwmod_name
1028 */
1029struct device *omap_device_get_by_hwmod_name(const char *oh_name)
1030{
1031 struct omap_hwmod *oh;
1032
1033 if (!oh_name) {
1034 WARN(1, "%s: no hwmod name!\n", __func__);
1035 return ERR_PTR(-EINVAL);
1036 }
1037
1038 oh = omap_hwmod_lookup(oh_name);
1039 if (IS_ERR_OR_NULL(oh)) {
1040 WARN(1, "%s: no hwmod for %s\n", __func__,
1041 oh_name);
1042 return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV);
1043 }
1044 if (IS_ERR_OR_NULL(oh->od)) {
1045 WARN(1, "%s: no omap_device for %s\n", __func__,
1046 oh_name);
1047 return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV);
1048 }
1049
1050 if (IS_ERR_OR_NULL(oh->od->pdev))
1051 return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV);
1052
1053 return &oh->od->pdev->dev;
1054}
1055EXPORT_SYMBOL(omap_device_get_by_hwmod_name);
1056
840/* 1057/*
841 * Public functions intended for use in omap_device_pm_latency 1058 * Public functions intended for use in omap_device_pm_latency
842 * .activate_func and .deactivate_func function pointers 1059 * .activate_func and .deactivate_func function pointers
@@ -917,8 +1134,13 @@ struct device omap_device_parent = {
917 .parent = &platform_bus, 1134 .parent = &platform_bus,
918}; 1135};
919 1136
1137static struct notifier_block platform_nb = {
1138 .notifier_call = _omap_device_notifier_call,
1139};
1140
920static int __init omap_device_init(void) 1141static int __init omap_device_init(void)
921{ 1142{
1143 bus_register_notifier(&platform_bus_type, &platform_nb);
922 return device_register(&omap_device_parent); 1144 return device_register(&omap_device_parent);
923} 1145}
924core_initcall(omap_device_init); 1146core_initcall(omap_device_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 20:53:51 -0400