aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap/timer32k.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-omap/timer32k.c')
-rw-r--r--arch/arm/plat-omap/timer32k.c44
1 files changed, 1 insertions, 43 deletions
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c
index ea76f1979a3d..ce034dc59d41 100644
--- a/arch/arm/plat-omap/timer32k.c
+++ b/arch/arm/plat-omap/timer32k.c
@@ -40,6 +40,7 @@
40#include <linux/interrupt.h> 40#include <linux/interrupt.h>
41#include <linux/sched.h> 41#include <linux/sched.h>
42#include <linux/spinlock.h> 42#include <linux/spinlock.h>
43
43#include <linux/err.h> 44#include <linux/err.h>
44#include <linux/clk.h> 45#include <linux/clk.h>
45#include <linux/clocksource.h> 46#include <linux/clocksource.h>
@@ -93,8 +94,6 @@ struct sys_timer omap_timer;
93#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ 94#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
94 (((nr_jiffies) * (clock_rate)) / HZ) 95 (((nr_jiffies) * (clock_rate)) / HZ)
95 96
96#if defined(CONFIG_ARCH_OMAP1)
97
98static inline void omap_32k_timer_write(int val, int reg) 97static inline void omap_32k_timer_write(int val, int reg)
99{ 98{
100 omap_writew(val, OMAP1_32K_TIMER_BASE + reg); 99 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
@@ -120,30 +119,6 @@ static inline void omap_32k_timer_stop(void)
120 119
121#define omap_32k_timer_ack_irq() 120#define omap_32k_timer_ack_irq()
122 121
123#elif defined(CONFIG_ARCH_OMAP2)
124
125static struct omap_dm_timer *gptimer;
126
127static inline void omap_32k_timer_start(unsigned long load_val)
128{
129 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
130 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
131 omap_dm_timer_start(gptimer);
132}
133
134static inline void omap_32k_timer_stop(void)
135{
136 omap_dm_timer_stop(gptimer);
137}
138
139static inline void omap_32k_timer_ack_irq(void)
140{
141 u32 status = omap_dm_timer_read_status(gptimer);
142 omap_dm_timer_write_status(gptimer, status);
143}
144
145#endif
146
147static void omap_32k_timer_set_mode(enum clock_event_mode mode, 122static void omap_32k_timer_set_mode(enum clock_event_mode mode,
148 struct clock_event_device *evt) 123 struct clock_event_device *evt)
149{ 124{
@@ -222,23 +197,6 @@ static struct irqaction omap_32k_timer_irq = {
222 197
223static __init void omap_init_32k_timer(void) 198static __init void omap_init_32k_timer(void)
224{ 199{
225 if (cpu_class_is_omap1())
226 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
227
228#ifdef CONFIG_ARCH_OMAP2
229 /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
230 if (cpu_is_omap24xx()) {
231 gptimer = omap_dm_timer_request_specific(1);
232 BUG_ON(gptimer == NULL);
233
234 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
235 setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
236 omap_dm_timer_set_int_enable(gptimer,
237 OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
238 OMAP_TIMER_INT_MATCH);
239 }
240#endif
241
242 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, 200 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
243 NSEC_PER_SEC, 201 NSEC_PER_SEC,
244 clockevent_32k_timer.shift); 202 clockevent_32k_timer.shift);