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-rw-r--r--arch/arm/plat-omap/sram.h107
1 files changed, 0 insertions, 107 deletions
diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h
deleted file mode 100644
index cefda2e09869..000000000000
--- a/arch/arm/plat-omap/sram.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/sram.h
3 *
4 * Interface for functions that need to be run in internal SRAM
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H
13
14#ifndef __ASSEMBLY__
15#include <asm/fncpy.h>
16
17int __init omap_sram_init(void);
18
19extern void *omap_sram_push_address(unsigned long size);
20
21/* Macro to push a function to the internal SRAM, using the fncpy API */
22#define omap_sram_push(funcp, size) ({ \
23 typeof(&(funcp)) _res = NULL; \
24 void *_sram_address = omap_sram_push_address(size); \
25 if (_sram_address) \
26 _res = fncpy(_sram_address, &(funcp), size); \
27 _res; \
28})
29
30extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
31
32extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
33 u32 base_cs, u32 force_unlock);
34extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
35 u32 mem_type);
36extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
37
38extern u32 omap3_configure_core_dpll(
39 u32 m2, u32 unlock_dll, u32 f, u32 inc,
40 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
41 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
42 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
43 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
44extern void omap3_sram_restore_context(void);
45
46/* Do not use these */
47extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
48extern unsigned long omap1_sram_reprogram_clock_sz;
49
50extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
51extern unsigned long omap24xx_sram_reprogram_clock_sz;
52
53extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
54 u32 base_cs, u32 force_unlock);
55extern unsigned long omap242x_sram_ddr_init_sz;
56
57extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
58 int bypass);
59extern unsigned long omap242x_sram_set_prcm_sz;
60
61extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
62 u32 mem_type);
63extern unsigned long omap242x_sram_reprogram_sdrc_sz;
64
65
66extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
67 u32 base_cs, u32 force_unlock);
68extern unsigned long omap243x_sram_ddr_init_sz;
69
70extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
71 int bypass);
72extern unsigned long omap243x_sram_set_prcm_sz;
73
74extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
75 u32 mem_type);
76extern unsigned long omap243x_sram_reprogram_sdrc_sz;
77
78extern u32 omap3_sram_configure_core_dpll(
79 u32 m2, u32 unlock_dll, u32 f, u32 inc,
80 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
81 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
82 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
83 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
84extern unsigned long omap3_sram_configure_core_dpll_sz;
85
86#ifdef CONFIG_PM
87extern void omap_push_sram_idle(void);
88#else
89static inline void omap_push_sram_idle(void) {}
90#endif /* CONFIG_PM */
91
92#endif /* __ASSEMBLY__ */
93
94/*
95 * OMAP2+: define the SRAM PA addresses.
96 * Used by the SRAM management code and the idle sleep code.
97 */
98#define OMAP2_SRAM_PA 0x40200000
99#define OMAP3_SRAM_PA 0x40200000
100#ifdef CONFIG_OMAP4_ERRATA_I688
101#define OMAP4_SRAM_PA 0x40304000
102#define OMAP4_SRAM_VA 0xfe404000
103#else
104#define OMAP4_SRAM_PA 0x40300000
105#endif
106#define AM33XX_SRAM_PA 0x40300000
107#endif
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