diff options
Diffstat (limited to 'arch/arm/plat-omap/sram.c')
| -rw-r--r-- | arch/arm/plat-omap/sram.c | 68 |
1 files changed, 43 insertions, 25 deletions
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index fa5297d643d3..65006df3f1b7 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c | |||
| @@ -6,6 +6,9 @@ | |||
| 6 | * Copyright (C) 2005 Nokia Corporation | 6 | * Copyright (C) 2005 Nokia Corporation |
| 7 | * Written by Tony Lindgren <tony@atomide.com> | 7 | * Written by Tony Lindgren <tony@atomide.com> |
| 8 | * | 8 | * |
| 9 | * Copyright (C) 2009 Texas Instruments | ||
| 10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
| 11 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | 12 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as | 13 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
| @@ -38,12 +41,14 @@ | |||
| 38 | #define OMAP1_SRAM_VA VMALLOC_END | 41 | #define OMAP1_SRAM_VA VMALLOC_END |
| 39 | #define OMAP2_SRAM_PA 0x40200000 | 42 | #define OMAP2_SRAM_PA 0x40200000 |
| 40 | #define OMAP2_SRAM_PUB_PA 0x4020f800 | 43 | #define OMAP2_SRAM_PUB_PA 0x4020f800 |
| 41 | #define OMAP2_SRAM_VA VMALLOC_END | 44 | #define OMAP2_SRAM_VA 0xe3000000 |
| 42 | #define OMAP2_SRAM_PUB_VA (VMALLOC_END + 0x800) | 45 | #define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) |
| 43 | #define OMAP3_SRAM_PA 0x40200000 | 46 | #define OMAP3_SRAM_PA 0x40200000 |
| 44 | #define OMAP3_SRAM_VA 0xd7000000 | 47 | #define OMAP3_SRAM_VA 0xd7000000 |
| 45 | #define OMAP3_SRAM_PUB_PA 0x40208000 | 48 | #define OMAP3_SRAM_PUB_PA 0x40208000 |
| 46 | #define OMAP3_SRAM_PUB_VA 0xd7008000 | 49 | #define OMAP3_SRAM_PUB_VA 0xd7008000 |
| 50 | #define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/ | ||
| 51 | #define OMAP4_SRAM_VA 0xd7000000 /*0xd70f0000*/ | ||
| 47 | 52 | ||
| 48 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 53 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 49 | #define SRAM_BOOTLOADER_SZ 0x00 | 54 | #define SRAM_BOOTLOADER_SZ 0x00 |
| @@ -87,6 +92,10 @@ static int is_sram_locked(void) | |||
| 87 | { | 92 | { |
| 88 | int type = 0; | 93 | int type = 0; |
| 89 | 94 | ||
| 95 | if (cpu_is_omap44xx()) | ||
| 96 | /* Not yet supported */ | ||
| 97 | return 0; | ||
| 98 | |||
| 90 | if (cpu_is_omap242x()) | 99 | if (cpu_is_omap242x()) |
| 91 | type = omap_rev() & OMAP2_DEVICETYPE_MASK; | 100 | type = omap_rev() & OMAP2_DEVICETYPE_MASK; |
| 92 | 101 | ||
| @@ -135,6 +144,10 @@ void __init omap_detect_sram(void) | |||
| 135 | omap_sram_base = OMAP3_SRAM_VA; | 144 | omap_sram_base = OMAP3_SRAM_VA; |
| 136 | omap_sram_start = OMAP3_SRAM_PA; | 145 | omap_sram_start = OMAP3_SRAM_PA; |
| 137 | omap_sram_size = 0x10000; /* 64K */ | 146 | omap_sram_size = 0x10000; /* 64K */ |
| 147 | } else if (cpu_is_omap44xx()) { | ||
| 148 | omap_sram_base = OMAP4_SRAM_VA; | ||
| 149 | omap_sram_start = OMAP4_SRAM_PA; | ||
| 150 | omap_sram_size = 0x8000; /* 32K */ | ||
| 138 | } else { | 151 | } else { |
| 139 | omap_sram_base = OMAP2_SRAM_VA; | 152 | omap_sram_base = OMAP2_SRAM_VA; |
| 140 | omap_sram_start = OMAP2_SRAM_PA; | 153 | omap_sram_start = OMAP2_SRAM_PA; |
| @@ -201,8 +214,23 @@ void __init omap_map_sram(void) | |||
| 201 | base = OMAP3_SRAM_PA; | 214 | base = OMAP3_SRAM_PA; |
| 202 | base = ROUND_DOWN(base, PAGE_SIZE); | 215 | base = ROUND_DOWN(base, PAGE_SIZE); |
| 203 | omap_sram_io_desc[0].pfn = __phys_to_pfn(base); | 216 | omap_sram_io_desc[0].pfn = __phys_to_pfn(base); |
| 217 | |||
| 218 | /* | ||
| 219 | * SRAM must be marked as non-cached on OMAP3 since the | ||
| 220 | * CORE DPLL M2 divider change code (in SRAM) runs with the | ||
| 221 | * SDRAM controller disabled, and if it is marked cached, | ||
| 222 | * the ARM may attempt to write cache lines back to SDRAM | ||
| 223 | * which will cause the system to hang. | ||
| 224 | */ | ||
| 225 | omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED; | ||
| 204 | } | 226 | } |
| 205 | 227 | ||
| 228 | if (cpu_is_omap44xx()) { | ||
| 229 | omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA; | ||
| 230 | base = OMAP4_SRAM_PA; | ||
| 231 | base = ROUND_DOWN(base, PAGE_SIZE); | ||
| 232 | omap_sram_io_desc[0].pfn = __phys_to_pfn(base); | ||
| 233 | } | ||
| 206 | omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ | 234 | omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ |
| 207 | iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); | 235 | iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); |
| 208 | 236 | ||
| @@ -242,20 +270,13 @@ void * omap_sram_push(void * start, unsigned long size) | |||
| 242 | return (void *)omap_sram_ceil; | 270 | return (void *)omap_sram_ceil; |
| 243 | } | 271 | } |
| 244 | 272 | ||
| 245 | static void omap_sram_error(void) | ||
| 246 | { | ||
| 247 | panic("Uninitialized SRAM function\n"); | ||
| 248 | } | ||
| 249 | |||
| 250 | #ifdef CONFIG_ARCH_OMAP1 | 273 | #ifdef CONFIG_ARCH_OMAP1 |
| 251 | 274 | ||
| 252 | static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); | 275 | static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); |
| 253 | 276 | ||
| 254 | void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) | 277 | void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) |
| 255 | { | 278 | { |
| 256 | if (!_omap_sram_reprogram_clock) | 279 | BUG_ON(!_omap_sram_reprogram_clock); |
| 257 | omap_sram_error(); | ||
| 258 | |||
| 259 | _omap_sram_reprogram_clock(dpllctl, ckctl); | 280 | _omap_sram_reprogram_clock(dpllctl, ckctl); |
| 260 | } | 281 | } |
| 261 | 282 | ||
| @@ -280,9 +301,7 @@ static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | |||
| 280 | void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | 301 | void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, |
| 281 | u32 base_cs, u32 force_unlock) | 302 | u32 base_cs, u32 force_unlock) |
| 282 | { | 303 | { |
| 283 | if (!_omap2_sram_ddr_init) | 304 | BUG_ON(!_omap2_sram_ddr_init); |
| 284 | omap_sram_error(); | ||
| 285 | |||
| 286 | _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, | 305 | _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, |
| 287 | base_cs, force_unlock); | 306 | base_cs, force_unlock); |
| 288 | } | 307 | } |
| @@ -292,9 +311,7 @@ static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val, | |||
| 292 | 311 | ||
| 293 | void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type) | 312 | void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type) |
| 294 | { | 313 | { |
| 295 | if (!_omap2_sram_reprogram_sdrc) | 314 | BUG_ON(!_omap2_sram_reprogram_sdrc); |
| 296 | omap_sram_error(); | ||
| 297 | |||
| 298 | _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); | 315 | _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); |
| 299 | } | 316 | } |
| 300 | 317 | ||
| @@ -302,9 +319,7 @@ static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); | |||
| 302 | 319 | ||
| 303 | u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) | 320 | u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) |
| 304 | { | 321 | { |
| 305 | if (!_omap2_set_prcm) | 322 | BUG_ON(!_omap2_set_prcm); |
| 306 | omap_sram_error(); | ||
| 307 | |||
| 308 | return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); | 323 | return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); |
| 309 | } | 324 | } |
| 310 | #endif | 325 | #endif |
| @@ -356,16 +371,17 @@ static inline int omap243x_sram_init(void) | |||
| 356 | static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, | 371 | static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, |
| 357 | u32 sdrc_actim_ctrla, | 372 | u32 sdrc_actim_ctrla, |
| 358 | u32 sdrc_actim_ctrlb, | 373 | u32 sdrc_actim_ctrlb, |
| 359 | u32 m2); | 374 | u32 m2, u32 unlock_dll, |
| 375 | u32 f, u32 sdrc_mr, u32 inc); | ||
| 360 | u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, | 376 | u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, |
| 361 | u32 sdrc_actim_ctrlb, u32 m2) | 377 | u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, |
| 378 | u32 f, u32 sdrc_mr, u32 inc) | ||
| 362 | { | 379 | { |
| 363 | if (!_omap3_sram_configure_core_dpll) | 380 | BUG_ON(!_omap3_sram_configure_core_dpll); |
| 364 | omap_sram_error(); | ||
| 365 | |||
| 366 | return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, | 381 | return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, |
| 367 | sdrc_actim_ctrla, | 382 | sdrc_actim_ctrla, |
| 368 | sdrc_actim_ctrlb, m2); | 383 | sdrc_actim_ctrlb, m2, |
| 384 | unlock_dll, f, sdrc_mr, inc); | ||
| 369 | } | 385 | } |
| 370 | 386 | ||
| 371 | /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ | 387 | /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ |
| @@ -406,6 +422,8 @@ int __init omap_sram_init(void) | |||
| 406 | omap243x_sram_init(); | 422 | omap243x_sram_init(); |
| 407 | else if (cpu_is_omap34xx()) | 423 | else if (cpu_is_omap34xx()) |
| 408 | omap34xx_sram_init(); | 424 | omap34xx_sram_init(); |
| 425 | else if (cpu_is_omap44xx()) | ||
| 426 | omap34xx_sram_init(); /* FIXME: */ | ||
| 409 | 427 | ||
| 410 | return 0; | 428 | return 0; |
| 411 | } | 429 | } |
