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Diffstat (limited to 'arch/arm/plat-omap/mcbsp.c')
-rw-r--r--arch/arm/plat-omap/mcbsp.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 9c9b7df3faf6..ea9475c86656 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -491,17 +491,20 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
491 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch, 491 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
492 OMAP_DMA_DATA_TYPE_S16, 492 OMAP_DMA_DATA_TYPE_S16,
493 length >> 1, 1, 493 length >> 1, 1,
494 OMAP_DMA_SYNC_ELEMENT); 494 OMAP_DMA_SYNC_ELEMENT,
495 0, 0);
495 496
496 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch, 497 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
497 OMAP_DMA_PORT_TIPB, 498 OMAP_DMA_PORT_TIPB,
498 OMAP_DMA_AMODE_CONSTANT, 499 OMAP_DMA_AMODE_CONSTANT,
499 mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1); 500 mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
501 0, 0);
500 502
501 omap_set_dma_src_params(mcbsp[id].dma_tx_lch, 503 omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
502 OMAP_DMA_PORT_EMIFF, 504 OMAP_DMA_PORT_EMIFF,
503 OMAP_DMA_AMODE_POST_INC, 505 OMAP_DMA_AMODE_POST_INC,
504 buffer); 506 buffer,
507 0, 0);
505 508
506 omap_start_dma(mcbsp[id].dma_tx_lch); 509 omap_start_dma(mcbsp[id].dma_tx_lch);
507 wait_for_completion(&(mcbsp[id].tx_dma_completion)); 510 wait_for_completion(&(mcbsp[id].tx_dma_completion));
@@ -531,17 +534,20 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
531 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch, 534 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
532 OMAP_DMA_DATA_TYPE_S16, 535 OMAP_DMA_DATA_TYPE_S16,
533 length >> 1, 1, 536 length >> 1, 1,
534 OMAP_DMA_SYNC_ELEMENT); 537 OMAP_DMA_SYNC_ELEMENT,
538 0, 0);
535 539
536 omap_set_dma_src_params(mcbsp[id].dma_rx_lch, 540 omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
537 OMAP_DMA_PORT_TIPB, 541 OMAP_DMA_PORT_TIPB,
538 OMAP_DMA_AMODE_CONSTANT, 542 OMAP_DMA_AMODE_CONSTANT,
539 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1); 543 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
544 0, 0);
540 545
541 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch, 546 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
542 OMAP_DMA_PORT_EMIFF, 547 OMAP_DMA_PORT_EMIFF,
543 OMAP_DMA_AMODE_POST_INC, 548 OMAP_DMA_AMODE_POST_INC,
544 buffer); 549 buffer,
550 0, 0);
545 551
546 omap_start_dma(mcbsp[id].dma_rx_lch); 552 omap_start_dma(mcbsp[id].dma_rx_lch);
547 wait_for_completion(&(mcbsp[id].rx_dma_completion)); 553 wait_for_completion(&(mcbsp[id].rx_dma_completion));
@@ -643,7 +649,7 @@ static const struct omap_mcbsp_info mcbsp_730[] = {
643}; 649};
644#endif 650#endif
645 651
646#ifdef CONFIG_ARCH_OMAP1510 652#ifdef CONFIG_ARCH_OMAP15XX
647static const struct omap_mcbsp_info mcbsp_1510[] = { 653static const struct omap_mcbsp_info mcbsp_1510[] = {
648 [0] = { .virt_base = OMAP1510_MCBSP1_BASE, 654 [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
649 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 655 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
@@ -712,7 +718,7 @@ static int __init omap_mcbsp_init(void)
712 mcbsp_count = ARRAY_SIZE(mcbsp_730); 718 mcbsp_count = ARRAY_SIZE(mcbsp_730);
713 } 719 }
714#endif 720#endif
715#ifdef CONFIG_ARCH_OMAP1510 721#ifdef CONFIG_ARCH_OMAP15XX
716 if (cpu_is_omap1510()) { 722 if (cpu_is_omap1510()) {
717 mcbsp_info = mcbsp_1510; 723 mcbsp_info = mcbsp_1510;
718 mcbsp_count = ARRAY_SIZE(mcbsp_1510); 724 mcbsp_count = ARRAY_SIZE(mcbsp_1510);