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-rw-r--r--arch/arm/plat-omap/include/mach/cpu.h22
-rw-r--r--arch/arm/plat-omap/include/mach/dma.h15
-rw-r--r--arch/arm/plat-omap/include/mach/io.h2
-rw-r--r--arch/arm/plat-omap/include/mach/sram.h6
4 files changed, 31 insertions, 14 deletions
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index fc60c4ebcc28..285eaa3a8275 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -30,6 +30,17 @@
30#ifndef __ASM_ARCH_OMAP_CPU_H 30#ifndef __ASM_ARCH_OMAP_CPU_H
31#define __ASM_ARCH_OMAP_CPU_H 31#define __ASM_ARCH_OMAP_CPU_H
32 32
33/*
34 * Omap device type i.e. EMU/HS/TST/GP/BAD
35 */
36#define OMAP2_DEVICE_TYPE_TEST 0
37#define OMAP2_DEVICE_TYPE_EMU 1
38#define OMAP2_DEVICE_TYPE_SEC 2
39#define OMAP2_DEVICE_TYPE_GP 3
40#define OMAP2_DEVICE_TYPE_BAD 4
41
42int omap_type(void);
43
33struct omap_chip_id { 44struct omap_chip_id {
34 u8 oc; 45 u8 oc;
35 u8 type; 46 u8 type;
@@ -424,17 +435,6 @@ IS_OMAP_TYPE(3430, 0x3430)
424 435
425 436
426int omap_chip_is(struct omap_chip_id oci); 437int omap_chip_is(struct omap_chip_id oci);
427int omap_type(void);
428
429/*
430 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
431 */
432#define OMAP2_DEVICE_TYPE_TEST 0
433#define OMAP2_DEVICE_TYPE_EMU 1
434#define OMAP2_DEVICE_TYPE_SEC 2
435#define OMAP2_DEVICE_TYPE_GP 3
436#define OMAP2_DEVICE_TYPE_BAD 4
437
438void omap2_check_revision(void); 438void omap2_check_revision(void);
439 439
440#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ 440#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 8c1eae88737e..7b939cc01962 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -389,6 +389,21 @@
389#define DMA_THREAD_FIFO_25 (0x02 << 14) 389#define DMA_THREAD_FIFO_25 (0x02 << 14)
390#define DMA_THREAD_FIFO_50 (0x03 << 14) 390#define DMA_THREAD_FIFO_50 (0x03 << 14)
391 391
392/* DMA4_OCP_SYSCONFIG bits */
393#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
394#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
395#define DMA_SYSCONFIG_EMUFREE (1 << 5)
396#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
397#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
398#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
399
400#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
401#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
402
403#define DMA_IDLEMODE_SMARTIDLE 0x2
404#define DMA_IDLEMODE_NO_IDLE 0x1
405#define DMA_IDLEMODE_FORCE_IDLE 0x0
406
392/* Chaining modes*/ 407/* Chaining modes*/
393#ifndef CONFIG_ARCH_OMAP1 408#ifndef CONFIG_ARCH_OMAP1
394#define OMAP_DMA_STATIC_CHAIN 0x1 409#define OMAP_DMA_STATIC_CHAIN 0x1
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 3b2814720569..73f483d56ca6 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -201,7 +201,7 @@
201#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa)) 201#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
202 202
203#ifdef __ASSEMBLER__ 203#ifdef __ASSEMBLER__
204#define IOMEM(x) x 204#define IOMEM(x) (x)
205#else 205#else
206#define IOMEM(x) ((void __force __iomem *)(x)) 206#define IOMEM(x) ((void __force __iomem *)(x))
207 207
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index dca7c16ae903..4d53cc59d7a3 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
24extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, 24extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25 u32 sdrc_actim_ctrla, 25 u32 sdrc_actim_ctrla,
26 u32 sdrc_actim_ctrlb, u32 m2, 26 u32 sdrc_actim_ctrlb, u32 m2,
27 u32 unlock_dll); 27 u32 unlock_dll, u32 f, u32 sdrc_mr,
28 u32 inc);
28 29
29/* Do not use these */ 30/* Do not use these */
30extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 31extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
62extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, 63extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
63 u32 sdrc_actim_ctrla, 64 u32 sdrc_actim_ctrla,
64 u32 sdrc_actim_ctrlb, u32 m2, 65 u32 sdrc_actim_ctrlb, u32 m2,
65 u32 unlock_dll); 66 u32 unlock_dll, u32 f, u32 sdrc_mr,
67 u32 inc);
66extern unsigned long omap3_sram_configure_core_dpll_sz; 68extern unsigned long omap3_sram_configure_core_dpll_sz;
67 69
68#endif 70#endif