aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-omap/include')
-rw-r--r--arch/arm/plat-omap/include/mach/debug-macro.S70
-rw-r--r--arch/arm/plat-omap/include/mach/entry-macro.S172
-rw-r--r--arch/arm/plat-omap/include/mach/mtd-xip.h61
-rw-r--r--arch/arm/plat-omap/include/mach/vmalloc.h21
-rw-r--r--arch/arm/plat-omap/include/plat/blizzard.h (renamed from arch/arm/plat-omap/include/mach/blizzard.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/board-ams-delta.h (renamed from arch/arm/plat-omap/include/mach/board-ams-delta.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/board-sx1.h (renamed from arch/arm/plat-omap/include/mach/board-sx1.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/board-voiceblue.h (renamed from arch/arm/plat-omap/include/mach/board-voiceblue.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/board.h (renamed from arch/arm/plat-omap/include/mach/board.h)20
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev.h (renamed from arch/arm/plat-omap/include/mach/clkdev.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h (renamed from arch/arm/plat-omap/include/mach/clock.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/clockdomain.h (renamed from arch/arm/plat-omap/include/mach/clockdomain.h)6
-rw-r--r--arch/arm/plat-omap/include/plat/common.h (renamed from arch/arm/plat-omap/include/mach/common.h)3
-rw-r--r--arch/arm/plat-omap/include/plat/control.h (renamed from arch/arm/plat-omap/include/mach/control.h)114
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h (renamed from arch/arm/plat-omap/include/mach/cpu.h)91
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h (renamed from arch/arm/plat-omap/include/mach/dma.h)5
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h (renamed from arch/arm/plat-omap/include/mach/dmtimer.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/dsp_common.h (renamed from arch/arm/plat-omap/include/mach/dsp_common.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/fpga.h (renamed from arch/arm/plat-omap/include/mach/fpga.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/gpio-switch.h (renamed from arch/arm/plat-omap/include/mach/gpio-switch.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h (renamed from arch/arm/plat-omap/include/mach/gpio.h)3
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc-smc91x.h (renamed from arch/arm/plat-omap/include/mach/gpmc-smc91x.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h (renamed from arch/arm/plat-omap/include/mach/gpmc.h)3
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h (renamed from arch/arm/plat-omap/include/mach/hardware.h)16
-rw-r--r--arch/arm/plat-omap/include/plat/hwa742.h (renamed from arch/arm/plat-omap/include/mach/hwa742.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/io.h (renamed from arch/arm/plat-omap/include/mach/io.h)124
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h (renamed from arch/arm/plat-omap/include/mach/iommu.h)2
-rw-r--r--arch/arm/plat-omap/include/plat/iommu2.h (renamed from arch/arm/plat-omap/include/mach/iommu2.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/iovmm.h (renamed from arch/arm/plat-omap/include/mach/iovmm.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/irda.h (renamed from arch/arm/plat-omap/include/mach/irda.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h (renamed from arch/arm/plat-omap/include/mach/irqs.h)234
-rw-r--r--arch/arm/plat-omap/include/plat/keypad.h (renamed from arch/arm/plat-omap/include/mach/keypad.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/lcd_mipid.h (renamed from arch/arm/plat-omap/include/mach/lcd_mipid.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/led.h (renamed from arch/arm/plat-omap/include/mach/led.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/mailbox.h (renamed from arch/arm/plat-omap/include/mach/mailbox.h)23
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h (renamed from arch/arm/plat-omap/include/mach/mcbsp.h)8
-rw-r--r--arch/arm/plat-omap/include/plat/mcspi.h (renamed from arch/arm/plat-omap/include/mach/mcspi.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/memory.h (renamed from arch/arm/plat-omap/include/mach/memory.h)7
-rw-r--r--arch/arm/plat-omap/include/plat/menelaus.h (renamed from arch/arm/plat-omap/include/mach/menelaus.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h (renamed from arch/arm/plat-omap/include/mach/mmc.h)2
-rw-r--r--arch/arm/plat-omap/include/plat/mux.h (renamed from arch/arm/plat-omap/include/mach/mux.h)114
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h (renamed from arch/arm/plat-omap/include/mach/nand.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/omap-alsa.h (renamed from arch/arm/plat-omap/include/mach/omap-alsa.h)4
-rw-r--r--arch/arm/plat-omap/include/plat/omap-pm.h (renamed from arch/arm/plat-omap/include/mach/omap-pm.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/omap1510.h (renamed from arch/arm/plat-omap/include/mach/omap1510.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/omap16xx.h (renamed from arch/arm/plat-omap/include/mach/omap16xx.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/omap24xx.h (renamed from arch/arm/plat-omap/include/mach/omap24xx.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/omap34xx.h (renamed from arch/arm/plat-omap/include/mach/omap34xx.h)11
-rw-r--r--arch/arm/plat-omap/include/plat/omap44xx.h (renamed from arch/arm/plat-omap/include/mach/omap44xx.h)10
-rw-r--r--arch/arm/plat-omap/include/plat/omap730.h (renamed from arch/arm/plat-omap/include/mach/omap730.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/omap7xx.h104
-rw-r--r--arch/arm/plat-omap/include/plat/omap850.h (renamed from arch/arm/plat-omap/include/mach/omap850.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h (renamed from arch/arm/plat-omap/include/mach/omap_device.h)2
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h (renamed from arch/arm/plat-omap/include/mach/omap_hwmod.h)2
-rw-r--r--arch/arm/plat-omap/include/plat/omapfb.h (renamed from arch/arm/plat-omap/include/mach/omapfb.h)2
-rw-r--r--arch/arm/plat-omap/include/plat/onenand.h (renamed from arch/arm/plat-omap/include/mach/onenand.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/param.h (renamed from arch/arm/plat-omap/include/mach/param.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h (renamed from arch/arm/plat-omap/include/mach/powerdomain.h)2
-rw-r--r--arch/arm/plat-omap/include/plat/prcm.h (renamed from arch/arm/plat-omap/include/mach/prcm.h)6
-rw-r--r--arch/arm/plat-omap/include/plat/sdrc.h (renamed from arch/arm/plat-omap/include/mach/sdrc.h)14
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h (renamed from arch/arm/plat-omap/include/mach/serial.h)4
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h (renamed from arch/arm/plat-omap/include/mach/smp.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h (renamed from arch/arm/plat-omap/include/mach/sram.h)7
-rw-r--r--arch/arm/plat-omap/include/plat/system.h (renamed from arch/arm/plat-omap/include/mach/system.h)2
-rw-r--r--arch/arm/plat-omap/include/plat/tc.h (renamed from arch/arm/plat-omap/include/mach/tc.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/timer-gp.h (renamed from arch/arm/plat-omap/include/mach/timer-gp.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/timex.h (renamed from arch/arm/plat-omap/include/mach/timex.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h (renamed from arch/arm/plat-omap/include/mach/uncompress.h)11
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h (renamed from arch/arm/plat-omap/include/mach/usb.h)19
69 files changed, 643 insertions, 656 deletions
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
deleted file mode 100644
index ac24050e3416..000000000000
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
1/* arch/arm/plat-omap/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17#ifdef CONFIG_ARCH_OMAP1
18 moveq \rx, #0xff000000 @ physical base address
19 movne \rx, #0xfe000000 @ virtual base
20 orr \rx, \rx, #0x00fb0000
21#ifdef CONFIG_OMAP_LL_DEBUG_UART3
22 orr \rx, \rx, #0x00009000 @ UART 3
23#endif
24#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
25 orr \rx, \rx, #0x00000800 @ UART 2 & 3
26#endif
27
28#elif CONFIG_ARCH_OMAP2
29 moveq \rx, #0x48000000 @ physical base address
30 movne \rx, #0xd8000000 @ virtual base
31 orr \rx, \rx, #0x0006a000
32#ifdef CONFIG_OMAP_LL_DEBUG_UART2
33 add \rx, \rx, #0x00002000 @ UART 2
34#endif
35#ifdef CONFIG_OMAP_LL_DEBUG_UART3
36 add \rx, \rx, #0x00004000 @ UART 3
37#endif
38
39#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
40 moveq \rx, #0x48000000 @ physical base address
41 movne \rx, #0xd8000000 @ virtual base
42 orr \rx, \rx, #0x0006a000
43#ifdef CONFIG_OMAP_LL_DEBUG_UART2
44 add \rx, \rx, #0x00002000 @ UART 2
45#endif
46#ifdef CONFIG_OMAP_LL_DEBUG_UART3
47 add \rx, \rx, #0x00fb0000 @ UART 3
48 add \rx, \rx, #0x00006000
49#endif
50#endif
51 .endm
52
53 .macro senduart,rd,rx
54 strb \rd, [\rx]
55 .endm
56
57 .macro busyuart,rd,rx
581001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
59 and \rd, \rd, #0x60
60 teq \rd, #0x60
61 beq 1002f
62 ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
63 and \rd, \rd, #0x60
64 teq \rd, #0x60
65 bne 1001b
661002:
67 .endm
68
69 .macro waituart,rd,rx
70 .endm
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
deleted file mode 100644
index a5592991634d..000000000000
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ /dev/null
@@ -1,172 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for OMAP-based platforms
5 *
6 * Copyright (C) 2009 Texas Instruments
7 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13#include <mach/hardware.h>
14#include <mach/io.h>
15#include <mach/irqs.h>
16#include <asm/hardware/gic.h>
17
18#if defined(CONFIG_ARCH_OMAP1)
19
20#if defined(CONFIG_ARCH_OMAP730) && \
21 (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
22#error "FIXME: OMAP730 doesn't support multiple-OMAP"
23#elif defined(CONFIG_ARCH_OMAP730)
24#define INT_IH2_IRQ INT_730_IH2_IRQ
25#elif defined(CONFIG_ARCH_OMAP15XX)
26#define INT_IH2_IRQ INT_1510_IH2_IRQ
27#elif defined(CONFIG_ARCH_OMAP16XX)
28#define INT_IH2_IRQ INT_1610_IH2_IRQ
29#else
30#warning "IH2 IRQ defaulted"
31#define INT_IH2_IRQ INT_1510_IH2_IRQ
32#endif
33
34 .macro disable_fiq
35 .endm
36
37 .macro get_irqnr_preamble, base, tmp
38 .endm
39
40 .macro arch_ret_to_user, tmp1, tmp2
41 .endm
42
43 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
44 ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
45 ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
46 ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
47 mov \irqstat, #0xffffffff
48 bic \tmp, \irqstat, \tmp
49 tst \irqnr, \tmp
50 beq 1510f
51
52 ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
53 cmp \irqnr, #0
54 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
55 cmpeq \irqnr, #INT_IH2_IRQ
56 ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
57 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
58 addeqs \irqnr, \irqnr, #32
591510:
60 .endm
61
62#endif
63#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
64 defined(CONFIG_ARCH_OMAP4)
65
66#include <mach/omap24xx.h>
67#include <mach/omap34xx.h>
68
69/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
70#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
71#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
72#elif defined(CONFIG_ARCH_OMAP34XX)
73#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
74#endif
75#if defined(CONFIG_ARCH_OMAP4)
76#include <mach/omap44xx.h>
77#endif
78#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */
79#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */
80
81 .macro disable_fiq
82 .endm
83
84 .macro get_irqnr_preamble, base, tmp
85 .endm
86
87 .macro arch_ret_to_user, tmp1, tmp2
88 .endm
89
90#ifndef CONFIG_ARCH_OMAP4
91 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
92 ldr \base, =OMAP2_VA_IC_BASE
93 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
94 cmp \irqnr, #0x0
95 bne 2222f
96 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
97 cmp \irqnr, #0x0
98 bne 2222f
99 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
100 cmp \irqnr, #0x0
1012222:
102 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
103 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
104
105 .endm
106#else
107 /*
108 * The interrupt numbering scheme is defined in the
109 * interrupt controller spec. To wit:
110 *
111 * Interrupts 0-15 are IPI
112 * 16-28 are reserved
113 * 29-31 are local. We allow 30 to be used for the watchdog.
114 * 32-1020 are global
115 * 1021-1022 are reserved
116 * 1023 is "spurious" (no interrupt)
117 *
118 * For now, we ignore all local interrupts so only return an
119 * interrupt if it's between 30 and 1020. The test_for_ipi
120 * routine below will pick up on IPIs.
121 * A simple read from the controller will tell us the number
122 * of the highest priority enabled interrupt.
123 * We then just need to check whether it is in the
124 * valid range for an IRQ (30-1020 inclusive).
125 */
126 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
127 ldr \base, =OMAP44XX_VA_GIC_CPU_BASE
128 ldr \irqstat, [\base, #GIC_CPU_INTACK]
129
130 ldr \tmp, =1021
131
132 bic \irqnr, \irqstat, #0x1c00
133
134 cmp \irqnr, #29
135 cmpcc \irqnr, \irqnr
136 cmpne \irqnr, \tmp
137 cmpcs \irqnr, \irqnr
138 .endm
139
140 /* We assume that irqstat (the raw value of the IRQ acknowledge
141 * register) is preserved from the macro above.
142 * If there is an IPI, we immediately signal end of interrupt
143 * on the controller, since this requires the original irqstat
144 * value which we won't easily be able to recreate later.
145 */
146
147 .macro test_for_ipi, irqnr, irqstat, base, tmp
148 bic \irqnr, \irqstat, #0x1c00
149 cmp \irqnr, #16
150 it cc
151 strcc \irqstat, [\base, #GIC_CPU_EOI]
152 it cs
153 cmpcs \irqnr, \irqnr
154 .endm
155
156 /* As above, this assumes that irqstat and base are preserved */
157
158 .macro test_for_ltirq, irqnr, irqstat, base, tmp
159 bic \irqnr, \irqstat, #0x1c00
160 mov \tmp, #0
161 cmp \irqnr, #29
162 itt eq
163 moveq \tmp, #1
164 streq \irqstat, [\base, #GIC_CPU_EOI]
165 cmp \tmp, #0
166 .endm
167#endif
168
169 .macro irq_prio_table
170 .endm
171
172#endif
diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/plat-omap/include/mach/mtd-xip.h
deleted file mode 100644
index f82a8dcaad94..000000000000
--- a/arch/arm/plat-omap/include/mach/mtd-xip.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * MTD primitives for XIP support. Architecture specific functions.
3 *
4 * Do not include this file directly. It's included from linux/mtd/xip.h
5 *
6 * Author: Vladimir Barinov <vbarinov@embeddedalley.com>
7 *
8 * (c) 2005 MontaVista Software, Inc. This file is licensed under the
9 * terms of the GNU General Public License version 2. This program is
10 * licensed "as is" without any warranty of any kind, whether express or
11 * implied.
12 */
13
14#ifndef __ARCH_OMAP_MTD_XIP_H__
15#define __ARCH_OMAP_MTD_XIP_H__
16
17#include <mach/hardware.h>
18#define OMAP_MPU_TIMER_BASE (0xfffec500)
19#define OMAP_MPU_TIMER_OFFSET 0x100
20
21typedef struct {
22 u32 cntl; /* CNTL_TIMER, R/W */
23 u32 load_tim; /* LOAD_TIM, W */
24 u32 read_tim; /* READ_TIM, R */
25} xip_omap_mpu_timer_regs_t;
26
27#define xip_omap_mpu_timer_base(n) \
28((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
29 (n)*OMAP_MPU_TIMER_OFFSET))
30
31static inline unsigned long xip_omap_mpu_timer_read(int nr)
32{
33 volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr);
34 return timer->read_tim;
35}
36
37#define xip_irqpending() \
38 (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR))
39#define xip_currtime() (~xip_omap_mpu_timer_read(0))
40
41/*
42 * It's permitted to do approxmation for xip_elapsed_since macro
43 * (see linux/mtd/xip.h)
44 */
45
46#ifdef CONFIG_MACH_OMAP_PERSEUS2
47#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7)
48#else
49#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
50#endif
51
52/*
53 * xip_cpu_idle() is used when waiting for a delay equal or larger than
54 * the system timer tick period. This should put the CPU into idle mode
55 * to save power and to be woken up only when some interrupts are pending.
56 * As above, this should not rely upon standard kernel code.
57 */
58
59#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
60
61#endif /* __ARCH_OMAP_MTD_XIP_H__ */
diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h
deleted file mode 100644
index b97dfafeebda..000000000000
--- a/arch/arm/plat-omap/include/mach/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x18000000)
21
diff --git a/arch/arm/plat-omap/include/mach/blizzard.h b/arch/arm/plat-omap/include/plat/blizzard.h
index 8d160f171372..8d160f171372 100644
--- a/arch/arm/plat-omap/include/mach/blizzard.h
+++ b/arch/arm/plat-omap/include/plat/blizzard.h
diff --git a/arch/arm/plat-omap/include/mach/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
index 51b102dc906b..51b102dc906b 100644
--- a/arch/arm/plat-omap/include/mach/board-ams-delta.h
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
diff --git a/arch/arm/plat-omap/include/mach/board-sx1.h b/arch/arm/plat-omap/include/plat/board-sx1.h
index 355adbdaae33..355adbdaae33 100644
--- a/arch/arm/plat-omap/include/mach/board-sx1.h
+++ b/arch/arm/plat-omap/include/plat/board-sx1.h
diff --git a/arch/arm/plat-omap/include/mach/board-voiceblue.h b/arch/arm/plat-omap/include/plat/board-voiceblue.h
index 27916b210f57..27916b210f57 100644
--- a/arch/arm/plat-omap/include/mach/board-voiceblue.h
+++ b/arch/arm/plat-omap/include/plat/board-voiceblue.h
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/plat/board.h
index 8e913c322810..abb17b604f82 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -12,7 +12,19 @@
12 12
13#include <linux/types.h> 13#include <linux/types.h>
14 14
15#include <mach/gpio-switch.h> 15#include <plat/gpio-switch.h>
16
17/*
18 * OMAP35x EVM revision
19 * Run time detection of EVM revision is done by reading Ethernet
20 * PHY ID -
21 * GEN_1 = 0x01150000
22 * GEN_2 = 0x92200000
23 */
24enum {
25 OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
26 OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
27};
16 28
17/* Different peripheral ids */ 29/* Different peripheral ids */
18#define OMAP_TAG_CLOCK 0x4f01 30#define OMAP_TAG_CLOCK 0x4f01
@@ -157,4 +169,10 @@ extern int omap_board_config_size;
157/* for TI reference platforms sharing the same debug card */ 169/* for TI reference platforms sharing the same debug card */
158extern int debug_card_init(u32 addr, unsigned gpio); 170extern int debug_card_init(u32 addr, unsigned gpio);
159 171
172/* OMAP3EVM revision */
173#if defined(CONFIG_MACH_OMAP3EVM)
174u8 get_omap3_evm_rev(void);
175#else
176#define get_omap3_evm_rev() (-EINVAL)
177#endif
160#endif 178#endif
diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/plat/clkdev.h
index 730c49d1ebd8..730c49d1ebd8 100644
--- a/arch/arm/plat-omap/include/mach/clkdev.h
+++ b/arch/arm/plat-omap/include/plat/clkdev.h
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 4b8b0d65cbf2..4b8b0d65cbf2 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h
index 99ebd886f134..eb734826e64e 100644
--- a/arch/arm/plat-omap/include/mach/clockdomain.h
+++ b/arch/arm/plat-omap/include/plat/clockdomain.h
@@ -16,9 +16,9 @@
16#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H 16#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
17#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H 17#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
18 18
19#include <mach/powerdomain.h> 19#include <plat/powerdomain.h>
20#include <mach/clock.h> 20#include <plat/clock.h>
21#include <mach/cpu.h> 21#include <plat/cpu.h>
22 22
23/* Clockdomain capability flags */ 23/* Clockdomain capability flags */
24#define CLKDM_CAN_FORCE_SLEEP (1 << 0) 24#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/plat/common.h
index fdeab421b4dc..064f1730f43b 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -31,6 +31,9 @@
31 31
32struct sys_timer; 32struct sys_timer;
33 33
34/* used by omap-smp.c and board-4430sdp.c */
35extern void __iomem *gic_cpu_base_addr;
36
34extern void omap_map_common_io(void); 37extern void omap_map_common_io(void);
35extern struct sys_timer omap_timer; 38extern struct sys_timer omap_timer;
36#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) 39#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/plat/control.h
index 826d317cdbec..2ae884378638 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -20,15 +20,18 @@
20 20
21#ifndef __ASSEMBLY__ 21#ifndef __ASSEMBLY__
22#define OMAP242X_CTRL_REGADDR(reg) \ 22#define OMAP242X_CTRL_REGADDR(reg) \
23 OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24#define OMAP243X_CTRL_REGADDR(reg) \ 24#define OMAP243X_CTRL_REGADDR(reg) \
25 OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26#define OMAP343X_CTRL_REGADDR(reg) \ 26#define OMAP343X_CTRL_REGADDR(reg) \
27 OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#else 28#else
29#define OMAP242X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 29#define OMAP242X_CTRL_REGADDR(reg) \
30#define OMAP243X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 30 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
31#define OMAP343X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 31#define OMAP243X_CTRL_REGADDR(reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
33#define OMAP343X_CTRL_REGADDR(reg) \
34 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
32#endif /* __ASSEMBLY__ */ 35#endif /* __ASSEMBLY__ */
33 36
34/* 37/*
@@ -109,6 +112,8 @@
109#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) 112#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
110#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) 113#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
111 114
115#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
116
112/* 34xx-only CONTROL_GENERAL register offsets */ 117/* 34xx-only CONTROL_GENERAL register offsets */
113#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) 118#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
114#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) 119#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
@@ -141,8 +146,51 @@
141#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 146#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
142#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 147#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
143#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 148#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
144#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) 149#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
145#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) 150 + ((i) >> 1) * 4 + (!(i) & 1) * 2)
151#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
152#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
153#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
154#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
155#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
156#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
157#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
158#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
159#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
160#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
161#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
162
163
164/* 34xx PADCONF register offsets */
165#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
166 (i)*2)
167#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
168#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
169#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
170#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
171#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
172#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
173#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
174#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
175#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
176#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
177#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
178#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
179#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
180#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
181#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
182#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
183#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
184#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
185
186/* 34xx GENERAL_WKUP regist offsets */
187#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
188 0x008 + (i))
189#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
190#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
191#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
192#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
193#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
146 194
147/* 34xx D2D idle-related pins, handled by PM core */ 195/* 34xx D2D idle-related pins, handled by PM core */
148#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 196#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
@@ -193,6 +241,9 @@
193#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 241#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
194#define OMAP2_PBIASLITEVMODE0 (1 << 0) 242#define OMAP2_PBIASLITEVMODE0 (1 << 0)
195 243
244/* CONTROL_PROG_IO1 bits */
245#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
246
196/* CONTROL_IVA2_BOOTMOD bits */ 247/* CONTROL_IVA2_BOOTMOD bits */
197#define OMAP3_IVA2_BOOTMOD_SHIFT 0 248#define OMAP3_IVA2_BOOTMOD_SHIFT 0
198#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) 249#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
@@ -202,6 +253,44 @@
202#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) 253#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
203#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) 254#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
204 255
256#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
257#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
258#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
259
260/*
261 * CONTROL OMAP STATUS register to identify OMAP3 features
262 */
263#define OMAP3_CONTROL_OMAP_STATUS 0x044c
264
265#define OMAP3_SGX_SHIFT 13
266#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
267#define FEAT_SGX_FULL 0
268#define FEAT_SGX_HALF 1
269#define FEAT_SGX_NONE 2
270
271#define OMAP3_IVA_SHIFT 12
272#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
273#define FEAT_IVA 0
274#define FEAT_IVA_NONE 1
275
276#define OMAP3_L2CACHE_SHIFT 10
277#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
278#define FEAT_L2CACHE_NONE 0
279#define FEAT_L2CACHE_64KB 1
280#define FEAT_L2CACHE_128KB 2
281#define FEAT_L2CACHE_256KB 3
282
283#define OMAP3_ISP_SHIFT 5
284#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
285#define FEAT_ISP 0
286#define FEAT_ISP_NONE 1
287
288#define OMAP3_NEON_SHIFT 4
289#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
290#define FEAT_NEON 0
291#define FEAT_NEON_NONE 1
292
293
205#ifndef __ASSEMBLY__ 294#ifndef __ASSEMBLY__
206#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ 295#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
207 defined(CONFIG_ARCH_OMAP4) 296 defined(CONFIG_ARCH_OMAP4)
@@ -212,6 +301,15 @@ extern u32 omap_ctrl_readl(u16 offset);
212extern void omap_ctrl_writeb(u8 val, u16 offset); 301extern void omap_ctrl_writeb(u8 val, u16 offset);
213extern void omap_ctrl_writew(u16 val, u16 offset); 302extern void omap_ctrl_writew(u16 val, u16 offset);
214extern void omap_ctrl_writel(u32 val, u16 offset); 303extern void omap_ctrl_writel(u32 val, u16 offset);
304
305extern void omap3_save_scratchpad_contents(void);
306extern void omap3_clear_scratchpad_contents(void);
307extern u32 *get_restore_pointer(void);
308extern u32 *get_es3_restore_pointer(void);
309extern u32 omap3_arm_context[128];
310extern void omap3_control_save_context(void);
311extern void omap3_control_restore_context(void);
312
215#else 313#else
216#define omap_ctrl_base_get() 0 314#define omap_ctrl_base_get() 0
217#define omap_ctrl_readb(x) 0 315#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index f129efb3075e..2e1789001dfe 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -30,6 +30,8 @@
30#ifndef __ASM_ARCH_OMAP_CPU_H 30#ifndef __ASM_ARCH_OMAP_CPU_H
31#define __ASM_ARCH_OMAP_CPU_H 31#define __ASM_ARCH_OMAP_CPU_H
32 32
33#include <linux/bitops.h>
34
33/* 35/*
34 * Omap device type i.e. EMU/HS/TST/GP/BAD 36 * Omap device type i.e. EMU/HS/TST/GP/BAD
35 */ 37 */
@@ -57,6 +59,23 @@ struct omap_chip_id {
57unsigned int omap_rev(void); 59unsigned int omap_rev(void);
58 60
59/* 61/*
62 * Define CPU revision bits
63 *
64 * Verbose meaning of the revision bits may be different for a silicon
65 * family. This difference can be handled separately.
66 */
67#define OMAP_REVBITS_00 0x00
68#define OMAP_REVBITS_10 0x10
69#define OMAP_REVBITS_20 0x20
70#define OMAP_REVBITS_30 0x30
71#define OMAP_REVBITS_40 0x40
72
73/*
74 * Get the CPU revision for OMAP devices
75 */
76#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
77
78/*
60 * Test if multicore OMAP support is needed 79 * Test if multicore OMAP support is needed
61 */ 80 */
62#undef MULTI_OMAP1 81#undef MULTI_OMAP1
@@ -161,6 +180,7 @@ IS_OMAP_CLASS(34xx, 0x34)
161IS_OMAP_SUBCLASS(242x, 0x242) 180IS_OMAP_SUBCLASS(242x, 0x242)
162IS_OMAP_SUBCLASS(243x, 0x243) 181IS_OMAP_SUBCLASS(243x, 0x243)
163IS_OMAP_SUBCLASS(343x, 0x343) 182IS_OMAP_SUBCLASS(343x, 0x343)
183IS_OMAP_SUBCLASS(363x, 0x363)
164 184
165#define cpu_is_omap7xx() 0 185#define cpu_is_omap7xx() 0
166#define cpu_is_omap15xx() 0 186#define cpu_is_omap15xx() 0
@@ -264,6 +284,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
264 * cpu_is_omap2423(): True for OMAP2423 284 * cpu_is_omap2423(): True for OMAP2423
265 * cpu_is_omap2430(): True for OMAP2430 285 * cpu_is_omap2430(): True for OMAP2430
266 * cpu_is_omap3430(): True for OMAP3430 286 * cpu_is_omap3430(): True for OMAP3430
287 * cpu_is_omap3505(): True for OMAP3505
288 * cpu_is_omap3517(): True for OMAP3517
267 */ 289 */
268#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff) 290#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
269 291
@@ -287,6 +309,8 @@ IS_OMAP_TYPE(2422, 0x2422)
287IS_OMAP_TYPE(2423, 0x2423) 309IS_OMAP_TYPE(2423, 0x2423)
288IS_OMAP_TYPE(2430, 0x2430) 310IS_OMAP_TYPE(2430, 0x2430)
289IS_OMAP_TYPE(3430, 0x3430) 311IS_OMAP_TYPE(3430, 0x3430)
312IS_OMAP_TYPE(3505, 0x3505)
313IS_OMAP_TYPE(3517, 0x3517)
290 314
291#define cpu_is_omap310() 0 315#define cpu_is_omap310() 0
292#define cpu_is_omap730() 0 316#define cpu_is_omap730() 0
@@ -301,7 +325,14 @@ IS_OMAP_TYPE(3430, 0x3430)
301#define cpu_is_omap2422() 0 325#define cpu_is_omap2422() 0
302#define cpu_is_omap2423() 0 326#define cpu_is_omap2423() 0
303#define cpu_is_omap2430() 0 327#define cpu_is_omap2430() 0
328#define cpu_is_omap3503() 0
329#define cpu_is_omap3515() 0
330#define cpu_is_omap3525() 0
331#define cpu_is_omap3530() 0
332#define cpu_is_omap3505() 0
333#define cpu_is_omap3517() 0
304#define cpu_is_omap3430() 0 334#define cpu_is_omap3430() 0
335#define cpu_is_omap3630() 0
305 336
306/* 337/*
307 * Whether we have MULTI_OMAP1 or not, we still need to distinguish 338 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
@@ -351,7 +382,27 @@ IS_OMAP_TYPE(3430, 0x3430)
351 382
352#if defined(CONFIG_ARCH_OMAP34XX) 383#if defined(CONFIG_ARCH_OMAP34XX)
353# undef cpu_is_omap3430 384# undef cpu_is_omap3430
385# undef cpu_is_omap3503
386# undef cpu_is_omap3515
387# undef cpu_is_omap3525
388# undef cpu_is_omap3530
389# undef cpu_is_omap3505
390# undef cpu_is_omap3517
354# define cpu_is_omap3430() is_omap3430() 391# define cpu_is_omap3430() is_omap3430()
392# define cpu_is_omap3503() (cpu_is_omap3430() && \
393 (!omap3_has_iva()) && \
394 (!omap3_has_sgx()))
395# define cpu_is_omap3515() (cpu_is_omap3430() && \
396 (omap3_has_iva()) && \
397 (!omap3_has_sgx()))
398# define cpu_is_omap3525() (cpu_is_omap3430() && \
399 (omap3_has_sgx()) && \
400 (!omap3_has_iva()))
401# define cpu_is_omap3530() (cpu_is_omap3430())
402# define cpu_is_omap3505() is_omap3505()
403# define cpu_is_omap3517() is_omap3517()
404# undef cpu_is_omap3630
405# define cpu_is_omap3630() is_omap363x()
355#endif 406#endif
356 407
357# if defined(CONFIG_ARCH_OMAP4) 408# if defined(CONFIG_ARCH_OMAP4)
@@ -382,6 +433,16 @@ IS_OMAP_TYPE(3430, 0x3430)
382#define OMAP3430_REV_ES3_0 0x34303034 433#define OMAP3430_REV_ES3_0 0x34303034
383#define OMAP3430_REV_ES3_1 0x34304034 434#define OMAP3430_REV_ES3_1 0x34304034
384 435
436#define OMAP3630_REV_ES1_0 0x36300034
437
438#define OMAP35XX_CLASS 0x35000034
439#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12))
440#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12))
441#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12))
442#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12))
443#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 12))
444#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 12))
445
385#define OMAP443X_CLASS 0x44300034 446#define OMAP443X_CLASS 0x44300034
386 447
387/* 448/*
@@ -405,6 +466,7 @@ IS_OMAP_TYPE(3430, 0x3430)
405#define CHIP_IS_OMAP3430ES2 (1 << 4) 466#define CHIP_IS_OMAP3430ES2 (1 << 4)
406#define CHIP_IS_OMAP3430ES3_0 (1 << 5) 467#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
407#define CHIP_IS_OMAP3430ES3_1 (1 << 6) 468#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
469#define CHIP_IS_OMAP3630ES1 (1 << 7)
408 470
409#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 471#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
410 472
@@ -416,11 +478,36 @@ IS_OMAP_TYPE(3430, 0x3430)
416 */ 478 */
417#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ 479#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
418 CHIP_IS_OMAP3430ES3_0 | \ 480 CHIP_IS_OMAP3430ES3_0 | \
419 CHIP_IS_OMAP3430ES3_1) 481 CHIP_IS_OMAP3430ES3_1 | \
420#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1) 482 CHIP_IS_OMAP3630ES1)
483#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
484 CHIP_IS_OMAP3630ES1)
421 485
422 486
423int omap_chip_is(struct omap_chip_id oci); 487int omap_chip_is(struct omap_chip_id oci);
424void omap2_check_revision(void); 488void omap2_check_revision(void);
425 489
490/*
491 * Runtime detection of OMAP3 features
492 */
493extern u32 omap3_features;
494
495#define OMAP3_HAS_L2CACHE BIT(0)
496#define OMAP3_HAS_IVA BIT(1)
497#define OMAP3_HAS_SGX BIT(2)
498#define OMAP3_HAS_NEON BIT(3)
499#define OMAP3_HAS_ISP BIT(4)
500
501#define OMAP3_HAS_FEATURE(feat,flag) \
502static inline unsigned int omap3_has_ ##feat(void) \
503{ \
504 return (omap3_features & OMAP3_HAS_ ##flag); \
505} \
506
507OMAP3_HAS_FEATURE(l2cache, L2CACHE)
508OMAP3_HAS_FEATURE(sgx, SGX)
509OMAP3_HAS_FEATURE(iva, IVA)
510OMAP3_HAS_FEATURE(neon, NEON)
511OMAP3_HAS_FEATURE(isp, ISP)
512
426#endif 513#endif
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 72f680b7180d..1c017b29b7e9 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -633,6 +633,11 @@ extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
633extern void omap_set_dma_src_endian_type(int lch, enum end_type etype); 633extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
634extern int omap_get_dma_index(int lch, int *ei, int *fi); 634extern int omap_get_dma_index(int lch, int *ei, int *fi);
635 635
636void omap_dma_global_context_save(void);
637void omap_dma_global_context_restore(void);
638
639extern void omap_dma_disable_irq(int lch);
640
636/* Chaining APIs */ 641/* Chaining APIs */
637#ifndef CONFIG_ARCH_OMAP1 642#ifndef CONFIG_ARCH_OMAP1
638extern int omap_request_dma_chain(int dev_id, const char *dev_name, 643extern int omap_request_dma_chain(int dev_id, const char *dev_name,
diff --git a/arch/arm/plat-omap/include/mach/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 20f1054c0a80..20f1054c0a80 100644
--- a/arch/arm/plat-omap/include/mach/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
diff --git a/arch/arm/plat-omap/include/mach/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h
index da97736f3efa..da97736f3efa 100644
--- a/arch/arm/plat-omap/include/mach/dsp_common.h
+++ b/arch/arm/plat-omap/include/plat/dsp_common.h
diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
index f1864a652f7a..f1864a652f7a 100644
--- a/arch/arm/plat-omap/include/mach/fpga.h
+++ b/arch/arm/plat-omap/include/plat/fpga.h
diff --git a/arch/arm/plat-omap/include/mach/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
index 10da0e07c0cf..10da0e07c0cf 100644
--- a/arch/arm/plat-omap/include/mach/gpio-switch.h
+++ b/arch/arm/plat-omap/include/plat/gpio-switch.h
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 633ff688b928..de7c54731cbe 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -76,7 +76,8 @@ extern void omap2_gpio_prepare_for_retention(void);
76extern void omap2_gpio_resume_after_retention(void); 76extern void omap2_gpio_resume_after_retention(void);
77extern void omap_set_gpio_debounce(int gpio, int enable); 77extern void omap_set_gpio_debounce(int gpio, int enable);
78extern void omap_set_gpio_debounce_time(int gpio, int enable); 78extern void omap_set_gpio_debounce_time(int gpio, int enable);
79 79extern void omap_gpio_save_context(void);
80extern void omap_gpio_restore_context(void);
80/*-------------------------------------------------------------------------*/ 81/*-------------------------------------------------------------------------*/
81 82
82/* Wrappers for "new style" GPIO calls, using the new infrastructure 83/* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
index b64fbee4d567..b64fbee4d567 100644
--- a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
+++ b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 9c99cda77ba6..696e0ca051b7 100644
--- a/arch/arm/plat-omap/include/mach/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -52,6 +52,7 @@
52#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 52#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
53#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) 53#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
54#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) 54#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
55#define GPMC_CONFIG7_CSVALID (1 << 6)
55 56
56/* 57/*
57 * Note that all values in this struct are in nanoseconds, while 58 * Note that all values in this struct are in nanoseconds, while
@@ -107,6 +108,8 @@ extern int gpmc_prefetch_enable(int cs, int dma_mode,
107 unsigned int u32_count, int is_write); 108 unsigned int u32_count, int is_write);
108extern void gpmc_prefetch_reset(void); 109extern void gpmc_prefetch_reset(void);
109extern int gpmc_prefetch_status(void); 110extern int gpmc_prefetch_status(void);
111extern void omap3_gpmc_save_context(void);
112extern void omap3_gpmc_restore_context(void);
110extern void __init gpmc_init(void); 113extern void __init gpmc_init(void);
111 114
112#endif 115#endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index 26c1fbff08aa..d5b26adfb890 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -39,9 +39,9 @@
39#include <asm/sizes.h> 39#include <asm/sizes.h>
40#ifndef __ASSEMBLER__ 40#ifndef __ASSEMBLER__
41#include <asm/types.h> 41#include <asm/types.h>
42#include <mach/cpu.h> 42#include <plat/cpu.h>
43#endif 43#endif
44#include <mach/serial.h> 44#include <plat/serial.h>
45 45
46/* 46/*
47 * --------------------------------------------------------------------------- 47 * ---------------------------------------------------------------------------
@@ -280,11 +280,11 @@
280 * --------------------------------------------------------------------------- 280 * ---------------------------------------------------------------------------
281 */ 281 */
282 282
283#include "omap730.h" 283#include <plat/omap7xx.h>
284#include "omap1510.h" 284#include <plat/omap1510.h>
285#include "omap16xx.h" 285#include <plat/omap16xx.h>
286#include "omap24xx.h" 286#include <plat/omap24xx.h>
287#include "omap34xx.h" 287#include <plat/omap34xx.h>
288#include "omap44xx.h" 288#include <plat/omap44xx.h>
289 289
290#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ 290#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/plat/hwa742.h
index 886248d32b49..886248d32b49 100644
--- a/arch/arm/plat-omap/include/mach/hwa742.h
+++ b/arch/arm/plat-omap/include/plat/hwa742.h
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/plat/io.h
index 8d32df32b0b1..7e5319f907d1 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -63,8 +63,24 @@
63#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ 63#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
64#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) 64#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
65 65
66#define OMAP2_IO_OFFSET 0x90000000 66#define OMAP2_L3_IO_OFFSET 0x90000000
67#define OMAP2_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */ 67#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
68
69
70#define OMAP2_L4_IO_OFFSET 0xb2000000
71#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
72
73#define OMAP4_L3_IO_OFFSET 0xb4000000
74#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
75
76#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
77#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
78
79#define OMAP4_GPMC_IO_OFFSET 0xa9000000
80#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
81
82#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
83#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
68 84
69/* 85/*
70 * ---------------------------------------------------------------------------- 86 * ----------------------------------------------------------------------------
@@ -83,24 +99,27 @@
83 */ 99 */
84 100
85/* We map both L3 and L4 on OMAP2 */ 101/* We map both L3 and L4 on OMAP2 */
86#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */ 102#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
87#define L3_24XX_VIRT 0xf8000000 103#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
88#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 104#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
89#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */ 105#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
90#define L4_24XX_VIRT 0xd8000000 106#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
91#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 107#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
92 108
93#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ 109#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
94#define L4_WK_243X_VIRT 0xd9000000 110#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
95#define L4_WK_243X_SIZE SZ_1M 111#define L4_WK_243X_SIZE SZ_1M
96#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ 112#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
97#define OMAP243X_GPMC_VIRT 0xFE000000 113#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
114 /* 0x6e000000 --> 0xfe000000 */
98#define OMAP243X_GPMC_SIZE SZ_1M 115#define OMAP243X_GPMC_SIZE SZ_1M
99#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE 116#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
100#define OMAP243X_SDRC_VIRT 0xFD000000 117 /* 0x6D000000 --> 0xfd000000 */
118#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
101#define OMAP243X_SDRC_SIZE SZ_1M 119#define OMAP243X_SDRC_SIZE SZ_1M
102#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE 120#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
103#define OMAP243X_SMS_VIRT 0xFC000000 121 /* 0x6c000000 --> 0xfc000000 */
122#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
104#define OMAP243X_SMS_SIZE SZ_1M 123#define OMAP243X_SMS_SIZE SZ_1M
105 124
106/* DSP */ 125/* DSP */
@@ -121,12 +140,12 @@
121 */ 140 */
122 141
123/* We map both L3 and L4 on OMAP3 */ 142/* We map both L3 and L4 on OMAP3 */
124#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */ 143#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
125#define L3_34XX_VIRT 0xf8000000 144#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
126#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 145#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
127 146
128#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */ 147#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
129#define L4_34XX_VIRT 0xd8000000 148#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
130#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ 149#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
131 150
132/* 151/*
@@ -134,28 +153,33 @@
134 * VPOM3430 was not working for Int controller 153 * VPOM3430 was not working for Int controller
135 */ 154 */
136 155
137#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */ 156#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
138#define L4_WK_34XX_VIRT 0xd8300000 157#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
139#define L4_WK_34XX_SIZE SZ_1M 158#define L4_WK_34XX_SIZE SZ_1M
140 159
141#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */ 160#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
142#define L4_PER_34XX_VIRT 0xd9000000 161 /* 0x49000000 --> 0xfb000000 */
162#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
143#define L4_PER_34XX_SIZE SZ_1M 163#define L4_PER_34XX_SIZE SZ_1M
144 164
145#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */ 165#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
146#define L4_EMU_34XX_VIRT 0xe4000000 166 /* 0x54000000 --> 0xfe800000 */
147#define L4_EMU_34XX_SIZE SZ_64M 167#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
168#define L4_EMU_34XX_SIZE SZ_8M
148 169
149#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */ 170#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
150#define OMAP34XX_GPMC_VIRT 0xFE000000 171 /* 0x6e000000 --> 0xfe000000 */
172#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
151#define OMAP34XX_GPMC_SIZE SZ_1M 173#define OMAP34XX_GPMC_SIZE SZ_1M
152 174
153#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */ 175#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
154#define OMAP343X_SMS_VIRT 0xFC000000 176 /* 0x6c000000 --> 0xfc000000 */
177#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
155#define OMAP343X_SMS_SIZE SZ_1M 178#define OMAP343X_SMS_SIZE SZ_1M
156 179
157#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */ 180#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
158#define OMAP343X_SDRC_VIRT 0xFD000000 181 /* 0x6D000000 --> 0xfd000000 */
182#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
159#define OMAP343X_SDRC_SIZE SZ_1M 183#define OMAP343X_SDRC_SIZE SZ_1M
160 184
161/* DSP */ 185/* DSP */
@@ -176,32 +200,54 @@
176 */ 200 */
177 201
178/* We map both L3 and L4 on OMAP4 */ 202/* We map both L3 and L4 on OMAP4 */
179#define L3_44XX_PHYS L3_44XX_BASE 203#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
180#define L3_44XX_VIRT 0xd4000000 204#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
181#define L3_44XX_SIZE SZ_1M 205#define L3_44XX_SIZE SZ_1M
182 206
183#define L4_44XX_PHYS L4_44XX_BASE 207#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
184#define L4_44XX_VIRT 0xda000000 208#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
185#define L4_44XX_SIZE SZ_4M 209#define L4_44XX_SIZE SZ_4M
186 210
187 211
188#define L4_WK_44XX_PHYS L4_WK_44XX_BASE 212#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
189#define L4_WK_44XX_VIRT 0xda300000 213#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
190#define L4_WK_44XX_SIZE SZ_1M 214#define L4_WK_44XX_SIZE SZ_1M
191 215
192#define L4_PER_44XX_PHYS L4_PER_44XX_BASE 216#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
193#define L4_PER_44XX_VIRT 0xd8000000 217 /* 0x48000000 --> 0xfa000000 */
218#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
194#define L4_PER_44XX_SIZE SZ_4M 219#define L4_PER_44XX_SIZE SZ_4M
195 220
221#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
222 /* 0x49000000 --> 0xfb000000 */
223#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
224#define L4_ABE_44XX_SIZE SZ_1M
225
196#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE 226#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
197#define L4_EMU_44XX_VIRT 0xe4000000 227 /* 0x54000000 --> 0xfe800000 */
198#define L4_EMU_44XX_SIZE SZ_64M 228#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
229#define L4_EMU_44XX_SIZE SZ_8M
199 230
200#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE 231#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
201#define OMAP44XX_GPMC_VIRT 0xe0000000 232 /* 0x50000000 --> 0xf9000000 */
233#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
202#define OMAP44XX_GPMC_SIZE SZ_1M 234#define OMAP44XX_GPMC_SIZE SZ_1M
203 235
204 236
237#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
238 /* 0x4c000000 --> 0xfd100000 */
239#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
240#define OMAP44XX_EMIF1_SIZE SZ_1M
241
242#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
243 /* 0x4d000000 --> 0xfd200000 */
244#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
245#define OMAP44XX_EMIF2_SIZE SZ_1M
246
247#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
248 /* 0x4e000000 --> 0xfd300000 */
249#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
250#define OMAP44XX_DMM_SIZE SZ_1M
205/* 251/*
206 * ---------------------------------------------------------------------------- 252 * ----------------------------------------------------------------------------
207 * Omap specific register access 253 * Omap specific register access
diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 46d41ac83dbf..0752af9d099e 100644
--- a/arch/arm/plat-omap/include/mach/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -107,7 +107,7 @@ struct iommu_platform_data {
107#if defined(CONFIG_ARCH_OMAP1) 107#if defined(CONFIG_ARCH_OMAP1)
108#error "iommu for this processor not implemented yet" 108#error "iommu for this processor not implemented yet"
109#else 109#else
110#include <mach/iommu2.h> 110#include <plat/iommu2.h>
111#endif 111#endif
112 112
113/* 113/*
diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/plat/iommu2.h
index 10ad05f410e9..10ad05f410e9 100644
--- a/arch/arm/plat-omap/include/mach/iommu2.h
+++ b/arch/arm/plat-omap/include/plat/iommu2.h
diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
index bdc7ce5d7a4a..bdc7ce5d7a4a 100644
--- a/arch/arm/plat-omap/include/mach/iovmm.h
+++ b/arch/arm/plat-omap/include/plat/iovmm.h
diff --git a/arch/arm/plat-omap/include/mach/irda.h b/arch/arm/plat-omap/include/plat/irda.h
index 40f60339d1c6..40f60339d1c6 100644
--- a/arch/arm/plat-omap/include/mach/irda.h
+++ b/arch/arm/plat-omap/include/plat/irda.h
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 28a165058b61..ce5dd2d1dc21 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -86,49 +86,26 @@
86#define INT_1610_SSR_FIFO_0 29 86#define INT_1610_SSR_FIFO_0 29
87 87
88/* 88/*
89 * OMAP-730 specific IRQ numbers for interrupt handler 1 89 * OMAP-7xx specific IRQ numbers for interrupt handler 1
90 */ 90 */
91#define INT_730_IH2_FIQ 0 91#define INT_7XX_IH2_FIQ 0
92#define INT_730_IH2_IRQ 1 92#define INT_7XX_IH2_IRQ 1
93#define INT_730_USB_NON_ISO 2 93#define INT_7XX_USB_NON_ISO 2
94#define INT_730_USB_ISO 3 94#define INT_7XX_USB_ISO 3
95#define INT_730_ICR 4 95#define INT_7XX_ICR 4
96#define INT_730_EAC 5 96#define INT_7XX_EAC 5
97#define INT_730_GPIO_BANK1 6 97#define INT_7XX_GPIO_BANK1 6
98#define INT_730_GPIO_BANK2 7 98#define INT_7XX_GPIO_BANK2 7
99#define INT_730_GPIO_BANK3 8 99#define INT_7XX_GPIO_BANK3 8
100#define INT_730_McBSP2TX 10 100#define INT_7XX_McBSP2TX 10
101#define INT_730_McBSP2RX 11 101#define INT_7XX_McBSP2RX 11
102#define INT_730_McBSP2RX_OVF 12 102#define INT_7XX_McBSP2RX_OVF 12
103#define INT_730_LCD_LINE 14 103#define INT_7XX_LCD_LINE 14
104#define INT_730_GSM_PROTECT 15 104#define INT_7XX_GSM_PROTECT 15
105#define INT_730_TIMER3 16 105#define INT_7XX_TIMER3 16
106#define INT_730_GPIO_BANK5 17 106#define INT_7XX_GPIO_BANK5 17
107#define INT_730_GPIO_BANK6 18 107#define INT_7XX_GPIO_BANK6 18
108#define INT_730_SPGIO_WR 29 108#define INT_7XX_SPGIO_WR 29
109
110/*
111 * OMAP-850 specific IRQ numbers for interrupt handler 1
112 */
113#define INT_850_IH2_FIQ 0
114#define INT_850_IH2_IRQ 1
115#define INT_850_USB_NON_ISO 2
116#define INT_850_USB_ISO 3
117#define INT_850_ICR 4
118#define INT_850_EAC 5
119#define INT_850_GPIO_BANK1 6
120#define INT_850_GPIO_BANK2 7
121#define INT_850_GPIO_BANK3 8
122#define INT_850_McBSP2TX 10
123#define INT_850_McBSP2RX 11
124#define INT_850_McBSP2RX_OVF 12
125#define INT_850_LCD_LINE 14
126#define INT_850_GSM_PROTECT 15
127#define INT_850_TIMER3 16
128#define INT_850_GPIO_BANK5 17
129#define INT_850_GPIO_BANK6 18
130#define INT_850_SPGIO_WR 29
131
132 109
133/* 110/*
134 * IRQ numbers for interrupt handler 2 111 * IRQ numbers for interrupt handler 2
@@ -206,120 +183,62 @@
206#define INT_1610_SHA1MD5 (91 + IH2_BASE) 183#define INT_1610_SHA1MD5 (91 + IH2_BASE)
207 184
208/* 185/*
209 * OMAP-730 specific IRQ numbers for interrupt handler 2 186 * OMAP-7xx specific IRQ numbers for interrupt handler 2
210 */ 187 */
211#define INT_730_HW_ERRORS (0 + IH2_BASE) 188#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
212#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE) 189#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
213#define INT_730_CFCD (2 + IH2_BASE) 190#define INT_7XX_CFCD (2 + IH2_BASE)
214#define INT_730_CFIREQ (3 + IH2_BASE) 191#define INT_7XX_CFIREQ (3 + IH2_BASE)
215#define INT_730_I2C (4 + IH2_BASE) 192#define INT_7XX_I2C (4 + IH2_BASE)
216#define INT_730_PCC (5 + IH2_BASE) 193#define INT_7XX_PCC (5 + IH2_BASE)
217#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE) 194#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
218#define INT_730_SPI_100K_1 (7 + IH2_BASE) 195#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
219#define INT_730_SYREN_SPI (8 + IH2_BASE) 196#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
220#define INT_730_VLYNQ (9 + IH2_BASE) 197#define INT_7XX_VLYNQ (9 + IH2_BASE)
221#define INT_730_GPIO_BANK4 (10 + IH2_BASE) 198#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
222#define INT_730_McBSP1TX (11 + IH2_BASE) 199#define INT_7XX_McBSP1TX (11 + IH2_BASE)
223#define INT_730_McBSP1RX (12 + IH2_BASE) 200#define INT_7XX_McBSP1RX (12 + IH2_BASE)
224#define INT_730_McBSP1RX_OF (13 + IH2_BASE) 201#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
225#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE) 202#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
226#define INT_730_UART_MODEM_1 (15 + IH2_BASE) 203#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
227#define INT_730_MCSI (16 + IH2_BASE) 204#define INT_7XX_MCSI (16 + IH2_BASE)
228#define INT_730_uWireTX (17 + IH2_BASE) 205#define INT_7XX_uWireTX (17 + IH2_BASE)
229#define INT_730_uWireRX (18 + IH2_BASE) 206#define INT_7XX_uWireRX (18 + IH2_BASE)
230#define INT_730_SMC_CD (19 + IH2_BASE) 207#define INT_7XX_SMC_CD (19 + IH2_BASE)
231#define INT_730_SMC_IREQ (20 + IH2_BASE) 208#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
232#define INT_730_HDQ_1WIRE (21 + IH2_BASE) 209#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
233#define INT_730_TIMER32K (22 + IH2_BASE) 210#define INT_7XX_TIMER32K (22 + IH2_BASE)
234#define INT_730_MMC_SDIO (23 + IH2_BASE) 211#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
235#define INT_730_UPLD (24 + IH2_BASE) 212#define INT_7XX_UPLD (24 + IH2_BASE)
236#define INT_730_USB_HHC_1 (27 + IH2_BASE) 213#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
237#define INT_730_USB_HHC_2 (28 + IH2_BASE) 214#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
238#define INT_730_USB_GENI (29 + IH2_BASE) 215#define INT_7XX_USB_GENI (29 + IH2_BASE)
239#define INT_730_USB_OTG (30 + IH2_BASE) 216#define INT_7XX_USB_OTG (30 + IH2_BASE)
240#define INT_730_CAMERA_IF (31 + IH2_BASE) 217#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
241#define INT_730_RNG (32 + IH2_BASE) 218#define INT_7XX_RNG (32 + IH2_BASE)
242#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE) 219#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
243#define INT_730_DBB_RF_EN (34 + IH2_BASE) 220#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
244#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE) 221#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
245#define INT_730_SHA1_MD5 (36 + IH2_BASE) 222#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
246#define INT_730_SPI_100K_2 (37 + IH2_BASE) 223#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
247#define INT_730_RNG_IDLE (38 + IH2_BASE) 224#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
248#define INT_730_MPUIO (39 + IH2_BASE) 225#define INT_7XX_MPUIO (39 + IH2_BASE)
249#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) 226#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
250#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE) 227#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
251#define INT_730_LLPC_OE_RISING (42 + IH2_BASE) 228#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
252#define INT_730_LLPC_VSYNC (43 + IH2_BASE) 229#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
253#define INT_730_WAKE_UP_REQ (46 + IH2_BASE) 230#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
254#define INT_730_DMA_CH6 (53 + IH2_BASE) 231#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
255#define INT_730_DMA_CH7 (54 + IH2_BASE) 232#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
256#define INT_730_DMA_CH8 (55 + IH2_BASE) 233#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
257#define INT_730_DMA_CH9 (56 + IH2_BASE) 234#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
258#define INT_730_DMA_CH10 (57 + IH2_BASE) 235#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
259#define INT_730_DMA_CH11 (58 + IH2_BASE) 236#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
260#define INT_730_DMA_CH12 (59 + IH2_BASE) 237#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
261#define INT_730_DMA_CH13 (60 + IH2_BASE) 238#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
262#define INT_730_DMA_CH14 (61 + IH2_BASE) 239#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
263#define INT_730_DMA_CH15 (62 + IH2_BASE) 240#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
264#define INT_730_NAND (63 + IH2_BASE) 241#define INT_7XX_NAND (63 + IH2_BASE)
265
266/*
267 * OMAP-850 specific IRQ numbers for interrupt handler 2
268 */
269#define INT_850_HW_ERRORS (0 + IH2_BASE)
270#define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE)
271#define INT_850_CFCD (2 + IH2_BASE)
272#define INT_850_CFIREQ (3 + IH2_BASE)
273#define INT_850_I2C (4 + IH2_BASE)
274#define INT_850_PCC (5 + IH2_BASE)
275#define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE)
276#define INT_850_SPI_100K_1 (7 + IH2_BASE)
277#define INT_850_SYREN_SPI (8 + IH2_BASE)
278#define INT_850_VLYNQ (9 + IH2_BASE)
279#define INT_850_GPIO_BANK4 (10 + IH2_BASE)
280#define INT_850_McBSP1TX (11 + IH2_BASE)
281#define INT_850_McBSP1RX (12 + IH2_BASE)
282#define INT_850_McBSP1RX_OF (13 + IH2_BASE)
283#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE)
284#define INT_850_UART_MODEM_1 (15 + IH2_BASE)
285#define INT_850_MCSI (16 + IH2_BASE)
286#define INT_850_uWireTX (17 + IH2_BASE)
287#define INT_850_uWireRX (18 + IH2_BASE)
288#define INT_850_SMC_CD (19 + IH2_BASE)
289#define INT_850_SMC_IREQ (20 + IH2_BASE)
290#define INT_850_HDQ_1WIRE (21 + IH2_BASE)
291#define INT_850_TIMER32K (22 + IH2_BASE)
292#define INT_850_MMC_SDIO (23 + IH2_BASE)
293#define INT_850_UPLD (24 + IH2_BASE)
294#define INT_850_USB_HHC_1 (27 + IH2_BASE)
295#define INT_850_USB_HHC_2 (28 + IH2_BASE)
296#define INT_850_USB_GENI (29 + IH2_BASE)
297#define INT_850_USB_OTG (30 + IH2_BASE)
298#define INT_850_CAMERA_IF (31 + IH2_BASE)
299#define INT_850_RNG (32 + IH2_BASE)
300#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE)
301#define INT_850_DBB_RF_EN (34 + IH2_BASE)
302#define INT_850_MPUIO_KEYPAD (35 + IH2_BASE)
303#define INT_850_SHA1_MD5 (36 + IH2_BASE)
304#define INT_850_SPI_100K_2 (37 + IH2_BASE)
305#define INT_850_RNG_IDLE (38 + IH2_BASE)
306#define INT_850_MPUIO (39 + IH2_BASE)
307#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
308#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE)
309#define INT_850_LLPC_OE_RISING (42 + IH2_BASE)
310#define INT_850_LLPC_VSYNC (43 + IH2_BASE)
311#define INT_850_WAKE_UP_REQ (46 + IH2_BASE)
312#define INT_850_DMA_CH6 (53 + IH2_BASE)
313#define INT_850_DMA_CH7 (54 + IH2_BASE)
314#define INT_850_DMA_CH8 (55 + IH2_BASE)
315#define INT_850_DMA_CH9 (56 + IH2_BASE)
316#define INT_850_DMA_CH10 (57 + IH2_BASE)
317#define INT_850_DMA_CH11 (58 + IH2_BASE)
318#define INT_850_DMA_CH12 (59 + IH2_BASE)
319#define INT_850_DMA_CH13 (60 + IH2_BASE)
320#define INT_850_DMA_CH14 (61 + IH2_BASE)
321#define INT_850_DMA_CH15 (62 + IH2_BASE)
322#define INT_850_NAND (63 + IH2_BASE)
323 242
324#define INT_24XX_SYS_NIRQ 7 243#define INT_24XX_SYS_NIRQ 7
325#define INT_24XX_SDMA_IRQ0 12 244#define INT_24XX_SDMA_IRQ0 12
@@ -558,9 +477,14 @@
558 477
559#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 478#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
560 479
480#define INTCPS_NR_MIR_REGS 3
481#define INTCPS_NR_IRQS 96
482
561#ifndef __ASSEMBLY__ 483#ifndef __ASSEMBLY__
562extern void omap_init_irq(void); 484extern void omap_init_irq(void);
563extern int omap_irq_pending(void); 485extern int omap_irq_pending(void);
486void omap_intc_save_context(void);
487void omap_intc_restore_context(void);
564#endif 488#endif
565 489
566#include <mach/hardware.h> 490#include <mach/hardware.h>
diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 3ae52ccc793c..3ae52ccc793c 100644
--- a/arch/arm/plat-omap/include/mach/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
diff --git a/arch/arm/plat-omap/include/mach/lcd_mipid.h b/arch/arm/plat-omap/include/plat/lcd_mipid.h
index 8e52c6572281..8e52c6572281 100644
--- a/arch/arm/plat-omap/include/mach/lcd_mipid.h
+++ b/arch/arm/plat-omap/include/plat/lcd_mipid.h
diff --git a/arch/arm/plat-omap/include/mach/led.h b/arch/arm/plat-omap/include/plat/led.h
index 25e451e7e2fd..25e451e7e2fd 100644
--- a/arch/arm/plat-omap/include/mach/led.h
+++ b/arch/arm/plat-omap/include/plat/led.h
diff --git a/arch/arm/plat-omap/include/mach/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index b7a6991814ec..729166b76a7c 100644
--- a/arch/arm/plat-omap/include/mach/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -6,9 +6,9 @@
6#include <linux/wait.h> 6#include <linux/wait.h>
7#include <linux/workqueue.h> 7#include <linux/workqueue.h>
8#include <linux/blkdev.h> 8#include <linux/blkdev.h>
9#include <linux/interrupt.h>
9 10
10typedef u32 mbox_msg_t; 11typedef u32 mbox_msg_t;
11typedef void (mbox_receiver_t)(mbox_msg_t msg);
12struct omap_mbox; 12struct omap_mbox;
13 13
14typedef int __bitwise omap_mbox_irq_t; 14typedef int __bitwise omap_mbox_irq_t;
@@ -29,8 +29,10 @@ struct omap_mbox_ops {
29 int (*fifo_empty)(struct omap_mbox *mbox); 29 int (*fifo_empty)(struct omap_mbox *mbox);
30 int (*fifo_full)(struct omap_mbox *mbox); 30 int (*fifo_full)(struct omap_mbox *mbox);
31 /* irq */ 31 /* irq */
32 void (*enable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); 32 void (*enable_irq)(struct omap_mbox *mbox,
33 void (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); 33 omap_mbox_irq_t irq);
34 void (*disable_irq)(struct omap_mbox *mbox,
35 omap_mbox_irq_t irq);
34 void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); 36 void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
35 int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); 37 int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
36 /* ctx */ 38 /* ctx */
@@ -42,6 +44,7 @@ struct omap_mbox_queue {
42 spinlock_t lock; 44 spinlock_t lock;
43 struct request_queue *queue; 45 struct request_queue *queue;
44 struct work_struct work; 46 struct work_struct work;
47 struct tasklet_struct tasklet;
45 int (*callback)(void *); 48 int (*callback)(void *);
46 struct omap_mbox *mbox; 49 struct omap_mbox *mbox;
47}; 50};
@@ -64,7 +67,7 @@ struct omap_mbox {
64 void (*err_notify)(void); 67 void (*err_notify)(void);
65}; 68};
66 69
67int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *); 70int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
68void omap_mbox_init_seq(struct omap_mbox *); 71void omap_mbox_init_seq(struct omap_mbox *);
69 72
70struct omap_mbox *omap_mbox_get(const char *); 73struct omap_mbox *omap_mbox_get(const char *);
@@ -93,4 +96,16 @@ static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
93 mbox->ops->restore_ctx(mbox); 96 mbox->ops->restore_ctx(mbox);
94} 97}
95 98
99static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
100 omap_mbox_irq_t irq)
101{
102 mbox->ops->enable_irq(mbox, irq);
103}
104
105static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
106 omap_mbox_irq_t irq)
107{
108 mbox->ops->disable_irq(mbox, irq);
109}
110
96#endif /* MAILBOX_H */ 111#endif /* MAILBOX_H */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index e0d6eca222cc..4f22e5bb7ff7 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -28,10 +28,10 @@
28#include <linux/spinlock.h> 28#include <linux/spinlock.h>
29 29
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <mach/clock.h> 31#include <plat/clock.h>
32 32
33#define OMAP730_MCBSP1_BASE 0xfffb1000 33#define OMAP7XX_MCBSP1_BASE 0xfffb1000
34#define OMAP730_MCBSP2_BASE 0xfffb1800 34#define OMAP7XX_MCBSP2_BASE 0xfffb1800
35 35
36#define OMAP1510_MCBSP1_BASE 0xe1011800 36#define OMAP1510_MCBSP1_BASE 0xe1011800
37#define OMAP1510_MCBSP2_BASE 0xfffb1000 37#define OMAP1510_MCBSP2_BASE 0xfffb1000
@@ -58,7 +58,7 @@
58#define OMAP44XX_MCBSP3_BASE 0x49026000 58#define OMAP44XX_MCBSP3_BASE 0x49026000
59#define OMAP44XX_MCBSP4_BASE 0x48074000 59#define OMAP44XX_MCBSP4_BASE 0x48074000
60 60
61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
62 62
63#define OMAP_MCBSP_REG_DRR2 0x00 63#define OMAP_MCBSP_REG_DRR2 0x00
64#define OMAP_MCBSP_REG_DRR1 0x02 64#define OMAP_MCBSP_REG_DRR1 0x02
diff --git a/arch/arm/plat-omap/include/mach/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 1254e4945b6f..1254e4945b6f 100644
--- a/arch/arm/plat-omap/include/mach/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/plat/memory.h
index 9ad41dc484c1..3325f7b49eaa 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -68,6 +68,13 @@
68 __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \ 68 __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
69 __dma; }) 69 __dma; })
70 70
71#define __arch_dma_to_page(dev, addr) \
72 ({ dma_addr_t __dma = addr; \
73 if (is_lbus_device(dev)) \
74 __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \
75 phys_to_page(__dma); \
76 })
77
71#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ 78#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
72 lbus_to_virt(addr) : \ 79 lbus_to_virt(addr) : \
73 __phys_to_virt(addr)); }) 80 __phys_to_virt(addr)); })
diff --git a/arch/arm/plat-omap/include/mach/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h
index 3122bf68c7ce..3122bf68c7ce 100644
--- a/arch/arm/plat-omap/include/mach/menelaus.h
+++ b/arch/arm/plat-omap/include/plat/menelaus.h
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 7229b9593301..29937137bf3e 100644
--- a/arch/arm/plat-omap/include/mach/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -15,7 +15,7 @@
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/mmc/host.h> 16#include <linux/mmc/host.h>
17 17
18#include <mach/board.h> 18#include <plat/board.h>
19 19
20#define OMAP15XX_NR_MMC 1 20#define OMAP15XX_NR_MMC 1
21#define OMAP16XX_NR_MMC 2 21#define OMAP16XX_NR_MMC 2
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index 0f49d2d563d9..ba77de601501 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -51,23 +51,13 @@
51 .pu_pd_reg = PU_PD_SEL_##reg, \ 51 .pu_pd_reg = PU_PD_SEL_##reg, \
52 .pu_pd_val = status, 52 .pu_pd_val = status,
53 53
54#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \ 54#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
55 .mux_reg = OMAP730_IO_CONF_##reg, \ 55 .mux_reg = OMAP7XX_IO_CONF_##reg, \
56 .mask_offset = mode_offset, \ 56 .mask_offset = mode_offset, \
57 .mask = mode, 57 .mask = mode,
58 58
59#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \ 59#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
60 .pull_reg = OMAP730_IO_CONF_##reg, \ 60 .pull_reg = OMAP7XX_IO_CONF_##reg, \
61 .pull_bit = bit, \
62 .pull_val = status,
63
64#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
65 .mux_reg = OMAP850_IO_CONF_##reg, \
66 .mask_offset = mode_offset, \
67 .mask = mode,
68
69#define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \
70 .pull_reg = OMAP850_IO_CONF_##reg, \
71 .pull_bit = bit, \ 61 .pull_bit = bit, \
72 .pull_val = status, 62 .pull_val = status,
73 63
@@ -84,21 +74,12 @@
84#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ 74#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
85 .pu_pd_val = status, 75 .pu_pd_val = status,
86 76
87#define MUX_REG_730(reg, mode_offset, mode) \ 77#define MUX_REG_7XX(reg, mode_offset, mode) \
88 .mux_reg = OMAP730_IO_CONF_##reg, \ 78 .mux_reg = OMAP7XX_IO_CONF_##reg, \
89 .mask_offset = mode_offset, \ 79 .mask_offset = mode_offset, \
90 .mask = mode, 80 .mask = mode,
91 81
92#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \ 82#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
93 .pull_bit = bit, \
94 .pull_val = status,
95
96#define MUX_REG_850(reg, mode_offset, mode) \
97 .mux_reg = OMAP850_IO_CONF_##reg, \
98 .mask_offset = mode_offset, \
99 .mask = mode,
100
101#define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \
102 .pull_bit = bit, \ 83 .pull_bit = bit, \
103 .pull_val = status, 84 .pull_val = status,
104 85
@@ -118,32 +99,21 @@
118 99
119/* 100/*
120 * OMAP730/850 has a slightly different config for the pin mux. 101 * OMAP730/850 has a slightly different config for the pin mux.
121 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and 102 * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
122 * not the FUNC_MUX_CTRL_x regs from hardware.h 103 * not the FUNC_MUX_CTRL_x regs from hardware.h
123 * - for pull-up/down, only has one enable bit which is is in the same register 104 * - for pull-up/down, only has one enable bit which is is in the same register
124 * as mux config 105 * as mux config
125 */ 106 */
126#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ 107#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
127 pull_bit, pull_status, debug_status)\
128{ \
129 .name = desc, \
130 .debug = debug_status, \
131 MUX_REG_730(mux_reg, mode_offset, mode) \
132 PULL_REG_730(mux_reg, pull_bit, pull_status) \
133 PU_PD_REG(NA, 0) \
134},
135
136#define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \
137 pull_bit, pull_status, debug_status)\ 108 pull_bit, pull_status, debug_status)\
138{ \ 109{ \
139 .name = desc, \ 110 .name = desc, \
140 .debug = debug_status, \ 111 .debug = debug_status, \
141 MUX_REG_850(mux_reg, mode_offset, mode) \ 112 MUX_REG_7XX(mux_reg, mode_offset, mode) \
142 PULL_REG_850(mux_reg, pull_bit, pull_status) \ 113 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
143 PU_PD_REG(NA, 0) \ 114 PU_PD_REG(NA, 0) \
144}, 115},
145 116
146
147#define MUX_CFG_24XX(desc, reg_offset, mode, \ 117#define MUX_CFG_24XX(desc, reg_offset, mode, \
148 pull_en, pull_mode, dbg) \ 118 pull_en, pull_mode, dbg) \
149{ \ 119{ \
@@ -232,45 +202,30 @@ struct pin_config {
232 202
233}; 203};
234 204
235enum omap730_index { 205enum omap7xx_index {
236 /* OMAP 730 keyboard */ 206 /* OMAP 730 keyboard */
237 E2_730_KBR0, 207 E2_7XX_KBR0,
238 J7_730_KBR1, 208 J7_7XX_KBR1,
239 E1_730_KBR2, 209 E1_7XX_KBR2,
240 F3_730_KBR3, 210 F3_7XX_KBR3,
241 D2_730_KBR4, 211 D2_7XX_KBR4,
242 C2_730_KBC0, 212 C2_7XX_KBC0,
243 D3_730_KBC1, 213 D3_7XX_KBC1,
244 E4_730_KBC2, 214 E4_7XX_KBC2,
245 F4_730_KBC3, 215 F4_7XX_KBC3,
246 E3_730_KBC4, 216 E3_7XX_KBC4,
247 217
248 /* USB */ 218 /* USB */
249 AA17_730_USB_DM, 219 AA17_7XX_USB_DM,
250 W16_730_USB_PU_EN, 220 W16_7XX_USB_PU_EN,
251 W17_730_USB_VBUSI, 221 W17_7XX_USB_VBUSI,
222
223 /* MMC */
224 MMC_7XX_CMD,
225 MMC_7XX_CLK,
226 MMC_7XX_DAT0,
252}; 227};
253 228
254enum omap850_index {
255 /* OMAP 850 keyboard */
256 E2_850_KBR0,
257 J7_850_KBR1,
258 E1_850_KBR2,
259 F3_850_KBR3,
260 D2_850_KBR4,
261 C2_850_KBC0,
262 D3_850_KBC1,
263 E4_850_KBC2,
264 F4_850_KBC3,
265 E3_850_KBC4,
266
267 /* USB */
268 AA17_850_USB_DM,
269 W16_850_USB_PU_EN,
270 W17_850_USB_VBUSI,
271};
272
273
274enum omap1xxx_index { 229enum omap1xxx_index {
275 /* UART1 (BT_UART_GATING)*/ 230 /* UART1 (BT_UART_GATING)*/
276 UART1_TX = 0, 231 UART1_TX = 0,
@@ -879,6 +834,10 @@ enum omap34xx_index {
879 AH4_3430_MMC2_DAT1, 834 AH4_3430_MMC2_DAT1,
880 AG4_3430_MMC2_DAT2, 835 AG4_3430_MMC2_DAT2,
881 AF4_3430_MMC2_DAT3, 836 AF4_3430_MMC2_DAT3,
837 AE4_3430_MMC2_DAT4,
838 AH3_3430_MMC2_DAT5,
839 AF3_3430_MMC2_DAT6,
840 AE3_3430_MMC2_DAT7,
882 841
883 /* MMC3 */ 842 /* MMC3 */
884 AF10_3430_MMC3_CLK, 843 AF10_3430_MMC3_CLK,
@@ -890,6 +849,11 @@ enum omap34xx_index {
890 849
891 /* SYS_NIRQ T2 INT1 */ 850 /* SYS_NIRQ T2 INT1 */
892 AF26_34XX_SYS_NIRQ, 851 AF26_34XX_SYS_NIRQ,
852
853 /* EHCI GPIO's for OMAP3EVM (Rev >= E) */
854 AH14_34XX_GPIO21,
855 AF9_34XX_GPIO22,
856 U3_34XX_GPIO61,
893}; 857};
894 858
895struct omap_mux_cfg { 859struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 631a7bed1eef..631a7bed1eef 100644
--- a/arch/arm/plat-omap/include/mach/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
diff --git a/arch/arm/plat-omap/include/mach/omap-alsa.h b/arch/arm/plat-omap/include/plat/omap-alsa.h
index bdf30a0f87f2..b53055b390d0 100644
--- a/arch/arm/plat-omap/include/mach/omap-alsa.h
+++ b/arch/arm/plat-omap/include/plat/omap-alsa.h
@@ -40,10 +40,10 @@
40#ifndef __OMAP_ALSA_H 40#ifndef __OMAP_ALSA_H
41#define __OMAP_ALSA_H 41#define __OMAP_ALSA_H
42 42
43#include <mach/dma.h> 43#include <plat/dma.h>
44#include <sound/core.h> 44#include <sound/core.h>
45#include <sound/pcm.h> 45#include <sound/pcm.h>
46#include <mach/mcbsp.h> 46#include <plat/mcbsp.h>
47#include <linux/platform_device.h> 47#include <linux/platform_device.h>
48 48
49#define DMA_BUF_SIZE (1024 * 8) 49#define DMA_BUF_SIZE (1024 * 8)
diff --git a/arch/arm/plat-omap/include/mach/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index 3ee41d711492..3ee41d711492 100644
--- a/arch/arm/plat-omap/include/mach/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/plat/omap1510.h
index d24004668138..d24004668138 100644
--- a/arch/arm/plat-omap/include/mach/omap1510.h
+++ b/arch/arm/plat-omap/include/plat/omap1510.h
diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h
index 0e69b504c25f..0e69b504c25f 100644
--- a/arch/arm/plat-omap/include/mach/omap16xx.h
+++ b/arch/arm/plat-omap/include/plat/omap16xx.h
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
index 696edfc145a6..696edfc145a6 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index f8d186a73712..077f05979f86 100644
--- a/arch/arm/plat-omap/include/mach/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -72,16 +72,15 @@
72#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F) 72#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F)
73#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007) 73#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
74 74
75#define OMAP34XX_IVA_INTC_BASE 0x40000000
76#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) 75#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
77#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
78#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) 76#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
77#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
78#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
79#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
80#define OMAP34XX_SR1_BASE 0x480C9000
81#define OMAP34XX_SR2_BASE 0x480CB000
79 82
80#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) 83#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
81 84
82#define OMAP34XX_DSP_BASE 0x58000000
83#define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0)
84#define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000)
85#define OMAP34XX_DSP_MMU_BASE (OMAP34XX_DSP_BASE + 0x2000000)
86#endif /* __ASM_ARCH_OMAP34XX_H */ 85#endif /* __ASM_ARCH_OMAP34XX_H */
87 86
diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index b3ba5ac7b4a4..e52902a15c1a 100644
--- a/arch/arm/plat-omap/include/mach/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -22,6 +22,9 @@
22#define L4_PER_44XX_BASE 0x48000000 22#define L4_PER_44XX_BASE 0x48000000
23#define L4_EMU_44XX_BASE 0x54000000 23#define L4_EMU_44XX_BASE 0x54000000
24#define L3_44XX_BASE 0x44000000 24#define L3_44XX_BASE 0x44000000
25#define OMAP44XX_EMIF1_BASE 0x4c000000
26#define OMAP44XX_EMIF2_BASE 0x4d000000
27#define OMAP44XX_DMM_BASE 0x4e000000
25#define OMAP4430_32KSYNCT_BASE 0x4a304000 28#define OMAP4430_32KSYNCT_BASE 0x4a304000
26#define OMAP4430_CM_BASE 0x4a004000 29#define OMAP4430_CM_BASE 0x4a004000
27#define OMAP4430_PRM_BASE 0x48306000 30#define OMAP4430_PRM_BASE 0x48306000
@@ -33,14 +36,11 @@
33#define IRQ_SIR_IRQ 0x0040 36#define IRQ_SIR_IRQ 0x0040
34#define OMAP44XX_GIC_DIST_BASE 0x48241000 37#define OMAP44XX_GIC_DIST_BASE 0x48241000
35#define OMAP44XX_GIC_CPU_BASE 0x48240100 38#define OMAP44XX_GIC_CPU_BASE 0x48240100
36#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
37#define OMAP44XX_SCU_BASE 0x48240000 39#define OMAP44XX_SCU_BASE 0x48240000
38#define OMAP44XX_VA_SCU_BASE OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE)
39#define OMAP44XX_LOCAL_TWD_BASE 0x48240600 40#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
40#define OMAP44XX_VA_LOCAL_TWD_BASE OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
41#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100
42#define OMAP44XX_WKUPGEN_BASE 0x48281000 41#define OMAP44XX_WKUPGEN_BASE 0x48281000
43#define OMAP44XX_VA_WKUPGEN_BASE OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE) 42
43#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
44 44
45#endif /* __ASM_ARCH_OMAP44XX_H */ 45#endif /* __ASM_ARCH_OMAP44XX_H */
46 46
diff --git a/arch/arm/plat-omap/include/mach/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h
index 14272bc1a6fd..14272bc1a6fd 100644
--- a/arch/arm/plat-omap/include/mach/omap730.h
+++ b/arch/arm/plat-omap/include/plat/omap730.h
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h
new file mode 100644
index 000000000000..53f52414b0e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap7xx.h
@@ -0,0 +1,104 @@
1/* arch/arm/plat-omap/include/mach/omap7xx.h
2 *
3 * Hardware definitions for TI OMAP7XX processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7 * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#ifndef __ASM_ARCH_OMAP7XX_H
31#define __ASM_ARCH_OMAP7XX_H
32
33/*
34 * ----------------------------------------------------------------------------
35 * Base addresses
36 * ----------------------------------------------------------------------------
37 */
38
39/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
40
41#define OMAP7XX_DSP_BASE 0xE0000000
42#define OMAP7XX_DSP_SIZE 0x50000
43#define OMAP7XX_DSP_START 0xE0000000
44
45#define OMAP7XX_DSPREG_BASE 0xE1000000
46#define OMAP7XX_DSPREG_SIZE SZ_128K
47#define OMAP7XX_DSPREG_START 0xE1000000
48
49/*
50 * ----------------------------------------------------------------------------
51 * OMAP7XX specific configuration registers
52 * ----------------------------------------------------------------------------
53 */
54#define OMAP7XX_CONFIG_BASE 0xfffe1000
55#define OMAP7XX_IO_CONF_0 0xfffe1070
56#define OMAP7XX_IO_CONF_1 0xfffe1074
57#define OMAP7XX_IO_CONF_2 0xfffe1078
58#define OMAP7XX_IO_CONF_3 0xfffe107c
59#define OMAP7XX_IO_CONF_4 0xfffe1080
60#define OMAP7XX_IO_CONF_5 0xfffe1084
61#define OMAP7XX_IO_CONF_6 0xfffe1088
62#define OMAP7XX_IO_CONF_7 0xfffe108c
63#define OMAP7XX_IO_CONF_8 0xfffe1090
64#define OMAP7XX_IO_CONF_9 0xfffe1094
65#define OMAP7XX_IO_CONF_10 0xfffe1098
66#define OMAP7XX_IO_CONF_11 0xfffe109c
67#define OMAP7XX_IO_CONF_12 0xfffe10a0
68#define OMAP7XX_IO_CONF_13 0xfffe10a4
69
70#define OMAP7XX_MODE_1 0xfffe1010
71#define OMAP7XX_MODE_2 0xfffe1014
72
73/* CSMI specials: in terms of base + offset */
74#define OMAP7XX_MODE2_OFFSET 0x14
75
76/*
77 * ----------------------------------------------------------------------------
78 * OMAP7XX traffic controller configuration registers
79 * ----------------------------------------------------------------------------
80 */
81#define OMAP7XX_FLASH_CFG_0 0xfffecc10
82#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
83#define OMAP7XX_FLASH_CFG_1 0xfffecc14
84#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
85
86/*
87 * ----------------------------------------------------------------------------
88 * OMAP7XX DSP control registers
89 * ----------------------------------------------------------------------------
90 */
91#define OMAP7XX_ICR_BASE 0xfffbb800
92#define OMAP7XX_DSP_M_CTL 0xfffbb804
93#define OMAP7XX_DSP_MMU_BASE 0xfffed200
94
95/*
96 * ----------------------------------------------------------------------------
97 * OMAP7XX PCC_UPLD configuration registers
98 * ----------------------------------------------------------------------------
99 */
100#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
101#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
102
103#endif /* __ASM_ARCH_OMAP7XX_H */
104
diff --git a/arch/arm/plat-omap/include/mach/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h
index c33f67981712..c33f67981712 100644
--- a/arch/arm/plat-omap/include/mach/omap850.h
+++ b/arch/arm/plat-omap/include/plat/omap850.h
diff --git a/arch/arm/plat-omap/include/mach/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index bd0e136db337..11a9773a4e7f 100644
--- a/arch/arm/plat-omap/include/mach/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -34,7 +34,7 @@
34#include <linux/kernel.h> 34#include <linux/kernel.h>
35#include <linux/platform_device.h> 35#include <linux/platform_device.h>
36 36
37#include <mach/omap_hwmod.h> 37#include <plat/omap_hwmod.h>
38 38
39/* omap_device._state values */ 39/* omap_device._state values */
40#define OMAP_DEVICE_STATE_UNKNOWN 0 40#define OMAP_DEVICE_STATE_UNKNOWN 0
diff --git a/arch/arm/plat-omap/include/mach/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1f79c20e2929..dbdd123eca16 100644
--- a/arch/arm/plat-omap/include/mach/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -35,7 +35,7 @@
35#include <linux/kernel.h> 35#include <linux/kernel.h>
36#include <linux/ioport.h> 36#include <linux/ioport.h>
37 37
38#include <mach/cpu.h> 38#include <plat/cpu.h>
39 39
40struct omap_device; 40struct omap_device;
41 41
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/plat/omapfb.h
index b226bdf45739..bfef7ab95f17 100644
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ b/arch/arm/plat-omap/include/plat/omapfb.h
@@ -168,7 +168,7 @@ enum omapfb_update_mode {
168#include <linux/fb.h> 168#include <linux/fb.h>
169#include <linux/mutex.h> 169#include <linux/mutex.h>
170 170
171#include <mach/board.h> 171#include <plat/board.h>
172 172
173#define OMAP_LCDC_INV_VSYNC 0x0001 173#define OMAP_LCDC_INV_VSYNC 0x0001
174#define OMAP_LCDC_INV_HSYNC 0x0002 174#define OMAP_LCDC_INV_HSYNC 0x0002
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index 72f433d7d827..72f433d7d827 100644
--- a/arch/arm/plat-omap/include/mach/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
diff --git a/arch/arm/plat-omap/include/mach/param.h b/arch/arm/plat-omap/include/plat/param.h
index 1eb4dc326979..1eb4dc326979 100644
--- a/arch/arm/plat-omap/include/mach/param.h
+++ b/arch/arm/plat-omap/include/plat/param.h
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index fa6461423bd0..3d45ee1d3cf4 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -19,7 +19,7 @@
19 19
20#include <asm/atomic.h> 20#include <asm/atomic.h>
21 21
22#include <mach/cpu.h> 22#include <plat/cpu.h>
23 23
24 24
25/* Powerdomain basic power states */ 25/* Powerdomain basic power states */
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index cda2a70397b4..e63e94e18975 100644
--- a/arch/arm/plat-omap/include/mach/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -27,9 +27,13 @@ u32 omap_prcm_get_reset_sources(void);
27void omap_prcm_arch_reset(char mode); 27void omap_prcm_arch_reset(char mode);
28int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); 28int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
29 29
30#endif 30#define START_PADCONF_SAVE 0x2
31#define PADCONF_SAVE_DONE 0x1
31 32
33void omap3_prcm_save_context(void);
34void omap3_prcm_restore_context(void);
32 35
36#endif
33 37
34 38
35 39
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 1c09c78a48f2..f704030d2a70 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -44,6 +44,12 @@
44#define SDRC_RFR_CTRL_1 0x0D4 44#define SDRC_RFR_CTRL_1 0x0D4
45#define SDRC_MANUAL_1 0x0D8 45#define SDRC_MANUAL_1 0x0D8
46 46
47#define SDRC_POWER_AUTOCOUNT_SHIFT 8
48#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
49#define SDRC_POWER_CLKCTRL_SHIFT 4
50#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
51#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
52
47/* 53/*
48 * These values represent the number of memory clock cycles between 54 * These values represent the number of memory clock cycles between
49 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 55 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
@@ -80,11 +86,11 @@
80 */ 86 */
81 87
82#define OMAP242X_SMS_REGADDR(reg) \ 88#define OMAP242X_SMS_REGADDR(reg) \
83 (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg) 89 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
84#define OMAP243X_SMS_REGADDR(reg) \ 90#define OMAP243X_SMS_REGADDR(reg) \
85 (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg) 91 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
86#define OMAP343X_SMS_REGADDR(reg) \ 92#define OMAP343X_SMS_REGADDR(reg) \
87 (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg) 93 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
88 94
89/* SMS register offsets - read/write with sms_{read,write}_reg() */ 95/* SMS register offsets - read/write with sms_{read,write}_reg() */
90 96
@@ -120,6 +126,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
120int omap2_sdrc_get_params(unsigned long r, 126int omap2_sdrc_get_params(unsigned long r,
121 struct omap_sdrc_params **sdrc_cs0, 127 struct omap_sdrc_params **sdrc_cs0,
122 struct omap_sdrc_params **sdrc_cs1); 128 struct omap_sdrc_params **sdrc_cs1);
129void omap2_sms_save_context(void);
130void omap2_sms_restore_context(void);
123 131
124#ifdef CONFIG_ARCH_OMAP2 132#ifdef CONFIG_ARCH_OMAP2
125 133
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index e249186d26e2..9951345a25d6 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -20,26 +20,22 @@
20#define OMAP_UART1_BASE 0xfffb0000 20#define OMAP_UART1_BASE 0xfffb0000
21#define OMAP_UART2_BASE 0xfffb0800 21#define OMAP_UART2_BASE 0xfffb0800
22#define OMAP_UART3_BASE 0xfffb9800 22#define OMAP_UART3_BASE 0xfffb9800
23#define OMAP_MAX_NR_PORTS 3
24#elif defined(CONFIG_ARCH_OMAP2) 23#elif defined(CONFIG_ARCH_OMAP2)
25/* OMAP2 serial ports */ 24/* OMAP2 serial ports */
26#define OMAP_UART1_BASE 0x4806a000 25#define OMAP_UART1_BASE 0x4806a000
27#define OMAP_UART2_BASE 0x4806c000 26#define OMAP_UART2_BASE 0x4806c000
28#define OMAP_UART3_BASE 0x4806e000 27#define OMAP_UART3_BASE 0x4806e000
29#define OMAP_MAX_NR_PORTS 3
30#elif defined(CONFIG_ARCH_OMAP3) 28#elif defined(CONFIG_ARCH_OMAP3)
31/* OMAP3 serial ports */ 29/* OMAP3 serial ports */
32#define OMAP_UART1_BASE 0x4806a000 30#define OMAP_UART1_BASE 0x4806a000
33#define OMAP_UART2_BASE 0x4806c000 31#define OMAP_UART2_BASE 0x4806c000
34#define OMAP_UART3_BASE 0x49020000 32#define OMAP_UART3_BASE 0x49020000
35#define OMAP_MAX_NR_PORTS 3
36#elif defined(CONFIG_ARCH_OMAP4) 33#elif defined(CONFIG_ARCH_OMAP4)
37/* OMAP4 serial ports */ 34/* OMAP4 serial ports */
38#define OMAP_UART1_BASE 0x4806a000 35#define OMAP_UART1_BASE 0x4806a000
39#define OMAP_UART2_BASE 0x4806c000 36#define OMAP_UART2_BASE 0x4806c000
40#define OMAP_UART3_BASE 0x48020000 37#define OMAP_UART3_BASE 0x48020000
41#define OMAP_UART4_BASE 0x4806e000 38#define OMAP_UART4_BASE 0x4806e000
42#define OMAP_MAX_NR_PORTS 4
43#endif 39#endif
44 40
45#define OMAP1510_BASE_BAUD (12000000/16) 41#define OMAP1510_BASE_BAUD (12000000/16)
diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index dcaa8fde7063..dcaa8fde7063 100644
--- a/arch/arm/plat-omap/include/mach/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 8974e3fc2691..16a1b458d53c 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -27,6 +27,7 @@ extern u32 omap3_configure_core_dpll(
27 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, 27 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
28 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, 28 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
29 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); 29 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
30extern void omap3_sram_restore_context(void);
30 31
31/* Do not use these */ 32/* Do not use these */
32extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 33extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -68,4 +69,10 @@ extern u32 omap3_sram_configure_core_dpll(
68 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); 69 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
69extern unsigned long omap3_sram_configure_core_dpll_sz; 70extern unsigned long omap3_sram_configure_core_dpll_sz;
70 71
72#ifdef CONFIG_PM
73extern void omap_push_sram_idle(void);
74#else
75static inline void omap_push_sram_idle(void) {}
76#endif /* CONFIG_PM */
77
71#endif 78#endif
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/plat/system.h
index ed8ec7477261..c58a4ef42a45 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/plat/system.h
@@ -9,7 +9,7 @@
9#include <asm/mach-types.h> 9#include <asm/mach-types.h>
10#include <mach/hardware.h> 10#include <mach/hardware.h>
11 11
12#include <mach/prcm.h> 12#include <plat/prcm.h>
13 13
14#ifndef CONFIG_MACH_VOICEBLUE 14#ifndef CONFIG_MACH_VOICEBLUE
15#define voiceblue_reset() do {} while (0) 15#define voiceblue_reset() do {} while (0)
diff --git a/arch/arm/plat-omap/include/mach/tc.h b/arch/arm/plat-omap/include/plat/tc.h
index d2fcd789bb9a..d2fcd789bb9a 100644
--- a/arch/arm/plat-omap/include/mach/tc.h
+++ b/arch/arm/plat-omap/include/plat/tc.h
diff --git a/arch/arm/plat-omap/include/mach/timer-gp.h b/arch/arm/plat-omap/include/plat/timer-gp.h
index c88d346b59d9..c88d346b59d9 100644
--- a/arch/arm/plat-omap/include/mach/timer-gp.h
+++ b/arch/arm/plat-omap/include/plat/timer-gp.h
diff --git a/arch/arm/plat-omap/include/mach/timex.h b/arch/arm/plat-omap/include/plat/timex.h
index 6d35767bc48f..6d35767bc48f 100644
--- a/arch/arm/plat-omap/include/mach/timex.h
+++ b/arch/arm/plat-omap/include/plat/timex.h
diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 0814c5f210c3..13c305d62127 100644
--- a/arch/arm/plat-omap/include/mach/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -19,12 +19,13 @@
19 19
20#include <linux/types.h> 20#include <linux/types.h>
21#include <linux/serial_reg.h> 21#include <linux/serial_reg.h>
22#include <mach/serial.h> 22#include <plat/serial.h>
23 23
24unsigned int system_rev; 24unsigned int system_rev;
25 25
26#define UART_OMAP_MDR1 0x08 /* mode definition register */ 26#define UART_OMAP_MDR1 0x08 /* mode definition register */
27#define OMAP_ID_730 0x355F 27#define OMAP_ID_730 0x355F
28#define OMAP_ID_850 0x362C
28#define ID_MASK 0x7fff 29#define ID_MASK 0x7fff
29#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) 30#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
30#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK 31#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
@@ -43,8 +44,12 @@ static void putc(int c)
43 uart = (volatile u8 *)(OMAP_UART3_BASE); 44 uart = (volatile u8 *)(OMAP_UART3_BASE);
44#elif defined(CONFIG_OMAP_LL_DEBUG_UART2) 45#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
45 uart = (volatile u8 *)(OMAP_UART2_BASE); 46 uart = (volatile u8 *)(OMAP_UART2_BASE);
46#else 47#elif defined(CONFIG_OMAP_LL_DEBUG_UART1)
47 uart = (volatile u8 *)(OMAP_UART1_BASE); 48 uart = (volatile u8 *)(OMAP_UART1_BASE);
49#elif defined(CONFIG_OMAP_LL_DEBUG_NONE)
50 return;
51#else
52 return;
48#endif 53#endif
49 54
50#ifdef CONFIG_ARCH_OMAP1 55#ifdef CONFIG_ARCH_OMAP1
@@ -53,7 +58,7 @@ static void putc(int c)
53 /* MMU is not on, so cpu_is_omapXXXX() won't work here */ 58 /* MMU is not on, so cpu_is_omapXXXX() won't work here */
54 unsigned int omap_id = omap_get_id(); 59 unsigned int omap_id = omap_get_id();
55 60
56 if (omap_id == OMAP_ID_730) 61 if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
57 shift = 0; 62 shift = 0;
58 63
59 if (check_port(uart, shift)) 64 if (check_port(uart, shift))
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index f337e1761e2c..33a500eb2f93 100644
--- a/arch/arm/plat-omap/include/mach/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -3,7 +3,22 @@
3#ifndef __ASM_ARCH_OMAP_USB_H 3#ifndef __ASM_ARCH_OMAP_USB_H
4#define __ASM_ARCH_OMAP_USB_H 4#define __ASM_ARCH_OMAP_USB_H
5 5
6#include <mach/board.h> 6#include <plat/board.h>
7
8#define OMAP3_HS_USB_PORTS 3
9enum ehci_hcd_omap_mode {
10 EHCI_HCD_OMAP_MODE_UNKNOWN,
11 EHCI_HCD_OMAP_MODE_PHY,
12 EHCI_HCD_OMAP_MODE_TLL,
13};
14
15struct ehci_hcd_omap_platform_data {
16 enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
17 unsigned phy_reset:1;
18
19 /* have to be valid if phy_reset is true and portx is in phy mode */
20 int reset_gpio_port[OMAP3_HS_USB_PORTS];
21};
7 22
8/*-------------------------------------------------------------------------*/ 23/*-------------------------------------------------------------------------*/
9 24
@@ -29,6 +44,8 @@
29 44
30extern void usb_musb_init(void); 45extern void usb_musb_init(void);
31 46
47extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
48
32#endif 49#endif
33 50
34void omap_usb_init(struct omap_usb_config *pdata); 51void omap_usb_init(struct omap_usb_config *pdata);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-05 04:29:31 -0400