1 files changed, 50 insertions, 2 deletions

diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 1bee0ac88760..ac16f1e9d0e0 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -66,6 +66,16 @@
 #define OMAP_TIMER_NEEDS_RESET                          0x10000000
 #define OMAP_TIMER_HAS_DSP_IRQ                          0x08000000
 
+/*
+ * timer errata flags
+ *
+ * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
+ * errata prevents us from using posted mode on these devices, unless the
+ * timer counter register is never read. For more details please refer to
+ * the OMAP3/4/5 errata documents.
+ */
+#define OMAP_TIMER_ERRATA_I103_I767                     0x80000000
+
 struct omap_timer_capability_dev_attr {
         u32 timer_capability;
 };
@@ -97,6 +107,7 @@ struct timer_regs {
 struct dmtimer_platform_data {
         /* set_timer_src - Only used for OMAP1 devices */
         int (*set_timer_src)(struct platform_device *pdev, int source);
+        u32 timer_errata;
         u32 timer_capability;
         int (*get_context_loss_count)(struct device *);
 };
@@ -273,6 +284,7 @@ struct omap_dm_timer {
         int ctx_loss_count;
         int revision;
         u32 capability;
+        u32 errata;
         struct platform_device *pdev;
         struct list_head node;
 };
@@ -344,10 +356,46 @@ static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
                 l |= 1 << 2;
 
         __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
+}
+
+/*
+ * __omap_dm_timer_enable_posted - enables write posted mode
+ * @timer:      pointer to timer instance handle
+ *
+ * Enables the write posted mode for the timer. When posted mode is enabled
+ * writes to certain timer registers are immediately acknowledged by the
+ * internal bus and hence prevents stalling the CPU waiting for the write to
+ * complete. Enabling this feature can improve performance for writing to the
+ * timer registers.
+ */
+static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
+{
+        if (timer->posted)
+                return;
+
+        if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
+                return;
 
-        /* Match hardware reset default of posted mode */
         __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
-                                        OMAP_TIMER_CTRL_POSTED, 0);
+                              OMAP_TIMER_CTRL_POSTED, 0);
+        timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
+        timer->posted = OMAP_TIMER_POSTED;
+}
+
+/**
+ * __omap_dm_timer_override_errata - override errata flags for a timer
+ * @timer:      pointer to timer handle
+ * @errata:     errata flags to be ignored
+ *
+ * For a given timer, override a timer errata by clearing the flags
+ * specified by the errata argument. A specific erratum should only be
+ * overridden for a timer if the timer is used in such a way the erratum
+ * has no impact.
+ */
+static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
+                                                   u32 errata)
+{
+        timer->errata &= ~errata;
 }
 
 static inline int __omap_dm_timer_set_source(struct clk *timer_fck,