74 files changed, 1507 insertions, 1360 deletions
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
deleted file mode 100644
index ac24050e3416..000000000000
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/* arch/arm/plat-omap/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-#ifdef CONFIG_ARCH_OMAP1
-                moveq   \rx, #0xff000000        @ physical base address
-                movne   \rx, #0xfe000000        @ virtual base
-                orr     \rx, \rx, #0x00fb0000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                orr     \rx, \rx, #0x00009000   @ UART 3
-#endif
-#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
-                orr     \rx, \rx, #0x00000800   @ UART 2 & 3
-#endif
-#elif  CONFIG_ARCH_OMAP2
-                moveq   \rx, #0x48000000        @ physical base address
-                movne   \rx, #0xd8000000        @ virtual base
-                orr     \rx, \rx, #0x0006a000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART2
-                add     \rx, \rx, #0x00002000   @ UART 2
-#endif
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                add     \rx, \rx, #0x00004000   @ UART 3
-#endif
-#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-                moveq   \rx, #0x48000000        @ physical base address
-                movne   \rx, #0xd8000000        @ virtual base
-                orr     \rx, \rx, #0x0006a000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART2
-                add     \rx, \rx, #0x00002000   @ UART 2
-#endif
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                add     \rx, \rx, #0x00fb0000   @ UART 3
-                add     \rx, \rx, #0x00006000
-#endif
-#endif
-                .endm
-                .macro  senduart,rd,rx
-                strb    \rd, [\rx]
-                .endm
-                .macro  busyuart,rd,rx
-1001:           ldrb    \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
-                and     \rd, \rd, #0x60
-                teq     \rd, #0x60
-                beq     1002f
-                ldrb    \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
-                and     \rd, \rd, #0x60
-                teq     \rd, #0x60
-                bne     1001b
-1002:
-                .endm
-                .macro  waituart,rd,rx
-                .endm
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
deleted file mode 100644
index a5592991634d..000000000000
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for OMAP-based platforms
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-#include <asm/hardware/gic.h>
-#if defined(CONFIG_ARCH_OMAP1)
-#if defined(CONFIG_ARCH_OMAP730) && \
-        (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
-#error "FIXME: OMAP730 doesn't support multiple-OMAP"
-#elif defined(CONFIG_ARCH_OMAP730)
-#define INT_IH2_IRQ             INT_730_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP15XX)
-#define INT_IH2_IRQ             INT_1510_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#define INT_IH2_IRQ             INT_1610_IH2_IRQ
-#else
-#warning "IH2 IRQ defaulted"
-#define INT_IH2_IRQ             INT_1510_IH2_IRQ
-#endif
-                .macro  disable_fiq
-                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
-                ldr     \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
-                ldr     \tmp, [\base, #IRQ_MIR_REG_OFFSET]
-                mov     \irqstat, #0xffffffff
-                bic     \tmp, \irqstat, \tmp
-                tst     \irqnr, \tmp
-                beq     1510f
-                ldr     \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
-                cmp     \irqnr, #0
-                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-                cmpeq   \irqnr, #INT_IH2_IRQ
-                ldreq   \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
-                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-                addeqs  \irqnr, \irqnr, #32
-1510:
-                .endm
-#endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
-#include <mach/omap24xx.h>
-#include <mach/omap34xx.h>
-/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
-#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
-#define OMAP2_VA_IC_BASE                OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
-#elif defined(CONFIG_ARCH_OMAP34XX)
-#define OMAP2_VA_IC_BASE                OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-#include <mach/omap44xx.h>
-#endif
-#define INTCPS_SIR_IRQ_OFFSET   0x0040          /* Active interrupt offset */
-#define ACTIVEIRQ_MASK          0x7f            /* Active interrupt bits */
-                .macro  disable_fiq
-                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-#ifndef CONFIG_ARCH_OMAP4
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =OMAP2_VA_IC_BASE
-                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-                cmp     \irqnr, #0x0
-                bne     2222f
-                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-                cmp     \irqnr, #0x0
-                bne     2222f
-                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-                cmp     \irqnr, #0x0
-2222:
-                ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-                and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-                .endm
-#else
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an
-                 * interrupt if it's between 30 and 1020.  The test_for_ipi
-                 * routine below will pick up on IPIs.
-                 * A simple read from the controller will tell us the number
-                 * of the highest priority enabled interrupt.
-                 * We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =OMAP44XX_VA_GIC_CPU_BASE
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-                ldr     \tmp, =1021
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                .endm
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt
-                 * on the controller, since this requires the original irqstat
-                 * value which we won't easily be able to recreate later.
-                 */
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                it      cc
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                it      cs
-                cmpcs   \irqnr, \irqnr
-                .endm
-                /* As above, this assumes that irqstat and base are preserved */
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                itt     eq
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
-#endif
-                .macro  irq_prio_table
-                .endm
-#endif
diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/plat-omap/include/mach/mtd-xip.h
deleted file mode 100644
index f82a8dcaad94..000000000000
--- a/arch/arm/plat-omap/include/mach/mtd-xip.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * MTD primitives for XIP support. Architecture specific functions.
- *
- * Do not include this file directly. It's included from linux/mtd/xip.h
- *
- * Author: Vladimir Barinov <vbarinov@embeddedalley.com>
- *
- * (c) 2005 MontaVista Software, Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2.  This program is
- * licensed "as is" without any warranty of any kind, whether express or
- * implied.
- */
-#ifndef __ARCH_OMAP_MTD_XIP_H__
-#define __ARCH_OMAP_MTD_XIP_H__
-#include <mach/hardware.h>
-#define OMAP_MPU_TIMER_BASE     (0xfffec500)
-#define OMAP_MPU_TIMER_OFFSET   0x100
-typedef struct {
-        u32 cntl;                       /* CNTL_TIMER, R/W */
-        u32 load_tim;                   /* LOAD_TIM,   W */
-        u32 read_tim;                   /* READ_TIM,   R */
-} xip_omap_mpu_timer_regs_t;
-#define xip_omap_mpu_timer_base(n)                                      \
-((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +    \
-        (n)*OMAP_MPU_TIMER_OFFSET))
-static inline unsigned long xip_omap_mpu_timer_read(int nr)
-{
-        volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr);
-        return timer->read_tim;
-}
-#define xip_irqpending()        \
-        (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR))
-#define xip_currtime()          (~xip_omap_mpu_timer_read(0))
-/*
- * It's permitted to do approxmation for xip_elapsed_since macro
- * (see linux/mtd/xip.h)
- */
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7)
-#else
-#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
-#endif
-/*
- * xip_cpu_idle() is used when waiting for a delay equal or larger than
- * the system timer tick period.  This should put the CPU into idle mode
- * to save power and to be woken up only when some interrupts are pending.
- * As above, this should not rely upon standard kernel code.
- */
-#define xip_cpu_idle()  asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
-#endif /* __ARCH_OMAP_MTD_XIP_H__ */
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
deleted file mode 100644
index b226bdf45739..000000000000
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * File: arch/arm/plat-omap/include/mach/omapfb.h
- *
- * Framebuffer driver for TI OMAP boards
- *
- * Copyright (C) 2004 Nokia Corporation
- * Author: Imre Deak <imre.deak@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-#ifndef __OMAPFB_H
-#define __OMAPFB_H
-#include <asm/ioctl.h>
-#include <asm/types.h>
-/* IOCTL commands. */
-#define OMAP_IOW(num, dtype)    _IOW('O', num, dtype)
-#define OMAP_IOR(num, dtype)    _IOR('O', num, dtype)
-#define OMAP_IOWR(num, dtype)   _IOWR('O', num, dtype)
-#define OMAP_IO(num)            _IO('O', num)
-#define OMAPFB_MIRROR           OMAP_IOW(31, int)
-#define OMAPFB_SYNC_GFX         OMAP_IO(37)
-#define OMAPFB_VSYNC            OMAP_IO(38)
-#define OMAPFB_SET_UPDATE_MODE  OMAP_IOW(40, int)
-#define OMAPFB_GET_CAPS         OMAP_IOR(42, struct omapfb_caps)
-#define OMAPFB_GET_UPDATE_MODE  OMAP_IOW(43, int)
-#define OMAPFB_LCD_TEST         OMAP_IOW(45, int)
-#define OMAPFB_CTRL_TEST        OMAP_IOW(46, int)
-#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
-#define OMAPFB_SET_COLOR_KEY    OMAP_IOW(50, struct omapfb_color_key)
-#define OMAPFB_GET_COLOR_KEY    OMAP_IOW(51, struct omapfb_color_key)
-#define OMAPFB_SETUP_PLANE      OMAP_IOW(52, struct omapfb_plane_info)
-#define OMAPFB_QUERY_PLANE      OMAP_IOW(53, struct omapfb_plane_info)
-#define OMAPFB_UPDATE_WINDOW    OMAP_IOW(54, struct omapfb_update_window)
-#define OMAPFB_SETUP_MEM        OMAP_IOW(55, struct omapfb_mem_info)
-#define OMAPFB_QUERY_MEM        OMAP_IOW(56, struct omapfb_mem_info)
-#define OMAPFB_CAPS_GENERIC_MASK        0x00000fff
-#define OMAPFB_CAPS_LCDC_MASK           0x00fff000
-#define OMAPFB_CAPS_PANEL_MASK          0xff000000
-#define OMAPFB_CAPS_MANUAL_UPDATE       0x00001000
-#define OMAPFB_CAPS_TEARSYNC            0x00002000
-#define OMAPFB_CAPS_PLANE_RELOCATE_MEM  0x00004000
-#define OMAPFB_CAPS_PLANE_SCALE         0x00008000
-#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
-#define OMAPFB_CAPS_WINDOW_SCALE        0x00020000
-#define OMAPFB_CAPS_WINDOW_OVERLAY      0x00040000
-#define OMAPFB_CAPS_WINDOW_ROTATE       0x00080000
-#define OMAPFB_CAPS_SET_BACKLIGHT       0x01000000
-/* Values from DSP must map to lower 16-bits */
-#define OMAPFB_FORMAT_MASK              0x00ff
-#define OMAPFB_FORMAT_FLAG_DOUBLE       0x0100
-#define OMAPFB_FORMAT_FLAG_TEARSYNC     0x0200
-#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC  0x0400
-#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY       0x0800
-#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY      0x1000
-#define OMAPFB_EVENT_READY      1
-#define OMAPFB_EVENT_DISABLED   2
-#define OMAPFB_MEMTYPE_SDRAM            0
-#define OMAPFB_MEMTYPE_SRAM             1
-#define OMAPFB_MEMTYPE_MAX              1
-enum omapfb_color_format {
-        OMAPFB_COLOR_RGB565 = 0,
-        OMAPFB_COLOR_YUV422,
-        OMAPFB_COLOR_YUV420,
-        OMAPFB_COLOR_CLUT_8BPP,
-        OMAPFB_COLOR_CLUT_4BPP,
-        OMAPFB_COLOR_CLUT_2BPP,
-        OMAPFB_COLOR_CLUT_1BPP,
-        OMAPFB_COLOR_RGB444,
-        OMAPFB_COLOR_YUY422,
-};
-struct omapfb_update_window {
-        __u32 x, y;
-        __u32 width, height;
-        __u32 format;
-        __u32 out_x, out_y;
-        __u32 out_width, out_height;
-        __u32 reserved[8];
-};
-struct omapfb_update_window_old {
-        __u32 x, y;
-        __u32 width, height;
-        __u32 format;
-};
-enum omapfb_plane {
-        OMAPFB_PLANE_GFX = 0,
-        OMAPFB_PLANE_VID1,
-        OMAPFB_PLANE_VID2,
-};
-enum omapfb_channel_out {
-        OMAPFB_CHANNEL_OUT_LCD = 0,
-        OMAPFB_CHANNEL_OUT_DIGIT,
-};
-struct omapfb_plane_info {
-        __u32 pos_x;
-        __u32 pos_y;
-        __u8  enabled;
-        __u8  channel_out;
-        __u8  mirror;
-        __u8  reserved1;
-        __u32 out_width;
-        __u32 out_height;
-        __u32 reserved2[12];
-};
-struct omapfb_mem_info {
-        __u32 size;
-        __u8  type;
-        __u8  reserved[3];
-};
-struct omapfb_caps {
-        __u32 ctrl;
-        __u32 plane_color;
-        __u32 wnd_color;
-};
-enum omapfb_color_key_type {
-        OMAPFB_COLOR_KEY_DISABLED = 0,
-        OMAPFB_COLOR_KEY_GFX_DST,
-        OMAPFB_COLOR_KEY_VID_SRC,
-};
-struct omapfb_color_key {
-        __u8  channel_out;
-        __u32 background;
-        __u32 trans_key;
-        __u8  key_type;
-};
-enum omapfb_update_mode {
-        OMAPFB_UPDATE_DISABLED = 0,
-        OMAPFB_AUTO_UPDATE,
-        OMAPFB_MANUAL_UPDATE
-};
-#ifdef __KERNEL__
-#include <linux/completion.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/mutex.h>
-#include <mach/board.h>
-#define OMAP_LCDC_INV_VSYNC             0x0001
-#define OMAP_LCDC_INV_HSYNC             0x0002
-#define OMAP_LCDC_INV_PIX_CLOCK         0x0004
-#define OMAP_LCDC_INV_OUTPUT_EN         0x0008
-#define OMAP_LCDC_HSVS_RISING_EDGE      0x0010
-#define OMAP_LCDC_HSVS_OPPOSITE         0x0020
-#define OMAP_LCDC_SIGNAL_MASK           0x003f
-#define OMAP_LCDC_PANEL_TFT             0x0100
-#define OMAPFB_PLANE_XRES_MIN           8
-#define OMAPFB_PLANE_YRES_MIN           8
-#ifdef CONFIG_ARCH_OMAP1
-#define OMAPFB_PLANE_NUM                1
-#else
-#define OMAPFB_PLANE_NUM                3
-#endif
-struct omapfb_device;
-struct lcd_panel {
-        const char      *name;
-        int             config;         /* TFT/STN, signal inversion */
-        int             bpp;            /* Pixel format in fb mem */
-        int             data_lines;     /* Lines on LCD HW interface */
-        int             x_res, y_res;
-        int             pixel_clock;    /* In kHz */
-        int             hsw;            /* Horizontal synchronization
-                                           pulse width */
-        int             hfp;            /* Horizontal front porch */
-        int             hbp;            /* Horizontal back porch */
-        int             vsw;            /* Vertical synchronization
-                                           pulse width */
-        int             vfp;            /* Vertical front porch */
-        int             vbp;            /* Vertical back porch */
-        int             acb;            /* ac-bias pin frequency */
-        int             pcd;            /* pixel clock divider.
-                                           Obsolete use pixel_clock instead */
-        int             (*init)         (struct lcd_panel *panel,
-                                         struct omapfb_device *fbdev);
-        void            (*cleanup)      (struct lcd_panel *panel);
-        int             (*enable)       (struct lcd_panel *panel);
-        void            (*disable)      (struct lcd_panel *panel);
-        unsigned long   (*get_caps)     (struct lcd_panel *panel);
-        int             (*set_bklight_level)(struct lcd_panel *panel,
-                                             unsigned int level);
-        unsigned int    (*get_bklight_level)(struct lcd_panel *panel);
-        unsigned int    (*get_bklight_max)  (struct lcd_panel *panel);
-        int             (*run_test)     (struct lcd_panel *panel, int test_num);
-};
-struct extif_timings {
-        int cs_on_time;
-        int cs_off_time;
-        int we_on_time;
-        int we_off_time;
-        int re_on_time;
-        int re_off_time;
-        int we_cycle_time;
-        int re_cycle_time;
-        int cs_pulse_width;
-        int access_time;
-        int clk_div;
-        u32 tim[5];             /* set by extif->convert_timings */
-        int converted;
-};
-struct lcd_ctrl_extif {
-        int  (*init)            (struct omapfb_device *fbdev);
-        void (*cleanup)         (void);
-        void (*get_clk_info)    (u32 *clk_period, u32 *max_clk_div);
-        unsigned long (*get_max_tx_rate)(void);
-        int  (*convert_timings) (struct extif_timings *timings);
-        void (*set_timings)     (const struct extif_timings *timings);
-        void (*set_bits_per_cycle)(int bpc);
-        void (*write_command)   (const void *buf, unsigned int len);
-        void (*read_data)       (void *buf, unsigned int len);
-        void (*write_data)      (const void *buf, unsigned int len);
-        void (*transfer_area)   (int width, int height,
-                                 void (callback)(void * data), void *data);
-        int  (*setup_tearsync)  (unsigned pin_cnt,
-                                 unsigned hs_pulse_time, unsigned vs_pulse_time,
-                                 int hs_pol_inv, int vs_pol_inv, int div);
-        int  (*enable_tearsync) (int enable, unsigned line);
-        unsigned long           max_transmit_size;
-};
-struct omapfb_notifier_block {
-        struct notifier_block   nb;
-        void                    *data;
-        int                     plane_idx;
-};
-typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
-                                          unsigned long event,
-                                          void *fbi);
-struct omapfb_mem_region {
-        u32             paddr;
-        void __iomem    *vaddr;
-        unsigned long   size;
-        u8              type;           /* OMAPFB_PLANE_MEM_* */
-        unsigned        alloc:1;        /* allocated by the driver */
-        unsigned        map:1;          /* kernel mapped by the driver */
-};
-struct omapfb_mem_desc {
-        int                             region_cnt;
-        struct omapfb_mem_region        region[OMAPFB_PLANE_NUM];
-};
-struct lcd_ctrl {
-        const char      *name;
-        void            *data;
-        int             (*init)           (struct omapfb_device *fbdev,
-                                           int ext_mode,
-                                           struct omapfb_mem_desc *req_md);
-        void            (*cleanup)        (void);
-        void            (*bind_client)    (struct omapfb_notifier_block *nb);
-        void            (*get_caps)       (int plane, struct omapfb_caps *caps);
-        int             (*set_update_mode)(enum omapfb_update_mode mode);
-        enum omapfb_update_mode (*get_update_mode)(void);
-        int             (*setup_plane)    (int plane, int channel_out,
-                                           unsigned long offset,
-                                           int screen_width,
-                                           int pos_x, int pos_y, int width,
-                                           int height, int color_mode);
-        int             (*set_rotate)     (int angle);
-        int             (*setup_mem)      (int plane, size_t size,
-                                           int mem_type, unsigned long *paddr);
-        int             (*mmap)           (struct fb_info *info,
-                                           struct vm_area_struct *vma);
-        int             (*set_scale)      (int plane,
-                                           int orig_width, int orig_height,
-                                           int out_width, int out_height);
-        int             (*enable_plane)   (int plane, int enable);
-        int             (*update_window)  (struct fb_info *fbi,
-                                           struct omapfb_update_window *win,
-                                           void (*callback)(void *),
-                                           void *callback_data);
-        void            (*sync)           (void);
-        void            (*suspend)        (void);
-        void            (*resume)         (void);
-        int             (*run_test)       (int test_num);
-        int             (*setcolreg)      (u_int regno, u16 red, u16 green,
-                                           u16 blue, u16 transp,
-                                           int update_hw_mem);
-        int             (*set_color_key)  (struct omapfb_color_key *ck);
-        int             (*get_color_key)  (struct omapfb_color_key *ck);
-};
-enum omapfb_state {
-        OMAPFB_DISABLED = 0,
-        OMAPFB_SUSPENDED= 99,
-        OMAPFB_ACTIVE   = 100
-};
-struct omapfb_plane_struct {
-        int                             idx;
-        struct omapfb_plane_info        info;
-        enum omapfb_color_format        color_mode;
-        struct omapfb_device            *fbdev;
-};
-struct omapfb_device {
-        int                     state;
-        int                     ext_lcdc;               /* Using external
-                                                           LCD controller */
-        struct mutex            rqueue_mutex;
-        int                     palette_size;
-        u32                     pseudo_palette[17];
-        struct lcd_panel        *panel;                 /* LCD panel */
-        const struct lcd_ctrl   *ctrl;                  /* LCD controller */
-        const struct lcd_ctrl   *int_ctrl;              /* internal LCD ctrl */
-        struct lcd_ctrl_extif   *ext_if;                /* LCD ctrl external
-                                                           interface */
-        struct device           *dev;
-        struct fb_var_screeninfo        new_var;        /* for mode changes */
-        struct omapfb_mem_desc          mem_desc;
-        struct fb_info                  *fb_info[OMAPFB_PLANE_NUM];
-};
-struct omapfb_platform_data {
-        struct omap_lcd_config          lcd;
-        struct omapfb_mem_desc          mem_desc;
-        void                            *ctrl_platform_data;
-};
-#ifdef CONFIG_ARCH_OMAP1
-extern struct lcd_ctrl omap1_lcd_ctrl;
-#else
-extern struct lcd_ctrl omap2_disp_ctrl;
-#endif
-extern void omapfb_reserve_sdram(void);
-extern void omapfb_register_panel(struct lcd_panel *panel);
-extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
-extern void omapfb_notify_clients(struct omapfb_device *fbdev,
-                                  unsigned long event);
-extern int  omapfb_register_client(struct omapfb_notifier_block *nb,
-                                   omapfb_notifier_callback_t callback,
-                                   void *callback_data);
-extern int  omapfb_unregister_client(struct omapfb_notifier_block *nb);
-extern int  omapfb_update_window_async(struct fb_info *fbi,
-                                       struct omapfb_update_window *win,
-                                       void (*callback)(void *),
-                                       void *callback_data);
-/* in arch/arm/plat-omap/fb.c */
-extern void omapfb_set_ctrl_platform_data(void *pdata);
-#endif /* __KERNEL__ */
-#endif /* __OMAPFB_H */
diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h
deleted file mode 100644
index b97dfafeebda..000000000000
--- a/arch/arm/plat-omap/include/mach/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x18000000)
diff --git a/arch/arm/plat-omap/include/mach/blizzard.h b/arch/arm/plat-omap/include/plat/blizzard.h
index 8d160f171372..8d160f171372 100644
--- a/arch/arm/plat-omap/include/mach/blizzard.h
+++ b/arch/arm/plat-omap/include/plat/blizzard.h
diff --git a/arch/arm/plat-omap/include/mach/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
index 51b102dc906b..51b102dc906b 100644
--- a/arch/arm/plat-omap/include/mach/board-ams-delta.h
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
diff --git a/arch/arm/plat-omap/include/mach/board-sx1.h b/arch/arm/plat-omap/include/plat/board-sx1.h
index 355adbdaae33..355adbdaae33 100644
--- a/arch/arm/plat-omap/include/mach/board-sx1.h
+++ b/arch/arm/plat-omap/include/plat/board-sx1.h
diff --git a/arch/arm/plat-omap/include/mach/board-voiceblue.h b/arch/arm/plat-omap/include/plat/board-voiceblue.h
index 27916b210f57..27916b210f57 100644
--- a/arch/arm/plat-omap/include/mach/board-voiceblue.h
+++ b/arch/arm/plat-omap/include/plat/board-voiceblue.h
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/plat/board.h
index 8e913c322810..376ce18216ff 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -12,7 +12,19 @@
 #include <linux/types.h>
-#include <mach/gpio-switch.h>
+#include <plat/gpio-switch.h>
+/*
+ * OMAP35x EVM revision
+ * Run time detection of EVM revision is done by reading Ethernet
+ * PHY ID -
+ *      GEN_1   = 0x01150000
+ *      GEN_2   = 0x92200000
+ */
+enum {
+        OMAP3EVM_BOARD_GEN_1 = 0,       /* EVM Rev between  A - D */
+        OMAP3EVM_BOARD_GEN_2,           /* EVM Rev >= Rev E */
+};
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK          0x4f01
@@ -102,15 +114,6 @@ struct omap_pwm_led_platform_data {
        void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
 };
-/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */
-struct omap_gpio_switch_config {
-        char name[12];
-        u16 gpio;
-        int flags:4;
-        int type:4;
-        int key_code:24; /* Linux key code */
-};
 struct omap_uart_config {
        /* Bit field of UARTs present; bit 0 --> UART1 */
        unsigned int enabled_uarts;
@@ -157,4 +160,10 @@ extern int omap_board_config_size;
 /* for TI reference platforms sharing the same debug card */
 extern int debug_card_init(u32 addr, unsigned gpio);
+/* OMAP3EVM revision */
+#if defined(CONFIG_MACH_OMAP3EVM)
+u8 get_omap3_evm_rev(void);
+#else
+#define get_omap3_evm_rev() (-EINVAL)
+#endif
 #endif
diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/plat/clkdev.h
index 730c49d1ebd8..730c49d1ebd8 100644
--- a/arch/arm/plat-omap/include/mach/clkdev.h
+++ b/arch/arm/plat-omap/include/plat/clkdev.h
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
new file mode 100644
index 000000000000..35b36caf5f91
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -0,0 +1,41 @@
+/*
+ * clkdev <-> OMAP integration
+ *
+ * Russell King <linux@arm.linux.org.uk>
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
+#include <asm/clkdev.h>
+struct omap_clk {
+        u16                             cpu;
+        struct clk_lookup               lk;
+};
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+#define CK_310          (1 << 0)
+#define CK_7XX          (1 << 1)
+#define CK_1510         (1 << 2)
+#define CK_16XX         (1 << 3)
+#define CK_243X         (1 << 4)
+#define CK_242X         (1 << 5)
+#define CK_343X         (1 << 6)
+#define CK_3430ES1      (1 << 7)
+#define CK_3430ES2      (1 << 8)
+#define CK_443X         (1 << 9)
+#endif
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 4b8b0d65cbf2..309b6d1dccdb 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -13,6 +13,8 @@
 #ifndef __ARCH_ARM_OMAP_CLOCK_H
 #define __ARCH_ARM_OMAP_CLOCK_H
+#include <linux/list.h>
 struct module;
 struct clk;
 struct clockdomain;
@@ -148,6 +150,8 @@ extern const struct clkops clkops_null;
 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
 #define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
 #define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
+#define CLOCK_IN_OMAP4430       (1 << 13)
+#define ALWAYS_ENABLED          (1 << 14)
 /* bits 13-31 are currently free */
 /* Clksel_rate flags */
@@ -156,6 +160,7 @@ extern const struct clkops clkops_null;
 #define RATE_IN_243X            (1 << 2)
 #define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
 #define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
+#define RATE_IN_4430            (1 << 5)
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h
index 99ebd886f134..eb734826e64e 100644
--- a/arch/arm/plat-omap/include/mach/clockdomain.h
+++ b/arch/arm/plat-omap/include/plat/clockdomain.h
@@ -16,9 +16,9 @@
 #ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
 #define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
-#include <mach/powerdomain.h>
+#include <plat/powerdomain.h>
-#include <mach/clock.h>
+#include <plat/clock.h>
-#include <mach/cpu.h>
+#include <plat/cpu.h>
 /* Clockdomain capability flags */
 #define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/plat/common.h
index fdeab421b4dc..32c22272425d 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -27,24 +27,15 @@
 #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
 #define __ARCH_ARM_MACH_OMAP_COMMON_H
-#include <linux/i2c.h>
+#include <plat/i2c.h>
 struct sys_timer;
+/* used by omap-smp.c and board-4430sdp.c */
+extern void __iomem *gic_cpu_base_addr;
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
-#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
-extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len);
-#else
-static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len)
-{
-        return 0;
-}
-#endif
 /* IO bases for various OMAP processors */
 struct omap_globals {
@@ -55,6 +46,7 @@ struct omap_globals {
        void __iomem    *ctrl;          /* System Control Module */
        void __iomem    *prm;           /* Power and Reset Management */
        void __iomem    *cm;            /* Clock Management */
+        void __iomem    *cm2;
 };
 void omap2_set_globals_242x(void);
@@ -68,4 +60,24 @@ void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
+/**
+ * omap_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_test_timeout(cond, timeout, index)                 \
+({                                                              \
+        for (index = 0; index < timeout; index++) {             \
+                if (cond)                                       \
+                        break;                                  \
+                udelay(1);                                      \
+        }                                                       \
+})
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/plat/control.h
index 826d317cdbec..2ae884378638 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -20,15 +20,18 @@
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
-        OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
 #define OMAP243X_CTRL_REGADDR(reg)                                      \
-        OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                      \
-        OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
 #else
-#define OMAP242X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP242X_CTRL_REGADDR(reg)                                      \
-#define OMAP243X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP343X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
 #endif /* __ASSEMBLY__ */
 /*
@@ -109,6 +112,8 @@
 #define OMAP24XX_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e0)
 #define OMAP24XX_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00e4)
+#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
 /* 34xx-only CONTROL_GENERAL register offsets */
 #define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
 #define OMAP343X_CONTROL_MEM_DFTRW0     (OMAP2_CONTROL_GENERAL + 0x0008)
@@ -141,8 +146,51 @@
 #define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
 #define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
-#define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02b0)
+#define OMAP343X_CONTROL_DEBOBS(i)      (OMAP2_CONTROL_GENERAL + 0x01B0 \
-#define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02b4)
+                                        + ((i) >> 1) * 4 + (!(i) & 1) * 2)
+#define OMAP343X_CONTROL_PROG_IO0       (OMAP2_CONTROL_GENERAL + 0x01D4)
+#define OMAP343X_CONTROL_PROG_IO1       (OMAP2_CONTROL_GENERAL + 0x01D8)
+#define OMAP343X_CONTROL_DSS_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E0)
+#define OMAP343X_CONTROL_CORE_DPLL_SPREADING    (OMAP2_CONTROL_GENERAL + 0x01E4)
+#define OMAP343X_CONTROL_PER_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E8)
+#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
+#define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02B0)
+#define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02B4)
+#define OMAP343X_CONTROL_SRAMLDO4       (OMAP2_CONTROL_GENERAL + 0x02B8)
+#define OMAP343X_CONTROL_SRAMLDO5       (OMAP2_CONTROL_GENERAL + 0x02C0)
+#define OMAP343X_CONTROL_CSI            (OMAP2_CONTROL_GENERAL + 0x02C4)
+/* 34xx PADCONF register offsets */
+#define OMAP343X_PADCONF_ETK(i)         (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
+                                                (i)*2)
+#define OMAP343X_PADCONF_ETK_CLK        OMAP343X_PADCONF_ETK(0)
+#define OMAP343X_PADCONF_ETK_CTL        OMAP343X_PADCONF_ETK(1)
+#define OMAP343X_PADCONF_ETK_D0         OMAP343X_PADCONF_ETK(2)
+#define OMAP343X_PADCONF_ETK_D1         OMAP343X_PADCONF_ETK(3)
+#define OMAP343X_PADCONF_ETK_D2         OMAP343X_PADCONF_ETK(4)
+#define OMAP343X_PADCONF_ETK_D3         OMAP343X_PADCONF_ETK(5)
+#define OMAP343X_PADCONF_ETK_D4         OMAP343X_PADCONF_ETK(6)
+#define OMAP343X_PADCONF_ETK_D5         OMAP343X_PADCONF_ETK(7)
+#define OMAP343X_PADCONF_ETK_D6         OMAP343X_PADCONF_ETK(8)
+#define OMAP343X_PADCONF_ETK_D7         OMAP343X_PADCONF_ETK(9)
+#define OMAP343X_PADCONF_ETK_D8         OMAP343X_PADCONF_ETK(10)
+#define OMAP343X_PADCONF_ETK_D9         OMAP343X_PADCONF_ETK(11)
+#define OMAP343X_PADCONF_ETK_D10        OMAP343X_PADCONF_ETK(12)
+#define OMAP343X_PADCONF_ETK_D11        OMAP343X_PADCONF_ETK(13)
+#define OMAP343X_PADCONF_ETK_D12        OMAP343X_PADCONF_ETK(14)
+#define OMAP343X_PADCONF_ETK_D13        OMAP343X_PADCONF_ETK(15)
+#define OMAP343X_PADCONF_ETK_D14        OMAP343X_PADCONF_ETK(16)
+#define OMAP343X_PADCONF_ETK_D15        OMAP343X_PADCONF_ETK(17)
+/* 34xx GENERAL_WKUP regist offsets */
+#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
+                                                0x008 + (i))
+#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
+#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
+#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
+#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
+#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
 /* 34xx D2D idle-related pins, handled by PM core */
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
@@ -193,6 +241,9 @@
 #define OMAP2_PBIASLITEPWRDNZ0          (1 << 1)
 #define OMAP2_PBIASLITEVMODE0           (1 << 0)
+/* CONTROL_PROG_IO1 bits */
+#define OMAP3630_PRG_SDMMC1_SPEEDCTRL   (1 << 20)
 /* CONTROL_IVA2_BOOTMOD bits */
 #define OMAP3_IVA2_BOOTMOD_SHIFT        0
 #define OMAP3_IVA2_BOOTMOD_MASK         (0xf << 0)
@@ -202,6 +253,44 @@
 #define OMAP3_PADCONF_WAKEUPEVENT0      (1 << 15)
 #define OMAP3_PADCONF_WAKEUPENABLE0     (1 << 14)
+#define OMAP343X_SCRATCHPAD_ROM         (OMAP343X_CTRL_BASE + 0x860)
+#define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
+#define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
+/*
+ * CONTROL OMAP STATUS register to identify OMAP3 features
+ */
+#define OMAP3_CONTROL_OMAP_STATUS       0x044c
+#define OMAP3_SGX_SHIFT                 13
+#define OMAP3_SGX_MASK                  (3 << OMAP3_SGX_SHIFT)
+#define         FEAT_SGX_FULL           0
+#define         FEAT_SGX_HALF           1
+#define         FEAT_SGX_NONE           2
+#define OMAP3_IVA_SHIFT                 12
+#define OMAP3_IVA_MASK                  (1 << OMAP3_SGX_SHIFT)
+#define         FEAT_IVA                0
+#define         FEAT_IVA_NONE           1
+#define OMAP3_L2CACHE_SHIFT             10
+#define OMAP3_L2CACHE_MASK              (3 << OMAP3_L2CACHE_SHIFT)
+#define         FEAT_L2CACHE_NONE       0
+#define         FEAT_L2CACHE_64KB       1
+#define         FEAT_L2CACHE_128KB      2
+#define         FEAT_L2CACHE_256KB      3
+#define OMAP3_ISP_SHIFT                 5
+#define OMAP3_ISP_MASK                  (1<< OMAP3_ISP_SHIFT)
+#define         FEAT_ISP                0
+#define         FEAT_ISP_NONE           1
+#define OMAP3_NEON_SHIFT                4
+#define OMAP3_NEON_MASK                 (1<< OMAP3_NEON_SHIFT)
+#define         FEAT_NEON               0
+#define         FEAT_NEON_NONE          1
 #ifndef __ASSEMBLY__
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
                defined(CONFIG_ARCH_OMAP4)
@@ -212,6 +301,15 @@ extern u32 omap_ctrl_readl(u16 offset);
 extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
+extern void omap3_save_scratchpad_contents(void);
+extern void omap3_clear_scratchpad_contents(void);
+extern u32 *get_restore_pointer(void);
+extern u32 *get_es3_restore_pointer(void);
+extern u32 omap3_arm_context[128];
+extern void omap3_control_save_context(void);
+extern void omap3_control_restore_context(void);
 #else
 #define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index f129efb3075e..9a028bdebb06 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -30,6 +30,8 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
+#include <linux/bitops.h>
 /*
 * Omap device type i.e. EMU/HS/TST/GP/BAD
 */
@@ -57,6 +59,23 @@ struct omap_chip_id {
 unsigned int omap_rev(void);
 /*
+ * Define CPU revision bits
+ *
+ * Verbose meaning of the revision bits may be different for a silicon
+ * family. This difference can be handled separately.
+ */
+#define OMAP_REVBITS_00         0x00
+#define OMAP_REVBITS_10         0x10
+#define OMAP_REVBITS_20         0x20
+#define OMAP_REVBITS_30         0x30
+#define OMAP_REVBITS_40         0x40
+/*
+ * Get the CPU revision for OMAP devices
+ */
+#define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
+/*
 * Test if multicore OMAP support is needed
 */
 #undef MULTI_OMAP1
@@ -157,10 +176,13 @@ IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
+IS_OMAP_CLASS(44xx, 0x44)
 IS_OMAP_SUBCLASS(242x, 0x242)
 IS_OMAP_SUBCLASS(243x, 0x243)
 IS_OMAP_SUBCLASS(343x, 0x343)
+IS_OMAP_SUBCLASS(363x, 0x363)
+IS_OMAP_SUBCLASS(443x, 0x443)
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
@@ -264,6 +286,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 * cpu_is_omap2423():   True for OMAP2423
 * cpu_is_omap2430():   True for OMAP2430
 * cpu_is_omap3430():   True for OMAP3430
+ * cpu_is_omap3505():   True for OMAP3505
+ * cpu_is_omap3517():   True for OMAP3517
 */
 #define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
@@ -287,6 +311,8 @@ IS_OMAP_TYPE(2422, 0x2422)
 IS_OMAP_TYPE(2423, 0x2423)
 IS_OMAP_TYPE(2430, 0x2430)
 IS_OMAP_TYPE(3430, 0x3430)
+IS_OMAP_TYPE(3505, 0x3505)
+IS_OMAP_TYPE(3517, 0x3517)
 #define cpu_is_omap310()                0
 #define cpu_is_omap730()                0
@@ -301,7 +327,14 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_is_omap2422()               0
 #define cpu_is_omap2423()               0
 #define cpu_is_omap2430()               0
+#define cpu_is_omap3503()               0
+#define cpu_is_omap3515()               0
+#define cpu_is_omap3525()               0
+#define cpu_is_omap3530()               0
+#define cpu_is_omap3505()               0
+#define cpu_is_omap3517()               0
 #define cpu_is_omap3430()               0
+#define cpu_is_omap3630()               0
 /*
 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
@@ -351,14 +384,34 @@ IS_OMAP_TYPE(3430, 0x3430)
 #if defined(CONFIG_ARCH_OMAP34XX)
 # undef cpu_is_omap3430
+# undef cpu_is_omap3503
+# undef cpu_is_omap3515
+# undef cpu_is_omap3525
+# undef cpu_is_omap3530
+# undef cpu_is_omap3505
+# undef cpu_is_omap3517
 # define cpu_is_omap3430()              is_omap3430()
+# define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
+                                                (!omap3_has_iva()) &&   \
+                                                (!omap3_has_sgx()))
+# define cpu_is_omap3515()              (cpu_is_omap3430() &&           \
+                                                (!omap3_has_iva()) &&   \
+                                                (omap3_has_sgx()))
+# define cpu_is_omap3525()              (cpu_is_omap3430() &&           \
+                                                (!omap3_has_sgx()) &&   \
+                                                (omap3_has_iva()))
+# define cpu_is_omap3530()              (cpu_is_omap3430())
+# define cpu_is_omap3505()              is_omap3505()
+# define cpu_is_omap3517()              is_omap3517()
+# undef cpu_is_omap3630
+# define cpu_is_omap3630()              is_omap363x()
 #endif
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
-# define cpu_is_omap44xx()              1
+# define cpu_is_omap44xx()              is_omap44xx()
-# define cpu_is_omap443x()              1
+# define cpu_is_omap443x()              is_omap443x()
 # endif
 /* Macros to detect if we have OMAP1 or OMAP2 */
@@ -382,7 +435,18 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP3430_REV_ES3_0      0x34303034
 #define OMAP3430_REV_ES3_1      0x34304034
-#define OMAP443X_CLASS          0x44300034
+#define OMAP3630_REV_ES1_0      0x36300034
+#define OMAP35XX_CLASS          0x35000034
+#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
+#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
+#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
+#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
+#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
+#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
+#define OMAP443X_CLASS          0x44300044
+#define OMAP4430_REV_ES1_0      0x44300044
 /*
 * omap_chip bits
@@ -405,6 +469,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define CHIP_IS_OMAP3430ES2             (1 << 4)
 #define CHIP_IS_OMAP3430ES3_0           (1 << 5)
 #define CHIP_IS_OMAP3430ES3_1           (1 << 6)
+#define CHIP_IS_OMAP3630ES1             (1 << 7)
 #define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
@@ -416,11 +481,36 @@ IS_OMAP_TYPE(3430, 0x3430)
 */
 #define CHIP_GE_OMAP3430ES2             (CHIP_IS_OMAP3430ES2 | \
                                         CHIP_IS_OMAP3430ES3_0 | \
-                                         CHIP_IS_OMAP3430ES3_1)
+                                         CHIP_IS_OMAP3430ES3_1 | \
-#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1)
+                                         CHIP_IS_OMAP3630ES1)
+#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1 | \
+                                         CHIP_IS_OMAP3630ES1)
 int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
+/*
+ * Runtime detection of OMAP3 features
+ */
+extern u32 omap3_features;
+#define OMAP3_HAS_L2CACHE               BIT(0)
+#define OMAP3_HAS_IVA                   BIT(1)
+#define OMAP3_HAS_SGX                   BIT(2)
+#define OMAP3_HAS_NEON                  BIT(3)
+#define OMAP3_HAS_ISP                   BIT(4)
+#define OMAP3_HAS_FEATURE(feat,flag)                    \
+static inline unsigned int omap3_has_ ##feat(void)      \
+{                                                       \
+        return (omap3_features & OMAP3_HAS_ ##flag);    \
+}                                                       \
+OMAP3_HAS_FEATURE(l2cache, L2CACHE)
+OMAP3_HAS_FEATURE(sgx, SGX)
+OMAP3_HAS_FEATURE(iva, IVA)
+OMAP3_HAS_FEATURE(neon, NEON)
+OMAP3_HAS_FEATURE(isp, ISP)
 #endif
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
new file mode 100644
index 000000000000..c66e464732df
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -0,0 +1,575 @@
+/*
+ * linux/include/asm-arm/arch-omap/display.h
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_ARCH_OMAP_DISPLAY_H
+#define __ASM_ARCH_OMAP_DISPLAY_H
+#include <linux/list.h>
+#include <linux/kobject.h>
+#include <linux/device.h>
+#include <asm/atomic.h>
+#define DISPC_IRQ_FRAMEDONE             (1 << 0)
+#define DISPC_IRQ_VSYNC                 (1 << 1)
+#define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
+#define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
+#define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
+#define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
+#define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
+#define DISPC_IRQ_GFX_END_WIN           (1 << 7)
+#define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
+#define DISPC_IRQ_OCP_ERR               (1 << 9)
+#define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
+#define DISPC_IRQ_VID1_END_WIN          (1 << 11)
+#define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
+#define DISPC_IRQ_VID2_END_WIN          (1 << 13)
+#define DISPC_IRQ_SYNC_LOST             (1 << 14)
+#define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
+#define DISPC_IRQ_WAKEUP                (1 << 16)
+struct omap_dss_device;
+struct omap_overlay_manager;
+enum omap_display_type {
+        OMAP_DISPLAY_TYPE_NONE          = 0,
+        OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
+        OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
+        OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
+        OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
+        OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
+};
+enum omap_plane {
+        OMAP_DSS_GFX    = 0,
+        OMAP_DSS_VIDEO1 = 1,
+        OMAP_DSS_VIDEO2 = 2
+};
+enum omap_channel {
+        OMAP_DSS_CHANNEL_LCD    = 0,
+        OMAP_DSS_CHANNEL_DIGIT  = 1,
+};
+enum omap_color_mode {
+        OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
+        OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
+        OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
+        OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
+        OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
+        OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
+        OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
+        OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
+        OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
+        OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
+        OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
+        OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
+        OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
+        OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
+        OMAP_DSS_COLOR_GFX_OMAP2 =
+                OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
+                OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
+                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
+                OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
+        OMAP_DSS_COLOR_VID_OMAP2 =
+                OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
+                OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
+                OMAP_DSS_COLOR_UYVY,
+        OMAP_DSS_COLOR_GFX_OMAP3 =
+                OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
+                OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
+                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
+                OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
+                OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
+                OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
+        OMAP_DSS_COLOR_VID1_OMAP3 =
+                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
+                OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
+                OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
+        OMAP_DSS_COLOR_VID2_OMAP3 =
+                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
+                OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
+                OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
+                OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
+                OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
+};
+enum omap_lcd_display_type {
+        OMAP_DSS_LCD_DISPLAY_STN,
+        OMAP_DSS_LCD_DISPLAY_TFT,
+};
+enum omap_dss_load_mode {
+        OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
+        OMAP_DSS_LOAD_CLUT_ONLY         = 1,
+        OMAP_DSS_LOAD_FRAME_ONLY        = 2,
+        OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
+};
+enum omap_dss_trans_key_type {
+        OMAP_DSS_COLOR_KEY_GFX_DST = 0,
+        OMAP_DSS_COLOR_KEY_VID_SRC = 1,
+};
+enum omap_rfbi_te_mode {
+        OMAP_DSS_RFBI_TE_MODE_1 = 1,
+        OMAP_DSS_RFBI_TE_MODE_2 = 2,
+};
+enum omap_panel_config {
+        OMAP_DSS_LCD_IVS                = 1<<0,
+        OMAP_DSS_LCD_IHS                = 1<<1,
+        OMAP_DSS_LCD_IPC                = 1<<2,
+        OMAP_DSS_LCD_IEO                = 1<<3,
+        OMAP_DSS_LCD_RF                 = 1<<4,
+        OMAP_DSS_LCD_ONOFF              = 1<<5,
+        OMAP_DSS_LCD_TFT                = 1<<20,
+};
+enum omap_dss_venc_type {
+        OMAP_DSS_VENC_TYPE_COMPOSITE,
+        OMAP_DSS_VENC_TYPE_SVIDEO,
+};
+enum omap_display_caps {
+        OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
+        OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
+};
+enum omap_dss_update_mode {
+        OMAP_DSS_UPDATE_DISABLED = 0,
+        OMAP_DSS_UPDATE_AUTO,
+        OMAP_DSS_UPDATE_MANUAL,
+};
+enum omap_dss_display_state {
+        OMAP_DSS_DISPLAY_DISABLED = 0,
+        OMAP_DSS_DISPLAY_ACTIVE,
+        OMAP_DSS_DISPLAY_SUSPENDED,
+};
+/* XXX perhaps this should be removed */
+enum omap_dss_overlay_managers {
+        OMAP_DSS_OVL_MGR_LCD,
+        OMAP_DSS_OVL_MGR_TV,
+};
+enum omap_dss_rotation_type {
+        OMAP_DSS_ROT_DMA = 0,
+        OMAP_DSS_ROT_VRFB = 1,
+};
+/* clockwise rotation angle */
+enum omap_dss_rotation_angle {
+        OMAP_DSS_ROT_0   = 0,
+        OMAP_DSS_ROT_90  = 1,
+        OMAP_DSS_ROT_180 = 2,
+        OMAP_DSS_ROT_270 = 3,
+};
+enum omap_overlay_caps {
+        OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
+        OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
+};
+enum omap_overlay_manager_caps {
+        OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
+};
+/* RFBI */
+struct rfbi_timings {
+        int cs_on_time;
+        int cs_off_time;
+        int we_on_time;
+        int we_off_time;
+        int re_on_time;
+        int re_off_time;
+        int we_cycle_time;
+        int re_cycle_time;
+        int cs_pulse_width;
+        int access_time;
+        int clk_div;
+        u32 tim[5];             /* set by rfbi_convert_timings() */
+        int converted;
+};
+void omap_rfbi_write_command(const void *buf, u32 len);
+void omap_rfbi_read_data(void *buf, u32 len);
+void omap_rfbi_write_data(const void *buf, u32 len);
+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
+                u16 x, u16 y,
+                u16 w, u16 h);
+int omap_rfbi_enable_te(bool enable, unsigned line);
+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
+                             unsigned hs_pulse_time, unsigned vs_pulse_time,
+                             int hs_pol_inv, int vs_pol_inv, int extif_div);
+/* DSI */
+void dsi_bus_lock(void);
+void dsi_bus_unlock(void);
+int dsi_vc_dcs_write(int channel, u8 *data, int len);
+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
+int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
+int dsi_vc_send_null(int channel);
+int dsi_vc_send_bta_sync(int channel);
+/* Board specific data */
+struct omap_dss_board_info {
+        int (*get_last_off_on_transaction_id)(struct device *dev);
+        int num_devices;
+        struct omap_dss_device **devices;
+        struct omap_dss_device *default_device;
+};
+struct omap_video_timings {
+        /* Unit: pixels */
+        u16 x_res;
+        /* Unit: pixels */
+        u16 y_res;
+        /* Unit: KHz */
+        u32 pixel_clock;
+        /* Unit: pixel clocks */
+        u16 hsw;        /* Horizontal synchronization pulse width */
+        /* Unit: pixel clocks */
+        u16 hfp;        /* Horizontal front porch */
+        /* Unit: pixel clocks */
+        u16 hbp;        /* Horizontal back porch */
+        /* Unit: line clocks */
+        u16 vsw;        /* Vertical synchronization pulse width */
+        /* Unit: line clocks */
+        u16 vfp;        /* Vertical front porch */
+        /* Unit: line clocks */
+        u16 vbp;        /* Vertical back porch */
+};
+#ifdef CONFIG_OMAP2_DSS_VENC
+/* Hardcoded timings for tv modes. Venc only uses these to
+ * identify the mode, and does not actually use the configs
+ * itself. However, the configs should be something that
+ * a normal monitor can also show */
+const extern struct omap_video_timings omap_dss_pal_timings;
+const extern struct omap_video_timings omap_dss_ntsc_timings;
+#endif
+struct omap_overlay_info {
+        bool enabled;
+        u32 paddr;
+        void __iomem *vaddr;
+        u16 screen_width;
+        u16 width;
+        u16 height;
+        enum omap_color_mode color_mode;
+        u8 rotation;
+        enum omap_dss_rotation_type rotation_type;
+        bool mirror;
+        u16 pos_x;
+        u16 pos_y;
+        u16 out_width;  /* if 0, out_width == width */
+        u16 out_height; /* if 0, out_height == height */
+        u8 global_alpha;
+};
+struct omap_overlay {
+        struct kobject kobj;
+        struct list_head list;
+        /* static fields */
+        const char *name;
+        int id;
+        enum omap_color_mode supported_modes;
+        enum omap_overlay_caps caps;
+        /* dynamic fields */
+        struct omap_overlay_manager *manager;
+        struct omap_overlay_info info;
+        /* if true, info has been changed, but not applied() yet */
+        bool info_dirty;
+        int (*set_manager)(struct omap_overlay *ovl,
+                struct omap_overlay_manager *mgr);
+        int (*unset_manager)(struct omap_overlay *ovl);
+        int (*set_overlay_info)(struct omap_overlay *ovl,
+                        struct omap_overlay_info *info);
+        void (*get_overlay_info)(struct omap_overlay *ovl,
+                        struct omap_overlay_info *info);
+        int (*wait_for_go)(struct omap_overlay *ovl);
+};
+struct omap_overlay_manager_info {
+        u32 default_color;
+        enum omap_dss_trans_key_type trans_key_type;
+        u32 trans_key;
+        bool trans_enabled;
+        bool alpha_enabled;
+};
+struct omap_overlay_manager {
+        struct kobject kobj;
+        struct list_head list;
+        /* static fields */
+        const char *name;
+        int id;
+        enum omap_overlay_manager_caps caps;
+        int num_overlays;
+        struct omap_overlay **overlays;
+        enum omap_display_type supported_displays;
+        /* dynamic fields */
+        struct omap_dss_device *device;
+        struct omap_overlay_manager_info info;
+        bool device_changed;
+        /* if true, info has been changed but not applied() yet */
+        bool info_dirty;
+        int (*set_device)(struct omap_overlay_manager *mgr,
+                struct omap_dss_device *dssdev);
+        int (*unset_device)(struct omap_overlay_manager *mgr);
+        int (*set_manager_info)(struct omap_overlay_manager *mgr,
+                        struct omap_overlay_manager_info *info);
+        void (*get_manager_info)(struct omap_overlay_manager *mgr,
+                        struct omap_overlay_manager_info *info);
+        int (*apply)(struct omap_overlay_manager *mgr);
+        int (*wait_for_go)(struct omap_overlay_manager *mgr);
+};
+struct omap_dss_device {
+        struct device dev;
+        enum omap_display_type type;
+        union {
+                struct {
+                        u8 data_lines;
+                } dpi;
+                struct {
+                        u8 channel;
+                        u8 data_lines;
+                } rfbi;
+                struct {
+                        u8 datapairs;
+                } sdi;
+                struct {
+                        u8 clk_lane;
+                        u8 clk_pol;
+                        u8 data1_lane;
+                        u8 data1_pol;
+                        u8 data2_lane;
+                        u8 data2_pol;
+                        struct {
+                                u16 regn;
+                                u16 regm;
+                                u16 regm3;
+                                u16 regm4;
+                                u16 lp_clk_div;
+                                u16 lck_div;
+                                u16 pck_div;
+                        } div;
+                        bool ext_te;
+                        u8 ext_te_gpio;
+                } dsi;
+                struct {
+                        enum omap_dss_venc_type type;
+                        bool invert_polarity;
+                } venc;
+        } phy;
+        struct {
+                struct omap_video_timings timings;
+                int acbi;       /* ac-bias pin transitions per interrupt */
+                /* Unit: line clocks */
+                int acb;        /* ac-bias pin frequency */
+                enum omap_panel_config config;
+                u8 recommended_bpp;
+                struct omap_dss_device *ctrl;
+        } panel;
+        struct {
+                u8 pixel_size;
+                struct rfbi_timings rfbi_timings;
+                struct omap_dss_device *panel;
+        } ctrl;
+        int reset_gpio;
+        int max_backlight_level;
+        const char *name;
+        /* used to match device to driver */
+        const char *driver_name;
+        void *data;
+        struct omap_dss_driver *driver;
+        /* helper variable for driver suspend/resume */
+        bool activate_after_resume;
+        enum omap_display_caps caps;
+        struct omap_overlay_manager *manager;
+        enum omap_dss_display_state state;
+        int (*enable)(struct omap_dss_device *dssdev);
+        void (*disable)(struct omap_dss_device *dssdev);
+        int (*suspend)(struct omap_dss_device *dssdev);
+        int (*resume)(struct omap_dss_device *dssdev);
+        void (*get_resolution)(struct omap_dss_device *dssdev,
+                        u16 *xres, u16 *yres);
+        int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
+        int (*check_timings)(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings);
+        void (*set_timings)(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings);
+        void (*get_timings)(struct omap_dss_device *dssdev,
+                        struct omap_video_timings *timings);
+        int (*update)(struct omap_dss_device *dssdev,
+                               u16 x, u16 y, u16 w, u16 h);
+        int (*sync)(struct omap_dss_device *dssdev);
+        int (*wait_vsync)(struct omap_dss_device *dssdev);
+        int (*set_update_mode)(struct omap_dss_device *dssdev,
+                        enum omap_dss_update_mode);
+        enum omap_dss_update_mode (*get_update_mode)
+                (struct omap_dss_device *dssdev);
+        int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
+        int (*get_te)(struct omap_dss_device *dssdev);
+        u8 (*get_rotate)(struct omap_dss_device *dssdev);
+        int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
+        bool (*get_mirror)(struct omap_dss_device *dssdev);
+        int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
+        int (*run_test)(struct omap_dss_device *dssdev, int test);
+        int (*memory_read)(struct omap_dss_device *dssdev,
+                        void *buf, size_t size,
+                        u16 x, u16 y, u16 w, u16 h);
+        int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
+        u32 (*get_wss)(struct omap_dss_device *dssdev);
+        /* platform specific  */
+        int (*platform_enable)(struct omap_dss_device *dssdev);
+        void (*platform_disable)(struct omap_dss_device *dssdev);
+        int (*set_backlight)(struct omap_dss_device *dssdev, int level);
+        int (*get_backlight)(struct omap_dss_device *dssdev);
+};
+struct omap_dss_driver {
+        struct device_driver driver;
+        int (*probe)(struct omap_dss_device *);
+        void (*remove)(struct omap_dss_device *);
+        int (*enable)(struct omap_dss_device *display);
+        void (*disable)(struct omap_dss_device *display);
+        int (*suspend)(struct omap_dss_device *display);
+        int (*resume)(struct omap_dss_device *display);
+        int (*run_test)(struct omap_dss_device *display, int test);
+        void (*setup_update)(struct omap_dss_device *dssdev,
+                        u16 x, u16 y, u16 w, u16 h);
+        int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
+        int (*wait_for_te)(struct omap_dss_device *dssdev);
+        u8 (*get_rotate)(struct omap_dss_device *dssdev);
+        int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
+        bool (*get_mirror)(struct omap_dss_device *dssdev);
+        int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
+        int (*memory_read)(struct omap_dss_device *dssdev,
+                        void *buf, size_t size,
+                        u16 x, u16 y, u16 w, u16 h);
+};
+int omap_dss_register_driver(struct omap_dss_driver *);
+void omap_dss_unregister_driver(struct omap_dss_driver *);
+int omap_dss_register_device(struct omap_dss_device *);
+void omap_dss_unregister_device(struct omap_dss_device *);
+void omap_dss_get_device(struct omap_dss_device *dssdev);
+void omap_dss_put_device(struct omap_dss_device *dssdev);
+#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
+struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
+struct omap_dss_device *omap_dss_find_device(void *data,
+                int (*match)(struct omap_dss_device *dssdev, void *data));
+int omap_dss_start_device(struct omap_dss_device *dssdev);
+void omap_dss_stop_device(struct omap_dss_device *dssdev);
+int omap_dss_get_num_overlay_managers(void);
+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
+int omap_dss_get_num_overlays(void);
+struct omap_overlay *omap_dss_get_overlay(int num);
+typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
+                unsigned long timeout);
+#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
+#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
+#endif
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 72f680b7180d..4ede9e17a0be 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -401,33 +401,6 @@
 /*----------------------------------------------------------------------------*/
-/* Hardware registers for LCD DMA */
-#define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
-#define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
-#define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
-#define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
-#define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
-#define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
-#define OMAP1610_DMA_LCD_BASE           (0xfffee300)
-#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
-#define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
-#define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
-#define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
-#define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
-#define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
-#define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
-#define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
-#define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
-#define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
-#define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
-#define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
-#define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
-#define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
-#define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
-#define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
-#define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 #define OMAP_DMA_HALF_IRQ               (1 << 2)
@@ -441,6 +414,8 @@
 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
+#define OMAP_DMA_CCR_EN                 (1 << 7)
 #define OMAP_DMA_DATA_TYPE_S8           0x00
 #define OMAP_DMA_DATA_TYPE_S16          0x01
 #define OMAP_DMA_DATA_TYPE_S32          0x02
@@ -503,14 +478,6 @@
 #define DMA_CH_PRIO_HIGH                0x1
 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
-/* LCD DMA block numbers */
-enum {
-        OMAP_LCD_DMA_B1_TOP,
-        OMAP_LCD_DMA_B1_BOTTOM,
-        OMAP_LCD_DMA_B2_TOP,
-        OMAP_LCD_DMA_B2_BOTTOM
-};
 enum omap_dma_burst_mode {
        OMAP_DMA_DATA_BURST_DIS = 0,
        OMAP_DMA_DATA_BURST_4,
@@ -633,6 +600,11 @@ extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
 extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
 extern int omap_get_dma_index(int lch, int *ei, int *fi);
+void omap_dma_global_context_save(void);
+void omap_dma_global_context_restore(void);
+extern void omap_dma_disable_irq(int lch);
 /* Chaining APIs */
 #ifndef CONFIG_ARCH_OMAP1
 extern int omap_request_dma_chain(int dev_id, const char *dev_name,
@@ -656,20 +628,13 @@ extern int omap_modify_dma_chain_params(int chain_id,
 extern int omap_dma_chain_status(int chain_id);
 #endif
-/* LCD DMA functions */
+#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
-extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
+#include <mach/lcd_dma.h>
-                                void *data);
+#else
-extern void omap_free_lcd_dma(void);
+static inline int omap_lcd_dma_running(void)
-extern void omap_setup_lcd_dma(void);
+{
-extern void omap_enable_lcd_dma(void);
+        return 0;
-extern void omap_stop_lcd_dma(void);
+}
-extern void omap_set_lcd_dma_ext_controller(int external);
+#endif
-extern void omap_set_lcd_dma_single_transfer(int single);
-extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
-                                int data_type);
-extern void omap_set_lcd_dma_b1_rotation(int rotate);
-extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
-extern void omap_set_lcd_dma_b1_mirror(int mirror);
-extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
 #endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-omap/include/mach/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 20f1054c0a80..20f1054c0a80 100644
--- a/arch/arm/plat-omap/include/mach/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
diff --git a/arch/arm/plat-omap/include/mach/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h
index da97736f3efa..da97736f3efa 100644
--- a/arch/arm/plat-omap/include/mach/dsp_common.h
+++ b/arch/arm/plat-omap/include/plat/dsp_common.h
diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
index f1864a652f7a..f1864a652f7a 100644
--- a/arch/arm/plat-omap/include/mach/fpga.h
+++ b/arch/arm/plat-omap/include/plat/fpga.h
diff --git a/arch/arm/plat-omap/include/mach/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
index 10da0e07c0cf..10da0e07c0cf 100644
--- a/arch/arm/plat-omap/include/mach/gpio-switch.h
+++ b/arch/arm/plat-omap/include/plat/gpio-switch.h
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 633ff688b928..de7c54731cbe 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -76,7 +76,8 @@ extern void omap2_gpio_prepare_for_retention(void);
 extern void omap2_gpio_resume_after_retention(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
+extern void omap_gpio_save_context(void);
+extern void omap_gpio_restore_context(void);
 /*-------------------------------------------------------------------------*/
 /* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
index b64fbee4d567..b64fbee4d567 100644
--- a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
+++ b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 9c99cda77ba6..e081338e0b23 100644
--- a/arch/arm/plat-omap/include/mach/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -45,13 +45,14 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(1)
+#define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(2)
 #define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
+#define GPMC_CONFIG7_CSVALID            (1 << 6)
 /*
 * Note that all values in this struct are in nanoseconds, while
@@ -107,6 +108,8 @@ extern int gpmc_prefetch_enable(int cs, int dma_mode,
                                        unsigned int u32_count, int is_write);
 extern void gpmc_prefetch_reset(void);
 extern int gpmc_prefetch_status(void);
+extern void omap3_gpmc_save_context(void);
+extern void omap3_gpmc_restore_context(void);
 extern void __init gpmc_init(void);
 #endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index 26c1fbff08aa..d5b26adfb890 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -39,9 +39,9 @@
 #include <asm/sizes.h>
 #ifndef __ASSEMBLER__
 #include <asm/types.h>
-#include <mach/cpu.h>
+#include <plat/cpu.h>
 #endif
-#include <mach/serial.h>
+#include <plat/serial.h>
 /*
 * ---------------------------------------------------------------------------
@@ -280,11 +280,11 @@
 * ---------------------------------------------------------------------------
 */
-#include "omap730.h"
+#include <plat/omap7xx.h>
-#include "omap1510.h"
+#include <plat/omap1510.h>
-#include "omap16xx.h"
+#include <plat/omap16xx.h>
-#include "omap24xx.h"
+#include <plat/omap24xx.h>
-#include "omap34xx.h"
+#include <plat/omap34xx.h>
-#include "omap44xx.h"
+#include <plat/omap44xx.h>
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/plat/hwa742.h
index 886248d32b49..886248d32b49 100644
--- a/arch/arm/plat-omap/include/mach/hwa742.h
+++ b/arch/arm/plat-omap/include/plat/hwa742.h
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
new file mode 100644
index 000000000000..585d9ca68b97
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -0,0 +1,39 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+#include <linux/i2c.h>
+#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len);
+#else
+static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len)
+{
+        return 0;
+}
+#endif
+int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len);
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/plat/io.h
index 8d32df32b0b1..7e5319f907d1 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -63,8 +63,24 @@
 #define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
 #define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
-#define OMAP2_IO_OFFSET         0x90000000
+#define OMAP2_L3_IO_OFFSET      0x90000000
-#define OMAP2_IO_ADDRESS(pa)    IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */
+#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
+#define OMAP2_L4_IO_OFFSET      0xb2000000
+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
+#define OMAP4_L3_IO_OFFSET      0xb4000000
+#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
+#define OMAP4_L3_PER_IO_OFFSET  0xb1100000
+#define OMAP4_L3_PER_IO_ADDRESS(pa)     IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
+#define OMAP4_GPMC_IO_OFFSET            0xa9000000
+#define OMAP4_GPMC_IO_ADDRESS(pa)       IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
+#define OMAP2_EMU_IO_OFFSET             0xaa800000      /* Emulation */
+#define OMAP2_EMU_IO_ADDRESS(pa)        IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
 /*
 * ----------------------------------------------------------------------------
@@ -83,24 +99,27 @@
 */
 /* We map both L3 and L4 on OMAP2 */
-#define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 */
+#define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 --> 0xf8000000*/
-#define L3_24XX_VIRT    0xf8000000
+#define L3_24XX_VIRT    (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
 #define L3_24XX_SIZE    SZ_1M           /* 44kB of 128MB used, want 1MB sect */
-#define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 */
+#define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 --> 0xfa000000 */
-#define L4_24XX_VIRT    0xd8000000
+#define L4_24XX_VIRT    (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_24XX_SIZE    SZ_1M           /* 1MB of 128MB used, want 1MB sect */
-#define L4_WK_243X_PHYS         L4_WK_243X_BASE         /* 0x49000000 */
+#define L4_WK_243X_PHYS         L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
-#define L4_WK_243X_VIRT         0xd9000000
+#define L4_WK_243X_VIRT         (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_WK_243X_SIZE         SZ_1M
-#define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE      /* 0x49000000 */
+#define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE
-#define OMAP243X_GPMC_VIRT      0xFE000000
+#define OMAP243X_GPMC_VIRT      (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
+                                                /* 0x6e000000 --> 0xfe000000 */
 #define OMAP243X_GPMC_SIZE      SZ_1M
 #define OMAP243X_SDRC_PHYS      OMAP243X_SDRC_BASE
-#define OMAP243X_SDRC_VIRT      0xFD000000
+                                                /* 0x6D000000 --> 0xfd000000 */
+#define OMAP243X_SDRC_VIRT      (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP243X_SDRC_SIZE      SZ_1M
 #define OMAP243X_SMS_PHYS       OMAP243X_SMS_BASE
-#define OMAP243X_SMS_VIRT       0xFC000000
+                                                /* 0x6c000000 --> 0xfc000000 */
+#define OMAP243X_SMS_VIRT       (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP243X_SMS_SIZE       SZ_1M
 /* DSP */
@@ -121,12 +140,12 @@
 */
 /* We map both L3 and L4 on OMAP3 */
-#define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 */
+#define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 --> 0xf8000000 */
-#define L3_34XX_VIRT            0xf8000000
+#define L3_34XX_VIRT            (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
 #define L3_34XX_SIZE            SZ_1M   /* 44kB of 128MB used, want 1MB sect */
-#define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 */
+#define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 --> 0xfa000000 */
-#define L4_34XX_VIRT            0xd8000000
+#define L4_34XX_VIRT            (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 /*
@@ -134,28 +153,33 @@
 * VPOM3430 was not working for Int controller
 */
-#define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 */
+#define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
-#define L4_WK_34XX_VIRT         0xd8300000
+#define L4_WK_34XX_VIRT         (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_WK_34XX_SIZE         SZ_1M
-#define L4_PER_34XX_PHYS        L4_PER_34XX_BASE /* 0x49000000 */
+#define L4_PER_34XX_PHYS        L4_PER_34XX_BASE
-#define L4_PER_34XX_VIRT        0xd9000000
+                                                /* 0x49000000 --> 0xfb000000 */
+#define L4_PER_34XX_VIRT        (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_PER_34XX_SIZE        SZ_1M
-#define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE /* 0x54000000 */
+#define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE
-#define L4_EMU_34XX_VIRT        0xe4000000
+                                                /* 0x54000000 --> 0xfe800000 */
-#define L4_EMU_34XX_SIZE        SZ_64M
+#define L4_EMU_34XX_VIRT        (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
+#define L4_EMU_34XX_SIZE        SZ_8M
-#define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE /* 0x6E000000 */
+#define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE
-#define OMAP34XX_GPMC_VIRT      0xFE000000
+                                                /* 0x6e000000 --> 0xfe000000 */
+#define OMAP34XX_GPMC_VIRT      (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP34XX_GPMC_SIZE      SZ_1M
-#define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE /* 0x6C000000 */
+#define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE
-#define OMAP343X_SMS_VIRT       0xFC000000
+                                                /* 0x6c000000 --> 0xfc000000 */
+#define OMAP343X_SMS_VIRT       (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP343X_SMS_SIZE       SZ_1M
-#define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE /* 0x6D000000 */
+#define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE
-#define OMAP343X_SDRC_VIRT      0xFD000000
+                                                /* 0x6D000000 --> 0xfd000000 */
+#define OMAP343X_SDRC_VIRT      (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP343X_SDRC_SIZE      SZ_1M
 /* DSP */
@@ -176,32 +200,54 @@
 */
 /* We map both L3 and L4 on OMAP4 */
-#define L3_44XX_PHYS            L3_44XX_BASE
+#define L3_44XX_PHYS            L3_44XX_BASE    /* 0x44000000 --> 0xf8000000 */
-#define L3_44XX_VIRT            0xd4000000
+#define L3_44XX_VIRT            (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
 #define L3_44XX_SIZE            SZ_1M
-#define L4_44XX_PHYS            L4_44XX_BASE
+#define L4_44XX_PHYS            L4_44XX_BASE    /* 0x4a000000 --> 0xfc000000 */
-#define L4_44XX_VIRT            0xda000000
+#define L4_44XX_VIRT            (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_44XX_SIZE            SZ_4M
-#define L4_WK_44XX_PHYS         L4_WK_44XX_BASE
+#define L4_WK_44XX_PHYS         L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
-#define L4_WK_44XX_VIRT         0xda300000
+#define L4_WK_44XX_VIRT         (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_WK_44XX_SIZE         SZ_1M
 #define L4_PER_44XX_PHYS        L4_PER_44XX_BASE
-#define L4_PER_44XX_VIRT        0xd8000000
+                                                /* 0x48000000 --> 0xfa000000 */
+#define L4_PER_44XX_VIRT        (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_PER_44XX_SIZE        SZ_4M
+#define L4_ABE_44XX_PHYS        L4_ABE_44XX_BASE
+                                                /* 0x49000000 --> 0xfb000000 */
+#define L4_ABE_44XX_VIRT        (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_ABE_44XX_SIZE        SZ_1M
 #define L4_EMU_44XX_PHYS        L4_EMU_44XX_BASE
-#define L4_EMU_44XX_VIRT        0xe4000000
+                                                /* 0x54000000 --> 0xfe800000 */
-#define L4_EMU_44XX_SIZE        SZ_64M
+#define L4_EMU_44XX_VIRT        (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
+#define L4_EMU_44XX_SIZE        SZ_8M
 #define OMAP44XX_GPMC_PHYS      OMAP44XX_GPMC_BASE
-#define OMAP44XX_GPMC_VIRT      0xe0000000
+                                                /* 0x50000000 --> 0xf9000000 */
+#define OMAP44XX_GPMC_VIRT      (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
 #define OMAP44XX_GPMC_SIZE      SZ_1M
+#define OMAP44XX_EMIF1_PHYS     OMAP44XX_EMIF1_BASE
+                                                /* 0x4c000000 --> 0xfd100000 */
+#define OMAP44XX_EMIF1_VIRT     (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
+#define OMAP44XX_EMIF1_SIZE     SZ_1M
+#define OMAP44XX_EMIF2_PHYS     OMAP44XX_EMIF2_BASE
+                                                /* 0x4d000000 --> 0xfd200000 */
+#define OMAP44XX_EMIF2_VIRT     (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
+#define OMAP44XX_EMIF2_SIZE     SZ_1M
+#define OMAP44XX_DMM_PHYS       OMAP44XX_DMM_BASE
+                                                /* 0x4e000000 --> 0xfd300000 */
+#define OMAP44XX_DMM_VIRT       (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
+#define OMAP44XX_DMM_SIZE       SZ_1M
 /*
 * ----------------------------------------------------------------------------
 * Omap specific register access
diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 46d41ac83dbf..0752af9d099e 100644
--- a/arch/arm/plat-omap/include/mach/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -107,7 +107,7 @@ struct iommu_platform_data {
 #if defined(CONFIG_ARCH_OMAP1)
 #error "iommu for this processor not implemented yet"
 #else
-#include <mach/iommu2.h>
+#include <plat/iommu2.h>
 #endif
 /*
diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/plat/iommu2.h
index 10ad05f410e9..10ad05f410e9 100644
--- a/arch/arm/plat-omap/include/mach/iommu2.h
+++ b/arch/arm/plat-omap/include/plat/iommu2.h
diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
index bdc7ce5d7a4a..bdc7ce5d7a4a 100644
--- a/arch/arm/plat-omap/include/mach/iovmm.h
+++ b/arch/arm/plat-omap/include/plat/iovmm.h
diff --git a/arch/arm/plat-omap/include/mach/irda.h b/arch/arm/plat-omap/include/plat/irda.h
index 40f60339d1c6..40f60339d1c6 100644
--- a/arch/arm/plat-omap/include/mach/irda.h
+++ b/arch/arm/plat-omap/include/plat/irda.h
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 28a165058b61..ce5dd2d1dc21 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -86,49 +86,26 @@
 #define INT_1610_SSR_FIFO_0     29
 /*
- * OMAP-730 specific IRQ numbers for interrupt handler 1
+ * OMAP-7xx specific IRQ numbers for interrupt handler 1
 */
-#define INT_730_IH2_FIQ         0
+#define INT_7XX_IH2_FIQ         0
-#define INT_730_IH2_IRQ         1
+#define INT_7XX_IH2_IRQ         1
-#define INT_730_USB_NON_ISO     2
+#define INT_7XX_USB_NON_ISO     2
-#define INT_730_USB_ISO         3
+#define INT_7XX_USB_ISO         3
-#define INT_730_ICR             4
+#define INT_7XX_ICR             4
-#define INT_730_EAC             5
+#define INT_7XX_EAC             5
-#define INT_730_GPIO_BANK1      6
+#define INT_7XX_GPIO_BANK1      6
-#define INT_730_GPIO_BANK2      7
+#define INT_7XX_GPIO_BANK2      7
-#define INT_730_GPIO_BANK3      8
+#define INT_7XX_GPIO_BANK3      8
-#define INT_730_McBSP2TX        10
+#define INT_7XX_McBSP2TX        10
-#define INT_730_McBSP2RX        11
+#define INT_7XX_McBSP2RX        11
-#define INT_730_McBSP2RX_OVF    12
+#define INT_7XX_McBSP2RX_OVF    12
-#define INT_730_LCD_LINE        14
+#define INT_7XX_LCD_LINE        14
-#define INT_730_GSM_PROTECT     15
+#define INT_7XX_GSM_PROTECT     15
-#define INT_730_TIMER3          16
+#define INT_7XX_TIMER3          16
-#define INT_730_GPIO_BANK5      17
+#define INT_7XX_GPIO_BANK5      17
-#define INT_730_GPIO_BANK6      18
+#define INT_7XX_GPIO_BANK6      18
-#define INT_730_SPGIO_WR        29
+#define INT_7XX_SPGIO_WR        29
-/*
- * OMAP-850 specific IRQ numbers for interrupt handler 1
- */
-#define INT_850_IH2_FIQ         0
-#define INT_850_IH2_IRQ         1
-#define INT_850_USB_NON_ISO     2
-#define INT_850_USB_ISO         3
-#define INT_850_ICR             4
-#define INT_850_EAC             5
-#define INT_850_GPIO_BANK1      6
-#define INT_850_GPIO_BANK2      7
-#define INT_850_GPIO_BANK3      8
-#define INT_850_McBSP2TX        10
-#define INT_850_McBSP2RX        11
-#define INT_850_McBSP2RX_OVF    12
-#define INT_850_LCD_LINE        14
-#define INT_850_GSM_PROTECT     15
-#define INT_850_TIMER3          16
-#define INT_850_GPIO_BANK5      17
-#define INT_850_GPIO_BANK6      18
-#define INT_850_SPGIO_WR        29
 /*
 * IRQ numbers for interrupt handler 2
@@ -206,120 +183,62 @@
 #define INT_1610_SHA1MD5        (91 + IH2_BASE)
 /*
- * OMAP-730 specific IRQ numbers for interrupt handler 2
+ * OMAP-7xx specific IRQ numbers for interrupt handler 2
 */
-#define INT_730_HW_ERRORS       (0 + IH2_BASE)
+#define INT_7XX_HW_ERRORS       (0 + IH2_BASE)
-#define INT_730_NFIQ_PWR_FAIL   (1 + IH2_BASE)
+#define INT_7XX_NFIQ_PWR_FAIL   (1 + IH2_BASE)
-#define INT_730_CFCD            (2 + IH2_BASE)
+#define INT_7XX_CFCD            (2 + IH2_BASE)
-#define INT_730_CFIREQ          (3 + IH2_BASE)
+#define INT_7XX_CFIREQ          (3 + IH2_BASE)
-#define INT_730_I2C             (4 + IH2_BASE)
+#define INT_7XX_I2C             (4 + IH2_BASE)
-#define INT_730_PCC             (5 + IH2_BASE)
+#define INT_7XX_PCC             (5 + IH2_BASE)
-#define INT_730_MPU_EXT_NIRQ    (6 + IH2_BASE)
+#define INT_7XX_MPU_EXT_NIRQ    (6 + IH2_BASE)
-#define INT_730_SPI_100K_1      (7 + IH2_BASE)
+#define INT_7XX_SPI_100K_1      (7 + IH2_BASE)
-#define INT_730_SYREN_SPI       (8 + IH2_BASE)
+#define INT_7XX_SYREN_SPI       (8 + IH2_BASE)
-#define INT_730_VLYNQ           (9 + IH2_BASE)
+#define INT_7XX_VLYNQ           (9 + IH2_BASE)
-#define INT_730_GPIO_BANK4      (10 + IH2_BASE)
+#define INT_7XX_GPIO_BANK4      (10 + IH2_BASE)
-#define INT_730_McBSP1TX        (11 + IH2_BASE)
+#define INT_7XX_McBSP1TX        (11 + IH2_BASE)
-#define INT_730_McBSP1RX        (12 + IH2_BASE)
+#define INT_7XX_McBSP1RX        (12 + IH2_BASE)
-#define INT_730_McBSP1RX_OF     (13 + IH2_BASE)
+#define INT_7XX_McBSP1RX_OF     (13 + IH2_BASE)
-#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_730_UART_MODEM_1    (15 + IH2_BASE)
+#define INT_7XX_UART_MODEM_1    (15 + IH2_BASE)
-#define INT_730_MCSI            (16 + IH2_BASE)
+#define INT_7XX_MCSI            (16 + IH2_BASE)
-#define INT_730_uWireTX         (17 + IH2_BASE)
+#define INT_7XX_uWireTX         (17 + IH2_BASE)
-#define INT_730_uWireRX         (18 + IH2_BASE)
+#define INT_7XX_uWireRX         (18 + IH2_BASE)
-#define INT_730_SMC_CD          (19 + IH2_BASE)
+#define INT_7XX_SMC_CD          (19 + IH2_BASE)
-#define INT_730_SMC_IREQ        (20 + IH2_BASE)
+#define INT_7XX_SMC_IREQ        (20 + IH2_BASE)
-#define INT_730_HDQ_1WIRE       (21 + IH2_BASE)
+#define INT_7XX_HDQ_1WIRE       (21 + IH2_BASE)
-#define INT_730_TIMER32K        (22 + IH2_BASE)
+#define INT_7XX_TIMER32K        (22 + IH2_BASE)
-#define INT_730_MMC_SDIO        (23 + IH2_BASE)
+#define INT_7XX_MMC_SDIO        (23 + IH2_BASE)
-#define INT_730_UPLD            (24 + IH2_BASE)
+#define INT_7XX_UPLD            (24 + IH2_BASE)
-#define INT_730_USB_HHC_1       (27 + IH2_BASE)
+#define INT_7XX_USB_HHC_1       (27 + IH2_BASE)
-#define INT_730_USB_HHC_2       (28 + IH2_BASE)
+#define INT_7XX_USB_HHC_2       (28 + IH2_BASE)
-#define INT_730_USB_GENI        (29 + IH2_BASE)
+#define INT_7XX_USB_GENI        (29 + IH2_BASE)
-#define INT_730_USB_OTG         (30 + IH2_BASE)
+#define INT_7XX_USB_OTG         (30 + IH2_BASE)
-#define INT_730_CAMERA_IF       (31 + IH2_BASE)
+#define INT_7XX_CAMERA_IF       (31 + IH2_BASE)
-#define INT_730_RNG             (32 + IH2_BASE)
+#define INT_7XX_RNG             (32 + IH2_BASE)
-#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_730_DBB_RF_EN       (34 + IH2_BASE)
+#define INT_7XX_DBB_RF_EN       (34 + IH2_BASE)
-#define INT_730_MPUIO_KEYPAD    (35 + IH2_BASE)
+#define INT_7XX_MPUIO_KEYPAD    (35 + IH2_BASE)
-#define INT_730_SHA1_MD5        (36 + IH2_BASE)
+#define INT_7XX_SHA1_MD5        (36 + IH2_BASE)
-#define INT_730_SPI_100K_2      (37 + IH2_BASE)
+#define INT_7XX_SPI_100K_2      (37 + IH2_BASE)
-#define INT_730_RNG_IDLE        (38 + IH2_BASE)
+#define INT_7XX_RNG_IDLE        (38 + IH2_BASE)
-#define INT_730_MPUIO           (39 + IH2_BASE)
+#define INT_7XX_MPUIO           (39 + IH2_BASE)
-#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
+#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
-#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_730_LLPC_OE_RISING  (42 + IH2_BASE)
+#define INT_7XX_LLPC_OE_RISING  (42 + IH2_BASE)
-#define INT_730_LLPC_VSYNC      (43 + IH2_BASE)
+#define INT_7XX_LLPC_VSYNC      (43 + IH2_BASE)
-#define INT_730_WAKE_UP_REQ     (46 + IH2_BASE)
+#define INT_7XX_WAKE_UP_REQ     (46 + IH2_BASE)
-#define INT_730_DMA_CH6         (53 + IH2_BASE)
+#define INT_7XX_DMA_CH6         (53 + IH2_BASE)
-#define INT_730_DMA_CH7         (54 + IH2_BASE)
+#define INT_7XX_DMA_CH7         (54 + IH2_BASE)
-#define INT_730_DMA_CH8         (55 + IH2_BASE)
+#define INT_7XX_DMA_CH8         (55 + IH2_BASE)
-#define INT_730_DMA_CH9         (56 + IH2_BASE)
+#define INT_7XX_DMA_CH9         (56 + IH2_BASE)
-#define INT_730_DMA_CH10        (57 + IH2_BASE)
+#define INT_7XX_DMA_CH10        (57 + IH2_BASE)
-#define INT_730_DMA_CH11        (58 + IH2_BASE)
+#define INT_7XX_DMA_CH11        (58 + IH2_BASE)
-#define INT_730_DMA_CH12        (59 + IH2_BASE)
+#define INT_7XX_DMA_CH12        (59 + IH2_BASE)
-#define INT_730_DMA_CH13        (60 + IH2_BASE)
+#define INT_7XX_DMA_CH13        (60 + IH2_BASE)
-#define INT_730_DMA_CH14        (61 + IH2_BASE)
+#define INT_7XX_DMA_CH14        (61 + IH2_BASE)
-#define INT_730_DMA_CH15        (62 + IH2_BASE)
+#define INT_7XX_DMA_CH15        (62 + IH2_BASE)
-#define INT_730_NAND            (63 + IH2_BASE)
+#define INT_7XX_NAND            (63 + IH2_BASE)
-/*
- * OMAP-850 specific IRQ numbers for interrupt handler 2
- */
-#define INT_850_HW_ERRORS       (0 + IH2_BASE)
-#define INT_850_NFIQ_PWR_FAIL   (1 + IH2_BASE)
-#define INT_850_CFCD            (2 + IH2_BASE)
-#define INT_850_CFIREQ          (3 + IH2_BASE)
-#define INT_850_I2C             (4 + IH2_BASE)
-#define INT_850_PCC             (5 + IH2_BASE)
-#define INT_850_MPU_EXT_NIRQ    (6 + IH2_BASE)
-#define INT_850_SPI_100K_1      (7 + IH2_BASE)
-#define INT_850_SYREN_SPI       (8 + IH2_BASE)
-#define INT_850_VLYNQ           (9 + IH2_BASE)
-#define INT_850_GPIO_BANK4      (10 + IH2_BASE)
-#define INT_850_McBSP1TX        (11 + IH2_BASE)
-#define INT_850_McBSP1RX        (12 + IH2_BASE)
-#define INT_850_McBSP1RX_OF     (13 + IH2_BASE)
-#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_850_UART_MODEM_1    (15 + IH2_BASE)
-#define INT_850_MCSI            (16 + IH2_BASE)
-#define INT_850_uWireTX         (17 + IH2_BASE)
-#define INT_850_uWireRX         (18 + IH2_BASE)
-#define INT_850_SMC_CD          (19 + IH2_BASE)
-#define INT_850_SMC_IREQ        (20 + IH2_BASE)
-#define INT_850_HDQ_1WIRE       (21 + IH2_BASE)
-#define INT_850_TIMER32K        (22 + IH2_BASE)
-#define INT_850_MMC_SDIO        (23 + IH2_BASE)
-#define INT_850_UPLD            (24 + IH2_BASE)
-#define INT_850_USB_HHC_1       (27 + IH2_BASE)
-#define INT_850_USB_HHC_2       (28 + IH2_BASE)
-#define INT_850_USB_GENI        (29 + IH2_BASE)
-#define INT_850_USB_OTG         (30 + IH2_BASE)
-#define INT_850_CAMERA_IF       (31 + IH2_BASE)
-#define INT_850_RNG             (32 + IH2_BASE)
-#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_850_DBB_RF_EN       (34 + IH2_BASE)
-#define INT_850_MPUIO_KEYPAD    (35 + IH2_BASE)
-#define INT_850_SHA1_MD5        (36 + IH2_BASE)
-#define INT_850_SPI_100K_2      (37 + IH2_BASE)
-#define INT_850_RNG_IDLE        (38 + IH2_BASE)
-#define INT_850_MPUIO           (39 + IH2_BASE)
-#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
-#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_850_LLPC_OE_RISING  (42 + IH2_BASE)
-#define INT_850_LLPC_VSYNC      (43 + IH2_BASE)
-#define INT_850_WAKE_UP_REQ     (46 + IH2_BASE)
-#define INT_850_DMA_CH6         (53 + IH2_BASE)
-#define INT_850_DMA_CH7         (54 + IH2_BASE)
-#define INT_850_DMA_CH8         (55 + IH2_BASE)
-#define INT_850_DMA_CH9         (56 + IH2_BASE)
-#define INT_850_DMA_CH10        (57 + IH2_BASE)
-#define INT_850_DMA_CH11        (58 + IH2_BASE)
-#define INT_850_DMA_CH12        (59 + IH2_BASE)
-#define INT_850_DMA_CH13        (60 + IH2_BASE)
-#define INT_850_DMA_CH14        (61 + IH2_BASE)
-#define INT_850_DMA_CH15        (62 + IH2_BASE)
-#define INT_850_NAND            (63 + IH2_BASE)
 #define INT_24XX_SYS_NIRQ       7
 #define INT_24XX_SDMA_IRQ0      12
@@ -558,9 +477,14 @@
 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
+#define INTCPS_NR_MIR_REGS      3
+#define INTCPS_NR_IRQS          96
 #ifndef __ASSEMBLY__
 extern void omap_init_irq(void);
 extern int omap_irq_pending(void);
+void omap_intc_save_context(void);
+void omap_intc_restore_context(void);
 #endif
 #include <mach/hardware.h>
diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 3ae52ccc793c..3ae52ccc793c 100644
--- a/arch/arm/plat-omap/include/mach/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
diff --git a/arch/arm/plat-omap/include/mach/lcd_mipid.h b/arch/arm/plat-omap/include/plat/lcd_mipid.h
index 8e52c6572281..8e52c6572281 100644
--- a/arch/arm/plat-omap/include/mach/lcd_mipid.h
+++ b/arch/arm/plat-omap/include/plat/lcd_mipid.h
diff --git a/arch/arm/plat-omap/include/mach/led.h b/arch/arm/plat-omap/include/plat/led.h
index 25e451e7e2fd..25e451e7e2fd 100644
--- a/arch/arm/plat-omap/include/mach/led.h
+++ b/arch/arm/plat-omap/include/plat/led.h
diff --git a/arch/arm/plat-omap/include/mach/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index b7a6991814ec..729166b76a7c 100644
--- a/arch/arm/plat-omap/include/mach/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -6,9 +6,9 @@
 #include <linux/wait.h>
 #include <linux/workqueue.h>
 #include <linux/blkdev.h>
+#include <linux/interrupt.h>
 typedef u32 mbox_msg_t;
-typedef void (mbox_receiver_t)(mbox_msg_t msg);
 struct omap_mbox;
 typedef int __bitwise omap_mbox_irq_t;
@@ -29,8 +29,10 @@ struct omap_mbox_ops {
        int             (*fifo_empty)(struct omap_mbox *mbox);
        int             (*fifo_full)(struct omap_mbox *mbox);
        /* irq */
-        void            (*enable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+        void            (*enable_irq)(struct omap_mbox *mbox,
-        void            (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+                                                omap_mbox_irq_t irq);
+        void            (*disable_irq)(struct omap_mbox *mbox,
+                                                omap_mbox_irq_t irq);
        void            (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
        int             (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
        /* ctx */
@@ -42,6 +44,7 @@ struct omap_mbox_queue {
        spinlock_t              lock;
        struct request_queue    *queue;
        struct work_struct      work;
+        struct tasklet_struct   tasklet;
        int     (*callback)(void *);
        struct omap_mbox        *mbox;
 };
@@ -64,7 +67,7 @@ struct omap_mbox {
        void                    (*err_notify)(void);
 };
-int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *);
+int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
 void omap_mbox_init_seq(struct omap_mbox *);
 struct omap_mbox *omap_mbox_get(const char *);
@@ -93,4 +96,16 @@ static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
        mbox->ops->restore_ctx(mbox);
 }
+static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
+                                        omap_mbox_irq_t irq)
+{
+        mbox->ops->enable_irq(mbox, irq);
+}
+static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
+                                         omap_mbox_irq_t irq)
+{
+        mbox->ops->disable_irq(mbox, irq);
+}
 #endif /* MAILBOX_H */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index e0d6eca222cc..4f22e5bb7ff7 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -28,10 +28,10 @@
 #include <linux/spinlock.h>
 #include <mach/hardware.h>
-#include <mach/clock.h>
+#include <plat/clock.h>
-#define OMAP730_MCBSP1_BASE     0xfffb1000
+#define OMAP7XX_MCBSP1_BASE     0xfffb1000
-#define OMAP730_MCBSP2_BASE     0xfffb1800
+#define OMAP7XX_MCBSP2_BASE     0xfffb1800
 #define OMAP1510_MCBSP1_BASE    0xe1011800
 #define OMAP1510_MCBSP2_BASE    0xfffb1000
@@ -58,7 +58,7 @@
 #define OMAP44XX_MCBSP3_BASE    0x49026000
 #define OMAP44XX_MCBSP4_BASE    0x48074000
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x02
diff --git a/arch/arm/plat-omap/include/mach/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 1254e4945b6f..1254e4945b6f 100644
--- a/arch/arm/plat-omap/include/mach/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/plat/memory.h
index 9ad41dc484c1..3325f7b49eaa 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -68,6 +68,13 @@
                __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
           __dma; })
+#define __arch_dma_to_page(dev, addr)   \
+        ({ dma_addr_t __dma = addr;                             \
+           if (is_lbus_device(dev))                             \
+                __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET;      \
+           phys_to_page(__dma);                                 \
+        })
 #define __arch_dma_to_virt(dev, addr)   ({ (void *) (is_lbus_device(dev) ? \
                                                lbus_to_virt(addr) : \
                                                __phys_to_virt(addr)); })
diff --git a/arch/arm/plat-omap/include/mach/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h
index 3122bf68c7ce..3122bf68c7ce 100644
--- a/arch/arm/plat-omap/include/mach/menelaus.h
+++ b/arch/arm/plat-omap/include/plat/menelaus.h
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 7229b9593301..29937137bf3e 100644
--- a/arch/arm/plat-omap/include/mach/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -15,7 +15,7 @@
 #include <linux/device.h>
 #include <linux/mmc/host.h>
-#include <mach/board.h>
+#include <plat/board.h>
 #define OMAP15XX_NR_MMC         1
 #define OMAP16XX_NR_MMC         2
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index 0f49d2d563d9..8f069cc80350 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -51,23 +51,13 @@
                                        .pu_pd_reg = PU_PD_SEL_##reg, \
                                        .pu_pd_val = status,
-#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
+#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
-                                        .mux_reg = OMAP730_IO_CONF_##reg, \
+                                        .mux_reg = OMAP7XX_IO_CONF_##reg, \
                                        .mask_offset = mode_offset, \
                                        .mask = mode,
-#define PULL_REG_730(reg, bit, status)  .pull_name = "OMAP730_IO_CONF_"#reg, \
+#define PULL_REG_7XX(reg, bit, status)  .pull_name = "OMAP7XX_IO_CONF_"#reg, \
-                                        .pull_reg = OMAP730_IO_CONF_##reg, \
+                                        .pull_reg = OMAP7XX_IO_CONF_##reg, \
-                                        .pull_bit = bit, \
-                                        .pull_val = status,
-#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
-                                        .mux_reg = OMAP850_IO_CONF_##reg, \
-                                        .mask_offset = mode_offset, \
-                                        .mask = mode,
-#define PULL_REG_850(reg, bit, status)  .pull_name = "OMAP850_IO_CONF_"#reg, \
-                                        .pull_reg = OMAP850_IO_CONF_##reg, \
                                        .pull_bit = bit, \
                                        .pull_val = status,
@@ -84,21 +74,12 @@
 #define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
                                        .pu_pd_val = status,
-#define MUX_REG_730(reg, mode_offset, mode) \
+#define MUX_REG_7XX(reg, mode_offset, mode) \
-                                        .mux_reg = OMAP730_IO_CONF_##reg, \
+                                        .mux_reg = OMAP7XX_IO_CONF_##reg, \
-                                        .mask_offset = mode_offset, \
-                                        .mask = mode,
-#define PULL_REG_730(reg, bit, status)  .pull_reg = OMAP730_IO_CONF_##reg, \
-                                        .pull_bit = bit, \
-                                        .pull_val = status,
-#define MUX_REG_850(reg, mode_offset, mode) \
-                                        .mux_reg = OMAP850_IO_CONF_##reg, \
                                        .mask_offset = mode_offset, \
                                        .mask = mode,
-#define PULL_REG_850(reg, bit, status)  .pull_reg = OMAP850_IO_CONF_##reg, \
+#define PULL_REG_7XX(reg, bit, status)  .pull_reg = OMAP7XX_IO_CONF_##reg, \
                                        .pull_bit = bit, \
                                        .pull_val = status,
@@ -118,32 +99,21 @@
 /*
 * OMAP730/850 has a slightly different config for the pin mux.
- * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
+ * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
 *   not the FUNC_MUX_CTRL_x regs from hardware.h
 * - for pull-up/down, only has one enable bit which is is in the same register
 *   as mux config
 */
-#define MUX_CFG_730(desc, mux_reg, mode_offset, mode,   \
+#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,   \
-                   pull_bit, pull_status, debug_status)\
-{                                                       \
-        .name =  desc,                                  \
-        .debug = debug_status,                          \
-        MUX_REG_730(mux_reg, mode_offset, mode)         \
-        PULL_REG_730(mux_reg, pull_bit, pull_status)    \
-        PU_PD_REG(NA, 0)                \
-},
-#define MUX_CFG_850(desc, mux_reg, mode_offset, mode,   \
                   pull_bit, pull_status, debug_status)\
 {                                                       \
        .name =  desc,                                  \
        .debug = debug_status,                          \
-        MUX_REG_850(mux_reg, mode_offset, mode)         \
+        MUX_REG_7XX(mux_reg, mode_offset, mode)         \
-        PULL_REG_850(mux_reg, pull_bit, pull_status)    \
+        PULL_REG_7XX(mux_reg, pull_bit, pull_status)    \
        PU_PD_REG(NA, 0)                \
 },
 #define MUX_CFG_24XX(desc, reg_offset, mode,                    \
                                pull_en, pull_mode, dbg)        \
 {                                                               \
@@ -160,58 +130,11 @@
 #define OMAP2_PULL_UP           (1 << 4)
 #define OMAP2_ALTELECTRICALSEL  (1 << 5)
-/* 34xx specific mux bit defines */
-#define OMAP3_INPUT_EN          (1 << 8)
-#define OMAP3_OFF_EN            (1 << 9)
-#define OMAP3_OFFOUT_EN         (1 << 10)
-#define OMAP3_OFFOUT_VAL        (1 << 11)
-#define OMAP3_OFF_PULL_EN       (1 << 12)
-#define OMAP3_OFF_PULL_UP       (1 << 13)
-#define OMAP3_WAKEUP_EN         (1 << 14)
-/* 34xx mux mode options for each pin. See TRM for options */
-#define OMAP34XX_MUX_MODE0      0
-#define OMAP34XX_MUX_MODE1      1
-#define OMAP34XX_MUX_MODE2      2
-#define OMAP34XX_MUX_MODE3      3
-#define OMAP34XX_MUX_MODE4      4
-#define OMAP34XX_MUX_MODE5      5
-#define OMAP34XX_MUX_MODE6      6
-#define OMAP34XX_MUX_MODE7      7
-/* 34xx active pin states */
-#define OMAP34XX_PIN_OUTPUT             0
-#define OMAP34XX_PIN_INPUT              OMAP3_INPUT_EN
-#define OMAP34XX_PIN_INPUT_PULLUP       (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
-                                                | OMAP2_PULL_UP)
-#define OMAP34XX_PIN_INPUT_PULLDOWN     (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
-/* 34xx off mode states */
-#define OMAP34XX_PIN_OFF_NONE           0
-#define OMAP34XX_PIN_OFF_OUTPUT_HIGH    (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
-                                                | OMAP3_OFFOUT_VAL)
-#define OMAP34XX_PIN_OFF_OUTPUT_LOW     (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
-#define OMAP34XX_PIN_OFF_INPUT_PULLUP   (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
-                                                | OMAP3_OFF_PULL_UP)
-#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
-#define OMAP34XX_PIN_OFF_WAKEUPENABLE   OMAP3_WAKEUP_EN
-#define MUX_CFG_34XX(desc, reg_offset, mux_value) {             \
-        .name           = desc,                                 \
-        .debug          = 0,                                    \
-        .mux_reg        = reg_offset,                           \
-        .mux_val        = mux_value                             \
-},
 struct pin_config {
        char                    *name;
        const unsigned int      mux_reg;
        unsigned char           debug;
-#if     defined(CONFIG_ARCH_OMAP34XX)
-        u16                     mux_val; /* Wake-up, off mode, pull, mux mode */
-#endif
 #if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
        const unsigned char mask_offset;
        const unsigned char mask;
@@ -232,45 +155,36 @@ struct pin_config {
 };
-enum omap730_index {
+enum omap7xx_index {
        /* OMAP 730 keyboard */
-        E2_730_KBR0,
+        E2_7XX_KBR0,
-        J7_730_KBR1,
+        J7_7XX_KBR1,
-        E1_730_KBR2,
+        E1_7XX_KBR2,
-        F3_730_KBR3,
+        F3_7XX_KBR3,
-        D2_730_KBR4,
+        D2_7XX_KBR4,
-        C2_730_KBC0,
+        C2_7XX_KBC0,
-        D3_730_KBC1,
+        D3_7XX_KBC1,
-        E4_730_KBC2,
+        E4_7XX_KBC2,
-        F4_730_KBC3,
+        F4_7XX_KBC3,
-        E3_730_KBC4,
+        E3_7XX_KBC4,
-        /* USB */
-        AA17_730_USB_DM,
-        W16_730_USB_PU_EN,
-        W17_730_USB_VBUSI,
-};
-enum omap850_index {
-        /* OMAP 850 keyboard */
-        E2_850_KBR0,
-        J7_850_KBR1,
-        E1_850_KBR2,
-        F3_850_KBR3,
-        D2_850_KBR4,
-        C2_850_KBC0,
-        D3_850_KBC1,
-        E4_850_KBC2,
-        F4_850_KBC3,
-        E3_850_KBC4,
        /* USB */
-        AA17_850_USB_DM,
+        AA17_7XX_USB_DM,
-        W16_850_USB_PU_EN,
+        W16_7XX_USB_PU_EN,
-        W17_850_USB_VBUSI,
+        W17_7XX_USB_VBUSI,
+        W18_7XX_USB_DMCK_OUT,
+        W19_7XX_USB_DCRST,
+        /* MMC */
+        MMC_7XX_CMD,
+        MMC_7XX_CLK,
+        MMC_7XX_DAT0,
+        /* I2C */
+        I2C_7XX_SCL,
+        I2C_7XX_SDA,
 };
 enum omap1xxx_index {
        /* UART1 (BT_UART_GATING)*/
        UART1_TX = 0,
@@ -726,172 +640,6 @@ enum omap24xx_index {
 };
-enum omap34xx_index {
-        /* 34xx I2C */
-        K21_34XX_I2C1_SCL,
-        J21_34XX_I2C1_SDA,
-        AF15_34XX_I2C2_SCL,
-        AE15_34XX_I2C2_SDA,
-        AF14_34XX_I2C3_SCL,
-        AG14_34XX_I2C3_SDA,
-        AD26_34XX_I2C4_SCL,
-        AE26_34XX_I2C4_SDA,
-        /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
-        Y8_3430_USB1HS_PHY_CLK,
-        Y9_3430_USB1HS_PHY_STP,
-        AA14_3430_USB1HS_PHY_DIR,
-        AA11_3430_USB1HS_PHY_NXT,
-        W13_3430_USB1HS_PHY_DATA0,
-        W12_3430_USB1HS_PHY_DATA1,
-        W11_3430_USB1HS_PHY_DATA2,
-        Y11_3430_USB1HS_PHY_DATA3,
-        W9_3430_USB1HS_PHY_DATA4,
-        Y12_3430_USB1HS_PHY_DATA5,
-        W8_3430_USB1HS_PHY_DATA6,
-        Y13_3430_USB1HS_PHY_DATA7,
-        /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
-        AA8_3430_USB2HS_PHY_CLK,
-        AA10_3430_USB2HS_PHY_STP,
-        AA9_3430_USB2HS_PHY_DIR,
-        AB11_3430_USB2HS_PHY_NXT,
-        AB10_3430_USB2HS_PHY_DATA0,
-        AB9_3430_USB2HS_PHY_DATA1,
-        W3_3430_USB2HS_PHY_DATA2,
-        T4_3430_USB2HS_PHY_DATA3,
-        T3_3430_USB2HS_PHY_DATA4,
-        R3_3430_USB2HS_PHY_DATA5,
-        R4_3430_USB2HS_PHY_DATA6,
-        T2_3430_USB2HS_PHY_DATA7,
-        /* TLL - HSUSB: 12-pin TLL Port 1*/
-        Y8_3430_USB1HS_TLL_CLK,
-        Y9_3430_USB1HS_TLL_STP,
-        AA14_3430_USB1HS_TLL_DIR,
-        AA11_3430_USB1HS_TLL_NXT,
-        W13_3430_USB1HS_TLL_DATA0,
-        W12_3430_USB1HS_TLL_DATA1,
-        W11_3430_USB1HS_TLL_DATA2,
-        Y11_3430_USB1HS_TLL_DATA3,
-        W9_3430_USB1HS_TLL_DATA4,
-        Y12_3430_USB1HS_TLL_DATA5,
-        W8_3430_USB1HS_TLL_DATA6,
-        Y13_3430_USB1HS_TLL_DATA7,
-        /* TLL - HSUSB: 12-pin TLL Port 2*/
-        AA8_3430_USB2HS_TLL_CLK,
-        AA10_3430_USB2HS_TLL_STP,
-        AA9_3430_USB2HS_TLL_DIR,
-        AB11_3430_USB2HS_TLL_NXT,
-        AB10_3430_USB2HS_TLL_DATA0,
-        AB9_3430_USB2HS_TLL_DATA1,
-        W3_3430_USB2HS_TLL_DATA2,
-        T4_3430_USB2HS_TLL_DATA3,
-        T3_3430_USB2HS_TLL_DATA4,
-        R3_3430_USB2HS_TLL_DATA5,
-        R4_3430_USB2HS_TLL_DATA6,
-        T2_3430_USB2HS_TLL_DATA7,
-        /* TLL - HSUSB: 12-pin TLL Port 3*/
-        AA6_3430_USB3HS_TLL_CLK,
-        AB3_3430_USB3HS_TLL_STP,
-        AA3_3430_USB3HS_TLL_DIR,
-        Y3_3430_USB3HS_TLL_NXT,
-        AA5_3430_USB3HS_TLL_DATA0,
-        Y4_3430_USB3HS_TLL_DATA1,
-        Y5_3430_USB3HS_TLL_DATA2,
-        W5_3430_USB3HS_TLL_DATA3,
-        AB12_3430_USB3HS_TLL_DATA4,
-        AB13_3430_USB3HS_TLL_DATA5,
-        AA13_3430_USB3HS_TLL_DATA6,
-        AA12_3430_USB3HS_TLL_DATA7,
-        /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
-        AF10_3430_USB1FS_PHY_MM1_RXDP,
-        AG9_3430_USB1FS_PHY_MM1_RXDM,
-        W13_3430_USB1FS_PHY_MM1_RXRCV,
-        W12_3430_USB1FS_PHY_MM1_TXSE0,
-        W11_3430_USB1FS_PHY_MM1_TXDAT,
-        Y11_3430_USB1FS_PHY_MM1_TXEN_N,
-        /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
-        AF7_3430_USB2FS_PHY_MM2_RXDP,
-        AH7_3430_USB2FS_PHY_MM2_RXDM,
-        AB10_3430_USB2FS_PHY_MM2_RXRCV,
-        AB9_3430_USB2FS_PHY_MM2_TXSE0,
-        W3_3430_USB2FS_PHY_MM2_TXDAT,
-        T4_3430_USB2FS_PHY_MM2_TXEN_N,
-        /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
-        AH3_3430_USB3FS_PHY_MM3_RXDP,
-        AE3_3430_USB3FS_PHY_MM3_RXDM,
-        AD1_3430_USB3FS_PHY_MM3_RXRCV,
-        AE1_3430_USB3FS_PHY_MM3_TXSE0,
-        AD2_3430_USB3FS_PHY_MM3_TXDAT,
-        AC1_3430_USB3FS_PHY_MM3_TXEN_N,
-        /* 34xx GPIO
-         *  - normally these are bidirectional, no internal pullup/pulldown
-         *  - "_UP" suffix (GPIO3_UP) if internal pullup is configured
-         *  - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
-         *  - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
-         */
-        AF26_34XX_GPIO0,
-        AF22_34XX_GPIO9,
-        AG9_34XX_GPIO23,
-        AH8_34XX_GPIO29,
-        U8_34XX_GPIO54_OUT,
-        U8_34XX_GPIO54_DOWN,
-        L8_34XX_GPIO63,
-        G25_34XX_GPIO86_OUT,
-        AG4_34XX_GPIO134_OUT,
-        AF4_34XX_GPIO135_OUT,
-        AE4_34XX_GPIO136_OUT,
-        AF6_34XX_GPIO140_UP,
-        AE6_34XX_GPIO141,
-        AF5_34XX_GPIO142,
-        AE5_34XX_GPIO143,
-        H19_34XX_GPIO164_OUT,
-        J25_34XX_GPIO170,
-        /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
-        H16_34XX_SDRC_CKE0,
-        H17_34XX_SDRC_CKE1,
-        /* MMC1 */
-        N28_3430_MMC1_CLK,
-        M27_3430_MMC1_CMD,
-        N27_3430_MMC1_DAT0,
-        N26_3430_MMC1_DAT1,
-        N25_3430_MMC1_DAT2,
-        P28_3430_MMC1_DAT3,
-        P27_3430_MMC1_DAT4,
-        P26_3430_MMC1_DAT5,
-        R27_3430_MMC1_DAT6,
-        R25_3430_MMC1_DAT7,
-        /* MMC2 */
-        AE2_3430_MMC2_CLK,
-        AG5_3430_MMC2_CMD,
-        AH5_3430_MMC2_DAT0,
-        AH4_3430_MMC2_DAT1,
-        AG4_3430_MMC2_DAT2,
-        AF4_3430_MMC2_DAT3,
-        /* MMC3 */
-        AF10_3430_MMC3_CLK,
-        AC3_3430_MMC3_CMD,
-        AE11_3430_MMC3_DAT0,
-        AH9_3430_MMC3_DAT1,
-        AF13_3430_MMC3_DAT2,
-        AF13_3430_MMC3_DAT3,
-        /* SYS_NIRQ T2 INT1 */
-        AF26_34XX_SYS_NIRQ,
-};
 struct omap_mux_cfg {
        struct pin_config       *pins;
        unsigned long           size;
@@ -901,14 +649,14 @@ struct omap_mux_cfg {
 #ifdef  CONFIG_OMAP_MUX
 /* setup pin muxing in Linux */
 extern int omap1_mux_init(void);
-extern int omap2_mux_init(void);
 extern int omap_mux_register(struct omap_mux_cfg *);
 extern int omap_cfg_reg(unsigned long reg_cfg);
 #else
 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
 static inline int omap1_mux_init(void) { return 0; }
-static inline int omap2_mux_init(void) { return 0; }
 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
 #endif
+extern int omap2_mux_init(void);
 #endif
diff --git a/arch/arm/plat-omap/include/mach/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 631a7bed1eef..631a7bed1eef 100644
--- a/arch/arm/plat-omap/include/mach/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
diff --git a/arch/arm/plat-omap/include/mach/omap-alsa.h b/arch/arm/plat-omap/include/plat/omap-alsa.h
index bdf30a0f87f2..b53055b390d0 100644
--- a/arch/arm/plat-omap/include/mach/omap-alsa.h
+++ b/arch/arm/plat-omap/include/plat/omap-alsa.h
@@ -40,10 +40,10 @@
 #ifndef __OMAP_ALSA_H
 #define __OMAP_ALSA_H
-#include <mach/dma.h>
+#include <plat/dma.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
-#include <mach/mcbsp.h>
+#include <plat/mcbsp.h>
 #include <linux/platform_device.h>
 #define DMA_BUF_SIZE    (1024 * 8)
diff --git a/arch/arm/plat-omap/include/mach/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index 3ee41d711492..3ee41d711492 100644
--- a/arch/arm/plat-omap/include/mach/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/plat/omap1510.h
index d24004668138..d24004668138 100644
--- a/arch/arm/plat-omap/include/mach/omap1510.h
+++ b/arch/arm/plat-omap/include/plat/omap1510.h
diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h
index 0e69b504c25f..7560b4d583a3 100644
--- a/arch/arm/plat-omap/include/mach/omap16xx.h
+++ b/arch/arm/plat-omap/include/plat/omap16xx.h
@@ -124,7 +124,7 @@
 #define TIPB_SWITCH_BASE                 (0xfffbc800)
 #define OMAP16XX_MMCSD2_SSW_MPU_CONF    (TIPB_SWITCH_BASE + 0x160)
-/* UART3 Registers Maping through MPU bus */
+/* UART3 Registers Mapping through MPU bus */
 #define UART3_RHR               (OMAP_UART3_BASE + 0)
 #define UART3_THR               (OMAP_UART3_BASE + 0)
 #define UART3_DLL               (OMAP_UART3_BASE + 0)
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
index 696edfc145a6..696edfc145a6 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index f8d186a73712..077f05979f86 100644
--- a/arch/arm/plat-omap/include/mach/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -72,16 +72,15 @@
 #define OMAP3430_ISP_CSI2A_END          (OMAP3430_ISP_CSI2A_BASE   + 0x16F)
 #define OMAP3430_ISP_CSI2PHY_END        (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
-#define OMAP34XX_IVA_INTC_BASE  0x40000000
 #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
-#define OMAP34XX_HSUSB_HOST_BASE        (L4_34XX_BASE + 0x64000)
 #define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
+#define OMAP34XX_UHH_CONFIG_BASE        (L4_34XX_BASE + 0x64000)
+#define OMAP34XX_OHCI_BASE      (L4_34XX_BASE + 0x64400)
+#define OMAP34XX_EHCI_BASE      (L4_34XX_BASE + 0x64800)
+#define OMAP34XX_SR1_BASE       0x480C9000
+#define OMAP34XX_SR2_BASE       0x480CB000
 #define OMAP34XX_MAILBOX_BASE           (L4_34XX_BASE + 0x94000)
-#define OMAP34XX_DSP_BASE       0x58000000
-#define OMAP34XX_DSP_MEM_BASE   (OMAP34XX_DSP_BASE + 0x0)
-#define OMAP34XX_DSP_IPI_BASE   (OMAP34XX_DSP_BASE + 0x1000000)
-#define OMAP34XX_DSP_MMU_BASE   (OMAP34XX_DSP_BASE + 0x2000000)
 #endif /* __ASM_ARCH_OMAP34XX_H */
diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index b3ba5ac7b4a4..ef870de43c29 100644
--- a/arch/arm/plat-omap/include/mach/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -22,9 +22,14 @@
 #define L4_PER_44XX_BASE                0x48000000
 #define L4_EMU_44XX_BASE                0x54000000
 #define L3_44XX_BASE                    0x44000000
+#define OMAP44XX_EMIF1_BASE             0x4c000000
+#define OMAP44XX_EMIF2_BASE             0x4d000000
+#define OMAP44XX_DMM_BASE               0x4e000000
 #define OMAP4430_32KSYNCT_BASE          0x4a304000
-#define OMAP4430_CM_BASE                0x4a004000
+#define OMAP4430_CM1_BASE               0x4a004000
-#define OMAP4430_PRM_BASE               0x48306000
+#define OMAP4430_CM_BASE                OMAP4430_CM1_BASE
+#define OMAP4430_CM2_BASE               0x4a008000
+#define OMAP4430_PRM_BASE               0x4a306000
 #define OMAP44XX_GPMC_BASE              0x50000000
 #define OMAP443X_SCM_BASE               0x4a002000
 #define OMAP443X_CTRL_BASE              OMAP443X_SCM_BASE
@@ -33,14 +38,11 @@
 #define IRQ_SIR_IRQ                     0x0040
 #define OMAP44XX_GIC_DIST_BASE          0x48241000
 #define OMAP44XX_GIC_CPU_BASE           0x48240100
-#define OMAP44XX_VA_GIC_CPU_BASE        OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
 #define OMAP44XX_SCU_BASE               0x48240000
-#define OMAP44XX_VA_SCU_BASE            OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE)
 #define OMAP44XX_LOCAL_TWD_BASE         0x48240600
-#define OMAP44XX_VA_LOCAL_TWD_BASE      OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
-#define OMAP44XX_LOCAL_TWD_SIZE         0x00000100
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
-#define OMAP44XX_VA_WKUPGEN_BASE        OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
+#define OMAP44XX_MAILBOX_BASE           (L4_44XX_BASE + 0xF4000)
 #endif /* __ASM_ARCH_OMAP44XX_H */
diff --git a/arch/arm/plat-omap/include/mach/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h
index 14272bc1a6fd..14272bc1a6fd 100644
--- a/arch/arm/plat-omap/include/mach/omap730.h
+++ b/arch/arm/plat-omap/include/plat/omap730.h
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h
new file mode 100644
index 000000000000..53f52414b0e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap7xx.h
@@ -0,0 +1,104 @@
+/* arch/arm/plat-omap/include/mach/omap7xx.h
+ *
+ * Hardware definitions for TI OMAP7XX processor.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
+ * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP7XX_H
+#define __ASM_ARCH_OMAP7XX_H
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+#define OMAP7XX_DSP_BASE        0xE0000000
+#define OMAP7XX_DSP_SIZE        0x50000
+#define OMAP7XX_DSP_START       0xE0000000
+#define OMAP7XX_DSPREG_BASE     0xE1000000
+#define OMAP7XX_DSPREG_SIZE     SZ_128K
+#define OMAP7XX_DSPREG_START    0xE1000000
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX specific configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_CONFIG_BASE     0xfffe1000
+#define OMAP7XX_IO_CONF_0       0xfffe1070
+#define OMAP7XX_IO_CONF_1       0xfffe1074
+#define OMAP7XX_IO_CONF_2       0xfffe1078
+#define OMAP7XX_IO_CONF_3       0xfffe107c
+#define OMAP7XX_IO_CONF_4       0xfffe1080
+#define OMAP7XX_IO_CONF_5       0xfffe1084
+#define OMAP7XX_IO_CONF_6       0xfffe1088
+#define OMAP7XX_IO_CONF_7       0xfffe108c
+#define OMAP7XX_IO_CONF_8       0xfffe1090
+#define OMAP7XX_IO_CONF_9       0xfffe1094
+#define OMAP7XX_IO_CONF_10      0xfffe1098
+#define OMAP7XX_IO_CONF_11      0xfffe109c
+#define OMAP7XX_IO_CONF_12      0xfffe10a0
+#define OMAP7XX_IO_CONF_13      0xfffe10a4
+#define OMAP7XX_MODE_1          0xfffe1010
+#define OMAP7XX_MODE_2          0xfffe1014
+/* CSMI specials: in terms of base + offset */
+#define OMAP7XX_MODE2_OFFSET    0x14
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX traffic controller configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_FLASH_CFG_0     0xfffecc10
+#define OMAP7XX_FLASH_ACFG_0    0xfffecc50
+#define OMAP7XX_FLASH_CFG_1     0xfffecc14
+#define OMAP7XX_FLASH_ACFG_1    0xfffecc54
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX DSP control registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_ICR_BASE        0xfffbb800
+#define OMAP7XX_DSP_M_CTL       0xfffbb804
+#define OMAP7XX_DSP_MMU_BASE    0xfffed200
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP7XX PCC_UPLD configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP7XX_PCC_UPLD_CTRL_BASE      (0xfffe0900)
+#define OMAP7XX_PCC_UPLD_CTRL           (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
+#endif /*  __ASM_ARCH_OMAP7XX_H */
diff --git a/arch/arm/plat-omap/include/mach/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h
index c33f67981712..c33f67981712 100644
--- a/arch/arm/plat-omap/include/mach/omap850.h
+++ b/arch/arm/plat-omap/include/plat/omap850.h
diff --git a/arch/arm/plat-omap/include/mach/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index bd0e136db337..dc1fac1d805c 100644
--- a/arch/arm/plat-omap/include/mach/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -34,7 +34,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
-#include <mach/omap_hwmod.h>
+#include <plat/omap_hwmod.h>
 /* omap_device._state values */
 #define OMAP_DEVICE_STATE_UNKNOWN       0
@@ -50,8 +50,8 @@
 * @pm_lats: ptr to an omap_device_pm_latency table
 * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
 * @pm_lat_level: array index of the last odpl entry executed - -1 if never
- * @dev_wakeup_lat: dev wakeup latency in microseconds
+ * @dev_wakeup_lat: dev wakeup latency in nanoseconds
- * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM
+ * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
 * @_state: one of OMAP_DEVICE_STATE_* (see above)
 * @flags: device flags
 *
@@ -137,5 +137,7 @@ struct omap_device_pm_latency {
 };
-#endif
+/* Get omap_device pointer from platform_device pointer */
+#define to_omap_device(x) container_of((x), struct omap_device, pdev)
+#endif
diff --git a/arch/arm/plat-omap/include/mach/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1f79c20e2929..007935a921ea 100644
--- a/arch/arm/plat-omap/include/mach/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -35,7 +35,7 @@
 #include <linux/kernel.h>
 #include <linux/ioport.h>
-#include <mach/cpu.h>
+#include <plat/cpu.h>
 struct omap_device;
@@ -50,6 +50,8 @@ struct omap_device;
 #define SYSC_ENAWAKEUP_MASK             (1 << SYSC_ENAWAKEUP_SHIFT)
 #define SYSC_SOFTRESET_SHIFT            1
 #define SYSC_SOFTRESET_MASK             (1 << SYSC_SOFTRESET_SHIFT)
+#define SYSC_AUTOIDLE_SHIFT             0
+#define SYSC_AUTOIDLE_MASK              (1 << SYSC_AUTOIDLE_SHIFT)
 /* OCP SYSSTATUS bit shifts/masks */
 #define SYSS_RESETDONE_SHIFT            0
@@ -62,7 +64,21 @@ struct omap_device;
 /**
- * struct omap_hwmod_dma_info - MPU address space handled by the hwmod
+ * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
+ * @name: name of the IRQ channel (module local name)
+ * @irq_ch: IRQ channel ID
+ *
+ * @name should be something short, e.g., "tx" or "rx".  It is for use
+ * by platform_get_resource_byname().  It is defined locally to the
+ * hwmod.
+ */
+struct omap_hwmod_irq_info {
+        const char      *name;
+        u16             irq;
+};
+/**
+ * struct omap_hwmod_dma_info - DMA channels used by the hwmod
 * @name: name of the DMA channel (module local name)
 * @dma_ch: DMA channel ID
 *
@@ -294,13 +310,17 @@ struct omap_hwmod_omap4_prcm {
 *     SDRAM controller, etc.
 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
 *     controller, etc.
+ * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
+ *     when module is enabled, rather than the default, which is to
+ *     enable autoidle
 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
 */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
 #define HWMOD_INIT_NO_RESET                     (1 << 2)
 #define HWMOD_INIT_NO_IDLE                      (1 << 3)
-#define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 4)
+#define HWMOD_NO_OCP_AUTOIDLE                   (1 << 4)
+#define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 5)
 /*
 * omap_hwmod._int_flags definitions
@@ -373,7 +393,7 @@ struct omap_hwmod_omap4_prcm {
 struct omap_hwmod {
        const char                      *name;
        struct omap_device              *od;
-        u8                              *mpu_irqs;
+        struct omap_hwmod_irq_info      *mpu_irqs;
        struct omap_hwmod_dma_info      *sdma_chs;
        union {
                struct omap_hwmod_omap2_prcm omap2;
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index 72f433d7d827..72f433d7d827 100644
--- a/arch/arm/plat-omap/include/mach/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
diff --git a/arch/arm/plat-omap/include/mach/param.h b/arch/arm/plat-omap/include/plat/param.h
index 1eb4dc326979..1eb4dc326979 100644
--- a/arch/arm/plat-omap/include/mach/param.h
+++ b/arch/arm/plat-omap/include/plat/param.h
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index fa6461423bd0..0b960051eaed 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -19,7 +19,7 @@
 #include <asm/atomic.h>
-#include <mach/cpu.h>
+#include <plat/cpu.h>
 /* Powerdomain basic power states */
@@ -28,6 +28,8 @@
 #define PWRDM_POWER_INACTIVE    0x2
 #define PWRDM_POWER_ON          0x3
+#define PWRDM_MAX_PWRSTS        4
 /* Powerdomain allowable state bitfields */
 #define PWRSTS_OFF_ON           ((1 << PWRDM_POWER_OFF) | \
                                 (1 << PWRDM_POWER_ON))
@@ -40,7 +42,10 @@
 /* Powerdomain flags */
 #define PWRDM_HAS_HDWR_SAR      (1 << 0) /* hardware save-and-restore support */
+#define PWRDM_HAS_MPU_QUIRK     (1 << 1) /* MPU pwr domain has MEM bank 0 bits
+                                          * in MEM bank 1 position. This is
+                                          * true for OMAP3430
+                                          */
 /*
 * Number of memory banks that are power-controllable.  On OMAP3430, the
@@ -85,15 +90,15 @@ struct powerdomain {
        /* Used to represent the OMAP chip types containing this pwrdm */
        const struct omap_chip_id omap_chip;
-        /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
-        const u8 dep_bit;
        /* Powerdomains that can be told to wake this powerdomain up */
        struct pwrdm_dep *wkdep_srcs;
        /* Powerdomains that can be told to keep this pwrdm from inactivity */
        struct pwrdm_dep *sleepdep_srcs;
+        /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
+        const u8 dep_bit;
        /* Possible powerdomain power states */
        const u8 pwrsts;
@@ -118,11 +123,11 @@ struct powerdomain {
        struct list_head node;
        int state;
-        unsigned state_counter[4];
+        unsigned state_counter[PWRDM_MAX_PWRSTS];
 #ifdef CONFIG_PM_DEBUG
        s64 timer;
-        s64 state_timer[4];
+        s64 state_timer[PWRDM_MAX_PWRSTS];
 #endif
 };
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index cda2a70397b4..e63e94e18975 100644
--- a/arch/arm/plat-omap/include/mach/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -27,9 +27,13 @@ u32 omap_prcm_get_reset_sources(void);
 void omap_prcm_arch_reset(char mode);
 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
-#endif
+#define START_PADCONF_SAVE 0x2
+#define PADCONF_SAVE_DONE  0x1
+void omap3_prcm_save_context(void);
+void omap3_prcm_restore_context(void);
+#endif
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 1c09c78a48f2..7b76f50564ba 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -44,6 +44,12 @@
 #define SDRC_RFR_CTRL_1         0x0D4
 #define SDRC_MANUAL_1           0x0D8
+#define SDRC_POWER_AUTOCOUNT_SHIFT      8
+#define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
+#define SDRC_POWER_CLKCTRL_SHIFT        4
+#define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
+#define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
 /*
 * These values represent the number of memory clock cycles between
 * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
@@ -80,15 +86,18 @@
 */
 #define OMAP242X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
 #define OMAP243X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
 #define OMAP343X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
 /* SMS register offsets - read/write with sms_{read,write}_reg() */
-#define SMS_SYSCONFIG           0x010
+#define SMS_SYSCONFIG                   0x010
+#define SMS_ROT_CONTROL(context)        (0x180 + 0x10 * context)
+#define SMS_ROT_SIZE(context)           (0x184 + 0x10 * context)
+#define SMS_ROT_PHYSICAL_BA(context)    (0x188 + 0x10 * context)
 /* REVISIT: fill in other SMS registers here */
@@ -120,6 +129,12 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 int omap2_sdrc_get_params(unsigned long r,
                          struct omap_sdrc_params **sdrc_cs0,
                          struct omap_sdrc_params **sdrc_cs1);
+void omap2_sms_save_context(void);
+void omap2_sms_restore_context(void);
+void omap2_sms_write_rot_control(u32 val, unsigned ctx);
+void omap2_sms_write_rot_size(u32 val, unsigned ctx);
+void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
 #ifdef CONFIG_ARCH_OMAP2
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index e249186d26e2..f5a4a92393ef 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -20,26 +20,22 @@
 #define OMAP_UART1_BASE         0xfffb0000
 #define OMAP_UART2_BASE         0xfffb0800
 #define OMAP_UART3_BASE         0xfffb9800
-#define OMAP_MAX_NR_PORTS       3
 #elif defined(CONFIG_ARCH_OMAP2)
 /* OMAP2 serial ports */
 #define OMAP_UART1_BASE         0x4806a000
 #define OMAP_UART2_BASE         0x4806c000
 #define OMAP_UART3_BASE         0x4806e000
-#define OMAP_MAX_NR_PORTS       3
 #elif defined(CONFIG_ARCH_OMAP3)
 /* OMAP3 serial ports */
 #define OMAP_UART1_BASE         0x4806a000
 #define OMAP_UART2_BASE         0x4806c000
 #define OMAP_UART3_BASE         0x49020000
-#define OMAP_MAX_NR_PORTS       3
 #elif defined(CONFIG_ARCH_OMAP4)
 /* OMAP4 serial ports */
 #define OMAP_UART1_BASE         0x4806a000
 #define OMAP_UART2_BASE         0x4806c000
 #define OMAP_UART3_BASE         0x48020000
 #define OMAP_UART4_BASE         0x4806e000
-#define OMAP_MAX_NR_PORTS       4
 #endif
 #define OMAP1510_BASE_BAUD      (12000000/16)
@@ -57,6 +53,7 @@
 #ifndef __ASSEMBLER__
 extern void __init omap_serial_early_init(void);
 extern void omap_serial_init(void);
+extern void omap_serial_init_port(int port);
 extern int omap_uart_can_sleep(void);
 extern void omap_uart_check_wakeup(void);
 extern void omap_uart_prepare_suspend(void);
diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index dcaa8fde7063..8983d54c4fd2 100644
--- a/arch/arm/plat-omap/include/mach/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -28,6 +28,8 @@
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
 /*
 * We use Soft IRQ1 as the IPI
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 8974e3fc2691..16a1b458d53c 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -27,6 +27,7 @@ extern u32 omap3_configure_core_dpll(
                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+extern void omap3_sram_restore_context(void);
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -68,4 +69,10 @@ extern u32 omap3_sram_configure_core_dpll(
                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
+#ifdef CONFIG_PM
+extern void omap_push_sram_idle(void);
+#else
+static inline void omap_push_sram_idle(void) {}
+#endif /* CONFIG_PM */
 #endif
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/plat/system.h
index ed8ec7477261..c58a4ef42a45 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/plat/system.h
@@ -9,7 +9,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
-#include <mach/prcm.h>
+#include <plat/prcm.h>
 #ifndef CONFIG_MACH_VOICEBLUE
 #define voiceblue_reset()               do {} while (0)
diff --git a/arch/arm/plat-omap/include/mach/tc.h b/arch/arm/plat-omap/include/plat/tc.h
index d2fcd789bb9a..d2fcd789bb9a 100644
--- a/arch/arm/plat-omap/include/mach/tc.h
+++ b/arch/arm/plat-omap/include/plat/tc.h
diff --git a/arch/arm/plat-omap/include/mach/timer-gp.h b/arch/arm/plat-omap/include/plat/timer-gp.h
index c88d346b59d9..c88d346b59d9 100644
--- a/arch/arm/plat-omap/include/mach/timer-gp.h
+++ b/arch/arm/plat-omap/include/plat/timer-gp.h
diff --git a/arch/arm/plat-omap/include/mach/timex.h b/arch/arm/plat-omap/include/plat/timex.h
index 6d35767bc48f..6d35767bc48f 100644
--- a/arch/arm/plat-omap/include/mach/timex.h
+++ b/arch/arm/plat-omap/include/plat/timex.h
diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 0814c5f210c3..13c305d62127 100644
--- a/arch/arm/plat-omap/include/mach/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -19,12 +19,13 @@
 #include <linux/types.h>
 #include <linux/serial_reg.h>
-#include <mach/serial.h>
+#include <plat/serial.h>
 unsigned int system_rev;
 #define UART_OMAP_MDR1          0x08    /* mode definition register */
 #define OMAP_ID_730             0x355F
+#define OMAP_ID_850             0x362C
 #define ID_MASK                 0x7fff
 #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
 #define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
@@ -43,8 +44,12 @@ static void putc(int c)
        uart = (volatile u8 *)(OMAP_UART3_BASE);
 #elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
        uart = (volatile u8 *)(OMAP_UART2_BASE);
-#else
+#elif defined(CONFIG_OMAP_LL_DEBUG_UART1)
        uart = (volatile u8 *)(OMAP_UART1_BASE);
+#elif defined(CONFIG_OMAP_LL_DEBUG_NONE)
+        return;
+#else
+        return;
 #endif
 #ifdef CONFIG_ARCH_OMAP1
@@ -53,7 +58,7 @@ static void putc(int c)
                /* MMU is not on, so cpu_is_omapXXXX() won't work here */
                unsigned int omap_id = omap_get_id();
-                if (omap_id == OMAP_ID_730)
+                if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
                        shift = 0;
                if (check_port(uart, shift))
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index f337e1761e2c..33a500eb2f93 100644
--- a/arch/arm/plat-omap/include/mach/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -3,7 +3,22 @@
 #ifndef __ASM_ARCH_OMAP_USB_H
 #define __ASM_ARCH_OMAP_USB_H
-#include <mach/board.h>
+#include <plat/board.h>
+#define OMAP3_HS_USB_PORTS      3
+enum ehci_hcd_omap_mode {
+        EHCI_HCD_OMAP_MODE_UNKNOWN,
+        EHCI_HCD_OMAP_MODE_PHY,
+        EHCI_HCD_OMAP_MODE_TLL,
+};
+struct ehci_hcd_omap_platform_data {
+        enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
+        unsigned                        phy_reset:1;
+        /* have to be valid if phy_reset is true and portx is in phy mode */
+        int     reset_gpio_port[OMAP3_HS_USB_PORTS];
+};
 /*-------------------------------------------------------------------------*/
@@ -29,6 +44,8 @@
 extern void usb_musb_init(void);
+extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
 #endif
 void omap_usb_init(struct omap_usb_config *pdata);
diff --git a/arch/arm/plat-omap/include/plat/vram.h b/arch/arm/plat-omap/include/plat/vram.h
new file mode 100644
index 000000000000..edd4987758a6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/vram.h
@@ -0,0 +1,62 @@
+/*
+ * VRAM manager for OMAP
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __OMAP_VRAM_H__
+#define __OMAP_VRAM_H__
+#include <linux/types.h>
+#define OMAP_VRAM_MEMTYPE_SDRAM         0
+#define OMAP_VRAM_MEMTYPE_SRAM          1
+#define OMAP_VRAM_MEMTYPE_MAX           1
+extern int omap_vram_add_region(unsigned long paddr, size_t size);
+extern int omap_vram_free(unsigned long paddr, size_t size);
+extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
+extern int omap_vram_reserve(unsigned long paddr, size_t size);
+extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
+                unsigned long *largest_free_block);
+#ifdef CONFIG_OMAP2_VRAM
+extern void omap_vram_set_sdram_vram(u32 size, u32 start);
+extern void omap_vram_set_sram_vram(u32 size, u32 start);
+extern void omap_vram_reserve_sdram(void);
+extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
+                                            unsigned long sram_vstart,
+                                            unsigned long sram_size,
+                                            unsigned long pstart_avail,
+                                            unsigned long size_avail);
+#else
+static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
+static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
+static inline void omap_vram_reserve_sdram(void) { }
+static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
+                                            unsigned long sram_vstart,
+                                            unsigned long sram_size,
+                                            unsigned long pstart_avail,
+                                            unsigned long size_avail)
+{
+        return 0;
+}
+#endif
+#endif
diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h
new file mode 100644
index 000000000000..d8a03ced3b10
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/vrfb.h
@@ -0,0 +1,50 @@
+/*
+ * VRFB Rotation Engine
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __OMAP_VRFB_H__
+#define __OMAP_VRFB_H__
+#define OMAP_VRFB_LINE_LEN 2048
+struct vrfb {
+        u8 context;
+        void __iomem *vaddr[4];
+        unsigned long paddr[4];
+        u16 xres;
+        u16 yres;
+        u16 xoffset;
+        u16 yoffset;
+        u8 bytespp;
+        bool yuv_mode;
+};
+extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
+extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
+extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
+                u8 bytespp);
+extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
+extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
+extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+                u16 width, u16 height,
+                unsigned bytespp, bool yuv_mode);
+extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
+extern void omap_vrfb_restore_context(void);
+#endif /* __VRFB_H */