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-rw-r--r--arch/arm/plat-omap/include/plat/board.h4
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev_omap.h1
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h28
-rw-r--r--arch/arm/plat-omap/include/plat/common.h8
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h44
-rw-r--r--arch/arm/plat-omap/include/plat/display.h26
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h11
-rw-r--r--arch/arm/plat-omap/include/plat/fpga.h92
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h18
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h1
-rw-r--r--arch/arm/plat-omap/include/plat/io.h12
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h16
-rw-r--r--arch/arm/plat-omap/include/plat/iovmm.h2
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h11
-rw-r--r--arch/arm/plat-omap/include/plat/l3_2xxx.h20
-rw-r--r--arch/arm/plat-omap/include/plat/l3_3xxx.h20
-rw-r--r--arch/arm/plat-omap/include/plat/l4_2xxx.h24
-rw-r--r--arch/arm/plat-omap/include/plat/l4_3xxx.h10
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h64
-rw-r--r--arch/arm/plat-omap/include/plat/mcspi.h11
-rw-r--r--arch/arm/plat-omap/include/plat/memory.h4
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h29
-rw-r--r--arch/arm/plat-omap/include/plat/multi.h4
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h11
-rw-r--r--arch/arm/plat-omap/include/plat/omap34xx.h16
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h25
-rw-r--r--arch/arm/plat-omap/include/plat/onenand.h10
-rw-r--r--arch/arm/plat-omap/include/plat/prcm.h1
-rw-r--r--arch/arm/plat-omap/include/plat/sdrc.h8
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h11
-rw-r--r--arch/arm/plat-omap/include/plat/smartreflex.h245
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h14
-rw-r--r--arch/arm/plat-omap/include/plat/system.h38
-rw-r--r--arch/arm/plat-omap/include/plat/ti816x.h27
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h7
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h59
-rw-r--r--arch/arm/plat-omap/include/plat/voltage.h155
37 files changed, 478 insertions, 609 deletions
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 3cf4fa25ab3d..97126dfd2888 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -151,14 +151,14 @@ struct omap_board_config_kernel {
151 const void *data; 151 const void *data;
152}; 152};
153 153
154extern const void *__omap_get_config(u16 tag, size_t len, int nr); 154extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
155 155
156#define omap_get_config(tag, type) \ 156#define omap_get_config(tag, type) \
157 ((const type *) __omap_get_config((tag), sizeof(type), 0)) 157 ((const type *) __omap_get_config((tag), sizeof(type), 0))
158#define omap_get_nr_config(tag, type, nr) \ 158#define omap_get_nr_config(tag, type, nr) \
159 ((const type *) __omap_get_config((tag), sizeof(type), (nr))) 159 ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
160 160
161extern const void *omap_get_var_config(u16 tag, size_t *len); 161extern const void *__init omap_get_var_config(u16 tag, size_t *len);
162 162
163extern struct omap_board_config_kernel *omap_board_config; 163extern struct omap_board_config_kernel *omap_board_config;
164extern int omap_board_config_size; 164extern int omap_board_config_size;
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 256ab3f1ec8f..f1899a3e4174 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -38,6 +38,7 @@ struct omap_clk {
38#define CK_3517 (1 << 9) 38#define CK_3517 (1 << 9)
39#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ 39#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
40#define CK_443X (1 << 11) 40#define CK_443X (1 << 11)
41#define CK_TI816X (1 << 12)
41 42
42 43
43#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) 44#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0adab19ea..006e599c6613 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
25 * @disable: fn ptr that enables the current clock in hardware 25 * @disable: fn ptr that enables the current clock in hardware
26 * @find_idlest: function returning the IDLEST register for the clock's IP blk 26 * @find_idlest: function returning the IDLEST register for the clock's IP blk
27 * @find_companion: function returning the "companion" clk reg for the clock 27 * @find_companion: function returning the "companion" clk reg for the clock
28 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
29 * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
28 * 30 *
29 * A "companion" clk is an accompanying clock to the one being queried 31 * A "companion" clk is an accompanying clock to the one being queried
30 * that must be enabled for the IP module connected to the clock to 32 * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
42 u8 *, u8 *); 44 u8 *, u8 *);
43 void (*find_companion)(struct clk *, void __iomem **, 45 void (*find_companion)(struct clk *, void __iomem **,
44 u8 *); 46 u8 *);
47 void (*allow_idle)(struct clk *);
48 void (*deny_idle)(struct clk *);
45}; 49};
46 50
47#ifdef CONFIG_ARCH_OMAP2PLUS 51#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -53,6 +57,7 @@ struct clkops {
53#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ 57#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
54#define RATE_IN_36XX (1 << 4) 58#define RATE_IN_36XX (1 << 4)
55#define RATE_IN_4430 (1 << 5) 59#define RATE_IN_4430 (1 << 5)
60#define RATE_IN_TI816X (1 << 6)
56 61
57#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 62#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
58#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) 63#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -104,7 +109,6 @@ struct clksel {
104 * @clk_ref: struct clk pointer to the clock's reference clock input 109 * @clk_ref: struct clk pointer to the clock's reference clock input
105 * @control_reg: register containing the DPLL mode bitfield 110 * @control_reg: register containing the DPLL mode bitfield
106 * @enable_mask: mask of the DPLL mode bitfield in @control_reg 111 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
107 * @rate_tolerance: maximum variance allowed from target rate (in Hz)
108 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() 112 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
109 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() 113 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
110 * @max_multiplier: maximum valid non-bypass multiplier value (actual) 114 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
@@ -130,12 +134,9 @@ struct clksel {
130 * XXX Some DPLLs have multiple bypass inputs, so it's not technically 134 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
131 * correct to only have one @clk_bypass pointer. 135 * correct to only have one @clk_bypass pointer.
132 * 136 *
133 * XXX @rate_tolerance should probably be deprecated - currently there
134 * don't seem to be any usecases for DPLL rounding that is not exact.
135 *
136 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, 137 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
137 * @last_rounded_n) should be separated from the runtime-fixed fields 138 * @last_rounded_n) should be separated from the runtime-fixed fields
138 * and placed into a differenct structure, so that the runtime-fixed data 139 * and placed into a different structure, so that the runtime-fixed data
139 * can be placed into read-only space. 140 * can be placed into read-only space.
140 */ 141 */
141struct dpll_data { 142struct dpll_data {
@@ -146,7 +147,6 @@ struct dpll_data {
146 struct clk *clk_ref; 147 struct clk *clk_ref;
147 void __iomem *control_reg; 148 void __iomem *control_reg;
148 u32 enable_mask; 149 u32 enable_mask;
149 unsigned int rate_tolerance;
150 unsigned long last_rounded_rate; 150 unsigned long last_rounded_rate;
151 u16 last_rounded_m; 151 u16 last_rounded_m;
152 u16 max_multiplier; 152 u16 max_multiplier;
@@ -171,12 +171,24 @@ struct dpll_data {
171 171
172#endif 172#endif
173 173
174/* struct clk.flags possibilities */ 174/*
175 * struct clk.flags possibilities
176 *
177 * XXX document the rest of the clock flags here
178 *
179 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
180 * bits share the same register. This flag allows the
181 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
182 * should be used. This is a temporary solution - a better approach
183 * would be to associate clock type-specific data with the clock,
184 * similar to the struct dpll_data approach.
185 */
175#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ 186#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
176#define CLOCK_IDLE_CONTROL (1 << 1) 187#define CLOCK_IDLE_CONTROL (1 << 1)
177#define CLOCK_NO_IDLE_PARENT (1 << 2) 188#define CLOCK_NO_IDLE_PARENT (1 << 2)
178#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ 189#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
179#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 190#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
191#define CLOCK_CLKOUTX2 (1 << 5)
180 192
181/** 193/**
182 * struct clk - OMAP struct clk 194 * struct clk - OMAP struct clk
@@ -292,6 +304,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
292extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); 304extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
293#endif 305#endif
294extern struct clk *omap_clk_get_by_name(const char *name); 306extern struct clk *omap_clk_get_by_name(const char *name);
307extern int omap_clk_enable_autoidle_all(void);
308extern int omap_clk_disable_autoidle_all(void);
295 309
296extern const struct clkops clkops_null; 310extern const struct clkops clkops_null;
297 311
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 6b8088ec74af..5288130be96e 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -35,6 +35,9 @@ struct sys_timer;
35 35
36extern void omap_map_common_io(void); 36extern void omap_map_common_io(void);
37extern struct sys_timer omap_timer; 37extern struct sys_timer omap_timer;
38extern bool omap_32k_timer_init(void);
39extern int __init omap_init_clocksource_32k(void);
40extern unsigned long long notrace omap_32k_sched_clock(void);
38 41
39extern void omap_reserve(void); 42extern void omap_reserve(void);
40 43
@@ -53,16 +56,13 @@ struct omap_globals {
53 unsigned long prm; /* Power and Reset Management */ 56 unsigned long prm; /* Power and Reset Management */
54 unsigned long cm; /* Clock Management */ 57 unsigned long cm; /* Clock Management */
55 unsigned long cm2; 58 unsigned long cm2;
56 unsigned long uart1_phys;
57 unsigned long uart2_phys;
58 unsigned long uart3_phys;
59 unsigned long uart4_phys;
60}; 59};
61 60
62void omap2_set_globals_242x(void); 61void omap2_set_globals_242x(void);
63void omap2_set_globals_243x(void); 62void omap2_set_globals_243x(void);
64void omap2_set_globals_3xxx(void); 63void omap2_set_globals_3xxx(void);
65void omap2_set_globals_443x(void); 64void omap2_set_globals_443x(void);
65void omap2_set_globals_ti816x(void);
66 66
67/* These get called from omap2_set_globals_xxxx(), do not call these */ 67/* These get called from omap2_set_globals_xxxx(), do not call these */
68void omap2_set_globals_tap(struct omap_globals *); 68void omap2_set_globals_tap(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 3fd8b4055727..8198bb6cdb5e 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -5,7 +5,7 @@
5 * 5 *
6 * Copyright (C) 2004, 2008 Nokia Corporation 6 * Copyright (C) 2004, 2008 Nokia Corporation
7 * 7 *
8 * Copyright (C) 2009 Texas Instruments. 8 * Copyright (C) 2009-11 Texas Instruments.
9 * 9 *
10 * Written by Tony Lindgren <tony.lindgren@nokia.com> 10 * Written by Tony Lindgren <tony.lindgren@nokia.com>
11 * 11 *
@@ -105,6 +105,12 @@ static inline int is_omap ##subclass (void) \
105 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ 105 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
106} 106}
107 107
108#define IS_TI_SUBCLASS(subclass, id) \
109static inline int is_ti ##subclass (void) \
110{ \
111 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
112}
113
108IS_OMAP_CLASS(7xx, 0x07) 114IS_OMAP_CLASS(7xx, 0x07)
109IS_OMAP_CLASS(15xx, 0x15) 115IS_OMAP_CLASS(15xx, 0x15)
110IS_OMAP_CLASS(16xx, 0x16) 116IS_OMAP_CLASS(16xx, 0x16)
@@ -118,6 +124,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
118IS_OMAP_SUBCLASS(363x, 0x363) 124IS_OMAP_SUBCLASS(363x, 0x363)
119IS_OMAP_SUBCLASS(443x, 0x443) 125IS_OMAP_SUBCLASS(443x, 0x443)
120 126
127IS_TI_SUBCLASS(816x, 0x816)
128
121#define cpu_is_omap7xx() 0 129#define cpu_is_omap7xx() 0
122#define cpu_is_omap15xx() 0 130#define cpu_is_omap15xx() 0
123#define cpu_is_omap16xx() 0 131#define cpu_is_omap16xx() 0
@@ -126,6 +134,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
126#define cpu_is_omap243x() 0 134#define cpu_is_omap243x() 0
127#define cpu_is_omap34xx() 0 135#define cpu_is_omap34xx() 0
128#define cpu_is_omap343x() 0 136#define cpu_is_omap343x() 0
137#define cpu_is_ti816x() 0
129#define cpu_is_omap44xx() 0 138#define cpu_is_omap44xx() 0
130#define cpu_is_omap443x() 0 139#define cpu_is_omap443x() 0
131 140
@@ -170,11 +179,11 @@ IS_OMAP_SUBCLASS(443x, 0x443)
170# undef cpu_is_omap24xx 179# undef cpu_is_omap24xx
171# define cpu_is_omap24xx() is_omap24xx() 180# define cpu_is_omap24xx() is_omap24xx()
172# endif 181# endif
173# if defined (CONFIG_ARCH_OMAP2420) 182# if defined (CONFIG_SOC_OMAP2420)
174# undef cpu_is_omap242x 183# undef cpu_is_omap242x
175# define cpu_is_omap242x() is_omap242x() 184# define cpu_is_omap242x() is_omap242x()
176# endif 185# endif
177# if defined (CONFIG_ARCH_OMAP2430) 186# if defined (CONFIG_SOC_OMAP2430)
178# undef cpu_is_omap243x 187# undef cpu_is_omap243x
179# define cpu_is_omap243x() is_omap243x() 188# define cpu_is_omap243x() is_omap243x()
180# endif 189# endif
@@ -189,11 +198,11 @@ IS_OMAP_SUBCLASS(443x, 0x443)
189# undef cpu_is_omap24xx 198# undef cpu_is_omap24xx
190# define cpu_is_omap24xx() 1 199# define cpu_is_omap24xx() 1
191# endif 200# endif
192# if defined(CONFIG_ARCH_OMAP2420) 201# if defined(CONFIG_SOC_OMAP2420)
193# undef cpu_is_omap242x 202# undef cpu_is_omap242x
194# define cpu_is_omap242x() 1 203# define cpu_is_omap242x() 1
195# endif 204# endif
196# if defined(CONFIG_ARCH_OMAP2430) 205# if defined(CONFIG_SOC_OMAP2430)
197# undef cpu_is_omap243x 206# undef cpu_is_omap243x
198# define cpu_is_omap243x() 1 207# define cpu_is_omap243x() 1
199# endif 208# endif
@@ -201,7 +210,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
201# undef cpu_is_omap34xx 210# undef cpu_is_omap34xx
202# define cpu_is_omap34xx() 1 211# define cpu_is_omap34xx() 1
203# endif 212# endif
204# if defined(CONFIG_ARCH_OMAP3430) 213# if defined(CONFIG_SOC_OMAP3430)
205# undef cpu_is_omap343x 214# undef cpu_is_omap343x
206# define cpu_is_omap343x() 1 215# define cpu_is_omap343x() 1
207# endif 216# endif
@@ -330,6 +339,7 @@ IS_OMAP_TYPE(3517, 0x3517)
330# undef cpu_is_omap3530 339# undef cpu_is_omap3530
331# undef cpu_is_omap3505 340# undef cpu_is_omap3505
332# undef cpu_is_omap3517 341# undef cpu_is_omap3517
342# undef cpu_is_ti816x
333# define cpu_is_omap3430() is_omap3430() 343# define cpu_is_omap3430() is_omap3430()
334# define cpu_is_omap3503() (cpu_is_omap3430() && \ 344# define cpu_is_omap3503() (cpu_is_omap3430() && \
335 (!omap3_has_iva()) && \ 345 (!omap3_has_iva()) && \
@@ -345,6 +355,7 @@ IS_OMAP_TYPE(3517, 0x3517)
345# define cpu_is_omap3517() is_omap3517() 355# define cpu_is_omap3517() is_omap3517()
346# undef cpu_is_omap3630 356# undef cpu_is_omap3630
347# define cpu_is_omap3630() is_omap363x() 357# define cpu_is_omap3630() is_omap363x()
358# define cpu_is_ti816x() is_ti816x()
348#endif 359#endif
349 360
350# if defined(CONFIG_ARCH_OMAP4) 361# if defined(CONFIG_ARCH_OMAP4)
@@ -389,9 +400,15 @@ IS_OMAP_TYPE(3517, 0x3517)
389#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8)) 400#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
390#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) 401#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
391 402
403#define TI816X_CLASS 0x81600034
404#define TI8168_REV_ES1_0 TI816X_CLASS
405#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
406
392#define OMAP443X_CLASS 0x44300044 407#define OMAP443X_CLASS 0x44300044
393#define OMAP4430_REV_ES1_0 OMAP443X_CLASS 408#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
394#define OMAP4430_REV_ES2_0 0x44301044 409#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
410#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
411#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
395 412
396/* 413/*
397 * omap_chip bits 414 * omap_chip bits
@@ -419,11 +436,16 @@ IS_OMAP_TYPE(3517, 0x3517)
419#define CHIP_IS_OMAP3630ES1_1 (1 << 9) 436#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
420#define CHIP_IS_OMAP3630ES1_2 (1 << 10) 437#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
421#define CHIP_IS_OMAP4430ES2 (1 << 11) 438#define CHIP_IS_OMAP4430ES2 (1 << 11)
439#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
440#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
441#define CHIP_IS_TI816X (1 << 14)
422 442
423#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 443#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
424 444
425#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ 445#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
426 CHIP_IS_OMAP4430ES2) 446 CHIP_IS_OMAP4430ES2 | \
447 CHIP_IS_OMAP4430ES2_1 | \
448 CHIP_IS_OMAP4430ES2_2)
427 449
428/* 450/*
429 * "GE" here represents "greater than or equal to" in terms of ES 451 * "GE" here represents "greater than or equal to" in terms of ES
@@ -455,6 +477,7 @@ extern u32 omap3_features;
455#define OMAP3_HAS_ISP BIT(4) 477#define OMAP3_HAS_ISP BIT(4)
456#define OMAP3_HAS_192MHZ_CLK BIT(5) 478#define OMAP3_HAS_192MHZ_CLK BIT(5)
457#define OMAP3_HAS_IO_WAKEUP BIT(6) 479#define OMAP3_HAS_IO_WAKEUP BIT(6)
480#define OMAP3_HAS_SDRC BIT(7)
458 481
459#define OMAP3_HAS_FEATURE(feat,flag) \ 482#define OMAP3_HAS_FEATURE(feat,flag) \
460static inline unsigned int omap3_has_ ##feat(void) \ 483static inline unsigned int omap3_has_ ##feat(void) \
@@ -469,5 +492,6 @@ OMAP3_HAS_FEATURE(neon, NEON)
469OMAP3_HAS_FEATURE(isp, ISP) 492OMAP3_HAS_FEATURE(isp, ISP)
470OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) 493OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
471OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) 494OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
495OMAP3_HAS_FEATURE(sdrc, SDRC)
472 496
473#endif 497#endif
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index 537f4e449f50..5e04ddc18fa8 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -23,6 +23,7 @@
23#include <linux/list.h> 23#include <linux/list.h>
24#include <linux/kobject.h> 24#include <linux/kobject.h>
25#include <linux/device.h> 25#include <linux/device.h>
26#include <linux/platform_device.h>
26#include <asm/atomic.h> 27#include <asm/atomic.h>
27 28
28#define DISPC_IRQ_FRAMEDONE (1 << 0) 29#define DISPC_IRQ_FRAMEDONE (1 << 0)
@@ -57,6 +58,7 @@ enum omap_display_type {
57 OMAP_DISPLAY_TYPE_SDI = 1 << 2, 58 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
58 OMAP_DISPLAY_TYPE_DSI = 1 << 3, 59 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
59 OMAP_DISPLAY_TYPE_VENC = 1 << 4, 60 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
61 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
60}; 62};
61 63
62enum omap_plane { 64enum omap_plane {
@@ -226,6 +228,23 @@ struct omap_dss_board_info {
226 struct omap_dss_device *default_device; 228 struct omap_dss_device *default_device;
227}; 229};
228 230
231#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
232/* Init with the board info */
233extern int omap_display_init(struct omap_dss_board_info *board_data);
234#else
235static inline int omap_display_init(struct omap_dss_board_info *board_data)
236{
237 return 0;
238}
239#endif
240
241struct omap_display_platform_data {
242 struct omap_dss_board_info *board_data;
243 /* TODO: Additional members to be added when PM is considered */
244
245 bool (*opt_clock_available)(const char *clk_role);
246};
247
229struct omap_video_timings { 248struct omap_video_timings {
230 /* Unit: pixels */ 249 /* Unit: pixels */
231 u16 x_res; 250 u16 x_res;
@@ -385,8 +404,8 @@ struct omap_dss_device {
385 struct { 404 struct {
386 u16 regn; 405 u16 regn;
387 u16 regm; 406 u16 regm;
388 u16 regm3; 407 u16 regm_dispc;
389 u16 regm4; 408 u16 regm_dsi;
390 409
391 u16 lp_clk_div; 410 u16 lp_clk_div;
392 411
@@ -544,6 +563,9 @@ int omap_dsi_update(struct omap_dss_device *dssdev,
544 int channel, 563 int channel,
545 u16 x, u16 y, u16 w, u16 h, 564 u16 x, u16 y, u16 w, u16 h,
546 void (*callback)(int, void *), void *data); 565 void (*callback)(int, void *), void *data);
566int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
567int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
568void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
547 569
548int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); 570int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
549void omapdss_dsi_display_disable(struct omap_dss_device *dssdev); 571void omapdss_dsi_display_disable(struct omap_dss_device *dssdev);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index dfa3aff9761b..d6c70d2f4030 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -3,6 +3,12 @@
3 * 3 *
4 * OMAP Dual-Mode Timers 4 * OMAP Dual-Mode Timers
5 * 5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
8 * Thara Gopinath <thara@ti.com>
9 *
10 * Platform device conversion and hwmod support.
11 *
6 * Copyright (C) 2005 Nokia Corporation 12 * Copyright (C) 2005 Nokia Corporation
7 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> 13 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
8 * PWM and clock framwork support by Timo Teras. 14 * PWM and clock framwork support by Timo Teras.
@@ -44,6 +50,11 @@
44#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 50#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
45#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 51#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
46 52
53/*
54 * IP revision identifier so that Highlander IP
55 * in OMAP4 can be distinguished.
56 */
57#define OMAP_TIMER_IP_VERSION_1 0x1
47struct omap_dm_timer; 58struct omap_dm_timer;
48extern struct omap_dm_timer *gptimer_wakeup; 59extern struct omap_dm_timer *gptimer_wakeup;
49extern struct sys_timer omap_timer; 60extern struct sys_timer omap_timer;
diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
index ae39bcb3f5ba..bd3c6324ae1f 100644
--- a/arch/arm/plat-omap/include/plat/fpga.h
+++ b/arch/arm/plat-omap/include/plat/fpga.h
@@ -30,18 +30,18 @@ extern void omap1510_fpga_init_irq(void);
30 * --------------------------------------------------------------------------- 30 * ---------------------------------------------------------------------------
31 */ 31 */
32/* maps in the FPGA registers and the ETHR registers */ 32/* maps in the FPGA registers and the ETHR registers */
33#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */ 33#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
34#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ 34#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
35#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ 35#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
36 36
37#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) 37#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
38#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ 38#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
39#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ 39#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
40#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ 40#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
41#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ 41#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
42#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ 42#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
43#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ 43#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
44#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ 44#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
45 45
46/* NOTE: most boards don't have a static mapping for the FPGA ... */ 46/* NOTE: most boards don't have a static mapping for the FPGA ... */
47struct h2p2_dbg_fpga { 47struct h2p2_dbg_fpga {
@@ -81,55 +81,55 @@ struct h2p2_dbg_fpga {
81 * OMAP-1510 FPGA 81 * OMAP-1510 FPGA
82 * --------------------------------------------------------------------------- 82 * ---------------------------------------------------------------------------
83 */ 83 */
84#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */ 84#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */
85#define OMAP1510_FPGA_SIZE SZ_4K 85#define OMAP1510_FPGA_SIZE SZ_4K
86#define OMAP1510_FPGA_START 0x08000000 /* PA */ 86#define OMAP1510_FPGA_START 0x08000000 /* PA */
87 87
88/* Revision */ 88/* Revision */
89#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) 89#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
90#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1) 90#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
91 91
92#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2) 92#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2)
93#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3) 93#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3)
94#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4) 94#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4)
95#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5) 95#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5)
96 96
97/* Interrupt status */ 97/* Interrupt status */
98#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6) 98#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6)
99#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7) 99#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7)
100 100
101/* Interrupt mask */ 101/* Interrupt mask */
102#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8) 102#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8)
103#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9) 103#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9)
104 104
105/* Reset registers */ 105/* Reset registers */
106#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa) 106#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa)
107#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb) 107#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb)
108 108
109#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc) 109#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc)
110#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe) 110#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe)
111#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf) 111#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf)
112#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14) 112#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14)
113#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15) 113#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15)
114#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16) 114#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16)
115#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18) 115#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18)
116#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100) 116#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100)
117#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101) 117#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101)
118#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102) 118#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102)
119 119
120#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204) 120#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204)
121 121
122#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205) 122#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205)
123#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206) 123#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206)
124#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207) 124#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207)
125#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208) 125#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208)
126#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209) 126#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209)
127#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a) 127#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a)
128#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b) 128#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b)
129#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c) 129#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c)
130#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d) 130#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d)
131#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e) 131#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e)
132#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210) 132#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210)
133 133
134#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) 134#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
135 135
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 85ded598853e..12b316165037 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -41,6 +41,8 @@
41#define GPMC_NAND_ADDRESS 0x0000000b 41#define GPMC_NAND_ADDRESS 0x0000000b
42#define GPMC_NAND_DATA 0x0000000c 42#define GPMC_NAND_DATA 0x0000000c
43 43
44#define GPMC_ENABLE_IRQ 0x0000000d
45
44/* ECC commands */ 46/* ECC commands */
45#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ 47#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
46#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ 48#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
@@ -78,6 +80,19 @@
78#define WR_RD_PIN_MONITORING 0x00600000 80#define WR_RD_PIN_MONITORING 0x00600000
79#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) 81#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
80#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) 82#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
83#define GPMC_IRQ_FIFOEVENTENABLE 0x01
84#define GPMC_IRQ_COUNT_EVENT 0x02
85
86#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
87#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
88
89enum omap_ecc {
90 /* 1-bit ecc: stored at end of spare area */
91 OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
92 OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
93 /* 1-bit ecc: stored at begining of spare area as romcode */
94 OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
95};
81 96
82/* 97/*
83 * Note that all values in this struct are in nanoseconds except sync_clk 98 * Note that all values in this struct are in nanoseconds except sync_clk
@@ -130,12 +145,11 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
130extern void gpmc_cs_free(int cs); 145extern void gpmc_cs_free(int cs);
131extern int gpmc_cs_set_reserved(int cs, int reserved); 146extern int gpmc_cs_set_reserved(int cs, int reserved);
132extern int gpmc_cs_reserved(int cs); 147extern int gpmc_cs_reserved(int cs);
133extern int gpmc_prefetch_enable(int cs, int dma_mode, 148extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
134 unsigned int u32_count, int is_write); 149 unsigned int u32_count, int is_write);
135extern int gpmc_prefetch_reset(int cs); 150extern int gpmc_prefetch_reset(int cs);
136extern void omap3_gpmc_save_context(void); 151extern void omap3_gpmc_save_context(void);
137extern void omap3_gpmc_restore_context(void); 152extern void omap3_gpmc_restore_context(void);
138extern void gpmc_init(void);
139extern int gpmc_read_status(int cmd); 153extern int gpmc_read_status(int cmd);
140extern int gpmc_cs_configure(int cs, int cmd, int wval); 154extern int gpmc_cs_configure(int cs, int cmd, int wval);
141extern int gpmc_nand_read(int cs, int cmd); 155extern int gpmc_nand_read(int cs, int cmd);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index d5b26adfb890..e87efe1499b8 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,5 +286,6 @@
286#include <plat/omap24xx.h> 286#include <plat/omap24xx.h>
287#include <plat/omap34xx.h> 287#include <plat/omap34xx.h>
288#include <plat/omap44xx.h> 288#include <plat/omap44xx.h>
289#include <plat/ti816x.h>
289 290
290#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ 291#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index ef4106c13183..d72ec85c97e6 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -259,7 +259,7 @@ struct omap_sdrc_params;
259extern void omap1_map_common_io(void); 259extern void omap1_map_common_io(void);
260extern void omap1_init_common_hw(void); 260extern void omap1_init_common_hw(void);
261 261
262#ifdef CONFIG_ARCH_OMAP2420 262#ifdef CONFIG_SOC_OMAP2420
263extern void omap242x_map_common_io(void); 263extern void omap242x_map_common_io(void);
264#else 264#else
265static inline void omap242x_map_common_io(void) 265static inline void omap242x_map_common_io(void)
@@ -267,7 +267,7 @@ static inline void omap242x_map_common_io(void)
267} 267}
268#endif 268#endif
269 269
270#ifdef CONFIG_ARCH_OMAP2430 270#ifdef CONFIG_SOC_OMAP2430
271extern void omap243x_map_common_io(void); 271extern void omap243x_map_common_io(void);
272#else 272#else
273static inline void omap243x_map_common_io(void) 273static inline void omap243x_map_common_io(void)
@@ -283,6 +283,14 @@ static inline void omap34xx_map_common_io(void)
283} 283}
284#endif 284#endif
285 285
286#ifdef CONFIG_SOC_OMAPTI816X
287extern void omapti816x_map_common_io(void);
288#else
289static inline void omapti816x_map_common_io(void)
290{
291}
292#endif
293
286#ifdef CONFIG_ARCH_OMAP4 294#ifdef CONFIG_ARCH_OMAP4
287extern void omap44xx_map_common_io(void); 295extern void omap44xx_map_common_io(void);
288#else 296#else
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 69230d685538..174f1b9c8c03 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -31,6 +31,7 @@ struct iommu {
31 struct clk *clk; 31 struct clk *clk;
32 void __iomem *regbase; 32 void __iomem *regbase;
33 struct device *dev; 33 struct device *dev;
34 void *isr_priv;
34 35
35 unsigned int refcount; 36 unsigned int refcount;
36 struct mutex iommu_lock; /* global for this whole object */ 37 struct mutex iommu_lock; /* global for this whole object */
@@ -47,7 +48,7 @@ struct iommu {
47 struct list_head mmap; 48 struct list_head mmap;
48 struct mutex mmap_lock; /* protect mmap */ 49 struct mutex mmap_lock; /* protect mmap */
49 50
50 int (*isr)(struct iommu *obj); 51 int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv);
51 52
52 void *ctx; /* iommu context: registres saved area */ 53 void *ctx; /* iommu context: registres saved area */
53 u32 da_start; 54 u32 da_start;
@@ -109,6 +110,13 @@ struct iommu_platform_data {
109 u32 da_end; 110 u32 da_end;
110}; 111};
111 112
113/* IOMMU errors */
114#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
115#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
116#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
117#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
118#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
119
112#if defined(CONFIG_ARCH_OMAP1) 120#if defined(CONFIG_ARCH_OMAP1)
113#error "iommu for this processor not implemented yet" 121#error "iommu for this processor not implemented yet"
114#else 122#else
@@ -154,11 +162,17 @@ extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
154extern void flush_iotlb_all(struct iommu *obj); 162extern void flush_iotlb_all(struct iommu *obj);
155 163
156extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); 164extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
165extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd,
166 u32 **ppte);
157extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); 167extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
158 168
159extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); 169extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
160extern struct iommu *iommu_get(const char *name); 170extern struct iommu *iommu_get(const char *name);
161extern void iommu_put(struct iommu *obj); 171extern void iommu_put(struct iommu *obj);
172extern int iommu_set_isr(const char *name,
173 int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
174 void *priv),
175 void *isr_priv);
162 176
163extern void iommu_save_ctx(struct iommu *obj); 177extern void iommu_save_ctx(struct iommu *obj);
164extern void iommu_restore_ctx(struct iommu *obj); 178extern void iommu_restore_ctx(struct iommu *obj);
diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
index bdc7ce5d7a4a..32a2f6c4d39e 100644
--- a/arch/arm/plat-omap/include/plat/iovmm.h
+++ b/arch/arm/plat-omap/include/plat/iovmm.h
@@ -71,8 +71,6 @@ struct iovm_struct {
71#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT)) 71#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
72 72
73#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT)) 73#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
74#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
75#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
76 74
77 75
78extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da); 76extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 2910de921c52..d77928370463 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -315,9 +315,12 @@
315#define INT_34XX_SSM_ABORT_IRQ 6 315#define INT_34XX_SSM_ABORT_IRQ 6
316#define INT_34XX_SYS_NIRQ 7 316#define INT_34XX_SYS_NIRQ 7
317#define INT_34XX_D2D_FW_IRQ 8 317#define INT_34XX_D2D_FW_IRQ 8
318#define INT_34XX_L3_DBG_IRQ 9
319#define INT_34XX_L3_APP_IRQ 10
318#define INT_34XX_PRCM_MPU_IRQ 11 320#define INT_34XX_PRCM_MPU_IRQ 11
319#define INT_34XX_MCBSP1_IRQ 16 321#define INT_34XX_MCBSP1_IRQ 16
320#define INT_34XX_MCBSP2_IRQ 17 322#define INT_34XX_MCBSP2_IRQ 17
323#define INT_34XX_GPMC_IRQ 20
321#define INT_34XX_MCBSP3_IRQ 22 324#define INT_34XX_MCBSP3_IRQ 22
322#define INT_34XX_MCBSP4_IRQ 23 325#define INT_34XX_MCBSP4_IRQ 23
323#define INT_34XX_CAM_IRQ 24 326#define INT_34XX_CAM_IRQ 24
@@ -411,7 +414,13 @@
411#define TWL_IRQ_END TWL6030_IRQ_END 414#define TWL_IRQ_END TWL6030_IRQ_END
412#endif 415#endif
413 416
414#define NR_IRQS TWL_IRQ_END 417/* GPMC related */
418#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
419#define OMAP_GPMC_NR_IRQS 7
420#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
421
422
423#define NR_IRQS OMAP_GPMC_IRQ_END
415 424
416#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 425#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
417 426
diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/plat-omap/include/plat/l3_2xxx.h
new file mode 100644
index 000000000000..b8b5641379b0
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l3_2xxx.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Sumit Semwal
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
15
16/* L3 CONNIDs */
17/* Display Sub system (DSS) */
18#define OMAP2_L3_CORE_FW_CONNID_DSS 8
19
20#endif
diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/plat-omap/include/plat/l3_3xxx.h
new file mode 100644
index 000000000000..cde1938c5f82
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l3_3xxx.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Sumit Semwal
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
15
16/* L3 Initiator IDs */
17/* Display Sub system (DSS) */
18#define OMAP3_L3_CORE_FW_INIT_ID_DSS 29
19
20#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/plat-omap/include/plat/l4_2xxx.h
new file mode 100644
index 000000000000..3f39cf8a35c6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l4_2xxx.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Sumit Semwal
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
15
16/* L4 CORE */
17/* Display Sub system (DSS) */
18#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28
19#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29
20#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30
21#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31
22#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32
23
24#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
index 5e1949375422..881a858b1ffc 100644
--- a/arch/arm/plat-omap/include/plat/l4_3xxx.h
+++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h
@@ -21,4 +21,14 @@
21#define OMAP3_L4_CORE_FW_I2C3_REGION 73 21#define OMAP3_L4_CORE_FW_I2C3_REGION 73
22#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74 22#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74
23 23
24/* Display Sub system (DSS) */
25#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP 2
26
27#define OMAP3_L4_CORE_FW_DSS_DSI_REGION 104
28#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION 3
29#define OMAP3_L4_CORE_FW_DSS_CORE_REGION 4
30#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION 4
31#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION 5
32#define OMAP3_L4_CORE_FW_DSS_VENC_REGION 6
33#define OMAP3_L4_CORE_FW_DSS_TA_REGION 7
24#endif 34#endif
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index b87d83ccd545..f8f690ab2997 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -37,6 +37,10 @@ static struct platform_device omap_mcbsp##port_nr = { \
37 .id = OMAP_MCBSP##port_nr, \ 37 .id = OMAP_MCBSP##port_nr, \
38} 38}
39 39
40#define MCBSP_CONFIG_TYPE2 0x2
41#define MCBSP_CONFIG_TYPE3 0x3
42#define MCBSP_CONFIG_TYPE4 0x4
43
40#define OMAP7XX_MCBSP1_BASE 0xfffb1000 44#define OMAP7XX_MCBSP1_BASE 0xfffb1000
41#define OMAP7XX_MCBSP2_BASE 0xfffb1800 45#define OMAP7XX_MCBSP2_BASE 0xfffb1800
42 46
@@ -48,32 +52,14 @@ static struct platform_device omap_mcbsp##port_nr = { \
48#define OMAP1610_MCBSP2_BASE 0xfffb1000 52#define OMAP1610_MCBSP2_BASE 0xfffb1000
49#define OMAP1610_MCBSP3_BASE 0xe1017000 53#define OMAP1610_MCBSP3_BASE 0xe1017000
50 54
51#define OMAP24XX_MCBSP1_BASE 0x48074000 55#ifdef CONFIG_ARCH_OMAP1
52#define OMAP24XX_MCBSP2_BASE 0x48076000
53#define OMAP2430_MCBSP3_BASE 0x4808c000
54#define OMAP2430_MCBSP4_BASE 0x4808e000
55#define OMAP2430_MCBSP5_BASE 0x48096000
56
57#define OMAP34XX_MCBSP1_BASE 0x48074000
58#define OMAP34XX_MCBSP2_BASE 0x49022000
59#define OMAP34XX_MCBSP2_ST_BASE 0x49028000
60#define OMAP34XX_MCBSP3_BASE 0x49024000
61#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
62#define OMAP34XX_MCBSP3_BASE 0x49024000
63#define OMAP34XX_MCBSP4_BASE 0x49026000
64#define OMAP34XX_MCBSP5_BASE 0x48096000
65
66#define OMAP44XX_MCBSP1_BASE 0x49022000
67#define OMAP44XX_MCBSP2_BASE 0x49024000
68#define OMAP44XX_MCBSP3_BASE 0x49026000
69#define OMAP44XX_MCBSP4_BASE 0x48096000
70
71#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
72 56
73#define OMAP_MCBSP_REG_DRR2 0x00 57#define OMAP_MCBSP_REG_DRR2 0x00
74#define OMAP_MCBSP_REG_DRR1 0x02 58#define OMAP_MCBSP_REG_DRR1 0x02
75#define OMAP_MCBSP_REG_DXR2 0x04 59#define OMAP_MCBSP_REG_DXR2 0x04
76#define OMAP_MCBSP_REG_DXR1 0x06 60#define OMAP_MCBSP_REG_DXR1 0x06
61#define OMAP_MCBSP_REG_DRR 0x02
62#define OMAP_MCBSP_REG_DXR 0x06
77#define OMAP_MCBSP_REG_SPCR2 0x08 63#define OMAP_MCBSP_REG_SPCR2 0x08
78#define OMAP_MCBSP_REG_SPCR1 0x0a 64#define OMAP_MCBSP_REG_SPCR1 0x0a
79#define OMAP_MCBSP_REG_RCR2 0x0c 65#define OMAP_MCBSP_REG_RCR2 0x0c
@@ -106,13 +92,6 @@ static struct platform_device omap_mcbsp##port_nr = { \
106#define OMAP_MCBSP_REG_XCCR 0x00 92#define OMAP_MCBSP_REG_XCCR 0x00
107#define OMAP_MCBSP_REG_RCCR 0x00 93#define OMAP_MCBSP_REG_RCCR 0x00
108 94
109#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
110#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
111
112#define AUDIO_MCBSP OMAP_MCBSP1
113#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
114#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
115
116#else 95#else
117 96
118#define OMAP_MCBSP_REG_DRR2 0x00 97#define OMAP_MCBSP_REG_DRR2 0x00
@@ -168,13 +147,6 @@ static struct platform_device omap_mcbsp##port_nr = { \
168#define OMAP_ST_REG_SFIRCR 0x28 147#define OMAP_ST_REG_SFIRCR 0x28
169#define OMAP_ST_REG_SSELCR 0x2C 148#define OMAP_ST_REG_SSELCR 0x2C
170 149
171#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
172#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
173
174#define AUDIO_MCBSP OMAP_MCBSP2
175#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
176#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
177
178#endif 150#endif
179 151
180/************************** McBSP SPCR1 bit definitions ***********************/ 152/************************** McBSP SPCR1 bit definitions ***********************/
@@ -428,8 +400,9 @@ struct omap_mcbsp_platform_data {
428#ifdef CONFIG_ARCH_OMAP3 400#ifdef CONFIG_ARCH_OMAP3
429 /* Sidetone block for McBSP 2 and 3 */ 401 /* Sidetone block for McBSP 2 and 3 */
430 unsigned long phys_base_st; 402 unsigned long phys_base_st;
431 u16 buffer_size;
432#endif 403#endif
404 u16 buffer_size;
405 unsigned int mcbsp_config_type;
433}; 406};
434 407
435struct omap_mcbsp_st_data { 408struct omap_mcbsp_st_data {
@@ -445,6 +418,7 @@ struct omap_mcbsp_st_data {
445struct omap_mcbsp { 418struct omap_mcbsp {
446 struct device *dev; 419 struct device *dev;
447 unsigned long phys_base; 420 unsigned long phys_base;
421 unsigned long phys_dma_base;
448 void __iomem *io_base; 422 void __iomem *io_base;
449 u8 id; 423 u8 id;
450 u8 free; 424 u8 free;
@@ -471,7 +445,6 @@ struct omap_mcbsp {
471 /* Protect the field .free, while checking if the mcbsp is in use */ 445 /* Protect the field .free, while checking if the mcbsp is in use */
472 spinlock_t lock; 446 spinlock_t lock;
473 struct omap_mcbsp_platform_data *pdata; 447 struct omap_mcbsp_platform_data *pdata;
474 struct clk *iclk;
475 struct clk *fclk; 448 struct clk *fclk;
476#ifdef CONFIG_ARCH_OMAP3 449#ifdef CONFIG_ARCH_OMAP3
477 struct omap_mcbsp_st_data *st_data; 450 struct omap_mcbsp_st_data *st_data;
@@ -480,7 +453,17 @@ struct omap_mcbsp {
480 u16 max_rx_thres; 453 u16 max_rx_thres;
481#endif 454#endif
482 void *reg_cache; 455 void *reg_cache;
456 unsigned int mcbsp_config_type;
483}; 457};
458
459/**
460 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
461 * @sidetone: name of the sidetone device
462 */
463struct omap_mcbsp_dev_attr {
464 const char *sidetone;
465};
466
484extern struct omap_mcbsp **mcbsp_ptr; 467extern struct omap_mcbsp **mcbsp_ptr;
485extern int omap_mcbsp_count, omap_mcbsp_cache_size; 468extern int omap_mcbsp_count, omap_mcbsp_cache_size;
486 469
@@ -488,8 +471,8 @@ extern int omap_mcbsp_count, omap_mcbsp_cache_size;
488#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; 471#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
489 472
490int omap_mcbsp_init(void); 473int omap_mcbsp_init(void);
491void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 474void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
492 int size); 475 struct omap_mcbsp_platform_data *config, int size);
493void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 476void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
494#ifdef CONFIG_ARCH_OMAP3 477#ifdef CONFIG_ARCH_OMAP3
495void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); 478void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
@@ -539,6 +522,9 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
539void omap2_mcbsp1_mux_clkr_src(u8 mux); 522void omap2_mcbsp1_mux_clkr_src(u8 mux);
540void omap2_mcbsp1_mux_fsr_src(u8 mux); 523void omap2_mcbsp1_mux_fsr_src(u8 mux);
541 524
525int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
526int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
527
542#ifdef CONFIG_ARCH_OMAP3 528#ifdef CONFIG_ARCH_OMAP3
543/* Sidetone specific API */ 529/* Sidetone specific API */
544int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); 530int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 1254e4945b6f..3d51b18131cc 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -1,8 +1,19 @@
1#ifndef _OMAP2_MCSPI_H 1#ifndef _OMAP2_MCSPI_H
2#define _OMAP2_MCSPI_H 2#define _OMAP2_MCSPI_H
3 3
4#define OMAP2_MCSPI_REV 0
5#define OMAP3_MCSPI_REV 1
6#define OMAP4_MCSPI_REV 2
7
8#define OMAP4_MCSPI_REG_OFFSET 0x100
9
4struct omap2_mcspi_platform_config { 10struct omap2_mcspi_platform_config {
5 unsigned short num_cs; 11 unsigned short num_cs;
12 unsigned int regs_offset;
13};
14
15struct omap2_mcspi_dev_attr {
16 unsigned short num_chipselect;
6}; 17};
7 18
8struct omap2_mcspi_device_config { 19struct omap2_mcspi_device_config {
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h
index f8d922fb5584..e6720aa2d553 100644
--- a/arch/arm/plat-omap/include/plat/memory.h
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -37,9 +37,9 @@
37 * Physical DRAM offset. 37 * Physical DRAM offset.
38 */ 38 */
39#if defined(CONFIG_ARCH_OMAP1) 39#if defined(CONFIG_ARCH_OMAP1)
40#define PHYS_OFFSET UL(0x10000000) 40#define PLAT_PHYS_OFFSET UL(0x10000000)
41#else 41#else
42#define PHYS_OFFSET UL(0x80000000) 42#define PLAT_PHYS_OFFSET UL(0x80000000)
43#endif 43#endif
44 44
45/* 45/*
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index f57f36abb07e..f38fef9f1310 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -24,25 +24,19 @@
24#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ 24#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
25 25
26#define OMAP24XX_NR_MMC 2 26#define OMAP24XX_NR_MMC 2
27#define OMAP34XX_NR_MMC 3
28#define OMAP44XX_NR_MMC 5
29#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE 27#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
30#define OMAP3_HSMMC_SIZE 0x200
31#define OMAP4_HSMMC_SIZE 0x1000
32#define OMAP2_MMC1_BASE 0x4809c000 28#define OMAP2_MMC1_BASE 0x4809c000
33#define OMAP2_MMC2_BASE 0x480b4000 29
34#define OMAP3_MMC3_BASE 0x480ad000
35#define OMAP4_MMC4_BASE 0x480d1000
36#define OMAP4_MMC5_BASE 0x480d5000
37#define OMAP4_MMC_REG_OFFSET 0x100 30#define OMAP4_MMC_REG_OFFSET 0x100
38#define HSMMC5 (1 << 4)
39#define HSMMC4 (1 << 3)
40#define HSMMC3 (1 << 2)
41#define HSMMC2 (1 << 1)
42#define HSMMC1 (1 << 0)
43 31
44#define OMAP_MMC_MAX_SLOTS 2 32#define OMAP_MMC_MAX_SLOTS 2
45 33
34#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(1)
35
36struct omap_mmc_dev_attr {
37 u8 flags;
38};
39
46struct omap_mmc_platform_data { 40struct omap_mmc_platform_data {
47 /* back-link to device */ 41 /* back-link to device */
48 struct device *dev; 42 struct device *dev;
@@ -71,6 +65,9 @@ struct omap_mmc_platform_data {
71 65
72 u64 dma_mask; 66 u64 dma_mask;
73 67
68 /* Integrating attributes from the omap_hwmod layer */
69 u8 controller_flags;
70
74 /* Register offset deviation */ 71 /* Register offset deviation */
75 u16 reg_offset; 72 u16 reg_offset;
76 73
@@ -159,8 +156,7 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
159 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) 156 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
160void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, 157void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
161 int nr_controllers); 158 int nr_controllers);
162void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, 159void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
163 int nr_controllers);
164int omap_mmc_add(const char *name, int id, unsigned long base, 160int omap_mmc_add(const char *name, int id, unsigned long base,
165 unsigned long size, unsigned int irq, 161 unsigned long size, unsigned int irq,
166 struct omap_mmc_platform_data *data); 162 struct omap_mmc_platform_data *data);
@@ -169,8 +165,7 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
169 int nr_controllers) 165 int nr_controllers)
170{ 166{
171} 167}
172static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, 168static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
173 int nr_controllers)
174{ 169{
175} 170}
176static inline int omap_mmc_add(const char *name, int id, unsigned long base, 171static inline int omap_mmc_add(const char *name, int id, unsigned long base,
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index ffd909fa5287..999ffba2690c 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -66,7 +66,7 @@
66# error "OMAP1 and OMAP2PLUS can't be selected at the same time" 66# error "OMAP1 and OMAP2PLUS can't be selected at the same time"
67# endif 67# endif
68#endif 68#endif
69#ifdef CONFIG_ARCH_OMAP2420 69#ifdef CONFIG_SOC_OMAP2420
70# ifdef OMAP_NAME 70# ifdef OMAP_NAME
71# undef MULTI_OMAP2 71# undef MULTI_OMAP2
72# define MULTI_OMAP2 72# define MULTI_OMAP2
@@ -74,7 +74,7 @@
74# define OMAP_NAME omap2420 74# define OMAP_NAME omap2420
75# endif 75# endif
76#endif 76#endif
77#ifdef CONFIG_ARCH_OMAP2430 77#ifdef CONFIG_SOC_OMAP2430
78# ifdef OMAP_NAME 78# ifdef OMAP_NAME
79# undef MULTI_OMAP2 79# undef MULTI_OMAP2
80# define MULTI_OMAP2 80# define MULTI_OMAP2
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 6562cd082bb1..d86d1ecf0068 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -8,8 +8,16 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <plat/gpmc.h>
11#include <linux/mtd/partitions.h> 12#include <linux/mtd/partitions.h>
12 13
14enum nand_io {
15 NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
16 NAND_OMAP_POLLED, /* polled mode, without prefetch */
17 NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
18 NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
19};
20
13struct omap_nand_platform_data { 21struct omap_nand_platform_data {
14 unsigned int options; 22 unsigned int options;
15 int cs; 23 int cs;
@@ -20,8 +28,11 @@ struct omap_nand_platform_data {
20 int (*nand_setup)(void); 28 int (*nand_setup)(void);
21 int (*dev_ready)(struct omap_nand_platform_data *); 29 int (*dev_ready)(struct omap_nand_platform_data *);
22 int dma_channel; 30 int dma_channel;
31 int gpmc_irq;
32 enum nand_io xfer_type;
23 unsigned long phys_base; 33 unsigned long phys_base;
24 int devsize; 34 int devsize;
35 enum omap_ecc ecc_opt;
25}; 36};
26 37
27/* minimum size for IO mapping */ 38/* minimum size for IO mapping */
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index 98fc8b4a4cc4..b9e85886b9d6 100644
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -56,8 +56,12 @@
56#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000) 56#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
57#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200) 57#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
58#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400) 58#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
59#define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800) 59#define OMAP3430_ISP_CSI2A_REGS1_BASE (OMAP3430_ISP_BASE + 0x1800)
60#define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970) 60#define OMAP3430_ISP_CSIPHY2_BASE (OMAP3430_ISP_BASE + 0x1970)
61#define OMAP3630_ISP_CSI2A_REGS2_BASE (OMAP3430_ISP_BASE + 0x19C0)
62#define OMAP3630_ISP_CSI2C_REGS1_BASE (OMAP3430_ISP_BASE + 0x1C00)
63#define OMAP3630_ISP_CSIPHY1_BASE (OMAP3430_ISP_BASE + 0x1D70)
64#define OMAP3630_ISP_CSI2C_REGS2_BASE (OMAP3430_ISP_BASE + 0x1DC0)
61 65
62#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F) 66#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
63#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077) 67#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
@@ -69,8 +73,12 @@
69#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB) 73#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
70#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB) 74#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
71#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F) 75#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
72#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F) 76#define OMAP3430_ISP_CSI2A_REGS1_END (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F)
73#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007) 77#define OMAP3430_ISP_CSIPHY2_END (OMAP3430_ISP_CSIPHY2_BASE + 0x00B)
78#define OMAP3630_ISP_CSI2A_REGS2_END (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F)
79#define OMAP3630_ISP_CSI2C_REGS1_END (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F)
80#define OMAP3630_ISP_CSIPHY1_END (OMAP3630_ISP_CSIPHY1_BASE + 0x00B)
81#define OMAP3630_ISP_CSI2C_REGS2_END (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F)
74 82
75#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) 83#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
76#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) 84#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1eee85a8abb3..1adea9c62984 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod macros, structures 2 * omap_hwmod macros, structures
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * Created in collaboration with (alphabetical order): Benoît Cousson, 7 * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -30,11 +30,11 @@
30#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H 30#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
31 31
32#include <linux/kernel.h> 32#include <linux/kernel.h>
33#include <linux/init.h>
33#include <linux/list.h> 34#include <linux/list.h>
34#include <linux/ioport.h> 35#include <linux/ioport.h>
35#include <linux/spinlock.h> 36#include <linux/spinlock.h>
36#include <plat/cpu.h> 37#include <plat/cpu.h>
37#include <plat/voltage.h>
38 38
39struct omap_device; 39struct omap_device;
40 40
@@ -90,6 +90,9 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
90struct omap_hwmod_mux_info { 90struct omap_hwmod_mux_info {
91 int nr_pads; 91 int nr_pads;
92 struct omap_device_pad *pads; 92 struct omap_device_pad *pads;
93 int nr_pads_dynamic;
94 struct omap_device_pad **pads_dynamic;
95 bool enabled;
93}; 96};
94 97
95/** 98/**
@@ -124,6 +127,7 @@ struct omap_hwmod_dma_info {
124 * struct omap_hwmod_rst_info - IPs reset lines use by hwmod 127 * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
125 * @name: name of the reset line (module local name) 128 * @name: name of the reset line (module local name)
126 * @rst_shift: Offset of the reset bit 129 * @rst_shift: Offset of the reset bit
130 * @st_shift: Offset of the reset status bit (OMAP2/3 only)
127 * 131 *
128 * @name should be something short, e.g., "cpu0" or "rst". It is defined 132 * @name should be something short, e.g., "cpu0" or "rst". It is defined
129 * locally to the hwmod. 133 * locally to the hwmod.
@@ -131,6 +135,7 @@ struct omap_hwmod_dma_info {
131struct omap_hwmod_rst_info { 135struct omap_hwmod_rst_info {
132 const char *name; 136 const char *name;
133 u8 rst_shift; 137 u8 rst_shift;
138 u8 st_shift;
134}; 139};
135 140
136/** 141/**
@@ -178,7 +183,8 @@ struct omap_hwmod_omap2_firewall {
178#define ADDR_TYPE_RT (1 << 1) 183#define ADDR_TYPE_RT (1 << 1)
179 184
180/** 185/**
181 * struct omap_hwmod_addr_space - MPU address space handled by the hwmod 186 * struct omap_hwmod_addr_space - address space handled by the hwmod
187 * @name: name of the address space
182 * @pa_start: starting physical address 188 * @pa_start: starting physical address
183 * @pa_end: ending physical address 189 * @pa_end: ending physical address
184 * @flags: (see omap_hwmod_addr_space.flags macros above) 190 * @flags: (see omap_hwmod_addr_space.flags macros above)
@@ -187,6 +193,7 @@ struct omap_hwmod_omap2_firewall {
187 * structure. GPMC is one example. 193 * structure. GPMC is one example.
188 */ 194 */
189struct omap_hwmod_addr_space { 195struct omap_hwmod_addr_space {
196 const char *name;
190 u32 pa_start; 197 u32 pa_start;
191 u32 pa_end; 198 u32 pa_end;
192 u8 flags; 199 u8 flags;
@@ -370,9 +377,11 @@ struct omap_hwmod_omap4_prcm {
370 * of standby, rather than relying on module smart-standby 377 * of standby, rather than relying on module smart-standby
371 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for 378 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
372 * SDRAM controller, etc. XXX probably belongs outside the main hwmod file 379 * SDRAM controller, etc. XXX probably belongs outside the main hwmod file
380 * XXX Should be HWMOD_SETUP_NO_RESET
373 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM 381 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
374 * controller, etc. XXX probably belongs outside the main hwmod file 382 * controller, etc. XXX probably belongs outside the main hwmod file
375 * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) 383 * XXX Should be HWMOD_SETUP_NO_IDLE
384 * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
376 * when module is enabled, rather than the default, which is to 385 * when module is enabled, rather than the default, which is to
377 * enable autoidle 386 * enable autoidle
378 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup 387 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
@@ -535,11 +544,12 @@ struct omap_hwmod {
535 const struct omap_chip_id omap_chip; 544 const struct omap_chip_id omap_chip;
536}; 545};
537 546
538int omap_hwmod_init(struct omap_hwmod **ohs); 547int omap_hwmod_register(struct omap_hwmod **ohs);
539struct omap_hwmod *omap_hwmod_lookup(const char *name); 548struct omap_hwmod *omap_hwmod_lookup(const char *name);
540int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), 549int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
541 void *data); 550 void *data);
542int omap_hwmod_late_init(void); 551
552int __init omap_hwmod_setup_one(const char *name);
543 553
544int omap_hwmod_enable(struct omap_hwmod *oh); 554int omap_hwmod_enable(struct omap_hwmod *oh);
545int _omap_hwmod_enable(struct omap_hwmod *oh); 555int _omap_hwmod_enable(struct omap_hwmod *oh);
@@ -555,6 +565,7 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
555int omap_hwmod_disable_clocks(struct omap_hwmod *oh); 565int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
556 566
557int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); 567int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
568int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
558 569
559int omap_hwmod_reset(struct omap_hwmod *oh); 570int omap_hwmod_reset(struct omap_hwmod *oh);
560void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); 571void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
@@ -589,6 +600,8 @@ int omap_hwmod_for_each_by_class(const char *classname,
589int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); 600int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
590u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); 601u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
591 602
603int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
604
592/* 605/*
593 * Chip variant-specific hwmod init routines - XXX should be converted 606 * Chip variant-specific hwmod init routines - XXX should be converted
594 * to use initcalls once the initial boot ordering is straightened out 607 * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index 1b430d5fdd54..2858667d2e4f 100644
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
@@ -15,12 +15,20 @@
15#define ONENAND_SYNC_READ (1 << 0) 15#define ONENAND_SYNC_READ (1 << 0)
16#define ONENAND_SYNC_READWRITE (1 << 1) 16#define ONENAND_SYNC_READWRITE (1 << 1)
17 17
18struct onenand_freq_info {
19 u16 maf_id;
20 u16 dev_id;
21 u16 ver_id;
22};
23
18struct omap_onenand_platform_data { 24struct omap_onenand_platform_data {
19 int cs; 25 int cs;
20 int gpio_irq; 26 int gpio_irq;
21 struct mtd_partition *parts; 27 struct mtd_partition *parts;
22 int nr_parts; 28 int nr_parts;
23 int (*onenand_setup)(void __iomem *, int freq); 29 int (*onenand_setup)(void __iomem *, int *freq_ptr);
30 int (*get_freq)(const struct onenand_freq_info *freq_info,
31 bool *clk_dep);
24 int dma_channel; 32 int dma_channel;
25 u8 flags; 33 u8 flags;
26 u8 regulator_can_sleep; 34 u8 regulator_can_sleep;
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index 2fdf8c80d390..267f43bb2a4e 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -28,7 +28,6 @@
28#define __ASM_ARM_ARCH_OMAP_PRCM_H 28#define __ASM_ARM_ARCH_OMAP_PRCM_H
29 29
30u32 omap_prcm_get_reset_sources(void); 30u32 omap_prcm_get_reset_sources(void);
31void omap_prcm_arch_reset(char mode, const char *cmd);
32int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, 31int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
33 const char *name); 32 const char *name);
34 33
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index efd87c8dda69..925b12b500dc 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -124,8 +124,14 @@ struct omap_sdrc_params {
124 u32 mr; 124 u32 mr;
125}; 125};
126 126
127void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 127#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
128void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
128 struct omap_sdrc_params *sdrc_cs1); 129 struct omap_sdrc_params *sdrc_cs1);
130#else
131static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
132 struct omap_sdrc_params *sdrc_cs1) {};
133#endif
134
129int omap2_sdrc_get_params(unsigned long r, 135int omap2_sdrc_get_params(unsigned long r,
130 struct omap_sdrc_params **sdrc_cs0, 136 struct omap_sdrc_params **sdrc_cs0,
131 struct omap_sdrc_params **sdrc_cs1); 137 struct omap_sdrc_params **sdrc_cs1);
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index cec5d56db2eb..2723f9166ea2 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -27,7 +27,7 @@
27 * 2. We assume printascii is called at least once before paging_init, 27 * 2. We assume printascii is called at least once before paging_init,
28 * and addruart has a chance to read OMAP_UART_INFO 28 * and addruart has a chance to read OMAP_UART_INFO
29 */ 29 */
30#define OMAP_UART_INFO (PHYS_OFFSET + 0x3ffc) 30#define OMAP_UART_INFO (PLAT_PHYS_OFFSET + 0x3ffc)
31 31
32/* OMAP1 serial ports */ 32/* OMAP1 serial ports */
33#define OMAP1_UART1_BASE 0xfffb0000 33#define OMAP1_UART1_BASE 0xfffb0000
@@ -51,6 +51,11 @@
51#define OMAP4_UART3_BASE 0x48020000 51#define OMAP4_UART3_BASE 0x48020000
52#define OMAP4_UART4_BASE 0x4806e000 52#define OMAP4_UART4_BASE 0x4806e000
53 53
54/* TI816X serial ports */
55#define TI816X_UART1_BASE 0x48020000
56#define TI816X_UART2_BASE 0x48022000
57#define TI816X_UART3_BASE 0x48024000
58
54/* External port on Zoom2/3 */ 59/* External port on Zoom2/3 */
55#define ZOOM_UART_BASE 0x10000000 60#define ZOOM_UART_BASE 0x10000000
56#define ZOOM_UART_VIRT 0xfa400000 61#define ZOOM_UART_VIRT 0xfa400000
@@ -81,6 +86,9 @@
81#define OMAP4UART2 OMAP2UART2 86#define OMAP4UART2 OMAP2UART2
82#define OMAP4UART3 43 87#define OMAP4UART3 43
83#define OMAP4UART4 44 88#define OMAP4UART4 44
89#define TI816XUART1 81
90#define TI816XUART2 82
91#define TI816XUART3 83
84#define ZOOM_UART 95 /* Only on zoom2/3 */ 92#define ZOOM_UART 95 /* Only on zoom2/3 */
85 93
86/* This is only used by 8250.c for omap1510 */ 94/* This is only used by 8250.c for omap1510 */
@@ -96,7 +104,6 @@
96 104
97struct omap_board_data; 105struct omap_board_data;
98 106
99extern void __init omap_serial_early_init(void);
100extern void omap_serial_init(void); 107extern void omap_serial_init(void);
101extern void omap_serial_init_port(struct omap_board_data *bdata); 108extern void omap_serial_init_port(struct omap_board_data *bdata);
102extern int omap_uart_can_sleep(void); 109extern int omap_uart_can_sleep(void);
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
deleted file mode 100644
index 6568c885f37a..000000000000
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ /dev/null
@@ -1,245 +0,0 @@
1/*
2 * OMAP Smartreflex Defines and Routines
3 *
4 * Author: Thara Gopinath <thara@ti.com>
5 *
6 * Copyright (C) 2010 Texas Instruments, Inc.
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008 Nokia Corporation
10 * Kalle Jokiniemi
11 *
12 * Copyright (C) 2007 Texas Instruments, Inc.
13 * Lesly A M <x0080970@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
21#define __ASM_ARM_OMAP_SMARTREFLEX_H
22
23#include <linux/platform_device.h>
24#include <plat/voltage.h>
25
26/*
27 * Different Smartreflex IPs version. The v1 is the 65nm version used in
28 * OMAP3430. The v2 is the update for the 45nm version of the IP
29 * used in OMAP3630 and OMAP4430
30 */
31#define SR_TYPE_V1 1
32#define SR_TYPE_V2 2
33
34/* SMART REFLEX REG ADDRESS OFFSET */
35#define SRCONFIG 0x00
36#define SRSTATUS 0x04
37#define SENVAL 0x08
38#define SENMIN 0x0C
39#define SENMAX 0x10
40#define SENAVG 0x14
41#define AVGWEIGHT 0x18
42#define NVALUERECIPROCAL 0x1c
43#define SENERROR_V1 0x20
44#define ERRCONFIG_V1 0x24
45#define IRQ_EOI 0x20
46#define IRQSTATUS_RAW 0x24
47#define IRQSTATUS 0x28
48#define IRQENABLE_SET 0x2C
49#define IRQENABLE_CLR 0x30
50#define SENERROR_V2 0x34
51#define ERRCONFIG_V2 0x38
52
53/* Bit/Shift Positions */
54
55/* SRCONFIG */
56#define SRCONFIG_ACCUMDATA_SHIFT 22
57#define SRCONFIG_SRCLKLENGTH_SHIFT 12
58#define SRCONFIG_SENNENABLE_V1_SHIFT 5
59#define SRCONFIG_SENPENABLE_V1_SHIFT 3
60#define SRCONFIG_SENNENABLE_V2_SHIFT 1
61#define SRCONFIG_SENPENABLE_V2_SHIFT 0
62#define SRCONFIG_CLKCTRL_SHIFT 0
63
64#define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22)
65
66#define SRCONFIG_SRENABLE BIT(11)
67#define SRCONFIG_SENENABLE BIT(10)
68#define SRCONFIG_ERRGEN_EN BIT(9)
69#define SRCONFIG_MINMAXAVG_EN BIT(8)
70#define SRCONFIG_DELAYCTRL BIT(2)
71
72/* AVGWEIGHT */
73#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2
74#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0
75
76/* NVALUERECIPROCAL */
77#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
78#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
79#define NVALUERECIPROCAL_RNSENP_SHIFT 8
80#define NVALUERECIPROCAL_RNSENN_SHIFT 0
81
82/* ERRCONFIG */
83#define ERRCONFIG_ERRWEIGHT_SHIFT 16
84#define ERRCONFIG_ERRMAXLIMIT_SHIFT 8
85#define ERRCONFIG_ERRMINLIMIT_SHIFT 0
86
87#define SR_ERRWEIGHT_MASK (0x07 << 16)
88#define SR_ERRMAXLIMIT_MASK (0xff << 8)
89#define SR_ERRMINLIMIT_MASK (0xff << 0)
90
91#define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31)
92#define ERRCONFIG_VPBOUNDINTST_V1 BIT(30)
93#define ERRCONFIG_MCUACCUMINTEN BIT(29)
94#define ERRCONFIG_MCUACCUMINTST BIT(28)
95#define ERRCONFIG_MCUVALIDINTEN BIT(27)
96#define ERRCONFIG_MCUVALIDINTST BIT(26)
97#define ERRCONFIG_MCUBOUNDINTEN BIT(25)
98#define ERRCONFIG_MCUBOUNDINTST BIT(24)
99#define ERRCONFIG_MCUDISACKINTEN BIT(23)
100#define ERRCONFIG_VPBOUNDINTST_V2 BIT(23)
101#define ERRCONFIG_MCUDISACKINTST BIT(22)
102#define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22)
103
104#define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \
105 ERRCONFIG_MCUACCUMINTST | \
106 ERRCONFIG_MCUVALIDINTST | \
107 ERRCONFIG_MCUBOUNDINTST | \
108 ERRCONFIG_MCUDISACKINTST)
109/* IRQSTATUS */
110#define IRQSTATUS_MCUACCUMINT BIT(3)
111#define IRQSTATUS_MCVALIDINT BIT(2)
112#define IRQSTATUS_MCBOUNDSINT BIT(1)
113#define IRQSTATUS_MCUDISABLEACKINT BIT(0)
114
115/* IRQENABLE_SET and IRQENABLE_CLEAR */
116#define IRQENABLE_MCUACCUMINT BIT(3)
117#define IRQENABLE_MCUVALIDINT BIT(2)
118#define IRQENABLE_MCUBOUNDSINT BIT(1)
119#define IRQENABLE_MCUDISABLEACKINT BIT(0)
120
121/* Common Bit values */
122
123#define SRCLKLENGTH_12MHZ_SYSCLK 0x3c
124#define SRCLKLENGTH_13MHZ_SYSCLK 0x41
125#define SRCLKLENGTH_19MHZ_SYSCLK 0x60
126#define SRCLKLENGTH_26MHZ_SYSCLK 0x82
127#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0
128
129/*
130 * 3430 specific values. Maybe these should be passed from board file or
131 * pmic structures.
132 */
133#define OMAP3430_SR_ACCUMDATA 0x1f4
134
135#define OMAP3430_SR1_SENPAVGWEIGHT 0x03
136#define OMAP3430_SR1_SENNAVGWEIGHT 0x03
137
138#define OMAP3430_SR2_SENPAVGWEIGHT 0x01
139#define OMAP3430_SR2_SENNAVGWEIGHT 0x01
140
141#define OMAP3430_SR_ERRWEIGHT 0x04
142#define OMAP3430_SR_ERRMAXLIMIT 0x02
143
144/**
145 * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
146 * pmic specific info to smartreflex driver
147 *
148 * @sr_pmic_init: API to initialize smartreflex on the PMIC side.
149 */
150struct omap_sr_pmic_data {
151 void (*sr_pmic_init) (void);
152};
153
154#ifdef CONFIG_OMAP_SMARTREFLEX
155/*
156 * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
157 * The smartreflex class driver should pass the class type.
158 * Should be used to populate the class_type field of the
159 * omap_smartreflex_class_data structure.
160 */
161#define SR_CLASS1 0x1
162#define SR_CLASS2 0x2
163#define SR_CLASS3 0x3
164
165/**
166 * struct omap_sr_class_data - Smartreflex class driver info
167 *
168 * @enable: API to enable a particular class smaartreflex.
169 * @disable: API to disable a particular class smartreflex.
170 * @configure: API to configure a particular class smartreflex.
171 * @notify: API to notify the class driver about an event in SR.
172 * Not needed for class3.
173 * @notify_flags: specify the events to be notified to the class driver
174 * @class_type: specify which smartreflex class.
175 * Can be used by the SR driver to take any class
176 * based decisions.
177 */
178struct omap_sr_class_data {
179 int (*enable)(struct voltagedomain *voltdm);
180 int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
181 int (*configure)(struct voltagedomain *voltdm);
182 int (*notify)(struct voltagedomain *voltdm, u32 status);
183 u8 notify_flags;
184 u8 class_type;
185};
186
187/**
188 * struct omap_sr_nvalue_table - Smartreflex n-target value info
189 *
190 * @efuse_offs: The offset of the efuse where n-target values are stored.
191 * @nvalue: The n-target value.
192 */
193struct omap_sr_nvalue_table {
194 u32 efuse_offs;
195 u32 nvalue;
196};
197
198/**
199 * struct omap_sr_data - Smartreflex platform data.
200 *
201 * @ip_type: Smartreflex IP type.
202 * @senp_mod: SENPENABLE value for the sr
203 * @senn_mod: SENNENABLE value for sr
204 * @nvalue_count: Number of distinct nvalues in the nvalue table
205 * @enable_on_init: whether this sr module needs to enabled at
206 * boot up or not.
207 * @nvalue_table: table containing the efuse offsets and nvalues
208 * corresponding to them.
209 * @voltdm: Pointer to the voltage domain associated with the SR
210 */
211struct omap_sr_data {
212 int ip_type;
213 u32 senp_mod;
214 u32 senn_mod;
215 int nvalue_count;
216 bool enable_on_init;
217 struct omap_sr_nvalue_table *nvalue_table;
218 struct voltagedomain *voltdm;
219};
220
221/* Smartreflex module enable/disable interface */
222void omap_sr_enable(struct voltagedomain *voltdm);
223void omap_sr_disable(struct voltagedomain *voltdm);
224void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
225
226/* API to register the pmic specific data with the smartreflex driver. */
227void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
228
229/* Smartreflex driver hooks to be called from Smartreflex class driver */
230int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
231void sr_disable(struct voltagedomain *voltdm);
232int sr_configure_errgen(struct voltagedomain *voltdm);
233int sr_configure_minmax(struct voltagedomain *voltdm);
234
235/* API to register the smartreflex class driver with the smartreflex driver */
236int sr_register_class(struct omap_sr_class_data *class_data);
237#else
238static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
239static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
240static inline void omap_sr_disable_reset_volt(
241 struct voltagedomain *voltdm) {}
242static inline void omap_sr_register_pmic(
243 struct omap_sr_pmic_data *pmic_data) {}
244#endif
245#endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 9967d5e855c7..f500fc34d065 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -12,7 +12,19 @@
12#define __ARCH_ARM_OMAP_SRAM_H 12#define __ARCH_ARM_OMAP_SRAM_H
13 13
14#ifndef __ASSEMBLY__ 14#ifndef __ASSEMBLY__
15extern void * omap_sram_push(void * start, unsigned long size); 15#include <asm/fncpy.h>
16
17extern void *omap_sram_push_address(unsigned long size);
18
19/* Macro to push a function to the internal SRAM, using the fncpy API */
20#define omap_sram_push(funcp, size) ({ \
21 typeof(&(funcp)) _res = NULL; \
22 void *_sram_address = omap_sram_push_address(size); \
23 if (_sram_address) \
24 _res = fncpy(_sram_address, &(funcp), size); \
25 _res; \
26})
27
16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); 28extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
17 29
18extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 30extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
index d0a119f735b4..c5fa9e929009 100644
--- a/arch/arm/plat-omap/include/plat/system.h
+++ b/arch/arm/plat-omap/include/plat/system.h
@@ -4,48 +4,14 @@
4 */ 4 */
5#ifndef __ASM_ARCH_SYSTEM_H 5#ifndef __ASM_ARCH_SYSTEM_H
6#define __ASM_ARCH_SYSTEM_H 6#define __ASM_ARCH_SYSTEM_H
7#include <linux/clk.h>
8 7
9#include <asm/mach-types.h> 8#include <asm/proc-fns.h>
10#include <mach/hardware.h>
11
12#include <plat/prcm.h>
13
14#ifndef CONFIG_MACH_VOICEBLUE
15#define voiceblue_reset() do {} while (0)
16#else
17extern void voiceblue_reset(void);
18#endif
19 9
20static inline void arch_idle(void) 10static inline void arch_idle(void)
21{ 11{
22 cpu_do_idle(); 12 cpu_do_idle();
23} 13}
24 14
25static inline void omap1_arch_reset(char mode, const char *cmd) 15extern void (*arch_reset)(char, const char *);
26{
27 /*
28 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
29 * "Global Software Reset Affects Traffic Controller Frequency".
30 */
31 if (cpu_is_omap5912()) {
32 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
33 DPLL_CTL);
34 omap_writew(0x8, ARM_RSTCT1);
35 }
36
37 if (machine_is_voiceblue())
38 voiceblue_reset();
39 else
40 omap_writew(1, ARM_RSTCT1);
41}
42
43static inline void arch_reset(char mode, const char *cmd)
44{
45 if (!cpu_class_is_omap2())
46 omap1_arch_reset(mode, cmd);
47 else
48 omap_prcm_arch_reset(mode, cmd);
49}
50 16
51#endif 17#endif
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti816x.h
new file mode 100644
index 000000000000..50510f5dda1e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/ti816x.h
@@ -0,0 +1,27 @@
1/*
2 * This file contains the address data for various TI816X modules.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ASM_ARCH_TI816X_H
17#define __ASM_ARCH_TI816X_H
18
19#define L4_SLOW_TI816X_BASE 0x48000000
20
21#define TI816X_SCM_BASE 0x48140000
22#define TI816X_CTRL_BASE TI816X_SCM_BASE
23#define TI816X_PRCM_BASE 0x48180000
24
25#define TI816X_ARM_INTC_BASE 0x48200000
26
27#endif /* __ASM_ARCH_TI816X_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ad98b85cae21..30b891c4a93f 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -93,6 +93,10 @@ static inline void flush(void)
93#define DEBUG_LL_ZOOM(mach) \ 93#define DEBUG_LL_ZOOM(mach) \
94 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) 94 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
95 95
96#define DEBUG_LL_TI816X(p, mach) \
97 _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \
98 TI816XUART##p)
99
96static inline void __arch_decomp_setup(unsigned long arch_id) 100static inline void __arch_decomp_setup(unsigned long arch_id)
97{ 101{
98 int port = 0; 102 int port = 0;
@@ -166,6 +170,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
166 DEBUG_LL_ZOOM(omap_zoom2); 170 DEBUG_LL_ZOOM(omap_zoom2);
167 DEBUG_LL_ZOOM(omap_zoom3); 171 DEBUG_LL_ZOOM(omap_zoom3);
168 172
173 /* TI8168 base boards using UART3 */
174 DEBUG_LL_TI816X(3, ti8168evm);
175
169 } while (0); 176 } while (0);
170} 177}
171 178
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 450a332f1009..02b96c8f6a17 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -7,15 +7,12 @@
7#include <plat/board.h> 7#include <plat/board.h>
8 8
9#define OMAP3_HS_USB_PORTS 3 9#define OMAP3_HS_USB_PORTS 3
10enum ehci_hcd_omap_mode {
11 EHCI_HCD_OMAP_MODE_UNKNOWN,
12 EHCI_HCD_OMAP_MODE_PHY,
13 EHCI_HCD_OMAP_MODE_TLL,
14 EHCI_HCD_OMAP_MODE_HSIC,
15};
16 10
17enum ohci_omap3_port_mode { 11enum usbhs_omap_port_mode {
18 OMAP_OHCI_PORT_MODE_UNUSED, 12 OMAP_USBHS_PORT_MODE_UNUSED,
13 OMAP_EHCI_PORT_MODE_PHY,
14 OMAP_EHCI_PORT_MODE_TLL,
15 OMAP_EHCI_PORT_MODE_HSIC,
19 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0, 16 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
20 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM, 17 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
21 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0, 18 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
@@ -25,24 +22,45 @@ enum ohci_omap3_port_mode {
25 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0, 22 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
26 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM, 23 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
27 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0, 24 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
28 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM, 25 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
29}; 26};
30 27
31struct ehci_hcd_omap_platform_data { 28struct usbhs_omap_board_data {
32 enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; 29 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
33 unsigned phy_reset:1;
34 30
35 /* have to be valid if phy_reset is true and portx is in phy mode */ 31 /* have to be valid if phy_reset is true and portx is in phy mode */
36 int reset_gpio_port[OMAP3_HS_USB_PORTS]; 32 int reset_gpio_port[OMAP3_HS_USB_PORTS];
33
34 /* Set this to true for ES2.x silicon */
35 unsigned es2_compatibility:1;
36
37 unsigned phy_reset:1;
38
39 /*
40 * Regulators for USB PHYs.
41 * Each PHY can have a separate regulator.
42 */
43 struct regulator *regulator[OMAP3_HS_USB_PORTS];
37}; 44};
38 45
39struct ohci_hcd_omap_platform_data { 46struct ehci_hcd_omap_platform_data {
40 enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS]; 47 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
48 int reset_gpio_port[OMAP3_HS_USB_PORTS];
49 struct regulator *regulator[OMAP3_HS_USB_PORTS];
50 unsigned phy_reset:1;
51};
41 52
42 /* Set this to true for ES2.x silicon */ 53struct ohci_hcd_omap_platform_data {
54 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
43 unsigned es2_compatibility:1; 55 unsigned es2_compatibility:1;
44}; 56};
45 57
58struct usbhs_omap_platform_data {
59 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
60
61 struct ehci_hcd_omap_platform_data *ehci_data;
62 struct ohci_hcd_omap_platform_data *ohci_data;
63};
46/*-------------------------------------------------------------------------*/ 64/*-------------------------------------------------------------------------*/
47 65
48#define OMAP1_OTG_BASE 0xfffb0400 66#define OMAP1_OTG_BASE 0xfffb0400
@@ -80,17 +98,22 @@ enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
80 98
81extern void usb_musb_init(struct omap_musb_board_data *board_data); 99extern void usb_musb_init(struct omap_musb_board_data *board_data);
82 100
83extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata); 101extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
84 102
85extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata); 103extern int omap_usbhs_enable(struct device *dev);
104extern void omap_usbhs_disable(struct device *dev);
86 105
87extern int omap4430_phy_power(struct device *dev, int ID, int on); 106extern int omap4430_phy_power(struct device *dev, int ID, int on);
88extern int omap4430_phy_set_clk(struct device *dev, int on); 107extern int omap4430_phy_set_clk(struct device *dev, int on);
89extern int omap4430_phy_init(struct device *dev); 108extern int omap4430_phy_init(struct device *dev);
90extern int omap4430_phy_exit(struct device *dev); 109extern int omap4430_phy_exit(struct device *dev);
91 110extern int omap4430_phy_suspend(struct device *dev, int suspend);
92#endif 111#endif
93 112
113extern void am35x_musb_reset(void);
114extern void am35x_musb_phy_power(u8 on);
115extern void am35x_musb_clear_irq(void);
116extern void am35x_musb_set_mode(u8 musb_mode);
94 117
95/* 118/*
96 * FIXME correct answer depends on hmc_mode, 119 * FIXME correct answer depends on hmc_mode,
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
deleted file mode 100644
index 5bd204e55c32..000000000000
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * OMAP Voltage Management Routines
3 *
4 * Author: Thara Gopinath <thara@ti.com>
5 *
6 * Copyright (C) 2009 Texas Instruments, Inc.
7 * Thara Gopinath <thara@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
15#define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
16
17#include <linux/err.h>
18
19#define VOLTSCALE_VPFORCEUPDATE 1
20#define VOLTSCALE_VCBYPASS 2
21
22/*
23 * OMAP3 GENERIC setup times. Revisit to see if these needs to be
24 * passed from board or PMIC file
25 */
26#define OMAP3_CLKSETUP 0xff
27#define OMAP3_VOLTOFFSET 0xff
28#define OMAP3_VOLTSETUP2 0xff
29
30/* Voltage value defines */
31#define OMAP3430_VDD_MPU_OPP1_UV 975000
32#define OMAP3430_VDD_MPU_OPP2_UV 1075000
33#define OMAP3430_VDD_MPU_OPP3_UV 1200000
34#define OMAP3430_VDD_MPU_OPP4_UV 1270000
35#define OMAP3430_VDD_MPU_OPP5_UV 1350000
36
37#define OMAP3430_VDD_CORE_OPP1_UV 975000
38#define OMAP3430_VDD_CORE_OPP2_UV 1050000
39#define OMAP3430_VDD_CORE_OPP3_UV 1150000
40
41#define OMAP3630_VDD_MPU_OPP50_UV 1012500
42#define OMAP3630_VDD_MPU_OPP100_UV 1200000
43#define OMAP3630_VDD_MPU_OPP120_UV 1325000
44#define OMAP3630_VDD_MPU_OPP1G_UV 1375000
45
46#define OMAP3630_VDD_CORE_OPP50_UV 1000000
47#define OMAP3630_VDD_CORE_OPP100_UV 1200000
48
49#define OMAP4430_VDD_MPU_OPP50_UV 930000
50#define OMAP4430_VDD_MPU_OPP100_UV 1100000
51#define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000
52#define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000
53
54#define OMAP4430_VDD_IVA_OPP50_UV 930000
55#define OMAP4430_VDD_IVA_OPP100_UV 1100000
56#define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000
57
58#define OMAP4430_VDD_CORE_OPP50_UV 930000
59#define OMAP4430_VDD_CORE_OPP100_UV 1100000
60
61/**
62 * struct voltagedomain - omap voltage domain global structure.
63 * @name: Name of the voltage domain which can be used as a unique
64 * identifier.
65 */
66struct voltagedomain {
67 char *name;
68};
69
70/**
71 * struct omap_volt_data - Omap voltage specific data.
72 * @voltage_nominal: The possible voltage value in uV
73 * @sr_efuse_offs: The offset of the efuse register(from system
74 * control module base address) from where to read
75 * the n-target value for the smartreflex module.
76 * @sr_errminlimit: Error min limit value for smartreflex. This value
77 * differs at differnet opp and thus is linked
78 * with voltage.
79 * @vp_errorgain: Error gain value for the voltage processor. This
80 * field also differs according to the voltage/opp.
81 */
82struct omap_volt_data {
83 u32 volt_nominal;
84 u32 sr_efuse_offs;
85 u8 sr_errminlimit;
86 u8 vp_errgain;
87};
88
89/**
90 * struct omap_volt_pmic_info - PMIC specific data required by voltage driver.
91 * @slew_rate: PMIC slew rate (in uv/us)
92 * @step_size: PMIC voltage step size (in uv)
93 * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV.
94 * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value.
95 */
96struct omap_volt_pmic_info {
97 int slew_rate;
98 int step_size;
99 u32 on_volt;
100 u32 onlp_volt;
101 u32 ret_volt;
102 u32 off_volt;
103 u16 volt_setup_time;
104 u8 vp_erroroffset;
105 u8 vp_vstepmin;
106 u8 vp_vstepmax;
107 u8 vp_vddmin;
108 u8 vp_vddmax;
109 u8 vp_timeout_us;
110 u8 i2c_slave_addr;
111 u8 pmic_reg;
112 unsigned long (*vsel_to_uv) (const u8 vsel);
113 u8 (*uv_to_vsel) (unsigned long uV);
114};
115
116unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
117void omap_vp_enable(struct voltagedomain *voltdm);
118void omap_vp_disable(struct voltagedomain *voltdm);
119int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
120 unsigned long target_volt);
121void omap_voltage_reset(struct voltagedomain *voltdm);
122void omap_voltage_get_volttable(struct voltagedomain *voltdm,
123 struct omap_volt_data **volt_data);
124struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
125 unsigned long volt);
126unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
127struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
128#ifdef CONFIG_PM
129int omap_voltage_register_pmic(struct voltagedomain *voltdm,
130 struct omap_volt_pmic_info *pmic_info);
131void omap_change_voltscale_method(struct voltagedomain *voltdm,
132 int voltscale_method);
133/* API to get the voltagedomain pointer */
134struct voltagedomain *omap_voltage_domain_lookup(char *name);
135
136int omap_voltage_late_init(void);
137#else
138static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
139 struct omap_volt_pmic_info *pmic_info)
140{
141 return -EINVAL;
142}
143static inline void omap_change_voltscale_method(struct voltagedomain *voltdm,
144 int voltscale_method) {}
145static inline int omap_voltage_late_init(void)
146{
147 return -EINVAL;
148}
149static inline struct voltagedomain *omap_voltage_domain_lookup(char *name)
150{
151 return ERR_PTR(-EINVAL);
152}
153#endif
154
155#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 02:41:25 -0500